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S S
Body (B)
• STANDARD SYMBOLS:
• Operation (simplified picture)
• Arrow on B indicates polarity of p-n junction formed between
• +ve voltage applied to GATE creates an electric field in the substrate and channel
underlying p-type region; this tends to force holes down into the
substrate, and attract electrons towards the surface • Position of G terminal distinguishes S from D
• Line representing channel is:
• For small VGS, the underlying region remains p-type, and no current
• Broken for Enh. Mode (channel normally OFF)
can flow between SOURCE and DRAIN
• Full for Depl. Mode (channel normally ON)
• For larger VGS, region near surface becomes inverted (i.e. changes
• SIMPLIFIED SYMBOLS (S & B connected):
from p-type to n-type), and an n-type CHANNEL is created. This
provides a current path between S and D
• Arrow on S:
• Appreciable channel conduction occurs only when VGS exceeds • Indicates normal direction of current flow in S
THRESHOLD VOLTAGE Vt (cf. arrow on BJT emitter)
• Distinguishes S from D
• Depletion mode device is similar, but has a built-in channel, so • Line representing channel is:
conduction can occur even when VGS = 0
• Thin for Enh. Mode
• Thick for Depl. Mode
NB: GATE is ELECTRICALLY ISOLATED by oxide layer, so
IG = 0; MOSFET is a voltage-controlled device !
• P-channel symbols obtained by reversing arrows
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 1 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 2
MOSFET Operation - 1 MOSFET Operation - 2
TRIODE or LINEAR REGION SATURATION or ACTIVE REGION
(VGS > Vt , VDS < VGS - Vt) (VGS > Vt , VDS VGS - Vt)
• If VDS continues to increase, the effective gate voltage at the drain end
• For small VDS, channel behaves as a linear resistance, with conductance eventually drops to Vt, and the channel “PINCHES OFF”:
proportional to (VGS - Vt):
VGS > Vt VVDS GS
DS==VVGS- Vt
ID
S
VGS > Vt IDsat
VDS small
ID n+ n+
S ID
p Pinch-off point
n+ n+ VDS
VDSsat
p n-Channel VGS - Vt
VDS
• This occurs when VGD = Vt or, equivalently:
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 3 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 4
MOSFET Operating Curves - 1 MOSFET Operating Curves - 2
• N-channel, Depl. Mode: • Boundary line between triode and saturation regions has the equation
ID = KVDS2 (i.e. Equn 3.4 with VDS = VGS - Vt)
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 5 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 6
MOSFET Small-Signal Model
• INPUT SIDE
• OUTPUT SIDE
• From Equn 3.5, we can write the Drain signal current in saturation
as:
id = gmvgs + vds/ro
where:
and:
ro = VDS/ID VA /ID (3.7)
SSEM:
G gmvgs D
vgs ro
NB VGS and ID in Equns 3.6 and 3.7 are quiescent values, so small-signal
parameters depend on bias conditions
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 7 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 8
Common-Source Amplifier Common-Source Amplifier
Quiescent Analysis Small-Signal Analysis
VDD id
gmvgs
RD vgs ro
RG1
O/P RG RD
I/P vin vout
vs RS
RG2
RS
• Small-signal equations:
NB: Always go back and check that the active mode assumption was valid
i.e. that the calculated values of VG, VS and VD satisfy VDS VGS - Vt • OUTPUT RESISTANCE: (not obvious!)
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 9 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 10
C-S Amplifier Active Loads
Biasing with D-G Feedback
• Replace RD (or RC in a BJT amplifier) by a transistor configured to act
as a constant current source
VDD
e.g. N-channel Depletion Load
RD
RG O/P
IDSS ro = VA /IDSS
I/P
• IG = 0, so VG= VD !!
ID
• VGD < Vt and (Enh. mode) MOSFET must be saturated
SAT
TRIODE
• VD obtained by solving
• SSEC:
RG
0 VDS
gmvgs 0 |Vt |
vgs ro
vin RD vout • Advantages over passive, linear RD:
- gm (RD//ro) if RG large
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 11 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 12
Discrete NMOS Amplifier - 1 Discrete NMOS Amplifier - 2
Full I/P-O/P Relationship
VDD
• Using load-line method:
Q2
ID
O/P
gm1 vin A
0 VDS1
vin ro1 ro2 vout VDD - |Vt2| VDD
0
I II III IV
Points to note: VDD - |Vt2| Q1 OFF SAT SAT TRI
B
Q2 TRI TRI SAT SAT
• No bias network is shown - we are assuming the I/P voltage contains
both signal and bias components
0 VIN
0 Vt1
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 13 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 14
Integrated NMOS Amplifier Integrated CMOS Amplifier
• Body terminals of both N-channel FETs are (necessarily) grounded:
• Active load is now provided by a P-channel (Enh. mode) FET:
VDD
VDD
Q2
VSG2
Q2
O/P
Q1 O/P
Q1
I/P
I/P
• VBS of upper FET varies with the output voltage, and this modifies the
channel resistance (body acts like a second gate). This is the BODY • No body effect, because both devices have fixed VBS
EFFECT
back to Av = - gm1(ro1//ro2)
• SSEC becomes:
• VSG2 establishes required drain bias current
gm1 vin gmb2vout
vin ro1 ro2 vout In practice, Q2/voltage source combination would be replaced by a
CURRENT MIRROR (next lecture!)
AV = - gm1(ro1//ro2//gmb2-1)
- (gm1/gm2).(1/)
EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 15 EE1&ISE1 Analogue Electronics 2008/2009 - Part 3 ASH 16
ANALOGUE ELECTRONICS
PROBLEMS 3
1. (a) When VGS > Vt and VDS is small, the channel of a MOSFET behaves as a voltage-
controlled resistor. Starting with the appropriate MOSFET equation, show that the
channel resistance in this regime is given by:
Hence sketch the relationship between vOUT and vIN at constant VG for the circuit below.
Your graph should cover the range 0 < vIN < 100 mV and show separate curves for VG =
2, 3, 4 and 5 V.
(b) On a separate graph, and for the same four VG values, show roughly how vOUT varies
with vIN over the range 0 < vIN < 10 V. (hint: in this case you need to consider what
happens to the input-output relationship when the MOSFET goes into saturation)
1 k
vIN vOUT
K = 1 mA/V2
Vt = 2 V
VG
2. For each of the configurations below, determine the operating mode of the MOSFET or,
if the mode is indeterminate, state all the possibilities.
> Vt
5. (a) For the common-source amplifier in Figure Q5, choose values of RS and RD to give a
drain bias current of 1 mA and a quiescent output voltage of 5 V.
(b) Draw a small-signal equivalent circuit for the amplifier, assuming CS is effectively
short-circuit at signal frequencies, and determine the small-signal macromodel parameters
Ri, Ro and Av.
+10 V
RD
1.5 M
O/P
I/P
K = 0.25 mA/V2
Vt = 1 V, VA = 100 V
1 M
RS CS
Figure Q5
- gmRD
AV = _______________________
1 + gmRS + (RS + RD)/ro
(b) Draw a small-signal equivalent circuit for the amplifier, and determine the small-
signal voltage gain.
+10 V
3 k
1 M O/P
K = 0.5 mA/V2
I/P Vt = 2 V, VA = 120 V
8. (a) Show that the quiescent output voltage of the amplifier in Figure Q8 overleaf is given
by:
VOUT = Vt1 + |Vt2|(K2/K1)
where the subscripts 1 and 2 denote the lower and upper FETs respectively. You should
assume that both devices are in saturation.
(b) Draw a small-signal equivalent circuit, neglecting RG, and show that if the small-
signal output resistances of the two FETs are equal (i.e. VA1 = VA2 = VA) then the voltage
gain may be written as:
Hence determine VOUT and Av for the case K1 = 0.5 mA/V2, Vt1 = 2 V, K2 = 1 mA/V2, Vt2
= -1 V, VA = 100 V.
9. (tricky) Figure Q9 shows an NMOS amplifier with an enhancement load. Draw a small-
signal equivalent circuit for this amplifier, and show that the voltage gain is given by:
Av = - gm1 (ro1//ro2//gm2-1)
Show also that if ro1 and ro2 are large compared to gm2-1, Av may be expressed as:
Av - (K1/K2)
Q2 Q2
RG O/P O/P
I/P Q1 I/P Q1
Figure Q8 Figure Q9
Answers
2 (a) sub-threshold i.e. off; (b) triode/saturation; (c) saturation; (d) triode
3 (a) VDS = 2 V, ID = 8 mA; (b) VDS = 6 V, ID = 72 mA
4 K = 0.0625 mA/V2, Vt = 1 V
5 (a) RS = 1 k, RD = 5 k; (b) Ri = 0.6 M, Ro = 4.76 k, Av = -4.76
7 (a) ID = 2 mA, VOUT = 4 V; (b) Av = -5.70
8 VOUT = (2 + 2) = 3.41 V, Av = -100/2 = -71