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CHAPTER 6
6.1 INTRODUCTION
The logic circuits whose outputs at any instant of time depend not
only on the present inputs but also on the past outputs are known as sequential
circuits. In sequential circuit, outputs are fed back to the input side. Thus an
output signal is a function of the present input signals and a sequence of
the past input signals. The block diagram of sequential circuit is shown in
Figure 6.1. It consists of a combinational circuit to which memory elements
are connected to form a feedback path. The storage elements are devices
capable of storing binary information. The binary information stored in these
elements at any given time defines the state of the sequential circuit at the
time.
ways and gives rise to different types of flip-flops. The most common types of
flip flops are
is removed, the state of the flip-flop is indeterminate, i.e., either state may
result, depending on whether the set or reset input of the flip-flop remains a 1
longer than the transition to 0 at the end of the pulse.
Q S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Intermediate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Intermediate
The characteristics table of the flip flop is shown in Table 6.1. This
table shows the operation of the flip flop in a tabular form. The Q is an
abbreviation of Q (t) and stands for the binary state of the flip flop before the
application of a clock pulse, referred to as the present state. The S and R
columns give the possible values of the inputs, and Q (t+1) is the state of the
flip flop after the application of a single pulse, referred to as the next state.
The table must be interpreted as follows: Given the present state Q and the
inputs S and R, the application of a single pulse in the CP input causes the flip
flop to go to the next state Q (t+1).
Next the SR flip flop is designed using majority gates with the help
of the characteristics equation. It is constructed by using 5 majority gates and
1 inverter as shown in Figure 6.4. The circuit have two inputs S and R along
with one control input Clock. The last two majority gates M4 and M5 form a
loop. The output of the flip flop is fed back to M4 and combined with the
input R'of majority gate M4 to produce R'Q. Here the gate M4 act as an AND
gate. The gate M5 is designed to perform OR operation which combine the
output of Majority gate M1 and M4.Hence the output of the gate M5 produce
the desired characteristic Equation (6.1).
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never equal to 1 at the same time. This is done in the D flip flop as shown in
Figure 6.6 (a). The D flip flop is a modification of the clocked SR flip-flop. It
has only two inputs: D and CP. The D input goes directly into the S input and
the complement of the D input goes to the R input. The D input is sampled
during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to
the set state (unless it was already set). If it is 0, the flip-flop switches to the
clear state.
Q D Q (t+1)
0 0 0
0 1 1
1 0 0
1 1 1
Q (t+1) = D (6.2)
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The binary information present at the data input of the D flip flop is
transferred to the Q output when the CP input is enabled. The output follows
the data input as long as the pulse remains in its 1 state. When the pulse goes
to 0, the binary information that was present at the data input at the time the
pulse transition occurred is retained at the Q output until the pulse input is
enabled again.
Next the D flip flop is designed with the help of the characteristic
equation. The flip flop is designed by two ways. First method is using
majority gates and the second method is using a QCA binary wire. In the first
method the flip flop is constructed by using 3 majority gates and 1 inverter as
shown in Figure 6.8. The circuit have one input D and along with one control
input Clock. The output Q of the flip flop is fed back to the majority gate M3
and combined with the input D to produce the output Q. Here the gate M1 act
as an AND gate and M2 act as an OR gate. The gate M3 is designed to
perform OR operation which combine the output of Majority gate M1 and
M2.Hence the output of the gate M3 produce the desired characteristic
Equation (6.2).
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pulse only if Q' was previously 1. The behavior of the JK flip flop is
demonstrated in the characteristics table. A clocked JK flip-flop is shown in
Figure 6.11.
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
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and no change occurs. When T = 1, Q (t+1) = Q', the state of the flip flop is
complemented.
Q T Q (t+1)
0 0 0
0 1 1
1 0 1
1 1 0
Clock. The output Q of the flip flop is fed back to the input majority gate M2
and the complement of the output is fed back to the majority gate M1. The
output of M1 and M2 are combined with the Clock input by M3. Here the
gate M3 act as an OR gate to produce TQ'+T'Q. The gate M4 is used to form
a loop and to produce the desired characteristic Equation (6.4).
There are two methods of shifting the data. They are 1) Serial
shifting and 2) Parallel shifting. The serial shifting shifts one bit at a time for
each clock pulse in a serial fashion, beginning with either MSB (Most
Significant Bit ) or LSB (Least Significant Bit)For example, a 4-bit register
requires four clock pulses to shift a bit from the input to the output. In parallel
shifting operation, all the data get shifted simultaneously during a single clock
pulse. Hence it is faster than the serial shifting method. These two methods
can be used to shift data into a register and out of the register.
Shift registers are classified into the following four types based on
how binary information is entered or shifted out. They are
The block diagrams of the four basic register types are shown in
Figure 6.19. The registers can be designed using flip flops (Morris Mano
1995). An n-bit shift register consists of n-flip flops and the required gates to
control the shift operation.
This type of shift register accepts data serially, i.e. 1 bit at a time on
a single input line. It produces the stored information on its single output also
in serial form. Delay data by one clock time for each stage. It will store a bit
of data for each register. Data may be shifted left using shift left register or
shifted right using shift right register.
A shift right register can be built using JK flip flops or D flip flops
as shown in Figure 6.20 and Figure 6.21 respectively. A JK flip flop based
shift register requires connection of both J and K inputs. Input data are
connected to the J and K inputs of the rightmost (lowest order) flip flop. To
input a 1, i.e., J = 1 and K = 0; to input a 0, a 0 at J input, i.e., J = 0 and K = 1,
should be applied. When a clock pulse is applied, the data will be shifted bit
by bit to the right.
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In the shift register using D flip flops; D input of the leftmost flip
flop is used as a serial input line. To input data 1, one should apply a 1 at D
input and to input data 0, a 0 at the D input should be applied.
For example, consider that all stages are reset and a steady logical 1
is applied at the serial input line connected to stage A. A 1 is applied at the
serial input line i.e., at D input of the first flip flop (right most). When the first
clock pulse is applied, flip flop A is SET, thus storing the 1. Next a 1 is
applied to the serial input, making D=1 for flip flop A and D=1 for flip flop B
because D input of B is connected to the QA output.
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When second clock pulse occurs, the 1 on the data input is shifted
to flip flop A and 1 in flip flop A is shifted to flip flop B. The next 1 in the
binary number is now applied at the serial line and a clock pulse is applied.
This 1 is entered into flip flop A and the 1stored in flip flop A is shifted to flip
flop B and the 1stored in flip flop B is shifted to flip flop C. This completes
the serial entry of the 3-bit binary number into the shift register. The data in
each stage after each of the three shift pulses is shown in Table 6.6. The
logical-1 input enters into stage A and then shifts right to stage C after 3clock
pulses. This is graphically explained in Figure 6.22.
For a JK FF, the data bit to be shifted into the flip flop must be
present at the J and K inputs when the clock transition from low to high
occurs. Since the data bit is either a 1 or a 0, there are two cases:1. To shift a 0
into the FF, J=0 and K=1and 2. To shift a 1 into the FF, J=1 and K=0.
The shift right register is constructed by using 3 flip flops (JK flip
flops or D flip flops).The flip flops are designed by using majority gates as
explained in previous section. The shift register is implemented by QCA cells
using flip flops implementation in section 6.2. It is a 3 bit shift register hence
3 flip flops are used in the design.
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In the JK flip flop design as shown in Figure 6.23, the shift register
is constructed by using 218 cells, with an area of 267,480 nm2 . The design of
each flip flop involves 4 clocking zones i.e, one clock cycle. Hence input-
output delay for the shift register design required 3 clock cycles. In the shift
register using D flip flop as shown Figure6.24, design involves only 31 cells
and delay of 3 clock cycles. The area required for this QCA design is 31,640
nm2 .
Figure 6.23 Layout SISO Shift right register using JK flip flop
Figure 6.24 Layout SISO Shift right register using D flip flop
A shift left register can be built using JK flip flops and D flip flops
as shown in Figure 6.25 and Figure 6.26 respectively. The clock pulse is
applied to all the flip flops simultaneously. When the shift or clock pulse
occurs, each flip flop is set or reset according to the data at the respective flip
flop input. Thus, the input data bit at serial input line is entered into stage A
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by the first clock pulse. At the same time, the data of stage A is shifted into
stage B and so on for the following stages. For each shift pulse, data stored in
the register stage shifts to the left by one stage. New data is entered in to stage
A, whereas the data present in stage C are shifted out (to the left) for use by
some other shift register or other building block of digital system.
Figure 6.25 Schematic of SISO Shift left register using D flip flop
Figure 6.26 Schematic of SISO Shift left register using JK flip flop
For example, consider that all stages are reset and a steady logical 1
is applied at the serial input line connected to stage A. The data in each stage
after each of the three shift pulses is shown in Table 6.7. The logical 1 input
enters into stage A and then shifts left to stage C after 3clock pulses.
Figure 6.27 Layout SISO Shift left register using JK flip flop
Figure 6.28 Layout SISO Shift left register using D flip flop
Figure 6.29 Schematic of SISO Shift right register using D flip flop
Figure 6.30 Schematic of SIPO Shift right register using JK flip flop
The shift register can be built by QCA cells using JK flip flops and
D flip flops are shown in Figure 6.31 to Figure 6.34.The SIPO shift registers
are implemented by QCA cells in both directions of data shifting. It consists
of one serial input S through which the data is entered in to the register
serially. The outputs A, B and C are taken from the flip flops in parallel. It is a
3 bit shift register hence 3 flip flops are used in the design.
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Figure 6.31 Layout of SIPO Shift right register using JK flip flop
Figure 6.32 Layout of SIPO Shift left register using JK flip flop
Figure 6.33 Layout of SIPO Shift right register using D flip flop
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Figure 6.34 Layout of SIPO Shift left register using D flip flop
Delay
Shift Register Complexity Area
(clock cycles)
SISO (D FF) 31 cells 565nm x 56nm 3
SIPO(D FF) 37 cells 565nm x 56nm 3
SISO/SIPO (JK FF) 218 cells 743nm x 360nm 3
the output from the previous flip-flop which limits its speed of operation. The
settling time in asynchronous counters, is the cumulative sum of the
individual settling times of flip-flops. It is also called a serial counter. In
synchronous counters, the speed limitation of ripple counter is overcome by
applying clock pulses simultaneously to all the flip flops which leads to the
settling time of the counter being equal to the propagation delay of a single
flip-flop. Hence synchronous counters also are also called parallel counters.
Single mode counters operate in single mode, i.e., it counts either in the Up
mode or in the DOWN mode, whereas multimode counters operate in both
UP and DOWN modes. Modulus counters are defined based on the number of
states they are capable of counting. For example, a MOD 10 counter has 10
states.
In this thesis, the 4-bit ring and Johnson counters are designed
using D flip flops. The 3-bit up counter is designed using JK flip flops which
counts upward from 0 to 7. The performance analyses of those circuits are
compared according to the complexity, area, and number of clock cycles.
A ring counter requires more flip-flops than a binary counter for the
same MOD number. For example, a MOD-8 ring counter requires 8 flip-flops
while a MOD-8 binary counter only requires 3 (23 = 8). So if a ring counter is
less efficient in the use of flip-flops than a binary counter, why do we still
need ring counters? One main reason is because ring counters are much easier
to decode. In fact, ring counters can be decoded without the use of logic gates.
The decoding signal is obtained at the output of its corresponding flip-flop.
Mehdi Askari et al (2008) have designed ring counter using QCA cells.
For the ring counter to operate properly, it must start with only one
flip-flop in the 1 state and all the others at 0. Since it is not possible to expect
the counter to come up to this state when power is first applied to the circuit,
it is necessary to preset the counter to the required starting state before the
clock pulses are applied. One way to do this is to apply a pulse to the
PRESET input of one of the flip-flops and the CLEAR inputs of all the others.
This will place a single 1 in the ring counter.
The 4-bit QCA ring counter design is shown in Figure 6.36. Every
different subsequent four clock zones is repeated alternatively and operates as
a D-FF, i.e., the clocked binary wire operates as a D FF. It is necessary that
D-FF3 output shift to D-FF0 after every clock cycle. So, feedback path only
includes a complete clock cycle.
There is a majority gate at the circuit input. Since one of its inputs
has logic “1”, majority gate is operated as a logic OR function. The “set”
input, for the purpose of the initial turn on the circuit has been connected to
the first flip-flop. The total number of cells required to implement a ring
counter is 82, with an area of 84000 nm2. This is achieved by using cell
minimization techniques.
Shift Pulse Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
The Johnson counter works in the following way: Take the initial
state of the counter to be 0000. On the first clock pulse, the inverse of the last
flip-flop will be fed into the first flip-flop, producing the state 1000. On the
second clock pulse, since the last flip-flop is still at level 0, another 1 will be
fed into the first flip-flop, giving the state 1100. On the third clock pulse, the
state 1110 is produced and on the fourth clock pulse, the state 1111 is
produced. On the fifth clock pulse, the inverse of the last flip-flop, now a 0,
will be shifted to the first flip-flop, giving the state 0111. On the sixth and
seventh clock pulse, using the same reasoning, we will get the state’s 0011
and 0001. On the ninth clock pulse, we will get the states 0000, which is the
initial state again. Hence, this Johnson counter has sixth distinct states: 0000,
1000, 1100, 1110, 1111,0111, 0011 and 0001, and the sequence is repeated so
long as there is input pulse. Thus this is a MOD-8 Johnson counter.
comparing with the binary counter using the speed up technique discussed
above. The reason for this is that for each state, two of the N flip-flops used
will be in a unique combination of states.
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
In this counter, the clock inputs of all the flip flops are connected
together so that the input clock signal is applied simultaneously to each flip
flop. Only the J and K inputs of FF1 is permanently connected to +1 while the
J and K inputs of the other flip flops are driven by some combination of flip
flop outputs. The J and K inputs of FF2 is connected with (A ) output of
FF1; the J and K inputs of FF3 is connected with AND operated output of A
and B.
majority gate logic, clock 2 is used for finding majority logic and clock 3 is
used to compute output. The output is available at clock 0 again.
6.5 CONCLUSION
In this chapter the different flip flops have been designed using
majority gates. The layouts and functionality checks were done using
QCADesigner and the designs are compared according to the complexity, area
and number of clock cycles. The operations of these circuits have been verified
according to the truth table. The proposed layouts are significantly smaller
than the same circuits using standard CMOS technology as well as the
existing circuits in QCA. The different types of shift registers and counters
have been designed and analyzed with the help of proposed D and JK flip
flops. It is shown that clocking requirements, number of zones, as well as the
underlying CMOS circuitry complexity are significantly reduced compared
with previous QCA circuits.