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CSE 577 Spring 2011

Current Source & Bias Circuits

Insoo Kim, Kyusun Choi


Mixed Signal CHIP Design Lab.
Department of Computer Science & Engineering
The Pennsylvania State University
Introduction
 Required Features of Current Source
 High Rout
 Wide Operation Range
 Constant Current Source
 Low PVT (Process, Voltage, Temperature) Sensitivity

 Required Features of Bias Circuit


 Low Rout
 Low PVT Sensitivity

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Current Source

• Basic Current Source


• Wilson Current Mirror
• Cascode Current Mirror
Ideal vs. Actual Current Source

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Simple NMOS Current Source

What’s the bad feature of this?

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Cascode Current Source

What’s the bad feature of this?

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Basic Current Mirror

What’s the bad feature of this?

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Wilson Current Mirror

g m1 (W / L)1
• I out = I ref ⋅ = I ref ⋅
g m2 (W / L) 2

What’s the drawback of this circuit?

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Cascode Current Mirror

But, it still has limited output swing problem.

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Wide Swing Cascode Current Mirror

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Bias Circuits

• Self Bias Circuits


• PTAT Bias Circuits
• Band gap Reference
Power Supply Dependency of Current Source

Consideration Factors
- VDD
- Channel Length Modulation
- Transistor Mismatch

How do we generate Iref independent


of the supply voltage?

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Self Biasing Circuit

What’s role of Rs?

What’s the advantage of these circuits?


What’s the problem of these circuits?
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Improved Self Biasing Circuit

Improved Circuit with Start-up Circuit


Improved Circuit eliminating * This Circuit is practical only if
Body Effect

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A Simple Temperature Compensation Concept

0℃

VDD VDD
90℃

M1(Ids)
Negative TC Positive TC

vr0 ZTC
v (Zero Temperature Coefficient)

M1

R1 M1(Vgs)
1. R1 is a conductor which has positive TC
2. M1 has negative TC below ZTC point
(Semiconductor)
3. If we control Vr0 below ZTC point, Vr0 become less
Self Bias Circuit sensitive to temperature due to opposite TC of M1
and R1

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Case Study (I) – Self Bias Circuit in DRAM

starter

ⓐ ⓑ

For Temp.
Compensation pmos diode
Vext

vref

What’s the drawback of these circuits?


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Case Study (II) – Self Bias Circuit in DRAM
Why does this circuit need the voltage buffer?
Why are PMOS current mirrors stacked in the reference bias circuit?
Voltage Buffer vr1

starter For Temp.
Compensation

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VBE Referenced CMOS Self-
Self-bias Circuit

How do we fabricate BJT in CMOS


* Temperature Sensitivity ~ - 4000 ppm/C
Process Technology?

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Realization of pnp BJT in CMOS Technology

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Vth Referenced CMOS Self-
Self-Bias Circuit

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Thermal Voltage Referenced CMOS Self-
Self-Bias Circuit

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Thermal Voltage Referenced CMOS Self-
Self-Bias Circuit

* Temp.
Sensitivity ~
+3300 ppm/C

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CMOS Band gap Reference

What’s the problem?

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(cont’d) CMOS Band gap Reference

Actual Implementation of CMOS Band Gap Reference

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Actual Implementation of CMOS Band gap Reference

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Design Lab. – Self Bias Circuit with Temp. Compensation

 Schematics

* AMIS 0.5um Tech

(a) Basic Schematic (b) actual implementation

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Design Lab. – Self Bias Circuit with Temp. Compensation

 Simulation Results

VDD
Vr0b

Vr0 (a)

Vr0 (b)

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Design Lab. – Self Bias Circuit with Temp. Compensation

 Simulation Results – Temp. Compensation


90C
25C 90C
25C

(a) (a)
-10C -10C

(b) (b)

Vr0 Current

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Design Lab. – Self Bias Circuit with Temp. Compensation

 Zero Temperature Coefficient Point

90C

25C

-10C
0.82V

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References
 Joongho Choi, “CMOS analog IC Design,” IDEC Lecture
Note, Mar. 1999.
 B. Razavi, “Design of Analog CMOS Integrated Circuits,”
McGraw-Hill, 2001.
 Hongjun Park, “CMOS Analog Integrated Circuits
Design,” Sigma Press, 1999.

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