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DOI 10.1007/s10470-012-9951-3
Abstract A new four quadrant voltage mode bulk input networks [1, 2], convolver in sensor applications [3]. Con-
analog multiplier is presented .The proposed multiplier is sidering the importance of multiplier and its applications, it
designed to operate in weak inversion. Multiplication is is challenging to design a multiplier suitable for low voltage
done by driving the bulk terminals of the MOS devices and low power operations.
which offers linear dynamic range of ±80 mV. The sim- Analog multiplier design was first reported in the work of
ulation shows, it has a linearity error of 5.6 %, THD of Gilbert [4] which was implemented using BJT. Since then
nearly 5 % and -3 dB band width of 221 kHz. Total number of works has been reported specially in CMOS
power consumption is very low i.e. 714 nW. The circuit technology based on (i) mode of input i.e. current mode and
operates at a supply voltage of 0.5 V and is designed using voltage mode and (ii) the region of the operation of MOS
180 nm CMOS technology. It is suitable for low power device. If we consider the designs based on strong inversion
bioelectronics and neural applications. regime, the voltage mode multipliers in saturation can be
found in [5, 6], in linear region can be found in [7, 8], and
Keywords Analog multiplier Bulk-input MOS circuits current mode multipliers can be found [9, 10]. For saturated
Four quadrant multiplication Low voltage and low power weak inversion regime, voltage mode multipliers are repor-
analog IC design MOS transistor Weak inversion ted in [11–13] and current mode multipliers in [14]. The
designs based on weak inversion region mostly followed the
Gilbert cell topology and modified Gilbert cell [15] for
1 Introduction voltage mode operation. The designs in weak inversion
suffered from poor dynamic range, limited voltage swing
Analog IC design has been revolutionized by the low voltage (few hundred mV) and limited band width. For low voltage
and low power design methodology especially when it and low power applications operating devices in weak
comes to portable, battery operated systems. In analog signal inversion is quite advantageous [16, 17]. One of the best
processing, four-quadrant-multiplication is one of the features being very low VDS:sat which nearly four times the
important operations performed on signals. It is used in a thermal voltage [18, 19].
number of applications including modulator, doublers, Usually the gate of the MOS device is used for control-
adaptive filters in communication circuit, in phase detection ling the inversion level, with the bulk terminal is tied to its
in Phase Locked Loop, as a mixer in a front-end receiver and own well. But this bulk terminal can be used to decrease or
synaptic multiplier in hardware implementation of neural increase the effective inversion layer charge by applying
some potential to it with respect to source, although it
comes at the cost of the mismatch in drain to source current
A. Panigrahi (&) P. K. Paul
IDS . If we consider a pMOS device, then effective inversion
Department of Electronics and Communication Engineering,
National Institute of Technology, Silchar, Assam, India layer can be increased by applying a negative potential to
e-mail: antaryami.mt.er09@gmail.com the n-type bulk with respect to p-type source which holds an
P. K. Paul exponential relationship with IDS . The exponential relation
e-mail: pkp059@gmail.com between IDS , VGS and VBS has been exploited to implement
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Analog Integr Circ Sig Process
2 Operation of the proposed multiplier is used for applying differential input and each device is
operated in saturated weak inversion. If two devices are
2.1 MOS in weak inversion with active bulk terminal biased in weak inversion in saturation (VDS 4UT) with
an initial assumption of matched devices, (mismatch is
Considering a p-MOS device operated in weak inversion considered in Sect. 3) the current expressions for the circuit
the drain to source current (ignoring the early effect shown in Fig. 1 can be written based on the Eq. (1) as;
VDS VE) can be given by [23, 24] Vgs1 ðg1ÞVbs1
Vgs ðg1ÞVbs h Vds i IDS1 ¼ ID0 e gUT e ð3Þ
gUT
kT
IDS2 ¼ ID0 e gUT e gUT
ð4Þ
and UT ¼ q . g is the subthreshold slope parameter which
ðg1ÞðVbs2 Vbs1 Þ
0
varies between 1 and 2 [18, 23], and b ¼ l Cox WL IDS2 ¼ IBIAS e gUT
ð5Þ
VE is the Early voltage which is nearly 10 V. As we have to Assuming Vbs2 ; Vbs1 are very small i.e jVbs2 j; jVbs1 j
operate the device in weak inversion so each pMOS has gUT
ðg1Þ i.e. taking g ¼ 1:2, it comes out to be nearly 155 mV.
been designed to operate below the VTH where IDS IS.
Ignoring the second order effects, for a given size of the This helps us to get more dynamic range as compared to
gate input multiplier circuits [11, 15]. Equation (5) can also
device inversion coefficient IC ¼ IIDSS should be less than be written as;
0.1 [19, 24, 25]. The trans-conductance parameter for the ðg1ÞVbs2 ðg1ÞVbs1
bulk input device is represented as [17, 25]; IDS2 ¼ IBIAS e gUT
e gUT
ð6Þ
oIDS
gmb ¼ oV bs
¼ ðg1Þ
gUT IDS . Since we are using bulk terminal, It can be expanded with the help of Taylor’s series for
threshold voltage for the MOS device will be affected, " #
which can be given by the expression [23]; ðg 1ÞVbs2 1 ðg 1ÞVbs2 2
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffi ¼ IBIAS 1 þ . . .
gUT 2! gUT
VTH ¼ VTH0 þ c jVSB þ /0 j j/0 j ð2Þ " #
ðg 1ÞVbs1 1 ðg 1ÞVbs1 2
VTH0 represents the threshold voltage when VSB is zero, 1þ þ ...
gUT 2! gUT
/0 ¼ 2/F þ r/; r/ is nearly 6UT at room temperature
and c is the body effect parameter which depends on the ð7Þ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
process and given by c ¼ 2 qC0 2si ND , where ND the The exponential i.e. Eq. (6) and its approximated series
ox
0
donor concentration per unit volume and Cox is the oxide expansion i.e. Eq. (7) will follow closely each other only
ðg1ÞVbs2;1
capacitance per unit area of the device in a given process. when gUT 1. To quantify the above fact the
two expressions and the difference between these two are
2.2 Exponential approximation circuit
plotted against ðg1ÞðVgUbs2
T
Vbs1Þ
which is shown in Figs. 2 and 3
The exponential function can be obtained by using a bulk respectively. The error between these two is less than .01 i.e.
ðg1ÞVbs2;1
input current mirror where gate is used for biasing and bulk 1 % when gUT \0:2:
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Analog Integr Circ Sig Process
" #
ðg 1ÞVin2 1 ðg 1ÞVin2 2
ffi IBIAS 1 þ þ
gUT 2! gUT
" # ð9Þ
ðg 1ÞVin1 1 ðg 1ÞVin1 2
1þ þ
gUT 2! gUT
" #
ðg 1ÞVin2 1 ðg 1ÞVin2 2
ffi IBIAS 1 þ þ
gUT 2! gUT ð10Þ
" #
ðg 1ÞVin1 1 ðg 1ÞVin1 2
1 þ
gUT 2! gUT
Fig. 2 Error between exponential and its approximation
ðg1ÞðV6 V5 Þ ðg1ÞðVin2 þVin1 Þ
IDS6 ¼ IBIAS e gUT
¼ IBIAS e gUT
" #
ðg 1ÞVin2 1 ðg 1ÞVin2 2
ffi IBIAS 1 þ
gUT 2! gUT ð11Þ
" #
ðg 1ÞVin1 1 ðg 1ÞVin1 2
1 þ
gUT 2! gUT
ðg1ÞðV8 V7 Þ ðg1ÞðVin2 Vin1 Þ
IDS8 ¼ IBIAS e" gUT
¼ IBIAS e gUT
#
ðg 1ÞVin2 1 ðg 1ÞVin2 2
ffi IBIAS 1 þ
gUT 2! gUT
" #
ðg 1ÞVin1 1 ðg 1ÞVin1 2
1þ þ ð12Þ
gUT 2! gUT
V4 ; V5 ; V6 ; V7 ; V8 , the input voltages can be written of the been biased in the weak inversion the total power is quite
form similar to [11]; V1 ¼ V7 ¼ Vb þ Vin1 ; V2 ¼ V4 ¼ Vb low.
Vin2 ; V3 ¼ V5 ¼ Vb Vin1 ; V6 ¼ V8 ¼ Vb þ Vin2 . The cur-
rent expression for IDS2 ; IDS4 ; IDS6 ; IDS8 can be written as
follows; 3 Formulation of mismatch for the multiplier
ðg1ÞðV2 V1 Þ ðg1ÞðVin2 þVin1 Þ
IDS2 ¼ IBIAS e ¼ IBIAS e
gUT gUT
ð8Þ The whole mismatch in the proposed circuit can be ana-
Neglecting the higher order terms Eq. (8) can be lyzed by considering variations due to the process depen-
approximated as; dent parameters and the mismatch in the bias voltages and
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Analog Integr Circ Sig Process
be considered in the parameter ID0 which can include b IDS8 ¼ q8 IBIAS e gUT
ð19Þ
mismatch (in weak inversion its effect can be neglected Now the sum of IDS2 and IDS6 can be written as;
[18]), VTH mismatch which exponentially vary the current
ðg1ÞðVin2 þVin1 Þ ðg1ÞðVin2 þVin1 Þ
[26] and g due to VBS (ignoring the effect of g in the ¼ IBIAS q þ Dq2;6 e gUT
e gUT
ð20Þ
exponential terms). These mismatches can be included by
taking a term ID0 ð1 þ DID0 Þ and the bias mismatch can be In a same way IDS4 and IDS8 can be summed up to form,
included at later stage simply writing IBIAS þ DIBIAS to the
ðg1ÞðVin2 Vin1 Þ ðg1ÞðVin2 Vin1 Þ
final current expression involving mismatch. The mismatch ¼ IBIAS q þ Dq4;8 e gUT
e gUT
ð21Þ
in VDS for each transistor pair can also be included for each
current expression i.e. Eqs. (8), (10–12) by introducing a From Eq. (4) Iout can be expanded with Taylor’s series
factor di;j where i and j represents transistor pair. From and final current expression can be written as;
Eq. (1) it can be written as;
ð g 1Þ 2
ðg1ÞVbs2;1 Iout ffi IBIAS q 4 Vin2 Vin1 þ kIBIAS ð22Þ
IDS2 ¼ IBIAS n2:1 e gUT
d2;1 ð15Þ gUT
where k accounts for the mismatch expressions due to
where n2:1 ¼ ðð1þDI D02 Þ
1þDID01 Þ the term that incorporates the
multiplied terms with Dq. Equation (22) gives the
mismatch for ID0 between two devices i.e. MP1 and MP2 approximated expression for the process dependent mis-
having variation of DID01 ; DID02 respectively. And Vbs2;1 ¼ match. If bias dependent mismatch is to be included then,
h Vds2 i h Vds1 i
Vbs2 Vbs1 and d2;1 ¼ 1 e gUT = 1 e gUT takes care IBIAS can be simply replaced by IBIAS ð1 þ DIBIAS Þ. DIBIAS
of the mismatch due to Vds between the two devices. The accounts for the variation due to bias current between four
Eq. (15) can be rewritten in the form of input voltages different pairs of the exponential approximation circuits.
[with reference to Eq. (8)] and a single mismatch term q The bias dependent mismatch can be significantly reduced
that gives rise to equation of the form; by providing proper biasing circuitry. To test the mismatch
effects on the circuit, Monte Carlo Simulation is performed
ðg1ÞðVin2 þVin1 Þ
IDS2 ¼ q2 IBIAS e gUT
ð16Þ for 100 runs with 30 % variation between the devices; the
result of DC error is limited within 5 %. It is also per-
where q2 ¼ n2;1 d2;1 and similar expression for other formed with mismatch in IBIAS ; the error comes within 5 %.
current equations can be written as [with reference to Eqs.
(10–12) for IDS4 , IDS6 , and IDS8 respectively];
ðg1ÞðVin2 Vin1 Þ 4 Results
IDS4 ¼ q4 IBIAS e gUT
ð17Þ
ðg1ÞðVin2 þVin1 Þ To test the performance of the proposed multiplier, 0.18 lm
IDS6 ¼ q6 IBIAS e gUT
ð18Þ 1P6M CMOS technology has been used. It has threshold
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Analog Integr Circ Sig Process
VDD 0.5 V
Vb 400 mV
IBIAS 300 nA
Input dynamic 60 mV (Vin1), 80 mV (Vin2)
range
-3 dB bandwidth 221 kHz at C = 10 pF, 50 mV DC, 80 mV,
10 kHz
THD % 5.82 (at 50 mV DC, 80 mV, 1 kHz)
5.76 (at 50 mV DC, 80 mV, 10 kHz)
3.13 (at 50 mV DC, 80 mV, 100 kHz)
7.79 (at 80 mV, 1 kHz, 50 mV DC)
7.71 (at 80 mV, 10 kHz, 50 mV DC)
Fig. 5 DC characteristics Vout - Vin2 4.11 (at 80 mV, 100 kHz, 50 mV DC)
Linearity error 5.6 %
Power 714.3 nW
Process used 0.18 lm 1P6M CMOS
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Analog Integr Circ Sig Process
5 Conclusion
References
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Analog Integr Circ Sig Process
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