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dn y dn−1 y dy
n
(t) + α n−1 n−1
(t) + . . . + α1 (t) + α0 y(t) = 0
dt dt dt
Given n initial conditions of the form,
dy dn−1 y
y(t0 ) = a0 , (t0 ) = a1 , . . . , n−1 (t0 ) = an−1 ,
dt dt
there exists a unique solution (say, f ).
Prove that φ1 (x) = φ2 (x) by showing that both functions satisfy the following differential equation:
df
(x) = f (x) with f (0) = 1
dx
Side note: Assume 00 = 1.
Solution:
φ1 (x = 0) = e0 = 1
dφ1
(x) = ex
dx
So φ1 satisfies the conditions.
00 ∞
0n
φ2 (x = 0) = +∑
1 n=1 n!
d ∞ ∞
df
∑ f (x) = ∑ (x)
dx n=0 n=0 dx
df d xn nxn−1
(x) = ( ) =
dx dx n! n!
dφ2 ∞
nx n−1
(x) = ∑
dx n=0 n!
dφ2 0x−1 ∞
nxn−1
(x) = +∑
dx 1 n=1 n!
dφ2 ∞
nxn−1
(x) = ∑
dx n=1 n!
dφ2 ∞
xn−1
(x) = ∑
dx n=1 (n − 1)!
Both φ1 and φ2 meet the conditions, therefore they must be the same function
d2 f df
2
(x) = − f (x) with f (0) = 1, (0) = 0
dx dx
Solution:
Initial conditions:
cos(0) = cos(−0) = 1
− sin(0) = 0
sin(−0) = 0
df
Both functions satisfy dx (0) =0
d 2 φ1
(x) = − cos(x) = −φ1 (x)
dx2
d 2 φ2
(x) = − cos(−x) = −φ2 (x)
dx2
Both functions satisfy all three conditions, so φ1 (x) = φ2 (x)
A Y
In general, a Boolean-formula circuit has an nMOS pull-down network to connect the output to 0 (GND)
and a pMOS pull-up network to connect the output to 1 (VDD ). The pull-up and pull-down networks in the
inverter example each consist of a single transistor.
In this problem, we will ask you to design pull-up networks when pull-down networks are given.
(a) The pull-down network of the Boolean formula (a 2-input NAND gate), Y = (A ∗ B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.
Solution:
From De Morgan’s laws, we have Y = A + B, which means that when A = 0 or B = 0, Y should be
pulled up to 1. Therefore we connect two pMOS transistors in parallel in the pull-up network.
(b) The pull-down network of the Boolean formula (a 2-input NOR gate), Y = (A + B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.
A B
Solution:
From De Morgan’s laws, we have Y = A ∗ B, which means that when A = 0 and B = 0, Y should be
pulled up to 1. Therefore we connect two pMOS transistors in series in the pull-up network.
A B
(c) The pull-down network of the Boolean formula, Y = (A ∗ B) +C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.
A
C
B
Solution:
Let Z be Z = A + B. From De Morgan’s laws, we have Y = A + B ∗ C = Z ∗ C, which means that
when Z = 1 and C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in parallel
as in part (a). Then we connect the two pMOS transistors of Z and the one pMOS transistor of C in
series in the pull-up network.
A
C
B
(d) The pull-down network of the Boolean formula, Y = (A + B) ∗C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.
A B
Solution:
Let Z be Z = A ∗ B. From De Morgan’s laws, we have Y = A ∗ B + C = Z + C, which means that
when Z = 1 or C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in series as in
part (b). Then we connect the two pMOS transistors of Z and the one pMOS transistor of C in parallel
in the pull-up network.
B C
A B
(e) You have designed four pull-up networks. What can you conclude about the rules for designing pull-up
networks when pull-down networks are given?
Solution:
The pull-up network is the complement of the pull-down network. Series connections of transistors
are changed to parallel connections, and vice versa.
Recall that the reason that we design things this way is to prevent power from being burned unneces-
sarily when the logical state is not changing. With this complementary configuration, either the top or
bottom network will be an open circuit. There will never be a path connecting VDD to ground.
(f) For the circuit below, write the truth table for inputs A and B with output Y. What boolean operation
is this?
Note some of the gate voltages are Ā and B̄
A B
A Ā
B B̄
Solution: In CMOS, if the gate of an nMOS is 1, the switch is closed and acts as a resistor. If the
gate voltage is 0, then it acts as an open. The opposite is true for pMOS.
To get the truth table, draw the circuit for each input case and see whether the output is connected to
ground or VDD
This is what the circuit should look like for A=0 B=0:
Y is connected to ground through resistors, so for the input combination A=0 B=0, Y=0. Repeat this
for the 3 other cases and you will get the following truth table:
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
This circuit is an XOR gate (A ⊕ B)
3. RC Circuit
Consider the circuit below, assume that when t ≤ 0, the capacitor has no charge stored (Vc (t = 0) = 0). At
t = 0, the switch closes. Assume Vs = 15 V, R = 500Ω, and C = 100µF.
(a) What are the boundary conditions for Ic (t) (i.e. what is Ic (t = 0) and Ic (t → ∞)?)
+ V Vc (t)
− s C
No charge is on the capacitor before time t = 0. Using q = VC, we know that Vc = 0V before t = 0.
Vc +VR −Vs = 0
Vc (t = 0) = 0
which means
VR (t = 0) = Vs
Ic (t → ∞) = 0A
R
(b) Use KVL and the relationship between charge and current (q = Idt) to find the first order differential
equation in terms of the current through the capacitor, Ic . Assume dV
dt = 0 (Hint: you will need to take
s
V1 +VR −Vs = 0
IR = Ic
Ic dIc dVs
+R − =0
C dt dt
dVs
dt = 0, so we end up with:
Ic dIc
+R =0
C dt
dIc Ic
=−
dt RC
Since this is a first order differential equation, λ is equal to the coefficient of the Ic term.
1
λ =−
RC
(d) Using the eigenvalue and boundary conditions found in previous parts, find an expression for Ic (t) in
terms of Vs , R and C
Solution:
dy
= Ay
dt
is
y(t) = Keλt
Where K is a constant and λ is the eigenvalue of the equation. To find K, we can plug in our boundary
condition at t=0
0 Vs
Ic (t = 0) = Ke− RC =
R
(e) What order of magnitude of time (nanoseconds, milliseconds, 10’s of seconds, etc.) does this circuit
settle (Ic is <5% of it’s initial value)?
Solution:
(f) Give 2 ways to reduce the settling time of the circuit if we are allowed to change one component in the
circuit.
Solution: to reduce settling time, reduce τ. We can achieve this by
1) Lowering the value of R
2) Lowering the value of C
Notice how the value of Vs does not change the settling time
(g) Sketch the current vs time plot of Ic (t) Make sure to label Ic (t) at t = 0, t = τ, t = 2τ, and t = 3τ
Solution:
Vs − t
Ic (t) = e RC
R
Ic (t) = 0.03e−20t
Ic (0) = 0.03A
Ic (τ) = 11.0mA
Ic (2τ) = 4.06mA
Ic (3τ) = 1.49mA
(a) For starters, what are the on-off conditions of the two switches? Please draw the RC circuit modeling
this inverter.
Vin Vout
GND
Solution:
VDD
RonP
Vin Vout
CL
RonN
GND
The upper switch is controlled by the voltage difference between gate (G) and source (S) voltages of
the pMOS. In this circuit, VG = Vin and VS = VDD . The on-condition for pMOS is VGS ≤ Vt p , where Vt p
is a negative number, around -0.4. Usually VDD is greater than |Vt p |. If VG = Vin = 0, VGS = VG −VS =
−VDD < Vt p , the switch will be on. If VG = Vin = VDD , for pMOS, VGS = VG −VS = 0 > Vt p , the switch
will be off.
The lower switch is controlled by the voltage difference between gate (G) and source (S) voltages of
the nMOS. In this circuit, VG = Vin and VS = GND. The on-condition for nMOS is VGS ≥ Vtn , where
Vtn is a positive number, around 0.4. If VG = Vin = VDD , VGS = VG −VS = VDD > Vtn , the switch will be
on. If VG = Vin = 0, for nMOS, VGS = VG −VS = 0 < Vtn , the switch will be off.
(b) Assume Vin = VDD for t < 0, and Vin = 0 for t ≥ 0. In other words, we are assuming the input to our
inverter can switch states infinitely fast (this is not true in real life, but gives us a good lower bound on
how fast an inverter can switch). How much energy does it take to fully charge CL ? Solution: When
Vin = VDD (for t < 0), nMOS is on, while pMOS is off. Vout is shorted to RonN , and there is no charge
on CL . Then when Vin becomes 0 for t ≥ 0, nMOS is off while pMOS is on. Vout is shorted to RonP ,
V2 h −t i∞ V 2
Z ∞
VDD R −tC
VDD × e onP L dt = DD × (−RonPCL ) e RonPCL = DD × (−RonPCL ) [0 − 1] = CL (VDD )2
0 RonP RonP 0 RonP
(c) Given the same condition as in (b), write down the differential equation that describes Vout (t) for t ≥ 0.
Solution: The current goes through the resistor RonP is the same as the current through CL . Therefore,
we could write down the differential equation as
dVout (VDD −Vout )
CL =
dt RonP
.
(d) What is the solution to this differential equation? Plot Vout (t) for t > 0.
Solution: We could decompose Vout into a steady state function (Vss ), and a transient function
(Vtransient ): Vout = Vss + Vtransient , such that dVdtout = dV
dt +
ss dVtransient
dt . The steady state value of Vout is
VDD (a constant), because in a long run, the capacitor behaves like an open circuit, while the resistor
behaves as a short circuit. That is, dVdtout = dVtransient
dt .
The initial state of Vtransient is −VDD , because the initial state of Vout = VDD + Vtransient is 0. Now we
could replace the variable Vout in the above differential equation with Vss +Vtransient and then keep only
the derivative of Vtransient at the left hand side, then we will get the following differential equation:
dVtransient (−Vtransient )
=
dt CL RonP
. The above differential equation looks like we apply some linear operator (derivative) to a function of
time, such that the derivative of this function is itself with a scalar. We are finding an eigen-function
of this linear operator! The solution to the differential equation should be in the form of Aest , where A
and s are some constants. Compare the desired form and the differential equation, we could conclude
−t
s = CL−1 s0
RonP . The initial state (t = 0) for Vtransient is Ae = A = −VDD , so Vtransient = −VDD × e
RonP CL
.
Finally, let’s put Vtransient and Vss together, we could get
−t
Vout (t) = VDD −VDD × e RonPCL
.
−t
Now let’s compute the time needed to reach Vout = VDD
2 : we need e
RonN CL
= 12 . Therefore t ≈ 0.69RonN CL =
0.69RCL .
(g) Now let’s consider the following scenario: there are N inverters on the chip in your cell phone. It takes
E Joules of energy to charge all of the inverters at once (from zero to VDD ). What is the value of CL ?
Solution: The energy required to charge one inverter is CL (VDD )2 , so to charge N inverters together,
we need E = CL (VDD )2 × N. That is, CL = N(VEDD )2 .
(h) Here we interpret a voltage V as logic "1" when V > VDD VDD
2 , and logic "0" when V < 2 . Let’s assume
the maximum frequency, f , at which an inverter can switch back and forth between logic "0" and
logic "1" at the output is the inverse of the propagation delay (i.e. we can only switch as fast as one
propagation delay). Find an expression that links f , CL , and R.
5. Digital-analog converter
A digital-analog converter (DAC) is a circuit for converting a digital representation of a number (binary)
into a corresponding analog voltage. In this problem, we will consider a DAC made out of resistors only
(resistive DAC) called the R-2R ladder. Here is the circuit for a 3-bit resistive DAC.
Let b0 , b1 , b2 = {0, 1} (that is, either 1 or 0), and let the voltage sources V0 = b0VDD , V1 = b1VDD , V2 = b2VDD ,
where VDD is the supply voltage.
As you may have noticed, (b2 , b1 , b0 ) represents a 3-bit binary (unsigned) number where each of bi is a
binary bit. We will now analyze how this converter functions.
V1 R V2 R
Vout
2R 2R 2R 2R
+ bV + +
− 0 DD − b1VDD − b2VDD
(e) Finally, solve for Vout in terms of VDD and the binary bits b2 , b1 , b0 .
Solution: From part (a)
b2VDD b1VDD b0VDD
+ + = Vout
2 4 8
(f) Explain how your results above show that the resistive DAC converts the 3-bit binary number (b2 , b1 , b0 )
to the output analog voltage VDD .
Solution: Every increment of 18 VDD on VDD represents an increment of 1 to the 3-bit binary number
(b2 b1 b0 )
For example, if Vout = 85 VDD , the input was 5 in binary (1 0 1)→ (b2 = 1 b1 = 0 b0 = 1).
Contributors:
• Siddharth Iyer.
• Yen-Sheng Ho.
• Kyle Tanghe.
• Yu-Yun Dai.
• Edward Wang.