Sequential Circuits (EE-5)

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ELECTRICAL ENGINEERING
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RK Kanodia
Ashish Murolia
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PREFACE
The 3rd edition of GATE Electrical Engineering has been revised exhaustively as per new GATE Syllabus. The book
has been completely revised in this edition, with the purpose not only of updating the material, but just as important,
making the book a better learning aid. This new edition is enriched by increasing the number of problems as well as
covering more topics of a subject. The book includes both the Multiple Choice Questions (MCQ) and Numerical Answer
Type (NAT) problems. Each problem is accompanied by a step-by-step and well-explained solution. To improve the
readability, the contents are represented with illustrative diagrams, standard notations, relatively consistent variable
naming and easy-to-understand explanations.
This new edition is the outcome of 10 successive years of compilation, revision & improvement of contents by
the authors and their team. In the past few years, a rumor was spread to defame the book that it has some errors.
After continuously reviewing each edition, we must say that the book is completely error-free from typos or any other
errors. Some of our friends and colleagues teaching in various GATE coachings also claimed that a few solutions in the
books are erroneous. We individually worked on those solutions and discussed them with some distinguish professors of
respective subjects. We must conclude that there is only a difference in method of solving which has been interpreted
as an Error by many readers. Also, the book has been thoroughly edited to remove many errors (mostly typos) which
had crept into the previous editions.
The few significant changes in this edition are as follows:

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SYLLABUS
Section 1: Engineering Mathematics

Linear Algebra: Matrix Algebra, Systems of linear equations, Eigenvalues, Eigenvectors.
Calculus: Mean value theorems, Theorems of integral calculus, Evaluation of definite and improper integrals, Partial
Derivatives, Maxima and minima, Multiple integrals, Fourier series, Vector identities, Directional derivatives, Line
integral, Surface integral, Volume integral, Stokes’s theorem, Gauss’s theorem, Green’s theorem.
Differential equations: First order equations (linear and nonlinear), Higher order linear differential equations with
constant coefficients, Method of variation of parameters, Cauchy’s equation, Euler’s equation, Initial and boundary
value problems, Partial Differential Equations, Method of separation of variables.
Complex variables: Analytic functions, Cauchy’s integral theorem, Cauchy’s integral formula, Taylor series, Laurent
series, Residue theorem, Solution integrals.
Probability and Statistics: Sampling theorems, Conditional probability, Mean, Median, Mode, Standard Deviation,
Random variables, Discrete and Continuous distributions, Poisson distribution, Normal distribution, Binomial
distribution, Correlation analysis, Regression analysis.
Numerical Methods: Solutions of nonlinear algebraic equations, Single and Multi-step methods for differential equations.
Transform Theory: Fourier Transform, Laplace Transform, z-Transform.
Section 2: Electric Circuits

Network graph, KCL, KVL, Node and Mesh analysis, Transient response of dc and ac networks, Sinusoidal steady-
state analysis, Resonance, Passive filters, Ideal current and voltage sources, Thevenin’s theorem, Norton’s theorem,
Superposition theorem, Maximum power transfer theorem, Two-port networks, Three phase circuits, Power and power
factor in ac circuits.
Section 3: Electromagnetic Fields

Coulomb’s Law, Electric Field Intensity, Electric Flux Density, Gauss’s Law, Divergence, Electric field and potential due
to point, line, plane and spherical charge distributions, Effect of dielectric medium, Capacitance of simple configurations,
Biot-Savart’s law, Ampere’s law, Curl, Faraday’s law, Lorentz force, Inductance, Magnetomotive force, Reluctance,
Magnetic circuits,Self and Mutual inductance of simple configurations.
Section 4: Signals and Systems

Representation of continuous and discrete-time signals, Shifting and scaling operations, Linear Time Invariant and
Causal systems, Fourier series representation of continuous periodic signals, Sampling theorem, Applications of Fourier
Transform, Laplace Transform and z-Transform.
Section 5: Electrical Machines
Single phase transformer: equivalent circuit, phasor diagram, open circuit and short circuit tests, regulation and efficiency;
Three phase transformers: connections, parallel operation; Auto-transformer, Electromechanical energy conversion
principles, DC machines: separately excited, series and shunt, motoring and generating mode of operation and their
characteristics, starting and speed control of dc motors; Three phase induction motors: principle of operation, types,
performance, torque-speed characteristics, no-load and blocked rotor tests, equivalent circuit, starting and speed control;
Operating principle of single phase induction motors; Synchronous machines: cylindrical and salient pole machines,
performance, regulation and parallel operation of generators, starting of synchronous motor, characteristics; Types of
losses and efficiency calculations of electric machines.
Section 6: Power Systems

Power generation concepts, ac and dc transmission concepts, Models and performance of transmission lines and cables,
Series and shunt compensation, Electric field distribution and insulators, Distribution systems, Per-unit quantities,
Bus admittance matrix, Gauss-Seidel and Newton-Raphson load flow methods, Voltage and Frequency control, Power
factor correction, Symmetrical components, Symmetrical and unsymmetrical fault analysis, Principles of over-current,
differential and distance protection; Circuit breakers, System stability concepts, Equal area criterion.
Section 7: Control Systems

Mathematical modeling and representation of systems, Feedback principle, transfer function, Block diagrams and Signal
flow graphs, Transient and Steady-state analysis of linear time invariant systems, Routh-Hurwitz and Nyquist criteria,
Bode plots, Root loci, Stability analysis, Lag, Lead and Lead-Lag compensators; P, PI and PID controllers; State space
model, State transition matrix.
Section 8: Electrical and Electronic Measurements

Bridges and Potentiometers, Measurement of voltage, current, power, energy and power factor; Instrument transformers,
Digital voltmeters and multimeters, Phase, Time and Frequency measurement; Oscilloscopes, Error analysis.
Section 9: Analog and Digital Electronics

Characteristics of diodes, BJT, MOSFET; Simple diode circuits: clipping, clamping, rectifiers; Amplifiers: Biasing,
Equivalent circuit and Frequency response; Oscillators and Feedback amplifiers; Operational amplifiers: Characteristics
and applications; Simple active filters, VCOs and Timers, Combinational and Sequential logic circuits, Multiplexer,
Demultiplexer, Schmitt trigger, Sample and hold circuits, A/D and D/A converters, 8085Microprocessor: Architecture,
Programming and Interfacing.
Section 10: Power Electronics

Characteristics of semiconductor power devices: Diode, Thyristor, Triac, GTO, MOSFET, IGBT; DC to DC conversion:
Buck, Boost and Buck-Boost converters; Single and three phase configuration of uncontrolled rectifiers, Line commutated
thyristor based converters, Bidirectional ac to dc voltage source converters, Issues of line current harmonics, Power factor,
Distortion factor of ac to dc converters, Single phase and three phase inverters, Sinusoidal pulse width modulation.
************
CONTENTS
ANALOG ELECTRONICS
CHAPTER 1 Diode Circuits 3-52

CHAPTER 2 BJT Biasing 53-104
CHAPTER 3 BJT Amplifiers 105-140
CHAPTER 4 FET Biasing 141-178
CHAPTER 5 FET Amplifiers 179-220
CHAPTER 6 Output Stages and Power Amplifiers 221-248
CHAPTER 7 Op-Amp Characteristics and Basic Circuits 249-288
CHAPTER 8 Op-Amp Application 289-338
CHAPTER 9 Active Filters 339-400
DIGITAL ELECTRONICS
CHAPTER 1 Number System and Codes 3-26

CHAPTER 2 Boolean Algebra and Logic Simplification 27-67
CHAPTER 3 The K-Map 69-88
CHAPTER 4 Combinational Circuits 89-116
CHAPTER 5 Sequential Circuits 117-138
CHAPTER 6 Logic Families 139-166
CHAPTER 7 Logic Families 167-188
CHAPTER 8 Microprocessors 189-208
POWER ELECTRONICS
CHAPTER 1 Power Semiconductor Devices 3-14

CHAPTER 2 Diode Circuits and Rectifiers 15-26
CHAPTER 3 Thyristor 27-44
CHAPTER 4 Phase Controlled Converters 45-68
CHAPTER 5 Choppers 69-84
CHAPTER 6 Inverters 85-102
CHAPTER 7 AC and DC Drives 103-112
**********
ALL RIGHT RESERVED BY NODIA AND COMPANY

GATE Electrical Engineering-2017
in 5 Volumes
by R.K. Kanodia & Ashish Murolia
Page
g 117 Sequential Circuits Chapter 5
CHAPTER 5
Sample Chapter of GATE Electrical Engineering-2017, Volume-5
SEQUENTIAL CIRCUITS
QUESTION 5.1 QUESTION 5.2
The input signal Vi shown below is applied to the FF in given The input signal Vi shown in figure below is applied to a FF
figure when initially in 0 state. Assume all timing constraints in given figure when initially in its 0-state. Assume all timing
are satisfied. The output Q is constraints are satisfied. The output Q is
. i n
co
a .
d i
n o
p.
o
sh
. in
o
a .c
d i
n o
p.
o
sh
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Engineering Mathematics Analog Electronics, Digital Electronics,
Signals and Systems
Power Electronics
Consider the circuit shown below. A latch is to defined inputs L and M (an LM latch). The

table specifying the desired next state at a clock pulse is
given in below. The expression for the next state Q+ is
L M Q Q+
0 0 0 0
0 0 1 0
The expression for the next state Q+ is
0 1 0 0
(A) xQ 0 1 1 0
1 0 0 1
(B) xQ
n
1 0 1 1
i
(C) x Q
.
1 1 0 1
o
(D) xuQ 1 1 1 0
a .c
d i (A) LM + MQ
o
QUESTION 5.4 (B) LM + LQ
. n (C) LM + MQ
p
In previous question, let the clock pulses be numbered
o
1, 2, 3, ... after the point at which the FF is reset ( 0). (D) LM + LQ
sh
The circuit is a
(A) even parity checker
(B) odd parity generator
(C) Both A and B QUESTION 5.7
in
(D) None of the above The J K F shown below is initially cleared and then
.
clocked for 5 pulses, the sequence at the Q output will be
o
a .c
QUESTION 5.5
d i
o
An AB flip-flop is constructed from an SR Flip-flop as shown
below. The expression for next state Q+ is
. n
o p (A) 0 1 0 0 0 0
sh
(B) 0 1 1 0 0 1
(C) 0 1 0 0 1 0
(D) 0 1 0 1 0 1
(A) AB + AQ
(B) AB + BQ
(C) Both A and B
(D) None of these

in 5 Volumes
Page
Consider a latch circuit shown in figure below, Which of the For the circuit shown below, what is the frequency of the
following set of input is invalid for circuit output Q
(A) Twice the input clock frequency

(A) R 00, H = 0
(B) Half the input clock frequency
n
(B) R 00,, H = 1
(C) R 11,, H = 1
. i
(C) Same as the input clock frequency
o
(D) Inverse of the propagation delay of the flip-flop
.c
(D) R 11,, H = 0
i a
o d
n
QUESTION 5.11
.
QUESTION 5.9
Consider the circuit shown below
o p Which of the following circuit functions as a J-K flip flop ?
sh
. in
The input signal V1 and V2 shown below is applied to the
co
.
above circuit. Assume initially output is in 0-state and all
i a
timing constraints are satisfied. The output Q is
o d
. n
o p
sh

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GATE EE vol-5
Signals and Systems
Power Electronics
In shown below initially A = 1 and B = 1, the input B is In the following circuit, Initially flip flop is cleared. If input

now replaced by a sequence 1 0 1 0 1 0 ... the outputs X and clock frequency is f , then frequency at output will be
Y will be
(A) 2ff
(A) Fixed at 0 and 1, respectively
n
f
i
(B)
.
(B) Fixed at 1 and 0, respectively 2
o
(C) X = 1 0 1 0 ... while Y = 1 0 1 0 ... (C)
(D) X = 1 0 1 0 ... while Y = 0 1 0 1 ...
.c will be same as input
ia
o d
. n
p
o
Consider a reset-dominant S R flip-flop shown in figure
sh
The digital circuit shown in the figure works as
below, which is reset when S R = racteristic equation
of the flip-flop is given as
. in
c o
(A) JK flip-flop
.
ia
Clocked RS flip-flop
Q n + 1 = SR + RQn
d
(C) T - flip-flop
Then combinational logic is
o
(D) Ring counter
(A) SA = S + R
. n
(B) SA S
SR
o p
sh
(C) SA SR
(D) SA S
SR QUESTION 5.16
A J-K flip flop can be made from and S-R flip flop by using
two additional
(A) AND gates
(B) OR gates
(C) NOT gates
(D) NOR gates

in 5 Volumes
Page
A sequential circuit using D flip-flop and logic gates is shown An X Y flip-flop whose characteristic table is given below
below where X and Y are the inputs and Z is the output. is to be implemented using a J-K flip-flop
The circuit is
X Y Qn + 1
0 0 1
0 1 Qn
1 0 Qn
1 1 0
n
This can be done by using
.i(A) J
o
Y
c
(A) S R FF with inputs X R and Y (B X,K
.
S Y
a
(B) S R FF with inputs X S and Y Y, K
i
R J X
d
(C) J K FF with inputs X J and Y K (D) J Y,K X
(D) J K FF with inputs X K and Y J
n o
p.
o
sh
QUESTION 5.20
QUESTION 5.18 The digital block shown below realized using two positive
Consider a circuit shown in figure. The circuit functions as edge triggered D -flip-flop. Assume that for t < t 0, Q Q 0
.in
o
a .c ircuit in the digital block is given by
d i
o
(A) D-flip-flop
(B) T-flip-flop
. n
(C) Output remains stable at '1'
o p
sh
(D) Output remains stable at '0'

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
Consider the following circuit Consider the partial implementation of a 2-bit counter using

T flip-flop following the sequence 0-2-3-1-0 as shown below
The flip-flop are positive edge trigger red D FFs. Each state
is designated as a two bit string Q Q1 . Let the initial state be
i n
00. The state transition sequence is
.
To complete the circuit the input X should be
co (A)
a . Q Q1
d i (C) ( )
o
(D) Q Q2
. n
o p
sh
QUESTION 5.24
The following serial data are applied to the flip-flop through

the AND gates as shown in figure. There is one clock pulse
for each bit time. Q is initially 0 and PRE and CLR are
in
high. If leftmost bits are applied first then output Q is
o.
. c
QUESTION 5.22
ia
o d
How many flip flops will be complemented in a 10-bit binary
n
ripple counter to reach the next count after the count
1001100111
p.
o
(A) 4
(B) 5
(C) 6
s h J1 : 1010011, J2 : 0111010, J 3 : 1111000
K1 : 0001110, K2 : 1101100, K 3 : 1010101
(D) 9 (A) 0000111

(B) 0011000
(C) 0101000
(D) 1010101

in 5 Volumes
Page
The circuit shown in figure below is The counter shown in figure below is a
(A) a MOS-2 counter
n
(B) a MOD-3 counter
i
(A) MOD-8 up counter
.
(C) generate sequence 00, 10, 01, 00 ...
o
(B) MOD-8 down counter
c
(D) generate sequence 00, 10, 00, 10, 00 ...
.
(C) MOD-6 up counter
ia
) MOD-6 down counter
o d
n
QUESTION 5.26
p.
Consider a sequential circuit shown in figure. Initially all the
o
QUESTION 5.29
flip-flop are reset. Output Q Q1 Q2 after clock pulse is
sh
For the circuit shown in figure below, what is the output
Q Q1 Q 0 , after four clock pulses. Initially all flip-flop are reset
. in
c o
a.
i
(A) 100
(B) 101
o d (A) 100
n
(C) 110
(D) 111
p. (B) 110
o
(C) 101
sh
(D) 010
QUESTION 5.27
A 4 bit modulo - 6 ripple counter uses JK flip-flop. If the

propagatuion delay of each FF is 50 ns, the maximum clock
frequency that can be used is equal to
_______ MHz

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Signals and Systems
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The counter shown in figure below counts from In previous question, the D-flip-flop are initialized to

Q Q2 Q 3 = 000 after 1 clock cycle, Q Q2 Q 3 is equal to
(A) 011
(B) 010
(C) 100
(D) 101
(A) 0 0 0 to 1 1 1
(B) 1 1 1 to 0 0 0
. i n
QUESTION 5.33
o
Consider a sequential circuit using three J-K flip-flops and
(C) 1 0 0 to 0 0 0
c
one AND gate shown in figure. Output of the circuit becomes
(D) 0 0 0 to 1 0 0
a . ter every N -clock cycles. The value of N is
d i
n o
QUESTION 5.3130 and 31 :
p.
o
sh
Consider the circuit shown in following figure :
_______
. in
c o
a . QUESTION 5.34
d i The mod-number of the asynchronous counter shown in
o
figure below is
n
The correct input output relationship between Y a , X2)
is
p.
o
(A) Y = X1 + X2
sh
(B) Y X1 X 2
(C) Y X1 5 X 2
(D) Y X1 5 X 2
_______

in 5 Volumes
Page
The three-stage Johnson counter as shown in figure below is A 4 bit ripple counter and a 4 bit synchronous counter are
clocked at a constant frequency of fc from the starting state made by flips flops having a propagation delay of 10 ns
of Q Q1 Q 0 = 101. The frequency of output Q Q1 Q 0 will be each. If the worst case delay in the ripple counter and the
synchronous counter be R and S respectively, then
(A) R = 10 ns, S = 40 ns
(B) R = 40 ns, S = 10 ns
(C) R = 10 ns, S = 30 ns
(D) R = 30 ns, S = 10 ns
(A)
fc
. i n
o
8
QUESTION 5.38
c
f
(B) c
.
6
a
initial contents of the 4-bit serial-in-parallel-out right-
i
(C)
fc hift, register shown in fig. below is 0 1 1 0. After three clock
d
3 pulses are applied, the contents of the shift register will be
o
f
(D) c
n
2
p.
o
QUESTION 5.36
sh (A) 0 0 0 0
The counter shown in the figure below has initially (B) 0 1 0 1

Q Q1 Q 0 = 000 . The status of Q Q1 Q 0 after the first pulse is (C) 1 1 1 1
.in
(D) 1 0 1
c o
a .
d i QUESTION 5.39
n o
.
A 4-bit right shift register is initialized to value 1000 for
p
( , Q2, Q , Q0). The D input is derived from Q , Q2 and Q 3
(A) 0 0 1
o
through two XOR gates as shown in fig. below. The pattern
sh
(B) 0 1 0 1000 will appear at
(C) 1 0 0
(D) 1 0 1
_______ th pulse

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Signals and Systems
Power Electronics
The 8-bit left shift register and D flip-flop shown in fig. A Mealy system produces a 1 output if the input has been

below is synchronized with same clock. The D flip-flop is 0 for at least two consecutive clocks followed immediately
initially cleared. by two or more consecutive 1’s. The minimum state for this
system is
_______
QUESTION 5.44
In previous question, the flip-flop required to implement this

The circuit act as
i n
system are
.
o
(A) Binary to 2’s complement converter _______
(B) Binary to Gray code converter
. c
(C) Binary to 1’s complement converter
i a
(D) Binary to Excess-3 code converter
o d
n
QUESTION 5.45
p. The output of a Mealy system is 1 if there has been a pattern
o
of 11000, otherwise 0. The minimum state for this system is
sh
QUESTION 5.41
_______
In previous question, if initially register contains byte B7,
then after 4 clock pulse contents of register will be
(A) 73
. in
(B) 72
QUESTION 5.46
(C) 7E
o
.c
To count from 0 to 1024 the number of required flip-flop is
(D) 74
ia
_______
o d
. n
p
QUESTION 5.42
o QUESTION 5.47
sh
The frequency of the pulse at z in the network shown in
figure below is Four memory chips of 16 # 4 size have their address buses
connected together. This system will be of size
(A) 64 # 4
(B) 32 # 8
(C) 16 # 16
_______ Hz (D) 256 # 1
_______

in 5 Volumes
Page
For the circuit shown below consider the statement : It is required to obtain 62.5 kHz from 10 MHz clock. Which
Assertion (A) : The circuit is sequential of the following block diagram represent it correctly ?
Reason (R) : There is a loop in circuit
Choose correct option

(A) Both A and R true and R is the correct explanation of
. i n
o
A
. c
(B) Both A and R true but R is not a correct explanation
a
on of A
i
QUESTION 5.52
d
(C) A is true but R is false
o
(D) A is false Consider the following decoder used as a generator of control
n
signal.
p.
o
QUESTION 5.49
sh
In the given counter each flip-flop has a propagation delay
of 8 n sec.
. in
co
a .
d i If RESET pulse occurs only at time t 0 then the control
n o
The worst-case (longest) delay time from a clock pulse to the
waveform for 32 clock pulse is given by :
p.
arrival of the counter in a given state is
o
sh
_______ nano sec
QUESTION 5.50
A binary counter is being pulsed by a 256 kHz clock signal.

The output frequency from the last flip-flop is 2 kHz. The
MOD number is
_______

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Consider the following 4-bit asynchronous binary counter. The MOD number of the given counter is

If each flip-flop has a propagation delay for 10 ns, then the
maximum clock frequency is
_______ MHz
. in
c o
a . _______
d i
o
QUESTION 5.54
Consider the following counter

. n
o p QUESTION 5.57
sh
Consider the following register which initially starts at
101001111000 state.
. in
c o
.
If counter starts at 000, what will be the count after 13 clock
ia
pulses ?
d
(A) 100
(B) 101
n o
(C) 110
p. The state of register after 10 clock pulse is
o
(D) 111
sh
(A) 110001110000
(B) 001111000010
(C) 010000111100
QUESTION 5.55 (D) 10100111100
The address bus width of a memory of size 1024 # 8 bits is
_______

in 5 Volumes
Page
QUESTION 5.58
Consider the following sequential circuit.

. i n
c o
For the given sequential circuit the next state equations for
a .
i
flip-flop A and B are
(A) A+ = A (Bl + X ) + Al (BXl + BlX )
o d
n
and B + = ABlX + B (Al + Xl)
+
(B) A = A (BlX ) + Al (BXl + BlX )
p.
and B + = A (Bl + X) + B (AlXl)
o
sh
(C) A+ = A (BlX ) + Al (BXl)
and B + = A (BlX ) + B (AlXl)
(D) A+ = A (Bl + X ) + Al (BXl + BlX )
and B + = AlX + BlXlAl
. in
************
c o
a .
d i
n o
p.
o
sh

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
SOLUTIONS

SOLUTION 5.1 SOLUTION 5.4
Correct option is (C). Correct option is (D).

Given FF is a negative edge triggered T flip-flop. So at the Q+ = x Q
n
negative edge of clock Vi FF will invert the output if there is
1 at input.
. i Q 1+ = Q 0 = x1 0 + x1 0 = x1
co 2 5 x1,
a . 3 = x 3 5 x 2 5 x1
SOLUTION 5.2
d i Q 4+ = x 4 5 x 3 5 x2 5 x1
o
So this generate the even parity and check odd parity.
Correct option is (A).

. n
p
At first rising edge of clock, D is HIGH. S ill be high
o
till 2nd rising edge of clock. At 2nd risin D is low so Q
sh
will be LOW till 3rd rising edge of clock. At 3rd rising edge,
D is HIGH, so Q will be HIGH will be HIGH till 5th rising. SOLUTION 5.5
edge. At 5th rising edge, D is LOW, so Q will be LOW till
6th rising edge. Correct option is (C).
The truth table is shown below
in
A B S R Q Q+
.
0 0 1 0 0 1
SOLUTION 5.3
c o 0 0 1 0 1 1
.
0 1 0 1 0 0
a
0 1 0 1 1 0
i
Correct option is (C).
d
1 0 0 0 0 0
o
1 0 0 0 1 1
n
1 1 1 1 0 #
.
x Q S R Q +
1 1 1 1 1
p
#
0 0 0 1 0
o Q+ = AB + AQ = AB + BQ
sh
0 1 1 0 1
1 0 1 0 1
1 1 0 1 0

in 5 Volumes
Page
Correct option is (D). Correct option is (A).

+
Q = LM + LMQ L( ) LM + LQ
LM Circuit shown in figure is a D-flip flop with input
D V1 and CLK = V2
L M Q+
0 0 0
0 1 0
1 0 1 SOLUTION 5.10
1 1 Q1
Correct option is (B).
Input to the D flip-flop is D Qn
Output Q Dn = Q n So, output will toggle at every clock
i n
pulse, output frequency will be half of input frequency.
.
c o
.
SOLUTION 5.7
i a
d
Correct option is (D).
SOLUTION 5.11
o
n
.
Initially J K Q Q Qn + 1 Qn+1
p
1 0 1 In option (D)
o
Clock 1st 1 1 0 1 1 0 Output of the MUX is
sh
2nd 0 1 1 0 0 1 Y =D S 1 S 0 I 0 + S1 S 0 I1 S1 S 0 I 2 + S1 S 0 I 3
3rd 1 1 0 1 1 0
Here, I Qn , I Q n , I1 = 0 , I 2 = 1
4th 0 1 1 0 0 1
5th 1 1 0 1 1 0 So, Y D = J KQ 0 J K + JKQ
J n
Next state
Therefore sequence is 0 1 0 1 0 1
in
Qn + 1 = D JQ KQn (by simplifying)
o.
. c
SOLUTION 5.8
i a
d
SOLUTION 5.12
o
n
Form table we get that R = 1 and H = 0 can not occur at Correct option is (A).
the same time
p. The truth table is as shown below
o
R H Q Q+ A B X Y
sh
0 0 0 0 1 1 0 1
0 0 1 0 1 0 0 1
0 1 0 0
0 1 1 1
1 0 0 #
1 0 1 #
1 1 0 1
1 1 1 1

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
Correct option is (D). Correct option is (A).

Characteristic equation for SR flip-flop is given as To realize a J-K flip flop from an S-R flip-flop, we should
Qn + 1 = S A + R A Qn have S JQ n , R KQn So, we have to use two additional
AND gate.
Comparing with above equation SA = SR
SOLUTION 5.17
SOLUTION 5.14
n
Z = XQ + YQ
i
Here T is
T =Q Q n & T = 1 (always)
o. The truth table is shown below
. c
So, output will toggle at each clock pulse. X Y Z
a
0 0 Q
i
The output sequence is 010101010...
0 1 0
Frequency of output is
f
2
o d 1 0 1
n
1 1 Q1
p. Comparing from the truth table of J K FF Y J,, X
o
J K
SOLUTION 5.15
sh
Input to the D-flip-flop can be written as SOLUTION 5.18
in
Dn = Q X Correct option is (B).
For a D-flip-flop output is
o. From the combinational logic

Let nput, Qn is present state, Qn + 1 is next state, then
Qn + 1 = D Qn 5 X
.c R =D Q, S D5Q
By Drawing the truth table
ia Characteristic equation of R-S flip-flop is given by

X Qn Qn + 1
o d Qn + 1 = S + RQn
n
0 0 0
.
0 1 1 So, Qn + 1 = ( )+( ) Qn
1
1
0
1
1
0
o p =( ) ( ) Qn
sh
=( ) (1 5 Q ) (D 5 Qn)
So, Q Qn for X = 0 and Q Q n for X = 1 = DQ n + DQn
This is a T-flip flop. For D = 0 , Q Qn
D = 1, Q Qn
So, the circuit function as a T-flip flop.

in 5 Volumes
Page
Correct option is (D). Correct option is (D).

Let Qn is the present state and Qn + 1 is next state of given In the circuit D0 = Q 0 ,
X Y flip-flop.
D1 = Q Q1
X Y Qn Qn + 1 Initial state " 00
0 0 0 1
Q0 Q1 D0 D1
0 0 1 1
0 0 1 1
0 1 0 0
1 1 0 1
0 1 1 1
0 1 1 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 1 1 (repeat)
n
1 1 0 0 So, the state transition sequence Q Q1 is
. i
1 1 0 0
co
.
Solving from K-map we get
a
Characteristic equation of X Y flip-flop is
Qn + 1 = Y Qn + XQn
d i
o
Characteristic equation of a J K flip-flop is given
Qn + 1 = JQ n + KQn
. n
Comparing J Y,K X
o p SOLUTION 5.22
sh
Correct option is (A).
Count is 1001100111
+1
SOLUTION 5.20
Next count is 1001101000
in
Correct option is (C). So, no. of FF to be complement = 4
The Input and output is as shown below
o.
. c
i a
d
SOLUTION 5.23
n o Correct option is (D).
p. Sequence 00-10-11-01-00
We have
o
sh
T1 = Q Q2 + Q Q1 = Q Q2

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
Correct option is (B). Correct answer is 5 MHz.

Applying the serial bits for J and K inputs of the flip-flop 4 bit uses 4 FF
Total delay Ntd = 4 # 50 ns = 200 # 10−9
CLK 1 2 3 4 5 6 7 1
f = = 5 MHz
J1 1 0 1 0 0 1 1 200 # 10−9
J2 0 1 1 1 0 1 0
J3 1 1 1 1 0 0 0
K1 0 0 0 1 1 1 0
K2 1 1 0 1 1 0 0
K3 1 0 1 0 1 0 1 SOLUTION 5.28
J 0 0 1 0 0 0 0
n
K 0 0 0 0 1 0 0 Correct option is (B).
. i
Q 0 0 1 1 0 0 0
It is a down counter because 0 state of previous FFs change
o
the state of next FF. You may trace the following sequence,
c
let initial state be 0 0 0
a . FF C B A
i
FF FF
d
J KC J K B J K A C+ B+ A+
o
1 1 1 1 1 1 1 1 1 1 1 1
SOLUTION 5.25
n
0 0 0 0 0 0 1 1 0 1 1 0

p. 0 0 0 1 1 0 1 1 1 1 0 1
o
0 0 0 0 0 1 1 1 0 1 0 0
sh
1 1 1 1 1 1 1 1 1 0 1 1
Present State FF Input Next State 0 0 1 0 0 0 1 1 0 0 1 0
+ +
QA QB TA TB Q Q
A B 0 0 1 1 1 0 1 1 1 0 0 1
0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0
0 1 1 1 1 0
1 0 1 0 0 0
in
1 1 1 1 0 0
From table it is clear that it is a MOD-3 counter.

o.
. c
SOLUTION 5.29
ia Correct option is (B).
SOLUTION 5.26
o d The truth table is as shown below
n
Q 2 Q1 Q 0 D 2 D1 D 0

p. Initially 0 0 0 0 0 1
o
At Clock 1 0 0 1 0 1 1
This is a 3 bit counter, so the output sequence is
sh
At Clock 2 0 1 1 1 1 1
At Clock 3 1 1 1 1 1 0
CLK Q2 Q1 Q0
At Clock 4 1 1 0 1 0 0
Initially 0 0 0
At Clock 5 1 0 0 0 0 1
1 0 0 1
At Clock 6 0 0 1 0 1 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

in 5 Volumes
Page
SOLUTION 5.30 CLK Q2 Q1 Q0 Z

Initially 0 0 0 1
1 1 1 0 0
It is a down counter because the inverted FF output drive
2 0 0 1 0
the clock inputs. The NAND gate will clear FFs A and B
3 1 0 0 0
when the count tries to recycle to 111. This will produce as
result of 100. Thus the counting sequence will be 100, 011, 4 0 1 0 0
010, 001, 000, 100 etc. 5 1 0 1 0

6 0 0 0
It is a modulo 6-counter So, output Z will be 1 after every

6 clock pulses
SOLUTION 5.31
. i n
o
From the figure
SOLUTION 5.34
. c
Y = X1 X1 + X 2 + X 2 + X 1 + X 2
a
ect answer is 24.
i
Y = X1 ( ) X2 ( )
It is a 5 bit ripple counter. At 11000 the output of NAND
A + B = AB
o d gate is LOW. This will clear all FF. So it is a Mod-24 counter.

Note that when 11000 occur, the CLR input is activated and
n
Y = X1 X1 + X1 X 2 + X 2 X1 + X 2 X 2
.
all FF are immediately cleared. So it is a MOD 24 counter
p
= X1 X 2 + X1 X 2 = X1 5 X 2 not MOD 25.
o
sh
SOLUTION 5.35
SOLUTION 5.32
in
.
The truth table is as shown below
Initially Q Q2 Q 3 = 000
o
In the circuit D1 = X Q3 = 0 Q Q0 Q Q2 Q Q1
X 2 = Q1 = 0
. c J2 K2 J 1 K1 J0 K0 Q 2+ Q 1+ Q 0+
ia
1 0 1
D2 = Y 050 = 1
d
X1 5 X 2 01 10 01 0 1 0
o
10 01 10 1 0 1
D 3 = Q2 = 0
n
01 10 01 0 1 0
.
Inputs to the flip flops are D1 = 0 , D1 = 1, D 3 10 01 10 1 0 1
After 1 clock cycle outputs are Q1 = 0 , Q
op Q3 = 0
We see that 1 0 1 repeat after every two cycles, hence
sh
f
frequency will be c .
2
SOLUTION 5.33
Correct answer is 6. SOLUTION 5.36

Let initially output is 1, then
At first cycle

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
J2 K2 = 10 & Q2 = 1, The output of XOR gate is Z bi + 1 5 bi and this output

J1 K1 = 01 & Q1 = 0, shift the register to left,

J 0 K 0 = 01 & Q0 = 0 Initially Z = 0
After 1st clock Z b7 5 0 = b7
After 2nd clock Z b7 5 b6
3rd clock Z b6 5 b5
4th clock Z b5 5 b 4
SOLUTION 5.37

In ripple counter delay 4 d 40 ns . The synchronous counter
are clocked simultaneously, then its worst delay will be equal
SOLUTION 5.41
to 10 ns.
n
. i 1011 0111, After four clock
co bl4 = b 3 b2 b1 b 0 = 7 ,
.
5
SOLUTION 5.38
a
bl3 = b7 5 0 1

d i bl2 = b7 b 6 = 1,
o
At pulse 1 input, 1 5 0 = 1 b1l = b6 b5 = 1
n
So contents are 1 0 1 1,
At pules 2 input 1 5 1 = 0
So contents are 0 1 0 1,
p. bl0 = b5 b4 = 0,
o
1 1 1 02 = E
At pules 3 input 0 5 1 = 1, contents are 1 0 1 0
sh
Correct answer is 6.
. in Correct answer is 5 MHz.
o
The truth table is as shown below 10-bit ring counter is a MOD-10, so it divides the 160 kHz
c
input by 10, therefore, w = 16 kHz . The four-bit parallel
CLK Q3 Q2 Q1 Q0 XOR 1
a .
XOR 2 ter is a MOD-16. Thus, the frequency at x = 1 kHz . The
i
MOD-25 ripple counter produces a frequency at y = 40 Hz
Initially 1 0 0 0 0 1
d
. (1 kHz/25 = 40 Hz). The four-bit Johnson Counter is a
o
1st 1 1 0 0 0 1
MOD-8. This, the frequency at z = 5 Hz .
n
2nd 1 1 1 0 1 0
.
3rd 0 1 1 1 0 0
4th
5th
0
0
0
0
1
0
1
1
0
1
o p 0
1
sh
6th 1 0 0 0
SOLUTION 5.43
The state diagram is as shown below
SOLUTION 5.40

in 5 Volumes
Page
SOLUTION 5.47

Since all chip has same address, the capacity of word will be
increased.
SOLUTION 5.48
There are 4 minimum state Correct option is (D).

There is no active loop in the network because variable b
interrupts the loop at two different point.
. i n
When b = ad , z 0 = ad
d+c
o
When z1 z 0 d , z 0 = e + c
c
As we can see from the equation there is no feed back of
.
SOLUTION 5.44 s in the physical loop, and the circuit is combinational.
i a
4 22 , Thus 2 FF are required.
o d
. n
p
SOLUTION 5.49
o
sh
Correct answer is 24 nano sec.
SOLUTION 5.45
tp ( ) = 3 (8 ) = 24 n sec
The state diagram is shown below
. in
SOLUTION 5.50
c o
.
ia
MOD Number = 256 kHz = 128
2 kHz
o d
. n
o p SOLUTION 5.51
sh
There are five minimum state is 5.
10 MHz = 1 MHz = 500 MHz = 250 kHz = 125 kHz
10 2 2 2 2
= 62.5 kHz
So the correct answer is
SOLUTION 5.46

10 flip-flop will count from 0 to 1023. Hence 11 flip-flop are
required to count from 0 to 1024.

GATE EE vol-3
GATE EE vol-5
Signals and Systems
Power Electronics
Correct option is (B). Correct answer is 14.

The output O 3 will be LOW only when A2, A1, A 0 = 011, This is a 4-bit counter, which would normally count from
E 3 1,, E2 0 . 0000 through 1111. The NAND inputs are D, C and B ,
This condition is present after the 28 th and 29 th negative which means that the counter will immediately recycle to
triggering of the clock. That is : 0000 when the 1110 (decimal 14) count is reached. Thus, the
28 10 = 011100 2 29 10 = 011101 2 counter actually has 14 stable states 0000 through 1101 and
is therefore a MOD 14 counter.
Thus, O 3 will appear are shown below :
SOLUTION 5.57
. i n
o
c
Initially " 101001111000
a . After 1st clock " 010100111100

SOLUTION 5.53
d i After 2 nd clock " 001010011110
Correct answer is 25 MHz.
n o After 3 rd clock " 000101001111
tp ( ) = 4 # 10 40 ns
p. After 4 th clock " 000010100111
o
So, the maximum clock frequency is After 5 th clock " 100001010011
sh
f max = 1 = 1
tp ( ) 40 ns After 6 th clock " 110000101001
= 25 MHz After 7 th clock " 111000010100
After 8 th clock " 111100001010
After 9 th clock " 011110000101
.in After 10 th clock " 001111000010
o
SOLUTION 5.54

. c
This is a counter that will recycle every 8 pulses (MOD
i a
d
counter). Count after 13 clock pulses is 5(101).
n o
.
SOLUTION 5.58
o p Correct option is (A).
sh
SOLUTION 5.55
A+ = AKAl + AlJA
Correct answer is 10. = A( l ) + Al ( l l )
There are 1024 memory location 1024 = 210 . Hence address
and B + = BlJB + BKBl
bus width = 10 bits.
= Bl ( l l)l + B ((Al + Xl)l)l
= BlAX + B ( l l)
= ABlX + B ( l l)
***********


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QUESTION 5.1 QUESTION 5.2

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QUESTION 5.3 QUESTION 5.6

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QUESTION 5.8 QUESTION 5.10

following set of input is invalid for circuit output Q

(A) Twice the input clock frequency

Consider the circuit shown below

o p Which of the following circuit functions as a J-K flip flop ?

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QUESTION 5.12 QUESTION 5.14

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QUESTION 5.17 QUESTION 5.19

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QUESTION 5.21 QUESTION 5.23

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The following serial data are applied to the flip-flop through

(D) 9 (A) 0000111

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QUESTION 5.25 QUESTION 5.28

(A) a MOS-2 counter

A 4 bit modulo - 6 ripple counter uses JK flip-flop. If the