CM3406 MPS

TM
CM3406
1.5A, 210KHz
Step-Down Converter
TM
The Future of Analog IC Technology
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION - ACCTON INTERNAL USE ONLY
DESCRIPTION FEATURES
The CM3406 is a monolithic step-down switch • 1.5A Continuous Output Current
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mode converter with a built-in internal power • 0.2Ω Internal Power MOSFET Switch
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MOSFET. It achieves 1.5A continuous output • Stable with Low ESR Output Ceramic Capacitors
U SE IA
current over a wide input supply range with • Up to 95% Efficiency
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excellent load and line regulation. • 20μA Shutdown Mode
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•
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Current mode operation provides fast transient Fixed 210KHz Frequency
response and eases loop stabilization. Fault • Thermal Shutdown
condition protection includes cycle-by-cycle • Cycle-by-Cycle Over Current Protection
current limiting and thermal shutdown. The • Wide 4.75V to 22V Operating Input Range
TR A DE
CM3406 requires a minimum number of readily • Output Adjustable from 1.23V to 18V
available standard external components. • Programmable Under Voltage Lockout
• Available in 8-Pin SO and PDIP Packages
TE
IS N I
EVALUATION BOARD REFERENCE
D R NF
Board Number Dimensions APPLICATIONS
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EV3406DS-00A 2.3”X x 1.4”Y x 0.5”Z •
•
Distributed Power Systems
Battery Chargers
T E O
• Pre-Regulator for Linear Regulators

O T C
“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic

Power Systems, Inc.
N IN S
TYPICAL APPLICATION
O N P
C4 Efficiency vs
D TO M
10nF Load Current

VIN
100
12V 3 2 VOUT = 5V
95
90
4 VOUT 85
EFFICIENCY (%)
ENABLE 8 SW
EN 2.5V/1.5A
SHUTDOWN 80
CM3406 D1 VOUT = 3.3V
75 VOUT = 2.5V
OPEN 1 B230A
NC
6 70
NOT USED FB
65
GND COMP 60
C
5 7 55
C3 50
C
4.7nF
VIN = 12V
C6 45
OPEN 40
A
0.25 0.50 0.75 1.00 1.25 1.50

LOAD CURRENT (A)
CM3406-EC01
CM3406_TAC_S01
CM3406 Rev. 1.6 www.MonolithicPower.com 1

10/29/2009 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved. 2009110322430097
www.DataSheet.in
TM
CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

ORDERING INFORMATION
Part Number* Package Top Marking Temperature
CM3406DP PDIP8
–40°C to +85°C
CM3406DS SOIC8 CM3406DS
* FOR LEAD FREE, ADD SUFFIX –LF (EG. CM3406DP–LF)
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** For Tape & Reel, add suffix –Z (eg. CM3406DS–Z)
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For Lead Free, add suffix –LF (eg. CM3406DS–LF–Z)
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PACKAGE REFERENCE
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TR A DE
TOP VIEW TOP VIEW
NC 1 8 EN NC 1 8 EN
BS 2 7 COMP BS 2
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7 COMP
IS N I
D R NF
IN 3 6 FB IN 3 6 FB
L SW 4 5 GND SW 4 5 GND
T E O
CM3406_PD01-PDIP8 CM3406_PD02-SOIC8
O T C
N IN S
ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance

(4)
θJA θJC
O N P
Supply Voltage (VIN)..................................... 24V PDIP8......................................95 ...... 55 ... °C/W

Switch Voltage (VSW).................. –1V to VIN + 1V SOIC8 ....................................105 ..... 50 ... °C/W
D TO M
Bootstrap Voltage (VBS) ....................... VSW + 6V

Feedback Voltage (VFB) .................–0.3V to +6V Notes:
1) Exceeding these ratings may damage the device.
Enable/UVLO Voltage (VEN)...........–0.3V to +6V 2) The maximum allowable power dissipation is a function of the
Comp Voltage (VCOMP) ...................–0.3V to +6V maximum junction temperature TJ(MAX), the junction-to-
Continuous Power Dissipation (TA = +25°C)(2) ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
PDIP8 ………………………………………..1.3W any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
SOIC8 ………………………………………..1.2W TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
Junction Temperature ...............................150°C into thermal shutdown. Internal thermal shutdown circuitry
C
Lead Temperature ....................................260°C protects the device from permanent damage.

3) The device is not guaranteed to function outside of its
Storage Temperature.............. –65°C to +150°C
C
operating conditions.
(3) 4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions
A
Input Voltage (VIN)..........................4.75V to 22V

Operating Temperature............. –40°C to +85°C

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ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Feedback Voltage VFB 4.75V ≤ VIN ≤ 22V 1.195 1.230 1.265 V
(5)
Upper Switch On Resistance 0.2 Ω
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Lower Switch On Resistance (5) 12 Ω
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Upper Switch Leakage VEN = 0V, VSW = 0V 10 μA
Current Limit (4)
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2.5 A
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Current Sense Transconductance
GCS 1.85 A/V
Output Current to Comp Pin Voltage
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Error Amplifier Voltage Gain AVEA 400 V/V
Error Amplifier Transconductance GEA ΔIC = ±10μA 450 700 1000 μA/V
Oscillator Frequency fS 210 KHz
TR A DE
Short Circuit Frequency VFB = 0V 130 KHz
Maximum Duty Cycle VFB = 1.0V 90 %
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Minimum Duty Cycle VFB = 1.5V 0 %
IS N I
D R NF
Enable Threshold ICC > 100μA 0.7 1.0 1.3 V
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Enable Pull Up Current
Under Voltage Lockout Threshold Rising
VEN = 0V 1.0
2.37
1.2
2.50 2.62
μA
V
T E O
Under Voltage Lockout Threshold

210 mV
Hysteresis
O T C
Supply Current (Shutdown) VEN ≤ 0.4V 20 35 μA

Supply Current (Quiescent) VEN ≥ 3.0 V, VFB =1.4V 0.9 1.1 mA
N IN S
Thermal Shutdown 160 °C

O N P
Note:
5) Guaranteed by design.
D TO M
C
C
A

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TM

PIN FUNCTIONS
Pin # Name Description
1 NC No Connect. Open, not used.
Bootstrap (C5). This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BS pins to form a floating supply across the power
2 BS
switch driver. The voltage across C5 is about 5V and is supplied by the internal +5V supply when
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the SW pin voltage is low.
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Supply Voltage. The CM3406 operates from a +4.75V unregulated input. C1 is needed to
3 IN
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prevent large voltage spikes from appearing at the input.
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4 SW Switch. This connects the inductor to either IN through M1 or to GND through M2.
Ground. This pin is the voltage reference for the regulated output voltage. For this reason care
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5 GND must be taken in its layout. This node should be placed outside of the D1 to C1 ground path to
prevent switching current spikes from inducing voltage noise into the part.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets the
TR A DE
output voltage. To prevent current limit run away during a short circuit fault condition the
6 FB
frequency foldback comparator lowers the oscillator frequency when the FB voltage is below
700mV.
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Compensation. This node is the output of the transconductance error amplifier and the input to
IS N I
D R NF
7 COMP the current comparator. Frequency compensation is done at this node by connecting a series R-
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C to ground.
Enable/UVLO. There is about 7V internal zener connected between EN and GND as block
diagram shows. The zener has 10mA maximum current rating. A voltage greater than 2.62V
T E O
8 EN enables operation. Leave EN unconnected if unused. An Under Voltage Lockout (UVLO)

function can be implemented by the addition of a resistor divider from VIN to GND. For complete
O T C
low current shutdown it’s the EN pin voltage needs to be less than 700mV.
N IN S
O N P
D TO M
C
C
A

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TM

BLOCK DIAGRAM
IN 2
INTERNAL CURRENT
5V SENSE
REGULATORS
AMPLIFIER +
OSCILLATOR
SLOPE
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COMP --
5V 1 BS
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130/210KHz
CLK M1
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+ + S Q
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R Q
3 SW
1.0V -- SHUTDOWN -- CURRENT
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COMPARATOR COMPARATOR
EN 7 M2
LOCKOUT
-- COMPARATOR
7.0V 1.8V
TR A DE
2.30V/
2.50V + + -- 4 GND
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FREQUENCY -- 0.7V 1.23V + ERROR
D R NF
FOLDBACK AMPLIFIER
COMPARATOR
L 5 FB 6 COMP CM3406_BD01
T E O
APPLICATION INFORMATION
O T C
the switched input voltage. A larger value inductor

COMPONENT SELECTION will result in less ripple current that will result in
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Setting the Output Voltage lower output ripple voltage. However, the larger
The output voltage is set using a resistive voltage value inductor will have a larger physical size,
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divider from the output voltage to FB pin. The higher series resistance, and/or lower saturation
voltage divider divides the output voltage down to
D TO M
current. A good rule for determining the

the feedback voltage by the ratio: inductance to use is to allow the peak-to-peak
R2 ripple current in the inductor to be approximately
VFB = VOUT 30% of the maximum switch current limit. Also,
R1 + R2
make sure that the peak inductor current is below
Where VFB is the feedback voltage and VOUT is the the maximum switch current limit. The inductance
output voltage. value can be calculated by:
Thus the output voltage is: VOUT ⎛ V ⎞
L= × ⎜⎜1 − OUT ⎟⎟
C
R1 + R2 f S × ΔIL ⎝ VIN ⎠
VOUT = 1.23 ×
R2
C
Where fS is the switching frequency, ΔIL is the

R2 can be as high as 100kΩ, but a typical value peak-to-peak inductor ripple current and VIN is the
A
is 10kΩ. Using that value, R1 is determined by: input voltage.

R1 = 8.18 × ( VOUT − 1.23)
For example, for a 3.3V output voltage, R2 is
10kΩ, and R1 is 17kΩ.
Inductor
The inductor is required to supply constant
current to the output load while being driven by

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TM

Choose an inductor that will not saturate under prevent excessive voltage ripple at input. The
the maximum inductor peak current. The peak input voltage ripple caused by capacitance can
inductor current can be calculated by: be estimated by:
ILOAD V ⎛ V ⎞
VOUT ⎛ V ⎞ ΔVIN = × OUT × ⎜⎜1 − OUT ⎟⎟
ILP = ILOAD + × ⎜⎜1 − OUT ⎟⎟ fS × C1 VIN ⎝ VIN ⎠
2 × fS × L ⎝ VIN ⎠
Output Capacitor
Where ILOAD is the load current.
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The output capacitor is required to maintain the
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Output Rectifier Diode DC output voltage. Ceramic, tantalum, or low
The output rectifier diode supplies the current to ESR electrolytic capacitors are recommended.
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the inductor when the high-side switch is off. To Low ESR capacitors are preferred to keep the
reduce losses due to the diode forward voltage output voltage ripple low. The output voltage
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and recovery times, use a Schottky diode. ripple can be estimated by:
Choose a diode whose maximum reverse VOUT ⎛ V ⎞ ⎛ 1 ⎞
ΔVOUT = × ⎜⎜1 − OUT ⎟⎟ × ⎜⎜ RESR + ⎟ Wh
voltage rating is greater than the maximum fS × L ⎝ VIN ⎠ ⎝ 8 × fS × C2 ⎟⎠
TR A DE
input voltage, and whose current rating is
ere RESR is the equivalent series resistance (ESR)
greater than the maximum load current.
value of the output capacitor and C2 is the output
Input Capacitor capacitance value.
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IS N I
The input current to the step-down converter is
D R NF
In the case of ceramic capacitors, the output
discontinuous, therefore a capacitor is required
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to supply the AC current to the step-down
converter while maintaining the DC input
voltage ripple is mainly caused by the
capacitance. For simplification, the output voltage
ripple can be estimated by:
T E O
voltage. Use low ESR capacitors for the best

performance. Ceramic capacitors are preferred, VOUT ⎛ V ⎞
O T C
ΔVOUT = × ⎜⎜1 − OUT ⎟⎟

but tantalum or low-ESR electrolytic capacitors 8 × fS
2
× L × C2 ⎝ VIN ⎠
may also suffice.
N IN S
Where L is the inductor value.

Since the input capacitor (C1) absorbs the input
switching current it requires an adequate ripple In the case of tantalum or electrolytic capacitors,
O N P
current rating. The RMS current in the input the ESR dominates the impedance at the
D TO M
capacitor can be estimated by: switching frequency. For simplification, the output
ripple can be approximated to:
VOUT ⎛⎜ VOUT ⎞
I C1 = ILOAD × × 1− ⎟
VIN ⎜⎝ VIN ⎟ VOUT ⎛ V ⎞
⎠ ΔVOUT = × ⎜1 − OUT ⎟⎟ × R ESR
f S × L ⎜⎝ VIN ⎠
The worst-case condition occurs at VIN = 2VOUT,
where: The characteristics of the output capacitor also
affect the stability of the regulation system. The
ILOAD
IC1 = CM3406 can be optimized for a wide range of
2 capacitance and ESR values.
C
For simplification, choose the input capacitor Compensation Components

C
whose RMS current rating greater than half of The CM3406 employs current mode control for
the maximum load current. easy compensation and fast transient response.
A
The system stability and transient response are

The input capacitor can be electrolytic, tantalum controlled through the COMP pin. COMP pin is
or ceramic. When using electrolytic or tantalum the output of the internal transconductance
capacitors, a small, high quality ceramic error amplifier. A series capacitor-resistor
capacitor, i.e. 0.1μF, should be placed as close combination sets a pole-zero combination to
to the IC as possible. When using ceramic control the characteristics of the control system.
capacitors, make sure that they have enough
capacitance to provide sufficient charge to

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TM

The DC gain of the voltage feedback loop is: Lower crossover frequencies result in slower
line and load transient responses, while higher
VFB
A VDC = R LOAD × G CS × A VEA × crossover frequencies could cause system
VOUT unstable. A good rule of thumb is to set the
Where RLOAD is the load resistor value, GCS is crossover frequency to below one-tenth of the
the current sense transconductance and AVEA is switching frequency.
the error amplifier voltage gain. To optimize the compensation components, the
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following procedure can be used:
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The system has two poles of importance. One
is due to the compensation capacitor (C3) and 1. Choose the compensation resistor (R3) to set
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the output resistor of error amplifier, and the
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the desired crossover frequency. Determine the
other is due to the output capacitor and the load R3 value by the following equation:
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resistor. These poles are located at:
2π × C2 × f C VOUT
GEA R3 = ×
fP1 = G EA × G CS VFB
2π × C3 × A VEA
TR A DE
Where fC is the desired crossover frequency,
1 which is typically less than one tenth of the
fP2 =
2π × C2 × R LOAD switching frequency.
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IS N I 2. Choose the compensation capacitor (C3) to
Where GEA is the error amplifier
D R NF
transconductance. achieve the desired phase margin. For
L
The system has one zero of importance, due to
the compensation capacitor (C3) and the
applications with typical inductor values, setting
the compensation zero, fZ1, to below one forth
T E O
of the crossover frequency provides sufficient

compensation resistor (R3). This zero is located phase margin. Determine the C3 value by the
O T C
at: following equation:

1 4
f Z1 = C3 >
N IN S
2π × C3 × R3 2π × R3 × f C
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The system may have another zero of Where, R3 is the compensation resistor value.
importance, if the output capacitor has a large
D TO M
3. Determine if the second compensation

capacitance and/or a high ESR value. The zero,
capacitor (C6) is required. It is required if the
due to the ESR and capacitance of the output
ESR zero of the output capacitor is located at
capacitor, is located at:
less than half of the switching frequency, or the
1 following relationship is valid:
fESR =
2π × C2 × R ESR f
1
< S
In this case, a third pole set by the 2π × C2 × R ESR 2
compensation capacitor (C6) and the
If this is the case, then add the second
C
compensation resistor (R3) is used to

compensation capacitor (C6) to set the pole fP3
compensate the effect of the ESR zero on the
C
at the location of the ESR zero. Determine the

loop gain. This pole is located at:
C6 value by the equation:
A
1
fP 3 = C2 × R ESR
2π × C6 × R3 C6 =
R3
The goal of compensation design is to shape
the converter transfer function to get a desired
loop gain. The system crossover frequency
where the feedback loop has the unity gain is
important.

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TM

PACKAGE INFORMATION
PDIP8
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L
U SE IA
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IB U NT
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TR A DE
TE
IS N I
D R NF
L
T E O
SOIC8
O T C
PIN 1 IDENT. 0.229(5.820)

0.244(6.200)
N IN S
0.150(3.810) 0.0075(0.191)
0.157(4.000) 0.0098(0.249)
O N P
SEE DETAIL "A"

D TO M
0.011(0.280) x 45o
0.020(0.508)
0.013(0.330)
0.020(0.508)
0.050(1.270)BSC
0.189(4.800)
0.197(5.004) 0o-8o
0.016(0.410)
0.049(1.250) 0.050(1.270)
DETAIL "A"
0.053(1.350)
0.068(1.730) 0.060(1.524)
C
SEATING PLANE
0.001(0.030)
C
0.004(0.101)
A
NOTE:
1) Control dimension is in inches. Dimension in bracket is millimeters.
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.

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TM

• Pre-Regulator for Linear Regulators

“MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic

10nF Load Current

0.25 0.50 0.75 1.00 1.25 1.50

CM3406 Rev. 1.6 www.MonolithicPower.com 1

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance

Supply Voltage (VIN)..................................... 24V PDIP8......................................95 ...... 55 ... °C/W

Bootstrap Voltage (VBS) ....................... VSW + 6V

Lead Temperature ....................................260°C protects the device from permanent damage.

Input Voltage (VIN)..........................4.75V to 22V

CM3406 Rev. 1.6 www.MonolithicPower.com 2

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

Under Voltage Lockout Threshold

Supply Current (Shutdown) VEN ≤ 0.4V 20 35 μA

Thermal Shutdown 160 °C

CM3406 Rev. 1.6 www.MonolithicPower.com 3

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

8 EN enables operation. Leave EN unconnected if unused. An Under Voltage Lockout (UVLO)

CM3406 Rev. 1.6 www.MonolithicPower.com 4

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

the switched input voltage. A larger value inductor

current. A good rule for determining the

Where fS is the switching frequency, ΔIL is the

is 10kΩ. Using that value, R1 is determined by: input voltage.

CM3406 Rev. 1.6 www.MonolithicPower.com 5

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

voltage. Use low ESR capacitors for the best

ΔVOUT = × ⎜⎜1 − OUT ⎟⎟

Where L is the inductor value.

For simplification, choose the input capacitor Compensation Components

The system stability and transient response are

CM3406 Rev. 1.6 www.MonolithicPower.com 6

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

of the crossover frequency provides sufficient

at: following equation:

3. Determine if the second compensation

compensation resistor (R3) is used to

at the location of the ESR zero. Determine the

CM3406 Rev. 1.6 www.MonolithicPower.com 7

CM3406 – 1.5A, 210KHz STEP-DOWN CONVERTER

PIN 1 IDENT. 0.229(5.820)

SEE DETAIL "A"

CM3406 Rev. 1.6 www.MonolithicPower.com 8

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