EDA Tools for 3D Designs & Packaging

April 12, 2015 · by electronics ·

Advertisement

As EDA tools gained commercial success in the late 1980’s, a need emerged for interoperability among
the tools. There’s no doubt left in the minds of semiconductor device manufacturers that the
processes required to build interposer-based and 3D IC devices are matured and ready for production.
However, manufacturers are still out in the design community because designing 3D ICs still poses a
challenge.

The possible
reason is lack of knowledge & training. With any new technology paradigm shift, there needs to be an
education to help design engineers find out how to get started. “Engineers are busy. Before they are
willing to make a commitment – before a program manager is willing to take a leap of faith – he or she
needs to be confident that all the pieces are there. To design in 3D, an efficient, streamlined 3D design
flow is required. A suitable EDA, Electronic Design Automation Tool, could be a gateway to new era of IC
designing. EM Media bought to you an in-depth analysis of role of EDA tools in 3D design & packaging.

Currently available, Electronic Design Automation (EDA) tools exist to handle complex IC systems, and
can therefore handle complex 3D designs as long as the software has the proper inputs from a foundry’s
Process-Design Kit. EDA tools have evolved in complexity such that Design-For-Test (DFT) methodologies
and technologies now exist to tackle 3D ICs. The IEEE 1838 working group on 3D interface standards is
intended for heterogeneous integration, allowing for different IC process technologies, design set-ups,
test, and design-for-test approaches. The standard defines test access features that enable the
transportation of test stimuli and responses for both a target die and its inter-die connections. Die
interfaces can be mis-aligned due to translation or rotation during assembly, and with die from different
fabs at different geometries it can be non – trivial to ensure that the rights pins are connected. Using a
precise EDA can helps us doing Die-stacking accurately. In short, “For successful adoption of 3D IC
technology it is important, that EDA tools for IC designing and packaging has to keep pace with a fast-
moving range of requirements being created by a dynamic and demanding industry.”

Before we move to our analysis on part of EDA tools in the technology of 3D ICs, we hereby introduce
3D ICs in brief.

3D IC Packaging refers to 3D integration schemes that rely on traditional methods of interconnect such
as wire bonding and flip chip to achieve vertical stacks. 3D packaging can be disseminated further into
3D system in package (3D SiP) and 3D wafer level package (3D WLP). Stacked memory die
interconnected with wire bonds, and package on package (PoP) configurations interconnected with
either wire bonds, or flip chips are 3D SiPs that have been in mainstream manufacturing for some time
and have a well established infrastructure. PoP is used for vertically integrating disparate technologies
such as 3D WLP uses wafer level processes such as redistribution layers (RDL) and wafer bumping
processes to form interconnects. 2.5D interposer is also a 3D WLP that interconnects die side-side on a
silicon, glass or organic interposer using TSVs and RDL. In all types of 3D Packaging, chips in the package
communicate using off-chip signaling, much as if they were mounted in separate packages on a normal
circuit board. 3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to stacking IC chips using
TSV interconnects, and monolithic 3D ICs, which use fab processes to realize 3D interconnects at the
local levels of the on-chip wiring hierarchy as set forth by the ITRS, this results in direct vertical
interconnects between device layers.

3D IC stacking or moving into the 3D by stacking multiple layers of IC will be the ultimate expression of
CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV) or
monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should
be both smaller and faster compared to functionally equivalent 2D chips and packages. However, 3D
ICs will likely always cost more than doing it in 2D, due to more steps being needed in manufacturing
in terms of costing & expertise.

Significance of EDA Tools for 3D IC Design and Packaging

IC manufacturers understand that wasted design cycles are costly and as IC process sizes shrink, the
complexity of the design grows. EDA tools are necessary to save time, reduce cost, and shorten design
cycles, because they automate numerous tasks and provide feedback that enables designers to identify
and correct design challenges before entering the costly prototype and manufacturing phase. Time-
saving is also a critical factor, to be considered. With silicon manufacturers and device makers looking to
pack an increasingly-powerful processing punch into ever-shrinking devices while simultaneously
reducing their electricity consumption, building efficient power management into initial semiconductor
design has become something of an obsession for the current generation of IC designers. Designing IC
with such concerns for dedicated products need extremely accurate EDA tools that can work on critical
parameters. Depending on the design, emulation can be a hundred times faster than using a software
simulator to verify power intent and run a lot more tests and get better coverage for the device overall.
The greater speed allows more scenarios to be explored and so identify power issues in the context of
the full system early in the design process.

A user-friendly EDA tools help to increase the number of designers able to analyze and understand the
architectural trade-off (performance, power, cost, etc.) of available alternatives and how they can
impact the manufacturing process (throughput, yields, quality, and reliability), or will broaden market
acceptance of 2.5/3D ICs, drive yield-learning and cost-reduction efforts. The use of path-finding or EDA
tools will enable designers to make better choices when faced with a myriad of options including the use
of true 3D ICs, 2.5D, or some other form of stacking using package-on-package with either a flip chip die
on the bottom package, an embedded die in the bottom package substrate, or a fan-out wafer level
package solution (FO-WLP). Support from the EDA tool community will be essential and allow for the
designer to think in 3D. While significant progress has been made, there are clearly improvements that
are required. The lack of optimal EDA tools has caused many of the large IDM/ODMs and major fabless
IC vendors to exert significant internal effort to enable engineers to design interposer solutions. This
includes scripting and modification of existing EDA tools to adapt them for path finding, floor-planning,
and design and verification of interposers. Now a days, fabless companies has the financial resources to
buy or fund an EDA company to enable them to do a 2.5D/3D IC design. In many ways, this is similar to
the early challenges with ASIC design, when multiple IP blocks were combined with custom logic into
one die. According to Cadence, 3D ICs do not need an entirely new design system, but do require new
design capabilities in architectural analysis, floor-planning, place and route, thermal analysis, timing,
signal integrity, IC and package co-design, especially regarding thermo-mechanical interactions, and test.

3D-IC design touches on so many areas of chip design

that tool suites are going to have to be updated in areas including some of them mentioned ahead. In
the application areas of EDA tools, what is likely to be much more challenging, though, is to upgrade
existing tools and methodologies so that they can handle multiple process technologies. The die and the
interposer are likely to be on different technologies and so you will need multi-technology-aware tools.
For example, for extraction, we’ll have to extract each element separately and then concatenate them
to create a single design file. The system needs to handle heterogenous process nodes, it needs to
understand TSVs, have updated routing strategies and a database to handle heterogeneous processes. It
sounds like an evolution but it actually takes a lot to do. Some of the key application areas are:

1. Circuit design and schematic capture for redistribution layers, interposer signal routing,
shielding and power

2. Place-and-route support, including TSV, micro-bump, redistribution layer and signal routing,
power mesh creation and interconnect checks

3. Design-for-test for stacked die and TSV

4. Integrated memory test, diagnostics and repair systems

5. Parasitic extraction support for TSV, micro-bump, interposer RDL and signal routing metal

6. Circuit simulation for multi-die interconnect analysis

7. Thermo-mechanical stress analysis of TSVS and micro-bumps in multi-die stacks

8. Physical verification

9. Extended design rule checking

10. Chip-level functional verification

11. Static timing analysis

12. IR/EM/SI and other electrical analysis

13. Assembly and yield

Major Points to Be Considered While Designing an IC Package with EDA Tools

Even though 3D integrated circuits show great benefits, there are several challenges for the adoption of
3D technology for future architecture design: Thermal management – The move from 2D to 3D design
could accentuate the thermal concerns due to the increased power density. To mitigate the thermal
impact, thermal-aware design techniques must be adopted for 3D architecture design. Design Tools and
methodologies – 3D integration technology will not be commercially viable without the support of EDA
tools and methodologies that allow architects and circuit designers to develop new architectures or
circuits using this technology. To efficiently exploit the benefits of 3D technologies, design tools and
methodologies to support 3D designs are imperative. Testing – One of the barriers to 3D technology
adoption is insufficient understanding of 3D testing issues and the lack of design-for-testability (DFT)
techniques for 3D ICs, which have remained largely unexplored in the research community.
Cadence Design Systems (India) Pvt Ltd

Mr. V.C. Patil, AE Director

Mr. Patil, joined us on this technological story with his expert views. As per Mr. Patil, there is a
disruptive change in consumers’ demands in electronics products. Consumers now want miniaturized
products with lots of functionality in a single gadget.This change in consumer requirements has driven
rapid evolution in technology capabilities and business necessities for system companies in the past
decade. In turn, semiconductor and chip designers have had to innovate at a phenomenal pace to keep
up. The relentless ask for electronic chips with increased performance and power targets, and the
growing demands from the computing and mobile industries has resulted in the development of three-
dimensional integrated circuit of 3D-IC, a design process integrating multiple dies in a single package.
Another key development that has added to the exponential rise in complexity of chip design is the
march towards advanced nodes. Today, designers are working with 14nm and 10nm nodes. 3D-ICs with
TSVs bring enormous possibilities to how a system can be built:

 Heterogeneous integration

 Improved performance

 Reduced power consumption

 Maximum functionality in a smaller form factor(end product miniaturization) to support

numerous applications in networking, graphics, mobile communications and networking.

The only way to meet technology requirements is through increased use of design automation, and
being able to complete the design virtually. Hence,EDA tools have a significant role to play in 3D-IC
design and packaging. Charting the design pathways; place and route; addressing stacking
considerations; floorplanning; TSV and microbump planning;and performance validation for signal
integrity, power, thermal, timing are some of the areas where EDA is critical. EDA tools are also needed
for final signoff verification that will need to include thermal, mechanical and power considerations in
addition to traditional design rule checking.

Talking about design considerations he said, though 3D-IC holds a lot of potential, it is still an evolving
methodology and there are number of design and verification challenges which need to be addressed.
Some of the challenges involved are as follows:

System-level exploration

Different D architectures need to be taken into consideration for evaluation at a very early stage to get
benefits from 3D-IC TSVs and make this technology cost-effective. System-level exploration for 3D-IC
TSV technology is a convergence of silicon and packaging with the design, making it possible to conceive
and design new architectures. Existing system-level exploration tools can provide early power, area, and
cost estimates, and they allow what-if explorations across architectures, silicon IP choices, and foundry
processes. However, to provide some guidance on trade-offs that system houses would have to make
between cost, power, and performance, these tools need to be extended to serve stacked die
implementations, package, and manufacturing considerations.

3D floor-planning

A TSV-aware 3D floor-planner must allocate optimized TSV resources with respect to logic gates as TSVs
can be very large compared to logic gates (they add more wire length and extra coupling, which is
mitigated by keep-out zones that add area).

3D implementation

A number of new considerations come into play when it comes to synthesis, placement, and routing for
3D-ICs. For instance, there are new layout rules that may be driven by features on adjacent die. The
back-side redistribution layer (RDL) is a new layout layer. And given their size, TSVs themselves are a
significant new layout feature. An implementation system that supports 3D-ICs must be made “double-
sided aware,” taking into account both the top and bottom of each die. This may call for a new modeling
and database infrastructure, TSV-specific tools, and support for a variety of stacking styles.

3D extraction and analysis

Extraction and analysis is quite complicated with 3D-ICs. Timing, signal integrity, power, and thermal
gradients must be analyzed across multiple die and take packaging into consideration. Existing
extraction and analysis tools must consider RLC parasitic for TSVs, micro-bumps, and interposer routing
and they must be made 3D-aware. When is the right time to sign off? What are the appropriate signoff
points? Can design rule checking (DRC) and layout-versus-schematics (LVS) run on the entire stack?
Should and can timing be verified for the entire stack? Is there any crosstalk between die? These are
some of the questions one needs to consider. Finally, for 3D-IC, electromagnetic interference (EMI) is a
potential concern and a consideration for analysis tools.

3D DFT

For 3D-ICs, one of the most critical factors is design for test (DFT). While wire-bonded systems-in-
package (SiPs) may have a few hundred interconnects, 3D-ICs may have thousands if not tens of
thousands of interconnects. Even a single defective TSV can render an entire stack unusable. If individual
TSVs have 99.9% yield, at least one defective TSV can be expected in a stack of 1,000 TSVs. To provide
test generation, the wrappers should support both the internal testing of each die as well as all the
inter-die interconnects logic and TSVs. In addition to the traditional fault models used for digital testing
(stuck-at, transition, stuck-open, bridge faults), 3D-ICs require specific interconnect fault models to test
the TSVs and micro-bumps. The package tool plays extremely important role. It should enable 3D DRC,
stacked die capability (such as multi-story building support), and, most importantly, should have
manufacturing-aware design rules embedded. Very complex IC placement configurations, heat flow
management considerations, and integrated electrical analysis are essential. For designers this means
that in addition to expanding EDA tools to be 3D-aware, they also have to start thinking in 3D.
Further he flashed light of Cadence EDA Tools. He said, even though 3D-IC technology has had
challenges such as lacking standards and supply chain, the good news is that 3D-IC enablement is
evolving. Cadence has been working closely with customers and ecosystem partners for the last six years
to develop a methodology for 3D-IC starting from planning to implementation, test, analysis,
verification, and ultimately signoff. Our 3D solution is validated and tested on several customer designs,
and includes:

 3D implementation (placement, optimization, routing) for custom and digital

 3D verification and analysis

 Design for test (DFT)

 IC/package co-design and system analysis

 System in Package (SiP) capability

 Required 3D-IC IP such as Wide I/O controller and PHY

 System-level exploration

3D ICs can bring in a lot of advantages, and can be used in a wide variety of applications.

 Lower costs are possible, because all functionality including analog and memory does not need
to move to advanced process nodes.

 It is easier to meet high interconnect speeds and bandwidth requirements, which will reach 100
Gbits/second for advanced memory technologies.

 3D ICs allow miniaturization, saving space on the board and in the end product. They’re ideal for
extremely compact mobile devices.

 3D ICs can reduce power because big drivers are no longer needed. A 3D stack can use small I/O
drivers with lower power. Further, reduced resistance-inductance-capacitance (RLC) helps
reduce power.

 Interconnect between packages is reduced, allowing for faster performance and a better power
profile.

 Time to market can be faster, thanks to modularity, the potential for “die reuse,” and the ability
to leave analog/RF at higher process nodes.

 Emerging technologies such as photonics or MEMS can potentially be integrated into 3D stacks.

Conclusion

3D ICs let design teams implement entire systems cost effectively in ONE package. For the most part,
existing IC implementation and analysis tools can be extended to comprehend a third dimension, and
allow 3D designers to rely on familiar and proven tools. Equally important is the availability of accurate
and complete manufacturing data and material characteristics provided to system and chip designers by
foundries, substrate, and packaging providers as well as OSATs. Ecosystem partners that work in relative
isolation on 2D ICs today will need to communicate and cooperate much more closely to design and
manufacture cost-effective 3D ICs. Exchange formats, interoperability standards, clarification of hand-off
responsibilities, may prove useful and will allow industry to be fully benefitted.