QuestaSim TCL Commands Cmds

ModelSim ®
Advanced Verification and Debugging
SE
Command Reference
Version 6.0b
Published: 15/Nov/04
CR-2
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ModelSim SE Command Reference

Technical support and updates CR-3
Technical support and updates

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CR-4
Where to find our documentation

ModelSim documentation is available from our website at www.model.com/support or in
the following formats and locations:
Document Format How to get it
ModelSim Installation & paper shipped with ModelSim

Licensing Guide
PDF select Help > Documentation; also available from the Support
page of our web site: www.model.com
ModelSim Quick Guide paper shipped with ModelSim

(command and feature
quick-reference) PDF select Help > Documentation, also available from the Support
ModelSim Tutorial PDF, HTML select Help > Documentation; also available from the Support
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Reference
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Foreign Language PDF, HTML select Help > Documentation

Interface Reference
Std_DevelopersKit User’s PDF www.model.com/support/documentation/BOOK/sdk_um.pdf
Manual
The Standard Developer’s Kit is for use with Mentor Graphics
QuickHDL.
Command Help ASCII type help [command name] at the prompt in the Transcript pane
Error message help ASCII type verror <msgNum> at the Transcript or shell prompt
Tcl Man Pages (Tcl HTML select Help > Tcl Man Pages, or find contents.htm in
manual) \modeltech\docs\tcl_help_html
Technotes HTML select Technotes dropdown on www.model.com/support

CR-5
Table of Contents
Technical support and updates CR-3 bookmark add wave CR-71
Where to find our documentation CR-4 bookmark delete wave CR-72
bookmark goto wave CR-73
Syntax and conventions (CR-9) bookmark list wave CR-74
bp CR-75
Documentation conventions CR-10
cd CR-78
File and directory pathnames CR-11
cdbg CR-79
Design object names CR-12
change CR-81
Wildcard characters CR-17
change_menu_cmd CR-83
ModelSim variables CR-17
check contention add CR-84
Simulation time units CR-18
check contention config CR-86
Comments in argument files CR-18
check contention off CR-87
Command shortcuts CR-18
check float add CR-88
Command history shortcuts CR-19
check float config CR-89
Numbering conventions CR-20
check float off CR-90
GUI_expression_format CR-22
check stable off CR-91
check stable on CR-92
Commands (CR-31)
checkpoint CR-93
Command reference table CR-32 compare add CR-94
.main clear CR-43 compare annotate CR-98
abort CR-44 compare clock CR-99
add button CR-45 compare configure CR-101
add dataflow CR-47 compare continue CR-103
add list CR-48 compare delete CR-104
add watch CR-51 compare end CR-105
add wave CR-52 compare info CR-106
add_menu CR-56 compare list CR-107
add_menucb CR-58 compare options CR-108
add_menuitem CR-59 compare reload CR-112
add_separator CR-60 compare reset CR-113
add_submenu CR-61 compare run CR-114
alias CR-62 compare savediffs CR-115
assertion fail CR-63 compare saverules CR-116
assertion pass CR-65 compare see CR-117
assertion report CR-67 compare start CR-119
batch_mode CR-69 compare stop CR-121
bd CR-70 compare update CR-122

CR-6 Table of Contents
configure CR-123 fcover save CR-175

context CR-127 find CR-176
coverage clear CR-128 force CR-180
coverage exclude CR-129 gdb dir CR-183
coverage reload CR-131 getactivecursortime CR-184
coverage report CR-132 getactivemarkertime CR-185
coverage save CR-135 help CR-186
dataset alias CR-136 history CR-187
dataset clear CR-137 lecho CR-188
dataset close CR-138 left CR-189
dataset info CR-139 log CR-191
dataset list CR-140 lshift CR-193
dataset open CR-141 lsublist CR-194
dataset rename CR-142 macro_option CR-195
dataset save CR-143 mem display CR-196
dataset snapshot CR-144 mem list CR-198
delete CR-146 mem load CR-199
describe CR-147 mem save CR-202
disablebp CR-148 mem search CR-204
disable_menu CR-149 modelsim CR-206
disable_menuitem CR-150 next CR-207
do CR-151 noforce CR-208
down CR-152 nolog CR-209
drivers CR-154 notepad CR-211
dumplog64 CR-155 noview CR-212
echo CR-156 nowhen CR-213
edit CR-157 onbreak CR-214
enablebp CR-158 onElabError CR-215
enable_menu CR-159 onerror CR-216
enable_menuitem CR-160 pause CR-217
environment CR-161 play CR-218
examine CR-162 pop CR-219
exit CR-166 power add CR-220
fcover clear CR-167 power report CR-221
fcover comment CR-168 power reset CR-222
fcover configure CR-169 precision CR-223
fcover reload CR-171 printenv CR-224
fcover report CR-173 profile clear CR-225

CR-7
profile interval CR-226 toggle add CR-279

profile off CR-227 toggle disable CR-281
profile on CR-228 toggle enable CR-282
profile option CR-229 toggle report CR-283
profile reload CR-230 toggle reset CR-284
profile report CR-231 transcribe CR-285
project CR-233 transcript CR-286
property list CR-234 transcript file CR-287
property wave CR-235 tssi2mti CR-288
push CR-237 unsetenv CR-289
pwd CR-238 up CR-290
quietly CR-239 vcd add CR-292
quit CR-240 vcd checkpoint CR-293
radix CR-241 vcd comment CR-294
readers CR-242 vcd dumpports CR-295
record CR-243 vcd dumpportsall CR-297
report CR-244 vcd dumpportsflush CR-298
restart CR-246 vcd dumpportslimit CR-299
restore CR-248 vcd dumpportsoff CR-300
resume CR-249 vcd dumpportson CR-301
right CR-250 vcd file CR-302
run CR-252 vcd files CR-304
sccom CR-254 vcd flush CR-306
scgenmod CR-258 vcd limit CR-307
search CR-260 vcd off CR-308
searchlog CR-262 vcd on CR-309
seetime CR-264 vcd2wlf CR-310
setenv CR-265 vcom CR-311
shift CR-266 vcover convert CR-319
show CR-267 vcover merge CR-320
simstats CR-268 vcover report CR-322
splitio CR-270 vcover stats CR-325
status CR-271 vdel CR-327
step CR-272 vdir CR-328
stop CR-273 verror CR-329
tb CR-274 vgencomp CR-330
tcheck_set CR-275 view CR-332
tcheck_status CR-277 virtual count CR-334

CR-8 Table of Contents
virtual define CR-335 wave create CR-397

virtual delete CR-336 wave edit CR-400
virtual describe CR-337 wave export CR-403
virtual expand CR-338 wave import CR-404
virtual function CR-339 wave modify CR-405
virtual hide CR-342 when CR-407
virtual log CR-343 where CR-412
virtual nohide CR-345 wlf2log CR-413
virtual nolog CR-346 wlf2vcd CR-415
virtual region CR-348 wlfman CR-416
virtual save CR-349 wlfrecover CR-420
virtual show CR-350 write cell_report CR-421
virtual signal CR-351 write format CR-422
virtual type CR-354 write list CR-424
vlib CR-356 write preferences CR-425
vlog CR-358 write report CR-426
vmake CR-369 write timing CR-427
vmap CR-370 write transcript CR-428
vopt CR-371 write tssi CR-429
vsim CR-373 write wave CR-431
vsim<info> CR-392
vsource CR-393 Index
wave CR-394

CR-9
Syntax and conventions

Chapter contents
Documentation conventions . . . . . . . . . . . . CR-10
File and directory pathnames . . . . . . . . . . . . CR-11
Design object names . . . . . . . . . . . . . . CR-12

Object name syntax . . . . . . . . . . . . . CR-12
SystemC class/structure/union member specification. . . . . CR-13
Specifying names . . . . . . . . . . . . . . CR-14
Escaping brackets and spaces in array slices . . . . . . . CR-15
Environment variables and pathnames . . . . . . . . CR-15
Name case sensitivity . . . . . . . . . . . . . CR-15
Extended identifiers . . . . . . . . . . . . . CR-16
Wildcard characters . . . . . . . . . . . . . . CR-17
ModelSim variables . . . . . . . . . . . . . . CR-17

Simulation time units . . . . . . . . . . . . . . CR-18
Comments in argument files . . . . . . . . . . . . CR-18
Command shortcuts . . . . . . . . . . . . . . CR-18

Command history shortcuts . . . . . . . . . . . . CR-19
Numbering conventions . . . . . . . . . . . . . CR-20

VHDL numbering conventions . . . . . . . . . . CR-20
Verilog numbering conventions . . . . . . . . . . CR-21
GUI_expression_format . . . . . . . . . . . . . CR-22
Expression typing . . . . . . . . . . . . . . CR-22
Expression syntax . . . . . . . . . . . . . . CR-23
Signal and subelement naming conventions . . . . . . . CR-27
Grouping and precedence . . . . . . . . . . . . CR-27
Concatenation of signals or subelements . . . . . . . . CR-27
Record field and SystemC class/structure/union members . . . CR-29
Searching for binary signal values in the GUI . . . . . . CR-29

CR-10 Syntax and conventions
Documentation conventions
This manual uses the following conventions to define ModelSim command syntax.
Syntax notation Description
< > angled brackets surrounding a syntax item indicate a user-

defined argument; do not enter the brackets in commands
[ ] square brackets generally indicate an optional item; if the
brackets surround several words, all must be entered as a group;
the brackets are not entereda
{ } braces indicate that the enclosed expression contains one or

more spaces yet should be treated as a single argument, or that
the expression contains square brackets for an index; for either
situation, the braces are entered
... an ellipsis indicates items that may appear more than once; the
ellipsis itself does not appear in commands
| the vertical bar indicates a choice between items on either side

of it; do not include the bar in the command
monospaced type monospaced type is used in command examples
# comments included with commands are preceded by the number

sign (#); useful for adding comments to DO files (macros)
a. One exception to this rule is when you are using Verilog syntax to designate an array
slice. For example,
add wave {vector1[4:0]}
The square brackets in this case denote an index. The braces prevent the Tcl interpreter
from treating the text within the square brackets as a Tcl command.
Note: Neither the prompt at the beginning of a line nor the <Enter> key that ends a line
is shown in the command examples.

File and directory pathnames CR-11
File and directory pathnames

Several ModelSim commands have arguments that point to files or directories. For
example, the -y argument to vlog specifies the Verilog source library directory to search for
undefined modules. Spaces in file pathnames must be escaped or the entire path must be
enclosed in quotes. For example:
vlog top.v -y C:/Documents\ and\ Settings/projects/dut
or
vlog top.v -y "C:/Documents and Settings/projects/dut"

Design object names

Design objects are organized hierarchically. Each of the following objects creates a new
level in the hierarchy:
• VHDL
component instantiation statement, block statement, and package
• Verilog
module instantiation, named fork, named begin, task and function
• SystemC
module instantiation
Object name syntax

The syntax for specifying object names in ModelSim is as follows:
[<datasetName><datasetSeparator>][<pathSeparator>][<hierarchicalPath>]<obje
ctName>[<elementSelection>]
where
datasetName
is the logical name of the WLF file in which the object exists. The currently active
simulation is the “sim” dataset. Any loaded WLF file is referred to by the logical name
specified when the WLF file was loaded. See Chapter 8 - WLF files (datasets) and
virtuals for more information.
datasetSeparator
is the character used to terminate the dataset name. The default is ’:’, though a different
character (other than ’\’) may be specified as the dataset separator via the
DatasetSeparator (UM-531) variable in the modelsim.ini file. The default is ':'. This
character must be different than the pathSeparator character.
pathSeparator
is the character used to separate hierarchical object names. Normally, '/' is used for
VHDL and '.' is used for Verilog, although other characters (except '\') may be specified
via the PathSeparator (UM-533) variable in the modelsim.ini file. This character must be
different than the datasetSeparator. Both '.' and '/' can be used for SystemC.
hierarchicalPath
is a set of hierarchical instance names separated by a path separator and ending in a path
separator prior to the objectName. For example, /top/proc/clk.
objectName
is the name of an object in a design.
elementSelection
indicates some combination of the following:
Array indexing - Single array elements are specified using either parentheses "()" or
square brackets "[]" around a single number.
Array slicing - Slices (or part-selects) of arrays are specified using either parentheses "()"
or square brackets "[]" around a range specification. A range is two numbers separated
by one of the following: " to ", " downto ", ":". See "Escaping brackets and spaces in array

slices" (CR-15) for important information about using square brackets in ModelSim
commands.
Record field selection - A record field is specified using a period "." followed by the
name of the field.
C++ class, structure, and union member selection - A class, structure, or union member
is specified using the record field specification syntax, described just above.
SystemC class/structure/union member specification

You can specify members of SystemC structures and classes using HDL record syntax. The
syntax for specifying members of a base class using ModelSim is different than C++. In
C++, it is not necessary to specify the base class:
<instance>.<base_member>
Whereas, in ModelSim you must include the name of the base class:
<instance>.<base>.<base_member>
Example
Let’s say you have a base class and a descendant class:
class dog
{
private:
int value;
};
class beagle : public dog

{
private:
int value;
dog d;
};
You have an sc_signal<> of type beagle somewhere in your code:

sc_signal<beagle> spot;
Legal names for viewing this signal are:

spot
spot.*
spot.value
spot.dog
spot.dog.*
spot.dog.value
Now, to examine the member value of the base class dog, you would type:
exa spot.dog.value
To examine the member value of member d, you would type:

exa spot.d.value
To examine the member value, you would type:

exa spot.value

Specifying names
We distinguish between four "types" of object names: simple, relative, fully-rooted, and
absolute.
A simple name does not contain any hierarchy. It is simply the name of an object (e.g., clk
or data[3:0]) in the current context.
A relative name does not start with a path separator and may or may not include a dataset
name or a hierarchical path (e.g., u1/data or view:clk). A relative name is relative to the
current context in the current or specified dataset.
A fully-rooted name starts with a path separator and includes a hierarchical path to an
object (e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-level
design unit name can be unspecified (e.g., /u1/clk). In this case, the first top-level instance
in the design is assumed.
An absolute name is an exactly specified hierarchical name containing a dataset name and
a fully rooted name (e.g., sim:/top/u1/clk).
The current dataset is used when accessing objects where a dataset name is not specified as
part of the name. The current dataset is determined by the dataset currently selected in the
Structure window or by the last dataset specified in an environment command (CR-161).
The current context in the current or specified dataset is used when accessing objects with
relative or simple names. The current context is either the current process, if any, or the
current instance if there is no current process or the current process is not in the current
instance. The situation of the current process not being in the current instance can occur,
for example, by selecting a different instance in the Structure tab or by using the
environment command (CR-161) to set the current context to a different instance.
Here are some examples of object names and what they specify:
Syntax Description
clk specifies the object clk in the current context
/top/clk specifies the object clk in the top-level design unit.
/top/block1/u2/clk specifies the object clk, two levels down from the
top-level design unit
block1/u2/clk specifies the object clk, two levels down from the
current context
array_sig[4] specifies an index of an array object
{array_sig(1 to 10)} specifies a slice of an array object in VHDL or

SystemC; see "Escaping brackets and spaces in
array slices" (CR-15) for more information
{mysignal[31:0]} specifies a slice of an array object in Verilog or

SystemC; see "Escaping brackets and spaces in
array slices" (CR-15) for more information
record_sig.field specifies a field of a record, a C++ class or structure

member, or a C++ base class

Escaping brackets and spaces in array slices

Because ModelSim is a Tcl-based tool, you must use curly braces (’{}’) to "escape" square
brackets and spaces when specifying array slices. For example:
toggle add {data[3:0]} or
toggle add {data(3 to 0)}
For complete details on Tcl syntax, see "Tcl command syntax" (UM-474).
Further details
As a Tcl-based tool, ModelSim commands follow Tcl syntax. One problem people
encounter with ModelSim commands is the use of square brackets (’[]’) or spaces when
specifying array slices. As shown on the previous page, square brackets are used to specify
slices of arrays (e.g., data[3:0]). However, in Tcl, square brackets signify command
substitution. Consider the following example:
set aluinputs [find -in alu/*]
ModelSim evaluates the find command first and then sets variable aluinputs to the result
of the find command. Obviously you don’t want this type of behavior when specifying an
array slice, so you would use curly brace escape characters:
add wave {/s/abc/data_in[10:1]}
You must also use the escape characters if using VHDL syntax with spaces:
add wave {/s/abc/data_in(10 downto 1)}
Environment variables and pathnames

You can substitute environment variables for pathnames in any argument that requires a
pathname. For example:
vlog -v $lib_path/und1
Assuming you have defined $lib_path on your system, vlog will locate the source library
file und1 and search it for undefined modules. See "Environment variables" (UM-521) for
more information.
Note: Environment variable expansion does not occur in files that are referenced via the
-f argument to vcom, vlog, or vsim.
Name case sensitivity

Name case sensitivity is different for VHDL and Verilog. VHDL names are not case
sensitive except for extended identifiers in VHDL 1076-1993 or later. In contrast, all
Verilog names are case sensitive.
Names in ModelSim commands are case sensitive when matched against case sensitive
identifiers, otherwise they are not case sensitive. SystemC names are case sensitive.

Extended identifiers
The following are supported formats for extended identifiers for any command that takes
an identifier.
{\ext ident!\ } # Note that trailing space before closing brace is required
\\ext\ ident\!\\ # All non-alpha characters escaped

Wildcard characters CR-17
Wildcard characters
Wildcard characters can be used in HDL object names in some simulator commands.
Conventions for wildcards are as follows:
Syntax Description
* matches any sequence of characters

? matches any single character
[] matches any one of the enclosed characters; a

hyphen can be used to specify a range (for
example, a-z, A-Z, 0-9); can be used only with
the find command (CR-176)
You can use the WildcardFilter Tcl preference variable to filter matching objects for the
add wave, add log, add list, and find commands.
Note: A wildcard character will never match a path separator. For example, /dut/* will
match /dut/siga and /dut/clk. However, /dut* won’t match either of those.
ModelSim variables
ModelSim variables can be referenced in simulator commands by preceding the name of
the variable with the dollar sign ($) character. ModelSim uses global Tcl variables for
simulator state variables, simulator control variables, simulator preference variables, and
user-defined variables (see "Preference variables located in Tcl files" (UM-540) for more
information).
See Appendix B - ModelSim variables in the User’s Manual for more information on
variables.
The report command (CR-244) returns a list of current settings for either the simulator state
or simulator control variables.

Simulation time units

You can specify the time unit for delays in all simulator commands that have time
arguments. For example:
force clk 1 50 ns, 1 100 ns -repeat 1 us
run 2 ms
Note that all the time units in a ModelSim command need not be the same.
Unless you specify otherwise as in the examples above, simulation time is always
expressed using the resolution units that are specified by the UserTimeUnit variable. See
UserTimeUnit (UM-534).
By default, the specified time units are assumed to be relative to the current time unless the
value is preceded by the character @, which signifies an absolute time specification.
Comments in argument files

Argument files may be loaded with the -f <filename> argument of the vcom, vlog, sccom
and vsim commands. The -f <filename> argument specifies a file that contains more
command line arguments.
Comments within the argument files follow these rules:
• All text in a line beginning with // to its end is treated as a comment.
• All text bracketed by /* ... */ is treated as a comment.
Also, program arguments can be placed on separate lines in the argument file, with the
newline characters treated as space characters. There is no need to put '\' at the end of each
line.
Command shortcuts
• You may abbreviate command syntax, but there’s a catch — the minimum number of
characters required to execute a command are those that make it unique. Remember, as
we add new commands some of the old shortcuts may not work. For this reason
ModelSim does not allow command name abbreviations in macro files. This minimizes
your need to update macro files as new commands are added.
• Multiple commands may be entered on one line if they are separated by semi-colons (;).
For example:
ModelSim> vlog -nodebug=ports level3.v level2.v ; vlog -nodebug top.v
The return value of the last function executed is the only one printed to the transcript.
This may cause some unexpected behavior in certain circumstances. Consider this
example:
vsim -c -do "run 20 ; simstats ; quit -f" top
You probably expect the simstats results to display in the Transcript window, but they
will not, because the last command is quit -f. To see the return values of intermediate
commands, you must explicitly print the results. For example:
vsim -do "run 20 ; echo [simstats]; quit -f" -c top

Command shortcuts CR-19
Command history shortcuts

The simulator command history may be reviewed, or commands may be reused, with these
shortcuts at the ModelSim/VSIM prompt:
Shortcut Description
!! repeats the last command
!n repeats command number n; n is the VSIM prompt number (e.g.,
for this prompt: VSIM 12>, n =12)
!abc repeats the most recent command starting with "abc"
^xyzâb^ replaces "xyz" in the last command with "ab"
up and down arrows scrolls through the command history with the keyboard arrows
click on prompt left-click once on a previous ModelSim or VSIM prompt in the
transcript to copy the command typed at that prompt to the active
cursor
his or history shows the last few commands (up to 50 are kept)

Numbering conventions
Numbers in ModelSim can be expressed in either VHDL or Verilog style. You can use two
styles for VHDL numbers and one for Verilog.
VHDL numbering conventions
VHDL Style 1
The first of two VHDL number styles is:
[ - ] [ radix # ] value [ # ]
Element Description
- indicates a negative number; optional
radix can be any base in the range 2 through 16 (2, 8, 10, or 16); by default,
numbers are assumed to be decimal; optional
value specifies the numeric value, expressed in the specified radix; required
# is a delimiter between the radix and the value; the first # sign is
required if a radix is used, the second is always optional
A ‘-’ can also be used to designate a "don’t care" element when you search for a signal value
or expression in the List or Wave window. If you want the ‘-’ to be read as a "don’t care"
element, rather than a negative sign, be sure to enclose the number in double quotes. For
instance, you would type "-0110--" as opposed to -0110--. If you don’t include the double
quotes, ModelSim will read the ‘-’ as a negative sign.
Examples
16#FFca23#
2#11111110
-23749
VHDL Style 2
The second VHDL number style is:
base "value"
Element Description
base specifies the base; binary: B, octal: O, hex: X; required

value specifies digits in the appropriate base with optional underscore
separators; default is decimal; required
Examples
B"11111110"
X"FFca23"

Numbering conventions CR-21
Searching for VHDL arrays in the Wave and List windows

Searching for signal values in the Wave or List window may not work correctly for VHDL
arrays if the target value is in decimal notation. You may get an error that the value is of
incompatible type. Since VHDL does not have a radix indicator for decimal, the target
value may get misinterpreted as a scalar value. Prefixing the value with the Verilog notation
'd should eliminate the problem, even if the signal is VHDL.
Verilog numbering conventions

Verilog numbers are expressed in the style:
[ - ] [ size ] [ base ] value
Element Description
- indicates a negative number; optional

size the number of bits in the number; optional
base specifies the base; binary: ‘b or ‘B, octal: ‘o or ‘O, decimal: ‘d or ‘D,
hex: ‘h or ‘H; optional
value specifies digits in the appropriate base with optional underscore

separators; default is decimal; required
A ‘-’ can also be used to designate a "don’t care" element when you search for a signal value
or expression in the List or Wave windows. If you want the ‘-’ to be read as a "don’t care"
element, rather than a negative sign, be sure to enclose the number in double quotes. For
instance, you would type "-0110--" as opposed to 7'b-0110--. If you don’t include the
double quotes, ModelSim will read the ‘-’ as a negative sign.
Examples
’b11111110 8’b11111110
’Hffca23 21’H1fca23
-23749
DOS pathnames require a backslash (\), but ModelSim will accept either a backslash or the
forward slash (/). It does this because by default ModelSim PE uses backslashes as
pathname separators. Therefore it cannot recognize extended identifiers.
You can change this behavior so that backslashes on comment lines are used for extended
identifiers, but then you can only use forward slashes when you need pathname delimiters.
To do this, "uncomment" the following line in the modelsim.ini file and set its value to zero.
BackslashesArePathnameDelimiters = 0
This will allow command lines that can reference signals, variables, and design unit names
that use extended identifiers; for example:
examine \clock 2x\

GUI_expression_format
The GUI_expression_format is an option of several simulator commands that operate
within the ModelSim GUI environment. The expressions help you locate and examine
objects within the List and Wave windows (expressions may also be used through the Edit
> Search menu in both windows). The commands that use the expression format are:
compare add (CR-94), compare clock (CR-99), compare configure (CR-101), configure
(CR-123), down (CR-152), examine (CR-162), left (CR-189), right (CR-250), searchlog (CR-
262), up (CR-290), virtual function (CR-339), and virtual signal (CR-351)
Expression typing
GUI expressions are typed. The supported types consist of the following scalar and array
types.
Scalar types
The scalar types are as follows: boolean, integer, real, time (64-bit integer), enumeration,
and signal state. Signal states are represented by the nine VHDL std_logic states: ’U’ ’X’
’0’ ’1’ ’Z’ ’W’ ’L’ ’H’ and ’-’.
Verilog states 0, 1, x, and z are mapped into these states and the Verilog strengths are
ignored. Conversion is done automatically when referencing Verilog nets or registers.
SystemC scalar types supported are: all the C/C++ types except class, structure, union, and
array, as well as SystemC types sc_logic and sc_bit.
Array types
The supported array types are signed and unsigned arrays of signal states. This would
correspond to the VHDL std_logic_array type. Verilog registers are automatically
converted to these array types. The array type can be treated as either UNSIGNED or
SIGNED, as in the IEEE std_logic_arith package. Normally, referencing a signal array
causes it to be treated as UNSIGNED by the expression evaluator; to cause it to be treated
as SIGNED, use casting as described below. Numeric operations supported on arrays are
performed by the expression evaluator via ModelSim’s built-in numeric_standard (and
similar) package routines. The expression evaluator selects the appropriate numeric routine
based on SIGNED or UNSIGNED properties of the array arguments and the result.
The enumeration types supported are any VHDL enumerated type. Enumeration literals
may be used in the expression as long as some variable of that enumeration type is
referenced in the expression. This is useful for sub-expressions of the form:
(/memory/state == reading)
The supported SystemC aggregate types are the C/C++ array types: union, class, structure,
and array. Also supported are the SystemC array types: sc_bv<w>, sc_lv<w>, sc_int<w>,
etc.

Expression syntax
GUI expressions generally follow C-language syntax, with both VHDL-specific and
Verilog-specific conventions supported. These expressions are not parsed by the Tcl parser,
and so do not support general Tcl; parentheses should be used rather than curly braces.
Procedure calls are not supported.
A GUI expression can include the following elements: Tcl macros, constants, array
constants, variables, array variables, signal attributes, operators, and casting.
Tcl macros
Macros are useful for pre-defined constants or for entire expressions that have been
previously saved. The substitution is done only once, when the expression is first parsed.
Macro syntax is:
$<name>
Substitutes the string value of the Tcl global variable <name>.
Constants
Type Values
boolean value true false TRUE FALSE
integer [0-9]+
real number <int>|([<int>].<int>[exp]) where the optional [exp] is: (e|E)[+|-][0-

9]+
time integer or real optionally followed by time unit
enumeration VHDL user-defined enumeration literal
single bit constants expressed as any of the following:

0 1 x X z Z U H L W ’U’ ’X’ ’0’ ’1’ ’Z’ ’W’ ’L’ ’H’ ’-’ 1’b0 1’b1
Array constants, expressed in any of the following formats
Type Values
VHDL # notation <int>#<alphanum>[#]

Example: 16#abc123#
VHDL bitstring "(U|X|0|1|Z|W|L|H|-)*"
Example: "11010X11"
Verilog notation [-][<int>]’(b|B|o|O|d|D|h|H) <alphanum>

(where <alphanum> includes 0-9, a-f, A-F, and ’-’)
Example: 12’hc91 (This is the preferred notation because it removes
the ambiguity about the number of bits.)
Based notation 0x..., 0X..., 0o..., 0O..., 0b..., OB...

ModelSim automatically zero fills unspecified upper bits.

Variables
Variable Type
Name of a signal The name may be a simple name, a VHDL or Verilog style extended
identifier, or a VHDL or Verilog style path. The signal must be one
of the following types:
-- VHDL signal of type INTEGER, REAL, or TIME
-- VHDL signal of type std_logic or bit
-- VHDL signal of type user-defined enumeration
-- Verilog net, Verilog register, Verilog integer, or Verilog real
-- SystemC primitive channels of type scalar (e.g. bool, int, etc.)
NOW Returns the value of time at the current location in the WLF file as
the WLF file is being scanned (not the most recent simulation time).
Array variables
Variable Type
Name of a signal -- VHDL signals of type bit_vector or std_logic_vector

-- Verilog register
-- Verilog net array
-- SystemC primitive channels of type vector (e.g. sc_bv, sc_int,
etc.)
A subrange or index may be specified in either VHDL or Verilog
syntax. Examples: mysignal(1 to 5), mysignal[1:5], mysignal (4),
mysignal [4]
Signal attributes
<name>’event
<name>’rising
<name>’falling
<name>’delayed()
<name>’hasX
The ’delayed attribute lets you assign a delay to a VHDL signal. To assign a delay to a
signal in Verilog, use “#” notation in a sub-expression (e.g., #-10 /top/signalA).
The hasX attribute lets you search for signals, nets, or registers that contains an X
(unknown) value.
See "Examples" (CR-26) below for further details on ’delayed and ’hasX.

Operators
Operator Description Operator Description

&& boolean and sll/SLL shift left logical
|| boolean or sla/SLA shift left arithmetic
! boolean not srl/SRL shift right logical

== equal sra/SRA shift right
arithmetic
!= not equal ror/ROR rotate right
=== exact equal rol/ROL rotate left
!== exact not equal + arithmetic add
< less than - arithmetic subtract
<= less than or equal * arithmetic multiply
> greater than / arithmetic divide

>= greater than or equal mod/MOD arithmetic modulus
not/NOT/~ unary bitwise rem/REM arithmetic

inversion remainder
and/AND/& bitwise and |<vector_expr> OR reduction
nand/NAND bitwise nand ^<vector_expr> XOR reduction
or/OR/| bitwise or
nor/NOR bitwise nor
xor/XOR bitwise xor
xnor/XNOR bitwise xnor
Note: Arithmetic operators use the std_logic_arith package.

Casting
Casting Description
(bool) convert to boolean
(boolean) convert to boolean
(int) convert to integer

(integer) convert to integer
(real) convert to real
(time) convert to 64-bit integer
(std_logic) convert to 9-state signal value

(signed) convert to signed vector
(unsigned) convert to unsigned vector
(std_logic_vector) convert to unsigned vector
Examples
/top/bus & $bit_mask
This expression takes the bitwise AND function of signal /top/bus and the array constant
contained in the global Tcl variable bit_mask.
clk’event && (/top/xyz == 16’hffae)
This expression evaluates to a boolean true when signal clk changes and signal /top/xyz
is equal to hex ffae; otherwise is false.
clk’rising && (mystate == reading) && (/top/u3/addr == 32’habcd1234)
Evaluates to a boolean true when signal clk just changed from low to high and signal
mystate is the enumeration reading and signal /top/u3/addr is equal to the specified 32-bit
hex constant; otherwise is false.
(/top/u3/addr and 32’hff000000) == 32’hac000000
Evaluates to a boolean true when the upper 8 bits of the 32-bit signal /top/u3/addr equals
hex ac.
/top/signalA'delayed(10ns)
This expression returns /top/signalA delayed by 10 ns.
/top/signalA'delayed(10 ns) && /top/signalB
This expression takes the logical AND of a delayed /top/signalA with /top/signalB.
virtual function { (#-10 /top/signalA) && /top/signalB}
mySignalB_AND_DelayedSignalA
This evaluates /top/signalA at 10 simulation time steps before the current time, and takes
the logical AND of the result with the current value of /top/signalB. The '#' notation uses
positive numbers for looking into the future, and negative numbers for delay. This
notation does not support the use of time units.

((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode == writing)
Evaluates to a boolean true when WLF file time is between 23 and 54 microseconds, clk
just changed from low to high, and signal mode is enumeration writing.
searchlog -expr {dbus'hasX} {0 ns} dbus
Searches for an ’X’ in dbus. This is equivalent to the expression: {dbus(0) == 'x' ||
dbus(1) == 'x'} . . .. This makes it possible to search for X values without having to write
a type specific literal.
Signal and subelement naming conventions

ModelSim supports naming conventions for VHDL and Verilog signal pathnames, VHDL
array indexing, Verilog bit selection, VHDL subrange specification, and Verilog part
selection. All supported naming conventions for VHDL and Verilog are valid for SystemC
designs.
Examples in Verilog and VHDL syntax:
top.chip.vlogsig
/top/chip/vhdlsig
vlogsig[3]
vhdlsig(9)
vlogsig[5:2]
vhdlsig(5 downto 2)
All of the above examples are valid for SystemC.
Grouping and precedence

Operator precedence generally follows that of the C language, but we recommend liberal
use of parentheses.
Concatenation of signals or subelements

Elements in the concatenation that are arrays are expanded so that each element in the array
becomes a top-level element of the concatenation. But for elements in the concatenation
that are records, the entire record becomes one top-level element in the result. To specify
that the records be broken down so that their subelements become top-level elements in the
concatenation, use the concat_flatten directive. Currently we do not support leaving full
arrays as elements in the result. (Please let us know if you need that option.)
If the elements being concatenated are of incompatible base types, a VHDL-style record
will be created. The record object can be expanded in the Objects and Wave windows just
like an array of compatible type elements.
Concatenation syntax for VHDL

<signalOrSliceName1> & <signalOrSliceName2> & ...
Concatenation syntax for Verilog

&{<signalOrSliceName1>, <signalOrSliceName2>, ... }
&{<count>{<signalOrSliceName1>}, <signalOrSliceName2>, ... }
Note that the concatenation syntax begins with "&{" rather than just "{". Repetition
multipliers are supported, as illustrated in the second line. The repetition element itself may
be an arbitrary concatenation subexpression.

Concatenation directives
A concatenation directive (as illustrated below) can be used to constrain the resulting array
range of a concatenation or influence how compound objects are treated. By default, the
concatenation will be created with a descending index range from (n-1) downto 0, where n
is the number of elements in the array.
(concat_range 31:0)<concatenationExpr> # Verilog syntax
(concat_range (31:0))<concatenationExpr> # Also Verilog syntax
(concat_range (31 downto 0))<concatenationExpr> # VHDL syntax
The concat_range directive completely specifies the index range.
(concat_ascending) <concatenationExpr>
The concat_ascending directive specifies that the index start at zero and increment
upwards.
(concat_flatten) <concatenationExpr>
The concat_flatten directive flattens the signal structure hierarchy.
(concat_noflatten) <concatenationExpr>
The concat_noflatten directive groups signals together without merging them into one
big array. The signals become elements of a record and retain their original names. When
expanded, the new signal looks just like a group of signals. The directive can be used
hierarchically with no limits on depth.
(concat_sort_wild_ascending) <concatenationExpr>
The concat_sort_wild_ascending directive gathers signals by name in ascending order
(the default is descending).
(concat_reverse) <concatenationExpr>
The concat_reverse directive reverses the bits of the concatenated signals.
Examples
&{ "mybusbasename*" }
Gathers all signals in the current context whose names begin with "mybusbasename",
sorts those names in descending order, and creates a bus with index range (n-1) downto
0, where n is the number of matching signals found. (Note that it currently does not derive
the index name from the tail of the one-bit signal name.)
(concat_range 13:4)&{ "mybusbasename*" }
Specifies the index range to be 13 downto 4, with the signals gathered by name in
descending order.
(concat_ascending)&{ "mybusbasename*" }
Specifies an ascending range of 0 to n-1, with the signals gathered by name in descending
order.
(concat_ascending)((concat_sort_wild_ascending)&{"mybusbasename*" })
Specifies an ascending range of 0 to n-1, with the signals gathered by name in ascending
order.
(concat_reverse)(bus1 & bus2)
Specifies that the bits of bus1 and bus2 be reversed in the output virtual signal.

Record field and SystemC class/structure/union members

Arbitrarily-nested arrays and records are supported, but operators will only operate on one
field at a time. That is, the expression {a == b} where a and b are records with multiple
fields, is not supported. This would have to be expressed as:
{(a.f1 == b.f1) && (a.f2 == b.f2)...}
Examples:
vhdlsig.field1
vhdlsig.field1.subfield1
vhdlsig.(5).field3
vhdlsig.field4(3 downto 0)
Searching for binary signal values in the GUI

When you use the GUI to search for signal values displayed in 4-state binary radix, you
should be aware of how ModelSim maps between binary radix and std_logic. The issue
arises because there is no “un-initialized” value in binary, while there is in std_logic. So,
ModelSim relies on mapping tables to determine whether a match occurs between the
displayed binary signal value and the underlying std_logic value.
This matching algorithm applies only to searching via the GUI. It does not apply to VHDL
or Verilog testbenches.
For comparing VHDL std_logic/std_ulogic objects, ModelSim uses the table shown below.
An entry of “0” in the table is “no match”; an entry of “1” is a “match”; an entry of “2” is
a match only if you set the Tcl variable STDLOGIC_X_MatchesAnything to 1. Note that
X will match a U, and - will match anything.
Search Matches as follows:

Entry
U X 0 1 Z W L H -
U 1 1 0 0 0 0 0 0 1
X 1 1 2 2 2 2 2 2 1
0 0 2 1 0 0 0 1 0 1
1 0 2 0 1 0 0 0 1 1
Z 0 2 0 0 1 0 0 0 1
W 0 2 0 0 0 1 0 0 1
L 0 2 1 0 0 0 1 0 1
H 0 2 0 1 0 0 0 1 1
- 1 1 1 1 1 1 1 1 1

For comparing Verilog net values, ModelSim uses the table shown below. An entry of “2”
is a match only if you set the Tcl variable “VLOG_X_MatchesAnything” to 1.
Search Matches as follows:

Entry
0 1 Z X
0 1 0 0 2
1 0 1 0 2
Z 0 0 1 2
X 2 2 2 1
This table also applies to SystemC types: sc_bit, sc_bv, sc_logic, sc_int, sc_uint, sc_bigint,
sc_biguint.

CR-31
Commands
Chapter contents
Command reference table . . . . . . . . . . . . . CR-32
The commands here are entered either in macro files or on the command line of the Main
window. Some commands are automatically entered on the command line when you use
the ModelSim graphical user interface.
Note that in addition to the simulation commands documented in this section, you can use
the Tcl commands described in the Tcl man pages (use the Main window menu selection:
Help > Tcl Man Pages).
Command syntax
See "Syntax and conventions" (CR-9) for complete command syntax information.
Note: ModelSim commands are case sensitive. Type them as they are shown in this
reference.

CR-32 Command reference table
Command reference table

The following table provides a brief description of each ModelSim command. Command
details, arguments, and examples can be found at the page numbers given in the Command
name column.
Command name Action
.main clear (CR-43) clears the Main window transcript

abort (CR-44) halts the execution of a macro file interrupted by a breakpoint or error
add button (CR-45) adds a user-defined button to the Main window button bar
add dataflow (CR-47) adds the specified object to the Dataflow window
add list (CR-48) lists VHDL signals and variables, and Verilog nets and registers, and their
values in the List window
add log also known as the log command; see log (CR-191)
add watch (CR-51) adds signals or variables to the Monitor window
add wave (CR-52) adds VHDL signals and variables, and Verilog nets and registers to the Wave
window
add_menu (CR-56) adds a menu to the menu bar of the specified window, using the specified
menu name
add_menucb (CR-58) creates a checkbox within the specified menu of the specified window
add_menuitem (CR-59) creates a menu item within the specified menu of the specified window
add_separator (CR-60) adds a separator as the next item in the specified menu path in the specified
window
add_submenu (CR-61) creates a cascading submenu within the specified menu path of the specified
window
alias (CR-62) creates a new Tcl procedure that evaluates the specified commands
assertion fail (CR-63) configures fail tracking for PSL assertions
assertion pass (CR-65) configures pass tracking for PSL assertions
assertion report (CR-67) produces a textual summary of PSL assertion results

batch_mode (CR-69) returns a 1 if ModelSim is operating in batch mode, otherwise returns a 0
bd (CR-70) deletes a breakpoint
bookmark add wave (CR-71) adds a bookmark to the specified Wave window
bookmark delete wave (CR-72) deletes bookmarks from the specified Wave window
bookmark goto wave (CR-73) zooms and scrolls a Wave window using the specified bookmark

Command reference table CR-33
Command name Action
bookmark list wave (CR-74) displays a list of available bookmarks
bp (CR-75) sets a breakpoint

cd (CR-78) changes the ModelSim local directory to the specified directory
cdbg (CR-79) provides command-line equivalents of the menu options that are available for
"C Debug" (UM-399)
change (CR-81) modifies the value of a VHDL variable or Verilog register variable
change_menu_cmd (CR-83) changes the command to be executed for a specified menu item label, in the
specified menu, in the specified window
check contention add (CR-84) enables contention checking for the specified nodes
check contention config (CR-86) writes checking messages to a file
check contention off (CR-87) disables contention checking for the specified nodes
check float add (CR-88) enables float checking for the specified nodes
check float config (CR-89) writes checking messages to a file
check float off (CR-90) disables float checking for the specified nodes
check stable off (CR-91) disables stability checking
check stable on (CR-92) enables stability checking on the entire design
checkpoint (CR-93) saves the state of your simulation
compare add (CR-94) compares signals in a reference design against signals in a test design
compare annotate (CR-98) marks a compare difference as "ignore" or tags it with a text message
compare clock (CR-99) defines a clock to be used with clocked-mode comparisons
compare configure (CR-101) modifies options for compare signals or regions
compare continue (CR-103) continues difference computation that had been suspended
compare delete (CR-104) deletes a signal or region from the current comparison
compare end (CR-105) closes the currently open comparison
compare info (CR-106) lists the results of the comparison
compare list (CR-107) lists all the compare add commands currently in effect
compare options (CR-108) sets defaults for options used in other compare commands
compare reload (CR-112) reloads a comparison previously saved with the compare savediffs command
compare reset (CR-113) clears the current compare differences

compare run (CR-114) runs the comparison on selected signals

Command name Action
compare savediffs (CR-115) saves comparison differences to a file that can be reloaded later
compare saverules (CR-116) saves comparison setup information to a file that can be reloaded later
compare see (CR-117) displays a comparison difference in the Wave window
compare start (CR-119) starts a new dataset comparison
compare stop (CR-121) halts active difference computation

compare update (CR-122) updates the comparison differences
configure (CR-123) invokes the List or Wave widget configure command for the current default
List or Wave window
context (CR-127) provides several operations on a context’s name
coverage clear (CR-128) clears all coverage data obtained during previous run commands
coverage exclude (CR-129) loads an exclusion filter file; or, allows you to exclude specific
coverage reload (CR-131) seeds the coverage statistics with the output of a previous coverage save
command
coverage report (CR-132) produces a textual output of the coverage statistics that have been gathered up
to this point
coverage save (CR-135) saves current coverage statistics to a file that can be reloaded later, preserving
instance-specific information
dataset alias (CR-136) assigns an additional name to a dataset
dataset clear (CR-137) clears the current simulation WLF file
dataset close (CR-138) closes a dataset
dataset info (CR-139) reports information about the specified dataset
dataset list (CR-140) lists the open dataset(s)

dataset open (CR-141) opens a dataset and references it by a logical name
dataset rename (CR-142) changes the logical name of an opened dataset
dataset save (CR-143) saves data from the current WLF file to a specified file
dataset snapshot (CR-144) saves data from the current WLF file at a specified interval
delete (CR-146) removes objects from either the List or Wave window
describe (CR-147) displays information about the specified HDL object

disablebp (CR-148) turns off breakpoints and when commands
disable_menu (CR-149) disables the specified menu within the specified window

Command name Action
disable_menuitem (CR-150) disables the specified menu item within the specified menu path of the
specified window
do (CR-151) executes commands contained in a macro file

down (CR-152) searches for signal transitions or values in the specified List window
drivers (CR-154) displays in the Main window the current value and scheduled future values
for all the drivers of a specified VHDL signal or Verilog net
dumplog64 (CR-155) dumps the contents of the vsim.wlf file in a readable format
echo (CR-156) displays a specified message in the Main window

edit (CR-157) invokes the editor specified by the EDITOR environment variable
enablebp (CR-158) turns on breakpoints and when commands turned off by the disablebp
command (CR-148)
enable_menu (CR-159) enables a previously-disabled menu
enable_menuitem (CR-160) enables a previously-disabled menu item
environment (CR-161) displays or changes the current dataset and region environment
examine (CR-162) examines one or more objects, and displays current values (or the values at a
specified previous time) in the Main window
exit (CR-166) exits the simulator and the ModelSim application
fcover clear (CR-167) clears the active functional coverage database
fcover comment (CR-168) adds comment meta-data to the active functional coverage database
fcover configure (CR-169) enables, disables, and sets coverage targets for PSL coverage directives
fcover reload (CR-171) reloads a previously saved functional coverage database
fcover report (CR-173) reports results of a functional coverage analysis

fcover save (CR-175) saves the active functional coverage database to a file
find (CR-176) displays the full pathnames of all objects in the design whose names match
the name specification you provide
force (CR-180) applies stimulus to VHDL signals and Verilog nets

gdb dir (CR-183) sets the source directory for FLI/PLI/VPI C source code when using C Debug
getactivecursortime (CR-184) gets the time of the active cursor in the Wave window
getactivemarkertime (CR-185) gets the time of the active marker in the List window
help (CR-186) displays in the Main window a brief description and syntax for the specified
command
history (CR-187) lists the commands executed during the current session

Command name Action
lecho (CR-188) takes one or more Tcl lists as arguments and pretty-prints them to the Main
window
left (CR-189) searches left (previous) for signal transitions or values in the specified Wave
window
log (CR-191) creates a wave log format (WLF) file containing simulation data for all
objects whose names match the provided specifications
lshift (CR-193) takes a Tcl list as an argument and shifts it in-place one place to the left,
eliminating the left-most element
lsublist (CR-194) returns a sublist of the specified Tcl list that matches the specified Tcl glob
pattern
macro_option (CR-195) controls the speed and delay of macro (DO file) playback, plus the level of
debugging feedback
mem display (CR-196) displays the memory contents of a selected instance to the screen
mem list (CR-198) displays a flattened list of all memory instances in the current or specified
context after a design has been elaborated
mem load (CR-199) updates the simulation memory contents of a specified instance
mem save (CR-202) saves the contents of a memory instance to a file in any of the supported
formats: Verilog binary, Verilog hex, and MTI memory pattern data
mem search (CR-204) finds and prints to the screen the first occurring match of a specified memory
pattern in the specified memory instance
modelsim (CR-206) starts the ModelSim GUI without prompting you to load a design; valid only
for Windows platforms
next (CR-207) continues a search; see the search command (CR-260)
noforce (CR-208) removes the effect of any active force (CR-180) commands on the selected
object
nolog (CR-209) suspends writing of data to the WLF file for the specified signals
notepad (CR-211) opens a simple text editor
noview (CR-212) closes a window in the ModelSim GUI
nowhen (CR-213) deactivates selected when (CR-407) commands

onbreak (CR-214) specifies command(s) to be executed when running a macro that encounters
a breakpoint in the source code
onElabError (CR-215) specifies one or more commands to be executed when an error is encountered
during elaboration
onerror (CR-216) specifies one or more commands to be executed when a running macro
encounters an error

Command name Action
pause (CR-217) interrupts the execution of a macro
play (CR-218) plays a sequence of keyboard and mouse actions that were previously saved
to a file with the record command (CR-243)
pop (CR-219) moves one level up the C callstack
power add (CR-220) specifies the signals or nets to track for power information
power report (CR-221) writes out the power information for the specified signals or nets
power reset (CR-222) resets power information to zero for the signals or nets specified with the
power add command (CR-220)
precision (CR-223) determines how real numbers display in the GUI
printenv (CR-224) echoes to the Main window the current names and values of all environment
variables
profile clear (CR-225) clears any statistical performance or memory allocation data that has been
gathered during previous run commands
profile interval (CR-226) selects the frequency with which the profiler collects samples during a run
command
profile off (CR-227) disables runtime statistical performance and memory allocation profiling
profile on (CR-228) enables runtime profiling of where your simulation is spending its time and
where memory is allocated
profile option (CR-229) allows various profiling options to be changed
profile reload (CR-230) reads in raw profile data from an external file created during memory
allocation profiling
profile report (CR-231) produces a textual output of the profiling statistics that have been gathered up
to this point
project (CR-233) performs common operations on new projects
property list (CR-234) changes one or more properties of the specified signal, net, or register in the
List window (GR-153)
property wave (CR-235) changes one or more properties of the specified signal, net, or register in the
Wave window (GR-211)
push (CR-237) moves one level down the C callstack
pwd (CR-238) displays the current directory path in the Main window
quietly (CR-239) turns off transcript echoing for the specified command
quit (CR-240) exits the simulator
radix (CR-241) specifies the default radix to be used

Command name Action
readers (CR-242) displays the names of all readers of the specified object
record (CR-243) starts recording a replayable trace of all keyboard and mouse actions
report (CR-244) displays the value of all simulator control variables, or the value of any
simulator state variables relevant to the current simulation
restart (CR-246) reloads the design elements and resets the simulation time to zero
restore (CR-248) restores the state of a simulation that was saved with a checkpoint command
(CR-93) during the current invocation of vsim
resume (CR-249) resumes execution of a macro file after a pause command (CR-217) or a
breakpoint
right (CR-250) searches right (next) for signal transitions or values in the specified Wave
window
run (CR-252) advances the simulation by the specified number of timesteps
sccom (CR-254) compiles SystemC design units
scgenmod (CR-258) creates a VHDL entity’s or Verilog module’s equivalent SystemC foreign
module declaration, writing it to standard output
search (CR-260) searches the specified window for one or more objects matching the specified
pattern(s)
searchlog (CR-262) searches one or more of the currently open logfiles for a specified condition
seetime (CR-264) scrolls the List or Wave window to make the specified time visible
setenv (CR-265) sets an environment variable
shift (CR-266) shifts macro parameter values down one place
show (CR-267) lists objects and subregions visible from the current environment
simstats (CR-268) reports performance-related statistics about active simulations
splitio (CR-270) operates on a VHDL inout or out port to create a new signal having the same
name as the port suffixed with “__o”
status (CR-271) lists all currently interrupted macros
step (CR-272) steps to the next HDL statement
stop (CR-273) stops simulation in batch files; used with the when command (CR-407)
tb (CR-274) displays a stack trace for the current process in the Transcript pane
tcheck_set (CR-275) modifies a timing check’s reporting or X generation status
tcheck_status (CR-277) prints the current status of timing checks to the Transcript pane
toggle add (CR-279) enables collection of toggle statistics for the specified nodes

Command name Action
toggle disable (CR-281) disables collection of toggle statistics for the specified nodes
toggle enable (CR-282) re-enables collection of toggle statistics for the specified nodes
toggle report (CR-283) displays to the Transcript pane a list of all nodes that have not transitioned to
both 0 and 1 at least once
toggle reset (CR-284) resets the toggle counts to zero for the specified nodes
transcribe (CR-285) displays a command in the Transcript pane, then executes the command
transcript (CR-286) controls echoing of commands executed in a macro file; also works at top
level in batch mode
transcript file (CR-287) sets or queries the pathname for the transcript file
tssi2mti (CR-288) converts a vector file in Fluence Technology (formerly TSSI) Standard
Events Format into a sequence of force (CR-180) and run (CR-252) commands
unsetenv (CR-289) deletes an environment variable
up (CR-290) searches for signal transitions or values in the specified List window
vcd add (CR-292) adds the specified objects to the VCD file
vcd checkpoint (CR-293) dumps the current values of all VCD variables to the VCD file
vcd comment (CR-294) inserts the specified comment in the VCD file
vcd dumpports (CR-295) creates a VCD file that captures port driver data
vcd dumpportsall (CR-297) creates a checkpoint in the VCD file that shows the current values of all
selected ports
vcd dumpportsflush (CR-298) flushes the VCD buffer to the VCD file
vcd dumpportslimit (CR-299) specifies the maximum size of the VCD file
vcd dumpportsoff (CR-300) turns off VCD dumping and records all dumped port values as x
vcd dumpportson (CR-301) turns on VCD dumping and records the current values of all selected ports
vcd file (CR-302) specifies the filename and state mapping for the VCD file created by a vcd
add command (CR-292)
vcd files (CR-304) specifies the filename and state mapping for the VCD file created by a vcd
add command (CR-292); supports multiple VCD files
vcd flush (CR-306) flushes the contents of the VCD file buffer to the VCD file
vcd limit (CR-307) specifies the maximum size of the VCD file
vcd off (CR-308) turns off VCD dumping and records all VCD variable values as x
vcd on (CR-309) turns on VCD dumping and records the current values of all VCD variables
vcd2wlf (CR-310) translates VCD files into WLF files

Command name Action
vcom (CR-311) compiles VHDL design units
vcover convert (CR-319) converts a 5.7 coverage file to a 5.8 format

vcover merge (CR-320) merges multiple code or functional coverage data files offline
vcover report (CR-322) reports on multiple code or functional coverage data files offline
vcover stats (CR-325) produces summary statistics from multiple coverage data files
vdel (CR-327) deletes a design unit from a specified library
vdir (CR-328) lists the contents of a design library
verror (CR-329) prints a detailed description of a message number
vgencomp (CR-330) writes a Verilog module’s equivalent VHDL component declaration to

standard output
view (CR-332) opens a ModelSim window and brings it to the front of the display
virtual count (CR-334) counts the number of currently defined virtuals that were not read in using a
macro file
virtual define (CR-335) prints the definition of a virtual signal or function in the form of a command
that can be used to re-create the object
virtual delete (CR-336) removes the matching virtuals
virtual describe (CR-337) prints a complete description of the data type of one or more virtual signals
virtual expand (CR-338) produces a list of all the non-virtual objects contained in the virtual signal(s)
virtual function (CR-339) creates a new signal that consists of logical operations on existing signals and
simulation time
virtual hide (CR-342) causes the specified real or virtual signals to not be displayed in the Objects
window
virtual log (CR-343) causes the sim-mode dependent signals of the specified virtual signals to be
logged by the simulator
virtual nohide (CR-345) redisplays a virtual previously hidden with virtual hide
virtual nolog (CR-346) stops the logging of the specified virtual signals
virtual region (CR-348) creates a new user-defined design hierarchy region

virtual save (CR-349) saves the definitions of virtuals to a file
virtual show (CR-350) lists the full path names of all the virtuals explicitly defined
virtual signal (CR-351) creates a new signal that consists of concatenations of signals and
subelements
virtual type (CR-354) creates a new enumerated type

Command name Action
vlib (CR-356) creates a design library
vlog (CR-358) compiles Verilog design units

vmake (CR-369) creates a makefile that can be used to reconstruct the specified library
vmap (CR-370) defines a mapping between a logical library name and a directory
vopt (CR-371) produces an optimized version of your design

vsim (CR-373) loads a new design into the simulator
vsim<info> (CR-392) returns information about the current vsim executable
vsource (CR-393) specifies an alternative file to use for the current source file
wave (CR-394) commands for manipulating cursors, for zooming, and for adjusting the wave
display view in the Wave window
wave create (CR-397) creates an editable waveform that can be used to create stimulus and drive
simulation
wave edit (CR-400) edits a created waveform
wave export (CR-403) exports created waveforms to a stimulus file
wave import (CR-404) imports an EVCD file previously created with a wave export command
wave modify (CR-405) modifies the parameters of a created waveform
when (CR-407) instructs ModelSim to perform actions when the specified conditions are met
where (CR-412) displays information about the system environment
wlf2log (CR-413) translates a ModelSim WLF file to a QuickSim II logfile
wlf2vcd (CR-415) translates a ModelSim WLF file to a VCD file
wlfman (CR-416) outputs information about or a new WLF file from an existing WLF file
wlfrecover (CR-420) attempts to repair an incomplete WLF file
write cell_report (CR-421) creates a report of cell instances in the design that are optimized
write format (CR-422) records the names and display options in a file of the objects currently being
displayed in the List or Wave window
write list (CR-424) records the contents of the most recently opened or specified List window in
a list output file
write preferences (CR-425) saves the current GUI preference settings to a Tcl preference file
write report (CR-426) prints a summary of the design being simulated
write transcript (CR-428) writes the contents of the Main window transcript to the specified file

Command name Action
write tssi (CR-429) records the contents of the default or specified List window in a “TSSI
format” file
write wave (CR-431) records the contents of the most currently opened or specified Wave window
in PostScript format

.main clear CR-43
.main clear
The .main clear command clears the Transcript pane. The behavior is the same as selecting
Edit > Clear when the Transcript pane is active.
Syntax
.main clear
Arguments
None.
See also
Main window (GR-14)

CR-44 abort
abort
The abort command halts the execution of a macro file interrupted by a breakpoint or error.
When macros are nested, you may choose to abort the last macro only, abort a specified
number of nesting levels, or abort all macros. The abort command may be used within a
macro to return early.
Syntax
abort
[<n> | all]
Arguments
<n> | all
An integer giving the number of nested macro levels to abort; all aborts all levels.
Optional. Default is 1.
See also
onbreak (CR-214), onElabError (CR-215), onerror (CR-216)

add button CR-45
add button
The add button command adds a user-defined button to the Main window button bar. New
buttons are added to the right end of the bar. You can also add buttons via the GUI (see
"Customize Toolbar dialog" (GR-106)).
Returns the path name of the button widget created.
Syntax
add button
<Text> <Cmd> [Disable | NoDisable] [{<option> <value> ...}]
Arguments
<Text>
The label to appear on the face of the button. Required.
<Cmd>
The command to be executed when the button is clicked with the left mouse button. To
echo the command and display the return value in the Main window, prefix the command
with the transcribe command (CR-285). Transcribe will also echo the results to the
Transcript pane. Required.
Disable | NoDisable
If Disable, the button will be grayed-out during a run and not active. If NoDisable, the
button will continue to be active during a run. Optional. The default is Disable.
{<option> <value> ...}
A list of option-value pairs that will be applied to the button widget. Optional. Any
properties belonging to Tk button widgets may be set. Useful options are foreground
color (-fg), background color (-bg), width (-width), and relief (-relief).
For a complete list of available options, use the configure command addressed to the
newly-created widget. For example:
.dockbar.tbf0.standard.tb.button_51 config
Note: Because the arguments are positional, a Disable | NoDisable option must be
specified in order to use the options argument.

CR-46 add button
Examples
add button pwd {transcribe pwd} NoDisable
Creates a button labeled “pwd” that invokes the transcribe command (CR-285) with the
pwd Tcl command, and echoes the command and its results to the Transcript pane (see
graphic below). The button remains active during a run.
add button date {transcribe exec date} Disable {-fg blue -bg yellow \
-activebackground red}
Creates a button labeled “date” that echoes the system date to the Transcript pane. The
button is disabled during a run; its colors are: blue foreground, yellow background, and
red active background.
add button doit {run 1000 ns; echo did it} Disable {-underline 1}
Creates a “doit” button and underlines the second character of the label, the "o" of "doit".
.dockbar.tbf0.standard.tb.button_13 config -command {run 10000} -bg red
Changes the button command to "run 10000" and changes the button background color
to red.
See also
transcribe (CR-285), "Customize Toolbar dialog" (GR-106)

add dataflow CR-47
add dataflow
The add dataflow command adds the specified process, signal, net, or register to the
Dataflow window. Wildcards are allowed.
Syntax
add dataflow
<object> [-window <wname>]
<object>
Specifies a process, signal, net, or register that you want to add to the Dataflow window.
Required. Multiple objects separated by spaces may be specified. Wildcards are allowed.
(Note that the WildcardFilter Tcl preference variable identifies types to ignore when
matching objects with wildcard patterns.)
-window <wname>
Adds the objects to the specified Dataflow window <wname> (e.g., dataflow2).
Optional. Used to specify a particular window when multiple instances of that window
type exist. Selects an existing window; does not create a new window. Use the view
command (CR-332) with the -new option to create a new window.
See also
Dataflow window (GR-128)

CR-48 add list
add list
The add list command adds the following objects and their values to the List window:
VHDL signals and variables; Verilog nets and registers; and SystemC primitive channels
(signals). User-defined buses may also be added.
If no port mode is specified, add list will display all objects in the selected region with
names matching the object name specification.
Limitations: VHDL variables and Verilog memories can be listed using the variable’s full
name only (no wildcards).
Syntax
add list
[-allowconstants] [-depth <level>] [-in] [-inout] [-internal]
[-label <name>] [-nodelta] [-notrigger | -trigger] [-optcells] [-out]
[-ports] [-<radix>] [-recursive] [-width <n>] [-window <wname>]
[[<object_name> | {<object_name> {sig1 sig2 sig3 ...}}] ...] ...
Arguments
-allowconstants
For use with wildcard searches. Specifies that constants matching the wildcard search
should be added to the List window. Optional. By default, constants are ignored because
they do not change.
-depth <level>
Restricts a recursive search (specified with the -recursive argument) to a certain level of
hierarchy. <level> is an integer greater than or equal to zero. For example, if you specify
-depth 1, the command descends only one level in the hierarchy. Optional.
-in
For use with wildcard searches. Specifies that the scope of the search is to include ports
of mode IN if they match the object_name specification. Optional.
-inout
of mode INOUT if they match the object_name specification. Optional.
-internal
For use with wildcard searches. Specifies that the scope of the search is to include
internal objects (non-port objects) if they match the object_name specification. VHDL
variables are not selected. Optional.
-label <name>
Specifies an alternative signal name to be displayed as a column heading in the listing.
Optional. This alternative name is not valid in a force (CR-180) or examine (CR-162)
command; however, it can be used in a search command (CR-260) with the list option.
-nodelta
Specifies that the delta column not be displayed when adding signals to the List window.
Optional. Identical to configure list -delta none.

add list CR-49
-notrigger
Specifies that objects are to be listed, but does not cause the List window to be updated
when the objects change value. Optional.
-optcells
Makes Verilog optimized cell ports visible when using wildcards. Optional. By default
Verilog optimized cell ports are not selected even if they match the specified wildcard
pattern.
-out
of mode OUT if they match the object_name specification. Optional.
-ports
For use with wildcard searches. Specifies that the scope of the search is to include all
ports. Optional. Has the same effect as specifying -in, -out, and -inout together.
-<radix>
Specifies the radix for the objects that follow in the command. Optional. Valid entries (or
any unique abbreviations) are: binary, ascii, unsigned, decimal, octal, hex, symbolic, and
default. If no radix is specified for an enumerated type, the default representation is used.
You can change the default radix for the current simulation using the radix command
(CR-241). You can change the default radix permanently by editing the DefaultRadix (UM-
531) variable in the modelsim.ini file.
If you specify a radix for an array of a VHDL enumerated type, ModelSim converts each
signal value to 1, 0, Z, or X.
-recursive
For use with wildcard searches. Specifies that the scope of the search is to descend
recursively into subregions. Optional. If omitted, the search is limited to the selected
region. You can use the -depth argument to specify how far down the hierarchy to
descend.
-trigger
Specifies that objects are to be listed and causes the List window to be updated when the
objects change value. Optional. Default.
-width <n>
Specifies the column width in characters. Optional.
-window <wname>
Adds objects to the specified List window <wname> (e.g., list2). Optional. Used to
specify a particular window when multiple instances of that window type exist. Selects
an existing window; does not create a new window. Use the view command (CR-332) with
the -new option to create a new window.
<object_name>
Specifies the name of the object to be listed. Optional. Wildcard characters are allowed.
(Note that the WildcardFilter Tcl preference variable identifies types to ignore when
matching objects with wildcard patterns.) Variables may be added if preceded by the
process name. For example,
add list myproc/int1

CR-50 add list
{<object_name> {sig1 sig2 sig3 ...}}

Creates a user-defined bus with the specified object name. The ‘sigi’ entries are signals
to be concatenated within the user-defined bus. Optional. Specified objects may be either
scalars or various sized arrays as long as they have the same element enumeration type.
Examples
add list -r /*
Lists all objects in the design.
add list *
Lists all objects in the region.
add list -in *
Lists all input ports in the region.
add list a -label sig /top/lower/sig {array_sig(9 to 23)}
Displays a List window containing three columns headed a, sig, and array_sig(9 to 23).
add list clk -notrigger a b c d
Lists clk, a, b, c, and d only when clk changes.
config list -strobeperiod {100 ns} -strobestart {0 ns} -usestrobe 1
add list -notrigger clk a b c d
Lists clk, a, b, c, and d every 100 ns.
add list -hex {mybus {msb {opcode(8 downto 1)} data}}
Creates a user-defined bus named "mybus" consisting of three signals; the bus is
displayed in hex.
add list vec1 -hex vec2 -dec vec3 vec4
Lists the object vec1 using symbolic values, lists vec2 in hexadecimal, and lists vec3 and
vec4 in decimal.
See also
add wave (CR-52), log (CR-191), "Extended identifiers" (CR-16)

add watch CR-51
add watch
The add watch command adds signals and variables to the Watch pane in the Main
window. SystemC objects and user-defined buses may also be added.
Syntax
add monitor
<object_name> ...
Arguments
<object_name>
Specifies the name of the object to be added. Wildcard characters are allowed. (Note that
the WildcardFilter Tcl preference variable identifies types to ignore when matching
objects with wildcard patterns.) Variables must be preceded by the process name. For
example,
add watch myproc/int1
See also
"Watch pane" (GR-208)

CR-52 add wave
add wave
The add wave command adds the following objects to the Wave window: VHDL signals
and variables; Verilog nets and registers; and SystemC primitive channels (signals).
User-defined buses may also be added.
If no port mode is specified, add wave will display all objects in the selected region with
names matching the object name specification.
Limitations: VHDL variables and Verilog memories can be added using the variable’s full
name only (no wildcards).
Syntax
add wave
[-allowconstants] [-color <standard_color_name>] [-depth <level>] [-expand
<signal_name>] [-<format>] [-height <pixels>] [-in] [-inout] [-internal]
[-label <name>] [-noupdate] [-offset <offset>] [-optcells] [-out] [-ports]
[-<radix>] [-recursive] [-scale <scale>] [-window <wname>]
[[-divider <divider_name>...] | [-label <name> | {<object_name> {sig1 sig2
sig3 ...}}] ...]
Arguments
-allowconstants
For use with wildcard searches. Specifies that constants matching the wildcard search
should be added to the Wave window. Optional. By default, constants are ignored
because they do not change.
-color <standard_color_name>
Specifies the color used to display a waveform. Optional. These are the standard
X Window color names, or rgb value (e.g., #357f77); enclose 2-word names (“light
blue”) in quotes.
-depth <level>
Restricts a recursive search (specified with the -recursive option) to a certain level of
-divider <divider_name>
Adds a divider to the Wave window. Optional. When a divider name is specified that
name appears in the pathnames column. One or more names can be specified. All names
listed after -divider are taken to be divider names. Names that begin with a hyphen (-)
are not allowed; however, names beginning with a space are valid. If a divider name is
not specified, ModelSim will insert an unnamed divider.
-expand <signal_name>
Causes a compound signal to be expanded immediately, but only one level down.
Optional. The <signal_name> is required, and may include wildcards.
-<format>
Specifies the display format of the objects:
literal
logic

add wave CR-53
analog-step
analog-interpolated
analog-backstep
Optional. Literal waveforms are displayed as a box containing the object value. Logic
signals may be U, X, 0, 1, Z, W, L, H, or ‘-’.
The way each state is displayed is specified by the logic type display preference (see
"Preference variables located in INI files" (UM-524)). Analog signals are sized by -scale
and by -offset. Analog-step changes to the new time before plotting the new Y.
Analog-interpolated draws a diagonal line. Analog-backstep plots the new Y before
moving to the new time. See "Formatting the Wave window" (UM-255) for more
information.
-height <pixels>
Specifies the height (in pixels) of the waveform. Optional.
-in
of mode IN if they match the object_name specification. Optional.
-inout
of mode INOUT if they match the object_name specification. Optional.
-internal
For use with wildcard searches. Specifies that the scope of the search is to include
internal objects (non-port objects) if they match the object_name specification. Optional.
-label <name>
Specifies an alternative name for the signal being added to the Wave window. Optional.
For example,
add wave -label c clock
adds the clock signal, labeled as "c", to the Wave window.
This alternative name is not valid in a force (CR-180) or examine (CR-162) command;
however, it can be used in a search command (CR-260) with the wave option.
-noupdate
Prevents the Wave window from updating when a series of add wave commands are
executed in series. Optional.
<object_name>
Specifies the names of objects to be included in the Wave window display. Optional.
Wildcard characters are allowed. Note that the WildcardFilter Tcl preference variable
identifies types to ignore when matching objects with wildcard patterns. Variables may
be added if preceded by the process name. For example,
add wave myproc/int1
{<object_name> {sig1 sig2 sig3 ...}}

Creates a user-defined bus with the specified object name. The ‘sigi’ entries are signals
to be concatenated within the user-defined bus. Optional.
Note: You can also select Tools > Combine Signals (Wave window) to create a
user-defined bus.

CR-54 add wave
-offset <offset>
Modifies an analog waveform’s position on the display. Optional. The offset value is part
of the wave positioning equation (see -scale below).
-optcells
pattern.
-out
of mode OUT if they match the object_name specification. Optional.
-ports
For use with wildcard searches. Specifies that the scope of the listing is to include ports
of modes IN, OUT, or INOUT. Optional.
-<radix>
Specifies the radix for the objects that follow in the command. Optional.
Valid entries (or any unique abbreviations) are: binary, ascii character, unsigned decimal,
octal, hex, symbolic, and default. If no radix is specified for an enumerated type, the
default representation is used. You can change the default radix for the current simulation
using the radix command (CR-241). You can change the default radix permanently by
editing the DefaultRadix (UM-531) variable in the modelsim.ini file.
-recursive
For use with wildcard searches. Specifies that the scope of the search is to descend
region. You can use the -depth argument to specify how far down the hierarchy to
descend.
-scale <scale>
Scales analog waveforms. Optional. The scale value is part of the wave positioning
equation shown below.
The position and size of the waveform is given by:

(signal_value + <offset>) * <scale>
If signal_value + <offset> = 0, the waveform will be aligned with its name. The <scale>
value determines the height of the waveform, 0 being a flat line.
-window <wname>
Adds objects to the specified window <wname> (e.g., wave2). Optional. Used to specify
a particular window when multiple instances of that window type exist. Selects an
existing window; does not create a new window. Use the view command (CR-332) with
the -new option to create a new window.
Examples
add wave -logic -color gold out2
Displays an object named out2. The object is specified as being a logic object presented
in gold.

add wave CR-55
add wave -hex {address {a_7 a_6 a_5 a_4 a_3 a_2 a_1 a_0}}
Displays a user-defined, hex formatted bus named address.
add wave *
Waves all objects in the region.
add wave -in *
Waves all input ports in the region.
add wave -hex {mybus {scalar1 vector1 scalar2}}
Creates a user-defined bus named "mybus" consisting of three signals. Scalar1 and
scalar2 are of type std_logic and vector1 is of type std_logic_vector (7 downto 1). The
bus is displayed in hex.
Slices and arrays may be added to the bus using either VHDL or Verilog syntax. For
example:
add wave {vector3(1)}
add wave {vector3[1]}
add wave {vector3(4 downto 0)}
add wave {vector3[4:0]}
add wave vec1 -hex vec2 -dec vec3 vec4

Adds the object vec1 to the Wave window using symbolic values, adds vec2 in
hexadecimal, and adds vec3 and vec4 in decimal.
add wave -divider " -Example- "
Adds a divider with the name "-Example-". Note that for this to work, the first hyphen of
the name must be preceded by a space.
add wave -divider
add wave -divider ""
add wave -divider {}
Adds an unnamed divider.
See also
add list (CR-48), log (CR-191), "Extended identifiers" (CR-16), "Concatenation directives"
(CR-28)

CR-56 add_menu
add_menu
The add_menu command adds a menu to the menu bar of the specified window, using the
specified menu name. Use the add_menuitem (CR-59), add_separator (CR-60),
add_menucb (CR-58), and add_submenu (CR-61) commands to complete the menu.
Returns the full Tk pathname of the new menu.
Color and other Tk properties of the menu may be changed, after creating the menu, using
the Tk menu widget configure command.
Syntax
add_menu
<window_name> <menu_name> [<shortcut> [-hide_menubutton]]
Arguments
<window_name>
Tk path of the window to contain the menu. Required.
Note that the path for the Main window must be expressed as "". All other window
pathnames begin with a period (.). You can also use a variable and the view <window
name> command to obtain the window path (see example below).
<menu_name>
Name to be given to the Tk menu widget. Required.
<shortcut>
Number of the letter in the menu name that is to be used as the shortcut. Numbering starts
with 0 (i.e., first letter = 0, second letter = 1, third letter = 2, etc.). Optional unless you
specify -hide_menubutton, in which case <shortcut> is required. Default is "-1", which
indicates no shortcut is to be used.
-hide_menubutton
Causes the new menu not to be displayed. Optional. You can add the menu later by
calling tk_popup on the menu path widget. Note that you must specify <shortcut> if
you specify -hide_menubutton.

add_menu CR-57
Examples
The following Tcl code is an example of creating user-customized menus. It adds a menu
containing a top-level item labeled "Do My Own Thing...", which prints
"my_own_thing.signals", and adds a cascading submenu labeled "changeCase" with two
entries, "To Upper" and "To Lower", which echo "my_to_upper" and "my_to_lower"
respectively. A checkbox that controls the value of myglobalvar (.signals:one) is also
added.
set myglobalvar 0
set wname [view wave]; # Gets the path to the Wave window
proc AddMyMenus {wname} {
global myglobalvar
set cmd1 "echo my_own_thing $wname"
set cmd2 "echo my_to_upper $wname"
set cmd3 "echo my_to_lower $wname"
# WindowName Menu MenuItem label Command

# ---------- ---- -------------------- -------
add_menu $wname mine 0;# 0th letter (M) is underlined
add_menuitem $wname mine "Do My Own Thing..." $cmd1
add_separator $wname mine ;#----------------------------
add_submenu $wname mine changeCase
add_menuitem $wname mine.changeCase "To Upper" $cmd2
add_menuitem $wname mine.changeCase "To Lower" $cmd3
add_submenu $wname mine vars
add_menucb $wname mine.vars "Feature One" -variable
myglobalvar
-onvalue 1 -offvalue 0 -indicatoron 1
}
AddMyMenus $wname
This example is available in the following DO file: <install_dir>/modeltech/examples/

addmenu.do. You can run the DO file to add the "Mine" menu shown in the illustration, or
modify the file for different results.
To execute the DO file, select Tools > Execute Macro (Main window), or use the do
command (CR-151).
See also
add_menucb (CR-58), add_menuitem (CR-59), add_separator (CR-60), add_submenu
(CR-61), change_menu_cmd (CR-83)

CR-58 add_menucb
add_menucb
The add_menucb command creates a checkbox within the specified menu of the specified
window. A checkbox is a small box with a label. Clicking on the box will toggle the state,
from on to off or the reverse. When the box is "on", the Tcl global variable <var> is set to
<onval>. When the box is "off", the global variable is set to <offval>. Also, if something
else changes the global variable, its current state is reflected in the state of the checkbox.
Returns nothing.
Syntax
add_menucb
<window_name> <menu_name> <Text> -variable <var> -onvalue <onval>
-offvalue <offval> [-indicatoron <val>]
Arguments
<window_name>
Tk path of the window containing the menu. Required. The path for the Main window
must be expressed as "". All other window pathnames begin with a period (.).
<menu_name>
Name of the Tk menu widget. Required.
<Text>
Text to be displayed next to the checkbox. Required.
-variable <var>
Global Tcl variable to be reflected and changed. Required.
-onvalue <onval>
Value to set the global Tcl variable to when the box is "on". Required.
-offvalue <offval>
Value to set the global Tcl variable to when the box is "off". Required.
-indicatoron <val>
0 or 1. If 1, the status indicator is displayed. Otherwise it is not displayed. Optional. The
default is 1.
Examples
add_menucb $wname mine.vars "Feature One" -variable myglobalvar($wname:one) \
-onvalue 1 -offvalue 0 -indicatoron 1
See also
add_menu (CR-56), add_menuitem (CR-59), add_separator (CR-60), add_submenu (CR-
61), change_menu_cmd (CR-83)
The add_menucb command is also used as part of the add_menu (CR-56) example.

add_menuitem CR-59
add_menuitem
The add_menuitem command creates a menu item within the specified menu of the
specified window. May be used within a submenu. Returns nothing.
Syntax
add_menuitem
<window_name> <menu_path> <Text> <Cmd> [<shortcut>]
Arguments
<window_name>
<menu_path>
Name of the Tk menu widget plus submenu path. Required.
<Text>
Text to be displayed. Required.
<Cmd>
The command to be executed when the menu item is selected with the left mouse button.
To echo the command and display the return value in the Main window, prefix the
command with the transcribe command (CR-285). Transcribe will also echo the results
to the Transcript pane. Required.
<shortcut>
with 0 (i.e., first letter = 0, second letter = 1, third letter = 2, etc.). Optional. Default is
"-1", which indicates no shortcut is to be used.
Examples
add_menuitem $wname user "Save Results As..." $my_save_cmd
See also
add_menu (CR-56), add_menucb (CR-58), add_separator (CR-60), add_submenu (CR-61),
change_menu_cmd (CR-83)
The add_menuitem command is also used as part of the add_menu (CR-56) example.

CR-60 add_separator
add_separator
The add_separator command adds a separator as the next item in the specified menu path
in the specified window. Returns nothing.
Syntax
add_separator
<window_name> <menu_path>
Arguments
<window_name>
<menu_path>
Examples
add_separator $wname user
See also
add_menu (CR-56), add_menucb (CR-58), add_menuitem (CR-59), add_submenu (CR-
The add_separator command is also used as part of the add_menu (CR-56) example.

add_submenu CR-61
add_submenu
The add_submenu command creates a cascading submenu within the specified menu path
of the specified window. May be used within a submenu.
Returns the full Tk path to the new submenu widget.
Syntax
add_submenu
<window_name> <menu_path> <name> [<shortcut>]
Arguments
<window_name>
<menu_path>
<name>
Name to be displayed on the submenu. Required.
<shortcut>
with 0 (i.e., first letter = 0, second letter = 1, third letter = 2, etc.). Optional. Default is
"-1", which indicates no shortcut is to be used.
See also
add_menu (CR-56), add_menucb (CR-58), add_menuitem (CR-59), add_separator (CR-
The add_submenu command is also used as part of the add_menu (CR-56) example.

CR-62 alias
alias
The alias command displays or creates user-defined aliases. Any arguments passed on
invocation of the alias will be passed through to the specified commands. Returns nothing.
Existing ModelSim commands (e.g., run, env, etc.) cannot be aliased.
Syntax
alias
[<name> ["<cmds>"]]
Arguments
<name>
Specifies the new procedure name to be used when invoking the commands.
"<cmds>"
Specifies the command or commands to be evaluated when the alias is invoked.
Examples
alias
Lists all aliases currently defined.
alias <name>
Lists the alias definition for the specified name if one exists.
alias myquit "write list ./mylist.save; quit -f"
Creates a Tcl procedure, "myquit", that when executed, writes the contents of the List
window to the file mylist.save by invoking write list (CR-424), and quits ModelSim by
invoking quit (CR-240).

assertion fail CR-63
assertion fail
The assertion fail command configures simulator behavior in response to an assertion
failure.
Syntax
assertion fail
[-action continue|break|exit] [-disable] [-enable] [-limit <count>|none]
[-log on|off] [-recursive] <path>...
Arguments
-action continue|break|exit
Specify the action to take when an assertion fails. This option may be specified multiple
times; it applies to all paths that follow it in the command line. One of the following
values is required:
continue–No action taken. This is not the same as disabling an assertion since logging
may still be enabled for the directive. This is the default value.
break–Halt simulation and return to the ModelSim prompt.
exit–Halt simulation and exit ModelSim.
You can change the permanent default by setting the AssertionFailAction (UM-529)
variable in the modelsim.ini file.
-disable
Turns off failure tracking for the specified assertions. Optional. Assertion failure tracking
is enabled by default. You can change the permanent default by setting the
AssertionFailEnable (UM-529) variable in the modelsim.ini file.
-enable
Turns on failure tracking for the specified assertions. Optional. Default. You can change
the permanent default by setting the AssertionFailEnable (UM-529) variable in the
modelsim.ini file.
-limit <count>|none
Sets a limit on the number of times ModelSim responds to an assertion failing. Optional.
By default the limit is set to 1. One of the following values is required:
<count>–Specify a whole number.
none–No limit; failure tracking remains enabled for the duration of the simulation.
Once the limit is reached for a particular assertion, ModelSim disables failure tracking
on that assertion. ModelSim continues to respond to others if their limit has not been
reached. You can change the permanent default by setting the AssertionFailLimit (UM-

CR-64 assertion fail
-log on|off
Specify whether to write a transcript message when an assertion fails. This option may
be specified multiple times; it applies to all paths that follow it in the command line. One
of the following values is required:
on–Enable transcript logging. Default.
off–Disable transcript logging.
You can change the permanent default by setting the AssertionFailLog (UM-529) variable
in the modelsim.ini file.
-recursive
For use with wildcard matching. Specifies that the scope of the matching is to descend
region. Applies to all paths specified in the command.
<path>...
Specifies the assertions to be affected. Required. Multiple paths and wildcards are
allowed. The path specifies assertions or a design region containing multiple assertions.
Examples
assertion fail -disable a.b.c.assert__0
Disables assertion a.b.c.assert__0.
assertion fail -log off a.b.c.assert__0 a.b.c.assert__1
Disables logging for assertions a.b.c.assert__0 and a.b.c.assert__1. The -log argument
applies to all paths that follow it on the command line.
assertion fail -log off a.b.c.assert__0 -log on a.b.c.assert__1
Disables logging for assertion a.b.c.assert__0 but enables it for a.b.c.assert__1.
assertion fail -limit 4
Sets the failure response limit to 4. Each assertion failure will be responded to a
maximum of 4 times during the current simulation.
See also
"Enabling/disabling failure and pass checking" (UM-377), "Setting failure and pass limits"
(UM-379), "Setting failure action" (UM-380), assertion pass command (CR-65), and assertion
report command (CR-67)

assertion pass CR-65
assertion pass
The assertion pass command configures simulator behavior in response to an assertion
pass.
Syntax
assertion pass
[-disable] [-enable] [-limit <count>|none] [-log on|off] [-recursive]
<path>...
Arguments
-disable
Turns off pass tracking for the specified assertions. Optional. Default. You can change
the permanent default by setting the AssertionPassEnable (UM-530) variable in the
modelsim.ini file.
-enable
Turns on pass tracking for the specified assertions. Optional. Assertion pass tracking is
disabled by default. You can change the permanent default by setting the
AssertionPassEnable (UM-530) variable in the modelsim.ini file.
-limit <count>|none
Sets a limit on the number of times ModelSim responds to an assertion pass. Optional.
By default the limit is set to 1. One of the following values is required:
<count>–Specify a whole number.
none–No limit; pass tracking remains enabled for the duration of the simulation.
This limit is global; it is applied to each assertion in the simulation. Once the limit is
reached for a particular assertion, ModelSim disables pass tracking on that assertion.
ModelSim continues to respond to others if their limit has not been reached. You can
change the permanent default by setting the AssertionPassLimit (UM-530) variable in the
modelsim.ini file.
-log on|off
Specify whether to write a transcript message when an assertion passes. This option may
be specified multiple times; it applies to all paths that follow it in the command line. One
of the following values is required:
on–Enable transcript logging. Default.
off–Disable transcript logging.
You can change the permanent default by setting the AssertionPassLog (UM-530) variable
-recursive
region. Applies to all paths specified in the command.
<path>...
Specifies the assertions to be affected. Required. Multiple paths and wildcards are

CR-66 assertion pass
Examples
assertion pass -enable -log on a.b.c.assert__0 -log off a.b.c.assert_1
Enables assertions a.b.c.assert__0 and a.b.c.assert__1 and turns logging on for
a.b.c.assert__0 but not a.b.c.assert__1.
See also
"Enabling/disabling failure and pass checking" (UM-377), "Setting failure and pass limits"
(UM-379), assertion fail command (CR-63), and assertion report command (CR-67)

assertion report CR-67
assertion report
The assertion report command returns a status report for each assertion matching the path
specification. By default the command prints a concise report containing only assertion
names and their fail and pass counts. Adding the -verbose argument to the command will
print the following:
• source language (PSL or other)
• assertion name (full path)
• design unit where the assertion is declared
• source language (VHDL)
• filename (line number)
• fail enable status (enabled or disabled)
• pass enable status (enabled or disabled)
• fail count
• pass count
• attempted flag (indicates whether the assertion has ever attempted evaluation)
• fail action
• fail log
• pass log
• fail limit
• pass limit
Normally, the report is formatted for users with one line of the report reserved for each
assertion specified by the path(s).
For a more interactive look at this data, open the Assertion Browser in the ModelSim GUI.
See "Viewing assertions in the Assertions pane" (UM-376) for details.
Syntax
assertion report
[-number] [-output <filename>] [-recursive] [-tcl_list] [-verbose]
<path>...
Arguments
-number
Report the number of assertions that match the path argument(s). This option overrides
the normal report.
-output <filename>
Specifies a file name for the report. The default is to write the report to the Transcript
(GUI mode) or stdout (batch mode). Environment variables may be used in the
pathname. Optional.

CR-68 assertion report
-recursive
recursively into subregions. Optional; if omitted, the search is limited to the selected
region.
-tcl_list
Format the report as a Tcl list.
-verbose
Produces the detailed report as noted in the command description above. Optional.
<path>...
Specifies the assertions on which to report. Required. Multiple names and wildcards are
Example
VSIM 1> assertion report *
# -----------------------------------------------------------------
# Name File(Line) Failure Pass
# Count Count
# -----------------------------------------------------------------
# /tb/assert__reset_state dramcon_sim.vhd(53) 0 0
# /tb/assert__test_read_response dramcon_sim.vhd(59) 0 0
# /tb/assert__test_write_response dramcon_sim.vhd(60) 0 0
# /tb/assert__check_as_deasserts dramcon_sim.vhd(64) 0 0
See also
"Viewing assertions in the Assertions pane" (UM-376)

batch_mode CR-69
batch_mode
The batch_mode command returns a 1 if ModelSim is operating in batch mode, otherwise
it returns a 0. It is typically used as a condition in an if statement.
Syntax
batch_mode
Arguments
None
Examples
Some GUI commands do not exist in batch mode. If you want to write a script that will
work in or out of batch mode, you can use the batch_mode command to determine which
command to use. For example:
if [batch_mode] {
log /*
} else {
add wave /*
See also
"ModelSim modes of operation" (UM-27)

CR-70 bd
bd
The bd command deletes a breakpoint. You must specify a filename and line number or a
specific breakpoint id#. You may specify multiple filename/line number pairs and id#s.
Syntax
bd
<filename> <line_number> | <id#>
Arguments
<filename>
Specifies the name of the source file in which the breakpoint is to be deleted. Required if
an id# is not specified. The filename must match the one used previously to set the
breakpoint, including whether a full pathname or a relative name was used.
<line_number>
Specifies the line number of the breakpoint to be deleted. Required if an id# is not
specified.
<id#>
Specifies the id number of the breakpoint to be deleted. Required if a filename and line
number are not specified. If you are deleting a C breakpoint, the id# will have a "c" prefix.
Examples
bd alu.vhd 127
Deletes the breakpoint at line 127 in the source file named alu.vhd.
bd 5
Deletes the breakpoint with id# 5.
bd 6 alu.vhd 234
Deletes the breakpoint with id# 6 and the breakpoint at line 234 in the source file named
alu.vhd.
bd c.4
Deletes the C breakpoint with id# c.4.
See also
bp (CR-75), onbreak (CR-214), Chapter 16 - C Debug

bookmark add wave CR-71
bookmark add wave

The bookmark add wave command creates a named reference to a specific zoom range
and scroll position in the specified Wave window. Bookmarks are saved in the wave format
file and are restored when the format file is read (see write format command (CR-422)).
Syntax
bookmark add wave
<label> [<zoomrange> [<topindex>]] [-window <window_name>]
Arguments
<label>
Specifies the name for the bookmark. Required.
<zoomrange>
Specifies a list of two times with optional units. Optional. These two times must be
enclosed in braces ({}) or quotation marks (""). One number can be specified, which
indicates a range from 0 to <n>.
<topindex>
Specifies the vertical scroll position of the window. Optional. Zoomrange must be
specified if you want to specify topindex. The number identifies which object the
window should be scrolled to. For example, specifying 20 means the Wave window will
be scrolled down to show the 20th object.
-window <window_name>
Specifies the window to which the bookmark will be added. Optional. If this argument is
omitted, the bookmark is added in the current default Wave window.
Examples
bookmark add wave foo {{10 ns} {1000 ns}} 20
Adds a bookmark named "foo" to the current default Wave window. The bookmark
marks a zoom range from 10ns to 1000ns and a scroll position of the 20th object in the
window.
See also
bookmark delete wave (CR-72), bookmark goto wave (CR-73), bookmark list wave (CR-
74),
write format (CR-422)

CR-72 bookmark delete wave
bookmark delete wave

The bookmark delete wave command deletes bookmarks from the specified Wave
window.
Syntax
bookmark delete wave
<label> [-all] [-window <window_name>]
Arguments
<label>
Specifies the name of the bookmark to delete. Required unless the -all switch is used.
-all
Specifies that all bookmarks in the window be deleted. Optional.
Specifies the window from which bookmark(s) will be deleted. Optional. If this argument
is omitted, bookmark(s) in the current default Wave window are deleted.
Examples
bookmark delete wave foo
Deletes the bookmark named "foo" from the current default Wave window.
bookmark delete wave -all -window wave1
Deletes all bookmarks from the Wave window named "wave1".
See also
bookmark add wave (CR-71), bookmark goto wave (CR-73), bookmark list wave (CR-74),

bookmark goto wave CR-73
bookmark goto wave

The bookmark goto wave command zooms and scrolls a Wave window using the
specified bookmark.
Syntax
bookmark goto wave
<label> [-window <window_name>]
Arguments
<label>
Specifies the bookmark to go to. Required.
Specifies the Wave window to which the bookmark applies. Optional. Bookmarks can be
used only in the windows in which they were originally created.
See also
bookmark add wave (CR-71), bookmark delete wave (CR-72), bookmark list wave (CR-
74),

CR-74 bookmark list wave
bookmark list wave

The bookmark list wave command displays a list of available bookmarks in the Transcript
pane.
Syntax
bookmark list wave
[-window <window_name>]
Arguments
Specifies the Wave window for which you want a list of bookmarks. Optional. If this
argument is omitted, ModelSim lists the bookmarks for the current default Wave
window.
See also
bookmark add wave (CR-71), bookmark delete wave (CR-72), bookmark goto wave (CR-
73),

bp CR-75
bp
The bp or breakpoint command either sets a file-line breakpoint or returns a list of currently
set breakpoints. A set breakpoint affects every instance in the design unless the
-inst <region> argument is used.
Syntax
bp
<filename> <line_number>
[-c [<function_name> | <file_name>:<line#> | <line#> | *0x<hex_address>]]
[-id <id#>] [-inst <region>] [-disable] [-cond {<condition_expression>}]
[{<command>...}] | [-query <filename> [<line_number> [<line_number>]]]
Arguments
<filename>
Specifies the name of the source file in which to set the breakpoint. Required if you are
setting HDL breakpoints.
<line_number>
Specifies the line number at which the breakpoint is to be set. Required if you are setting
HDL breakpoints.
-c [<function_name> | <file_name>:<line#> | <line#> | *0x<hex_address>]
Sets a C breakpoint in SystemC designs, or when you are using "C Debug" (UM-399). The
-c argument is required when setting C breakpoints to distinguish them from HDL
breakpoints. See examples below.
-id <id#>
Attempts to assign this id number to the breakpoint. Optional. If the id number you
specify is already used, ModelSim will return an error.
Note: Ids for breakpoints are assigned from the same pool as those used for the when
command (CR-407). So, even if you haven’t used an id number for a breakpoint, it’s
possible it is used for a when command.
-inst <region>
Sets the breakpoint so it applies only to the specified region. Optional.
-disable
Sets the breakpoint to a disabled state. Optional. You can enable the breakpoint later
using the enablebp command (CR-158). By default, breakpoints are enabled when they
are set.
-cond {<condition_expression>}
Specifies condition(s) that determine whether the breakpoint is hit. Optional. If the
condition is true, the simulation stops at the breakpoint. If false, the simulation bypasses
the breakpoint. A condition cannot refer to a VHDL variable (only a signal).

CR-76 bp
The condition can be an expression with these operators:
Name Operator
equals ==, =
not equal !=, /=
AND &&, AND

OR ||, OR
The operands may be object names, signame’event, or constants. Subexpressions in

parentheses are permitted. The command will be executed when the expression is
evaluated as TRUE or 1.
The formal BNF syntax is:
condition ::= Name | { expression }
expression ::= expression AND relation

| expression OR relation
| relation
relation ::= Name = Literal

| Name /= Literal
| Name ' EVENT
| ( expression )
Literal ::= '<char>' | “<bitstring>” | <bitstring>
The "=" operator can occur only between a Name and a Literal. This means that you
cannot compare the value of two signals; i.e., Name = Name is not possible.
{<command>...}
Specifies one or more commands that are to be executed at the breakpoint. Optional.
Multiple commands must be separated by semicolons (;) or placed on multiple lines. The
entire command must be placed in curly braces.
Any commands that follow a run (CR-252) or step (CR-272) command will be ignored. A
run or step command terminates the breakpoint sequence. This applies if macros are
used within the bp command string as well. A restore (CR-248) command should not be
used.
If many commands are needed after the breakpoint, they can be placed in a macro file.
-query <filename> [<line_number> [<line_number>]]
Returns information about the breakpoints set in the specified file. The information
returned varies depending on which arguments you specify. See the examples below for
details.

bp CR-77
Examples
bp
Lists all existing breakpoints in the design, including the source file names, line numbers,
breakpoint id#s, and any commands that have been assigned to breakpoints.
bp alu.vhd 147
Sets a breakpoint in the source file alu.vhd at line 147.
bp alu.vhd 147 {do macro.do}
Executes the macro.do macro file when the breakpoint is hit.
bp -disable test.vhd 22 {echo [exa var1]; echo [exa var2]}
Sets a breakpoint on line 22 of test.vhd. When the breakpoint is hit, the values of variables
var1 and var2 are examined. This breakpoint is initially disabled; it can be enabled with
the enablebp command (CR-158).
bp test.vhd 14 {if {$now /= 100} then {cont}}
Sets a breakpoint in every instantiation of the file test.vhd at line 14. When that
breakpoint is executed, the command is run. This command causes the simulator to
continue if the current simulation time is not 100.
bp -query testadd.vhd
Lists the line number and enabled/disabled status (1 = enabled, 0 = disabled) of all
breakpoints in testadd.vhd.
bp -query testadd.vhd 48
Lists details about the breakpoint on line 48. The output comprises six pieces of
information: the first item (0 or 1) designates whether a breakpoint exists on the
line (1 = exists, 0 = doesn’t exist); the second item is always 1; the third item is the file
name in the compiled source; the fourth item is the breakpoint line number; the fifth item
is the breakpoint id; and the sixth item (0 or 1) designates whether the breakpoint is
enabled (1) or disabled (0).
bp -query testadd.vhd 2 59
Lists all executable lines in testadd.vhd between lines 2 and 59.
bp -c and_gate_init
Sets a C breakpoint at the entry to C function and_gate_init.
bp -c and_gate.c:46
Sets a C breakpoint at line 46 in the file and_gate.c.
bp -c 44
Sets a C breakpoint at line 44 in the current C or SystemC file.
bp -c *0xff130504
Sets a C breakpoint at hexadecimal address 0xff130504.
Note: Any breakpoints set in VHDL code and called by either resolution functions or
functions that appear in a port map are ignored.
See also
add button (CR-45), bd (CR-70), disablebp (CR-148), enablebp (CR-158), onbreak (CR-214),
when (CR-407), Chapter 6 - SystemC simulation, Chapter 16 - C Debug

CR-78 cd
cd
The cd command changes the ModelSim local directory to the specified directory. This
command cannot be executed while a simulation is in progress. Also, executing a cd
command will close the current project.
Syntax
cd
[<dir>]
Arguments
<dir>
The directory to which to change. Optional. If no directory is specified, ModelSim
changes to your home directory.

cdbg CR-79
cdbg
The cdbg command provides command-line equivalents of the menu options that are
available for "C Debug" (UM-399). For some of the commands there is a required argument
"on | off". The value can be either 'on' or 'off'. For example:
cdbg enable_auto_step on
cdbg stop_on_quit off
Syntax
cdbg
auto_find_bp | debug_on | enable_auto_step on|off | init_mode_complete |
init_mode_setup | interrupt | keep_user_init_bps on|off | quit |
refresh_source_window | set_debugger <path> |
show_source_balloon on|off | stop_on_quit on|off | trace_entry_point
on|off [<function_name>]
Arguments
auto_find_bp
Sets breakpoints on all currently known function entry points. See "Finding function
entry points with Auto find bp" (UM-406). Equivalent to selecting Tools > C Debug >
Auto find bp.
debug_on
Enables the C Debugger. Equivalent to selecting Tools > C Debug > Start C Debug.
enable_auto_step on|off
Enables/disables auto-step mode. See "Identifying all registered function calls" (UM-407).
Equivalent to selecting Tools > C Debug > Enable auto step.
init_mode_complete
Continues loading the design without stopping at functions calls. See "Debugging
functions during elaboration" (UM-410). Equivalent to selecting Tools > C Debug >
Complete load.
init_mode_setup
Enables initialization mode. See "Debugging functions during elaboration" (UM-410).
Equivalent to selecting Tools > C Debug > Init mode.
interrupt
Reactivates the C debugger when stopped in HDL code. Equivalent to selecting Tools >
C Debug > C Interrupt or clicking the 'C Interrupt' toolbar button.
keep_user_init_bps on|off
Specifies whether breakpoints set during initialization mode are retained after the design
finishes loading. See "Debugging functions during elaboration" (UM-410). Equivalent to
toggling the 'Keep user init bps' button in the C Debug setup dialog.
quit
Quits the C Debugger. Equivalent to selecting Tools > C Debug > Quit C Debug.
refresh_source_window
Re-opens a C source file if you close the Source window inadvertently while stopped in
the C debugger. Equivalent to selecting Tools > C Debug > Refresh.

CR-80 cdbg
set_debugger <path>
Sets the path to your gdb installation. Equivalent to selecting Tools > C Debug > C
Debug Setup and entering a custom path. The argument path is required and is the
complete pathname to the gdb executable. For example:
cdbg set_debugger_path /usr/bin/gdb
show_source_balloon on|off
Enables/disables the source balloon popup. See "C Debug setup dialog" (GR-99).
Equivalent to toggling the 'Show balloon' button on the C Debug setup dialog.
stop_on_quit on|off
Enables/disables debugging capability when the simulator is exiting. See "Debugging
functions when quitting simulation" (UM-414). Equivalent to toggling the 'Stop on quit'
button on the C Debug setup dialog.
trace_entry_point on|off [<function_name>]
Helps debug an FLI/PLI application when a design is loaded with vsim -trace_foreign
ModelSim stops at a C breakpoint each time a named FLI or PLI function is called from
your application. Once at the breakpoint, use the tb command (CR-274) and pop
command (CR-219) to investigate the C code at the place the function was called.

change CR-81
change
The change command modifies the value of a VHDL constant, generic, or variable;
Verilog register or variable; or C variable if running C Debug (UM-399).
Syntax
change
<variable> <value>
Arguments
<variable>
Specifies the name of one of the following types of objects:
VHDL
• Scalar variables, constants, and generics of all types except FILE
• Scalar subelements of composite variables, constants, and generics of all types
except FILE
• One-dimensional arrays of enumerated character types (including slices)
• Access types (an access type pointer can be set to "null"; the value that an access type
points to can be changed as specified above)
Verilog
• Parameters
• Registers and memories
• Integer, real, realtime, and time variables
• Subelements of register, integer, real, realtime, and time multi-dimensional arrays
(all dimensions must be specified)
• Bit-selects and part-selects of the above except for objects whose basic type is real
C
• Scalar C variables of type int, char, double, or float
• Individual fields of a C structure
• SystemC primitive channels are not supported
The name can be a full hierarchical name or a relative name. A relative name is relative
to the current environment. Wildcards cannot be used. Required.
<value>
Defines a value for the variable. Required. The specified value must be appropriate for
the type of the variable. Values that contain spaces must be enclosed with quotation
marks or curly braces (see Examples).
Note that the initial type of a parameter determines the type of value that it can be given.
For example, if a parameter is initially equal to 3.14 then only real values can be set on
it. Also note that changing the value of a parameter or generic will not modify any design
elements that depended on the parameter or generic during elaboration (for example,
sizes of arrays).

CR-82 change
Examples
change count 16#FFFF
Changes the value of the variable count to the hexadecimal value FFFF.
change {rega[16]} 0
Changes the value of the element of rega that is specified by the index (i.e., 16).
change {foo[20:22]} 011
Changes the value of the set of elements of foo that is specified by the slice (i.e., 20:22).
change x 1.5
Sets the value of x (type double) to 1.5.
change a1.c1 0
Sets the value of structure member a1.c1 (type int) to 0.
change val_b my_string
Sets val_b (type char *) to point to the string my_string.
change val_b "my string"
Sets val_b (type char *) to point to the string my string. Since there is a space in the value,
it must be enclosed by quotation marks or curly braces.
change file_name \"test2.txt\"
Sets the Verilog register file_name to "test2.txt". Note that the quote marks are escaped
with ’\’.
change mytimegeneric {500 ps}
Sets the time value of the mytimegeneric variable to 500 ps. The time value is enclosed
by curly braces (or quotation marks) because of the space between the value and the
units.
See also
force (CR-180)

change_menu_cmd CR-83
change_menu_cmd
The change_menu_cmd command changes the command to be executed for a specified
menu item label, in the specified menu, in the specified window. The menu path and label
must already exist for this command to function. Returns nothing.
Syntax
change_menu_cmd
<window_name> <menu_path> <label> <Cmd>
Arguments
<window_name>
<menu_path>
Name of an existing Tk menu widget plus any submenu path. Required.
<label>
Current label on the menu item. Required.
<Cmd>
New Tcl command to be executed when selected. Required.
See also
add_menu (CR-56), add_menucb (CR-58), add_menuitem (CR-59), add_separator (CR-
60), add_submenu (CR-61)

CR-84 check contention add
check contention add

The check contention add command enables contention checking for the specified nodes.
The allowed nodes are Verilog nets and VHDL signals of types std_logic and
std_logic_vector. Any other node types and nodes that don't have multiple drivers are
silently ignored by the command.
Syntax
check contention add
[-r] [-in] [-out] [-inout] [-internal] [-ports] <node_name>
Arguments
-r
Specifies that contention checking is enabled recursively into subregions. Optional. If
omitted, contention check enabling is limited to the current region.
-in
Enables checking on nodes of mode IN. Optional.
-out
Enables checking on nodes of mode OUT. Optional.
-inout
Enables checking on nodes of mode INOUT. Optional.
-internal
Enables checking on internal (non-port) objects. Optional.
-ports
Enables checking on nodes of modes IN, OUT, or INOUT. Optional.
<node_name>
Enables checking for the named node(s). Required.
Description
Bus contention checking detects bus fights on nodes that have multiple drivers. A bus fight
occurs when two or more drivers drive a node with the same strength and that strength is
the strongest of all drivers currently driving the node. The following table provides some
examples for two drivers driving a std_logic signal:
driver 1 driver 2 fight

Z Z no
0 0 yes
1 Z no
0 1 yes
L 1 no

check contention add CR-85
driver 1 driver 2 fight
L H yes
Detection of a bus fight results in an error message specifying the node and its drivers’
current driving values. If a node's drivers later change value and the node is still in
contention, a message is issued giving the new values of the drivers. A message is also
issued when the contention ends. The bus contention checking commands can be used on
VHDL and Verilog designs.
See also
check contention config command (CR-86), check contention off command (CR-87)

CR-86 check contention config
check contention config

The check contention config command allows you to write checking messages to a file
(messages display on your screen by default). You may also configure the contention time
limit.
Syntax
check contention config
[-file <filename>] [-time <limit>]
Arguments
-file <filename>
Specifies a file to which to write contention messages. Optional. If this option is selected,
the messages are not displayed to the screen.
-time <limit>
Specifies a time limit that a node may be in contention. Optional. Contention is detected
if a node is in contention for as long as or longer than the limit. The default limit is 0.
See also
check contention add command (CR-84), check contention off command (CR-87)

check contention off CR-87
check contention off

The check contention off command disables contention checking for the specified nodes.
Syntax
check contention off
[-all] [-r] [-in] [-out] [-inout] [-internal] [-ports] <node_name>
Arguments
-all
Disables contention checking for all nodes that have checking enabled. Optional.
-r
Specifies that contention checking is disabled recursively into subregions. Optional. If
omitted, contention check disabling is limited to the current region.
-in
Disables checking on nodes of mode IN. Optional.
-out
Disables checking on nodes of mode OUT. Optional.
-inout
Disables checking on nodes of mode INOUT. Optional.
-internal
Disables checking on internal (non-port) objects. Optional.
-ports
Disables checking on nodes of modes IN, OUT, or INOUT. Optional.
<node_name>
Disables checking for the named node(s). Required.
See also
check contention add command (CR-84), check contention config command (CR-86)

CR-88 check float add
check float add

The check float add command enables float checking for the specified nodes. The allowed
nodes are Verilog nets and VHDL signals of type std_logic and std_logic_vector (other
types are silently ignored).
You can set a time limit (the default is zero) for float checking using the -time <limit>
argument to the check float config command (CR-89). If you choose to modify the limit,
you should do so prior to invoking any check float add commands.
Syntax
check float add
[-r] [-in] [-out] [-inout] [-internal] [-ports] <node_name>
Arguments
-r
Specifies that float checking is enabled recursively into subregions. Optional. If omitted,
float check enabling is limited to the current region.
-in
Enables checking on nodes of mode IN. Optional.
-out
Enables checking on nodes of mode OUT. Optional.
-inout
Enables checking on nodes of mode INOUT. Optional.
-internal
Enables checking on internal (non-port) objects. Optional.
-ports
Enables checking on nodes of modes IN, OUT, or INOUT. Optional.
<node_name>
Enables checking for the named node(s). Required.
Description
Bus float checking detects nodes that are in the high impedance state for a time equal to or
exceeding a user-defined limit. This is an error in some technologies. Detection of a float
violation results in an error message identifying the node. A message is also issued when
the float violation ends. The bus float checking commands can be used on VHDL and
Verilog designs.
See also
check float config command (CR-89), check float off command (CR-90)

check float config CR-89
check float config

The check float config command allows you to write checking messages to a file
(messages display on your screen by default). You may also configure the float time limit.
Syntax
check float config
[-file <filename>] [-time <limit>]
Arguments
-file <filename>
Specifies a file to which to write float messages. Optional. If this option is selected, the
messages are not displayed to the screen.
-time <limit>
Specifies a time limit that a node may be floating. Optional. An error is detected if a node
is floating for as long as or longer than the limit. The default limit is 0. Note that you
should configure the time limit prior to invoking any check float add commands.
See also
check float add command (CR-88), check float off command (CR-90)

CR-90 check float off
check float off

The check float off command disables float checking for the specified nodes.
Syntax
check float off
[-all] [-r] [-in] [-out] [-inout] [-internal] [-ports] <node_name>
Arguments
-all
Disables float checking for all nodes that have checking enabled. Optional.
-r
Specifies that float checking is disabled recursively into subregions. Optional. If omitted,
float check disabling is limited to the current region.
-in
Disables checking on nodes of mode IN. Optional.
-out
Disables checking on nodes of mode OUT. Optional.
-inout
Disables checking on nodes of mode INOUT. Optional.
-internal
Disables checking on internal (non-port) objects. Optional.
-ports
Disables checking on nodes of modes IN, OUT, or INOUT. Optional.
<node_name>
Disables checking for the named node(s). Required.
See also
check float add command (CR-88), check float config command (CR-89)

check stable off CR-91
check stable off

The check stable off command disables stability checking. You may later enable it with
check stable on (CR-92), and meanwhile, the clock cycle numbers and boundaries are still
tracked.
Syntax
check stable off
Arguments
None.
See also
check stable on command (CR-92)

CR-92 check stable on
check stable on
The check stable on command enables stability checking on the entire design.
Syntax
check stable on
[-file <filename>] [-period <time>] [-strobe <time>]
Arguments
-file <filename>
Specifies a file to which to write the error messages. If this option is selected, the
messages are not displayed to the screen. Optional.
-period <time>
Specifies the clock period (which is assumed to begin at the time the check stable on
command is issued). Optional. This option is required the first time you invoke the check
stable on command. It is not required if you later enable checking after it was disabled
with the check stable off command (CR-91).
-strobe <time>
Specifies the elapsed time within each clock cycle that the stability check is performed.
Optional. The default strobe time is the period time. If the strobe time falls on a period
boundary, then the check is actually performed one timestep earlier. Normally the strobe
time is specified as less than or equal to the period, but if it is greater than the period, then
the check will skip cycles.
Description
Design stability checking detects when circuit activity has not settled within a period you
define for synchronous designs. You specify the clock period for the design and the strobe
time within the period during which the circuit must be stable. A violation is detected and
an error message is issued if there are pending driver events at the strobe time. The message
identifies the driver that has a pending event, the node that it drives, and the cycle number.
The design stability checking commands can be used on VHDL and Verilog designs.
Examples
check stable on -period "100 ps" -strobe "199 ps"
Performs a stability check 99 ps into each even numbered clock cycle (cycle numbers
start at 1).
See also
check stable off command (CR-91)

checkpoint CR-93
checkpoint
The checkpoint command saves the state of your simulation. The checkpoint command
saves the simulation kernel state, the vsim.wlf file, the list of the design objects shown in
the List and Wave windows, the file pointer positions for files opened under VHDL and the
Verilog $fopen system task, the states of foreign architectures, and VCD output. Changes
you made interactively while running vsim are not saved; for example, macros, virtual
objects, command-line interface additions like user-defined commands, and states of
graphical user interface windows are not saved. Also, toggle statistics (see the toggle
report command (CR-283)) are not saved.
Once saved, a checkpoint file may be used with the restore command (CR-248) during the
same simulation to restore the simulation to a previous state. A VSIM session may also be
started with a checkpoint file by using the vsim -restore command (CR-373).
Compression of the checkpoint file is controlled by the CheckpointCompressMode
If a checkpoint occurs while ModelSim is writing a VCD file, the entire VCD file is copied
into the checkpoint file. Since VCD files can be very large, it is possible that disk space
problems could occur. Consequently, ModelSim issues a warning in this situation.
Checkpoint files are platform dependent–you cannot checkpoint on one platform and
restore on another.
Syntax
checkpoint
<filename>
Arguments
<filename>
Specifies the name of the checkpoint file. Required.
See also
restore (CR-248), restart (CR-246), vsim (CR-373), "The difference between checkpoint/
restore and restart" (UM-87)

CR-94 compare add
compare add
The compare add command compares signals in a reference design against signals in a test
design. You can specify whether to compare two signals, all signals in the region, or just
ports or a subset of ports. Constant signals such as parameters and generics are ignored. See
"Waveform Compare" (UM-270) for a general overview of waveform comparisons.
The table below shows how compares work between specified reference objects and test
objects.
Reference Test object Result

object
signal signal compare the two signals
signal region compare a signal with a name matching the

reference signal in the specified test region
region region compare all matching signals in both regions
glob expression signal legal only if the glob expression selects only one
signal
glob expression region compare all signals matching the glob expression
that match signals in the test region
The compare add command supports arguments that specify how each signal state
matches std_logic or Verilog values (e.g., -vhdlmatches, see below). Since state matching
can also be set on a global basis with the compare options command or PrefCompare() Tcl
variables, ModelSim follows state match settings in this order:
1 Use local matching values specified when the compare was created using compare add
or subsequently configured using compare configure.
2 If no local values were set, use global matching values set with the compare options
command.
3 If no compare options were set, use default matching values specified by PrefCompare
Tcl variables.
Syntax
compare add
-clock <name> [-help] [-label <label>] [-list] [-<mode>] [-nowin]
[-rebuild] [-recursive] [-separator <string>] [-tol <delay>]
[-tolLead <delay>] [-tolTrail <delay>] [-verbose]
[-vhdlmatches {<ref-logic-value>=<test-logic-value>:...}]
[-vlogmatches {<ref-logic-value>=<test-logic-value>:...}]
[-wavepane <n>] [-wave] [-when {<expression>}] [-win <wname>]
<referencePath> [<testPath>]

compare add CR-95
Arguments
-clock <name>
Specifies the clock definition to use when sampling the specified regions. Required for a
clocked comparison; not used for asynchronous comparisons.
-help
Lists the description and syntax for the compare add command in the Transcript pane.
Optional.
-label <label>
Specifies a name for the comparison when it is displayed in the Wave window. Optional.
-list
Causes specified comparisons to be displayed in the default List window. Optional.
-<mode>
Specifies the mode of signal types that are compared. Optional. The actual values the
option may take are -in, -out, -inout, -internal, -ports, and -all. You can use more than one
mode option in the same command.
-nowin
Specifies that compare signals shouldn’t be added to any window. Optional. By default,
compare signals are added to the default Wave window. See -wave below.
-rebuild
Rebuilds a fragmented bus in the test design region and compares it with the
corresponding bus in the reference design region. Optional. If a signal is found having
the same name as the reference signal, the -rebuild option is ignored. When rebuilding
the test signal, the name of the reference signal is used as the wildcard prefix.
-recursive
Specifies that signals should also be selected in all nested subregions, and subregions of
those, etc. Optional.
-separator <string>
Used with the -rebuild option. When a bus has been broken into bits (bit blasted) by a
synthesis tool, ModelSim expects a separator between the base bus name and the bit
indication. This option identifies that separator. The default is "_". For example, the
signal "mybus" might be broken down into "mybus_0", "mybus_1", etc.
-tol <delay>
Specifies the maximum time a test signal edge is allowed to lead or trail a reference edge
in an asynchronous comparison. Optional. The default is 0. If a unit (e.g., ps) is used with
the time value, the time must be placed in curly braces.
-tolLead <delay>
Specifies the maximum time a test signal edge is allowed to lead a reference edge in an
asynchronous comparison. Optional. The default is 0. If a unit (e.g., ps) is used with the
time value, the time must be placed in curly braces.

CR-96 compare add
-tolTrail <delay>
Specifies the maximum time a test signal edge is allowed to trail a reference edge in an
asynchronous comparison. Optional. The default is 0. If a unit is used (e.g., ps) with the
Graphical representation of tolLead and tolTrail
Reference Signal
Test Signal
tolLead
tolTrail
-verbose
Prints information in the Transcript pane confirming the signals selected for comparison
and any type conversions employed. Optional.
-vhdlmatches {<ref-logic-value>=<test-logic-value>:...}
Specifies how VHDL signal states in the reference dataset should match values in the test
dataset. Optional. Values are specified in a colon-separated list of match values. For
example:
-vhdlmatches {X=XUD:Z=ZD:1=1HD}
Default is {U=UWXD:X=UWXD:0=0LD:1=1HD:Z=ZD:W=UWXD:L=0LD:H=1HD:
D=UX01ZWLHD}. The 'D' character represents the '-' "don't care" std_logic value.
-vlogmatches {<ref-logic-value>=<test-logic-value>:...}
Specifies how Verilog signal states in the reference dataset should match values in the
test dataset. Optional. Values are specified in a colon-separated list of match values. For
example:
-vlogmatches {0=0:1=1:Z=Z}
Default is {0=0:1=1:Z=Z:X=X}.
-wavepane <n>
Specifies the pane of the Wave window in which the differences will be viewed.
Optional.
-wave
Specifies that compare signals be added automatically to the default Wave window.
Optional. Default.
-when {<expression>}
Specifies a conditional expression that must evaluate to "true" or "1" for differences to
be reported. Optional. The expression is evaluated at the start of an observed difference.
See "GUI_expression_format" (CR-22) for legal expression syntax.
-win <wname>
Specifies a particular window to which to add objects. Optional. Used to specify a
particular window when multiple instances of that window type exist.

compare add CR-97
<referencePath>
Specifies either an absolute or relative path to the reference signal or region, or a glob
expression. Required. Relative paths are relative to the current context of the reference
dataset. If you specify a glob expression, it will match signals only in the containing
context.
<testPath>
Specifies an absolute or relative path to the test signal or region. Cannot be a glob
expression. Optional. If omitted, the test path defaults to the same path as
<referencePath> except for the dataset name.
Examples
compare add /*
Selects signals in the reference and test dataset top region according to the default mode.
Uses asynchronous comparison with the default tolerances. Assumes that the top regions
of the reference and test datasets have the same name and contain the same signals with
the same names.
compare add -port -clock myclock10 gold:.test_ringbuf.ring_inst
Selects port signals of instance .test_ringbuf.ring_inst in both datasets to be compared
and sampled on strobe myclock10.
compare add -r gold:/top/cpu test:/testbench/cpu
Selects all signals in the cpu region to be compared asynchronously using the default
tolerances. Requires that the reference and test relative hierarchies and signal names
within the cpu region be identical, but they need not be the same above the cpu region.
compare add -clock clock12 gold:.top.s1
Specifies that signal gold:.top.s1 should be sampled at clock12 and compared with
test:.top.s1, also sampled at clock12.
compare add -tolLead {3 ns} -tolTrail {5 ns} gold:/asynch/abc/s1 sim:/flat/
sigabc
Specifies that signal gold:/asynch/abc/s1 should be compared asynchronously with
signal sim:/flat/sigabc using a leading tolerance of 3 ns and a trailing tolerance of 5 ns.
compare add -rebuild gold:.counter1.count test:.counter2.cnt
Causes signals test:.counter2.cnt_dd to be rebuilt into bus test:.counter2.cnt[...] and
compared against gold:.counter1.count.
See also
compare annotate (CR-98), compare clock (CR-99), compare configure (CR-101),
compare continue (CR-103), compare delete (CR-104), compare end (CR-105), compare
info (CR-106), compare list (CR-107), compare options (CR-108), compare reload (CR-112),
compare reset (CR-113), compare run (CR-114), compare savediffs (CR-115), compare
saverules (CR-116), compare see (CR-117), compare start (CR-119), compare stop (CR-
121), compare update (CR-122), and "Waveform Compare" (UM-270)

CR-98 compare annotate
compare annotate
The compare annotate command either flags a comparison difference as "ignore" or adds
a text string annotation to the difference. The text string appears when the difference is
viewed in info popups or in the output of a compare info command (CR-106).
Syntax
compare annotate
[-ignore] [-noignore] [-text <message>] <idNum1> [<idNum2>...]
Arguments
-ignore
Flags the specified difference as "ignore." Optional.
-noignore
Undoes a previous -ignore command. Optional.
-text <message>
Adds a text string annotation to the difference that is shown wherever the difference is
viewed. Optional.
<idNum1>
Identifies the difference number to annotate. Required. You can obtain a difference’s
number using the compare start command (CR-119) or a popup dialog. Difference
numbers are ordered by time of the difference start, but there may be more than one
difference starting at a given time.
<idNum2>...
Identifies a second, third, etc. difference number to be annotated in the same way as
idNum1. Optional. These are individual references; ranges of numbers cannot be
specified.
Examples
compare annotate -ignore 1 2 10
Flags difference numbers 1, 2, and 10 as "ignore."
compare annotate -text "THIS IS A CRITICAL PROBLEM" 12
Annotates difference number 12 with the message "THIS IS A CRITICAL PROBLEM."
See also
compare add (CR-94), compare info (CR-106), and "Waveform Compare" (UM-270)

compare clock CR-99
compare clock
The compare clock command defines a clock that can then be used for clocked-mode
comparisons. In clocked-mode comparisons, signals are sampled and compared only at or
just after an edge on some signal.
Syntax
compare clock
[-delete] [-offset <delay>] [-rising | -falling | -both]
[-when {<expression>}] <clock_name> <signal_path>
Arguments
-delete
Deletes an existing compare clock. Optional.
-offset <delay>
Specifies a time value for delaying the sample time beyond the specified signal edge.
Optional. The default is 0. If a unit (e.g., ps) is used with the time value, the time must
be placed in curly braces.
-rising
Specifies that the rising edge of the specified signal should be used. Optional. This is the
default.
-falling
Specifies that the falling edge of the specified signal should be used. Optional. The
default is rising.
-both
Specifies that both the rising and the falling edge of the specified signal should be used.
Optional. The default is rising.
Specifies a conditional expression that must evaluate to "true" or "1" for that clock edge
to be used as a strobe. Optional. The expression is evaluated at the time of the clock edge,
rather than after the delay has been applied. See "GUI_expression_format" (CR-22) for
legal expression syntax.
<clock_name>
A name for this clock definition. Required. This name will be used with the compare add
command when doing a clocked-mode comparison.
<signal_path>
A full path to the signal whose edges are to be used as the strobe trigger. Required.

CR-100 compare clock
Examples
compare clock -rising strobe gold:.top.clock
Defines a clocked compare strobe named "strobe" that samples signals on the rising edge
of signal gold:.top.clock.
compare clock -rising -delay {12 ns} clock12 gold:/mydesign/clka
Defines a clocked compare strobe named "clock12" that samples signals 12 ns after the
rising edge of signal gold:/mydesign/clka.
See also
compare add (CR-94), "Waveform Compare" (UM-270)

compare configure CR-101
compare configure
The compare configure command modifies options for compare signals and regions. The
modified options are applied to all objects in the specified compare path.
Syntax
compare configure
[-clock <name>] [-recursive] [-tol <delay>] [-tolLead <delay>] [-tolTrail
<delay>] [-vhdlmatches {<ref-logic-value>=<test-logic-value>:...}]
[-when {<expression>}] <comparePath>
Arguments
-clock <name>
Changes the strobe signal for the comparison. Optional. If the comparison is currently
asynchronous, it will be changed to clocked. This switch may not be used with the -tol,
-tolLead, and -tolTrail options.
-recursive
Specifies that signals should also be selected in all nested subregions, and subregions of
those, etc. Optional.
-tol <delay>
Specifies the default maximum time the test signal edge is allowed to trail or lead the
reference edge in an asynchronous comparison. Optional. The default is 0. If a unit is
used (e.g., ps) with the time value, the time must be in curly braces.
-tolLead <delay>
Specifies the maximum time a test signal edge is allowed to lead a reference edge in an
asynchronous comparison. Optional. The default is 0. If a unit (e.g., ps) is used with the
-tolTrail <delay>
Specifies the maximum time a test signal edge is allowed to trail a reference edge in an
asynchronous comparison. Optional. The default is 0. If a unit is used (e.g., ps) with the
example:
Default is {U=UWXD:X=UWXD:0=0LD:1=1HD:Z=ZD:W=UWXD:L=0LD:H=1HD:
-=UX01ZWLHD}.

CR-102 compare configure
example:
Default is {0=0:1=1:Z=Z:X=X}.
Specifies a conditional expression that must evaluate to "true" or "1" for differences to
be reported. Optional. The expression is evaluated at the start of an observed difference.
See "GUI_expression_format" (CR-22) for legal expression syntax.
<comparePath>
Identifies the path of a compare signal, region, or glob expression. Required.
See also

compare continue CR-103
compare continue
This command is used to continue with comparison difference computations that were
suspended using the compare stop button or Control-C. If the comparison was not
suspended, compare continue has no effect.
Syntax
compare continue
Arguments
None
See also
compare stop (CR-121), "Waveform Compare" (UM-270)

CR-104 compare delete
compare delete
The compare delete command deletes a comparison object from the currently open
comparison.
Syntax
compare delete
[-recursive] <objectPath>
Arguments
-recursive
Deletes a region recursively. Optional.
<objectPath>
Path to the comparison object to be deleted (e.g., compare:/top\clk<>clk\). Required.
The dataset prefix is not needed.
See also

compare end CR-105
compare end
The compare end command closes the active comparison without saving any information.
Syntax
compare end
Arguments
None
See also

CR-106 compare info
compare info
The compare info command lists the results of the comparison in the Main window
transcript. To save the information to a file, use the -write argument.
Syntax
compare info
[-all] [-count] [-primaryonly] [-signals] [-secondaryonly]
[<startNum> [<endNum>]] [-summary] [-write <filename>]
Arguments
-all
Lists all differences (even those marked as "ignore") in the output. Optional. By default,
ignored differences are not listed in the output of a compare info command.
-count
Returns the total number of primary differences found.
-primaryonly
Lists only differences on individual bits, ignoring aggregate values such as a bus.
Optional.
-signals
Returns a Tcl list of compare signal names that have at least one difference.
-secondaryonly
Lists only aggregate value differences such as a bus, ignoring the individual bits.
<startNum> [<endNum>]
Specifies the difference numbers to start and end the list with. Optional. If omitted,
ModelSim starts the listing with the first difference and ends it with the last. If just
endNum is omitted, ModelSim ends the listing with the last difference.
-summary
Lists only summary information. Optional.
-write <filename>
Saves the summary information to <filename> rather than the Main window transcript.
Optional.
Examples
compare info
Lists all errors in the Main window transcript.
compare info -summary
Lists only an error summary in the Main window transcript.
compare info -write myerrorfile 20 50
Writes errors 20 through 50 to the file myerrorfile.
See also
compare add (CR-94), compare annotate (CR-98), "Waveform Compare" (UM-270)

compare list CR-107
compare list
Displays in the Transcript pane a list of all the compare add commands currently in effect.
Syntax
compare list
[-expand]
Arguments
-expand
Expands groups specified by the compare add command to individual signals. Optional.
See also

CR-108 compare options
compare options
The compare options command sets defaults for various waveform comparison
commands. Those defaults are used when other compare commands are invoked during the
current session. To set defaults permanently, edit the appropriate PrefCompare() Tcl
variable in the pref.tcl file (see "Preference variables located in Tcl files" (UM-540) for
details).
If no arguments are used, compare options returns the current setting for all options. If one
option is given that requires a value, and if that value is not given, compare options returns
the current value of that option.
Syntax
compare options
[-addwave] [-hide] [-noaddwave] [-show] [-ignoreVlogStrengths]
[-noignoreVlogStrengths] [-maxsignal <n>] [-maxtotal <n>]
[-listwin <name>] [-<mode>] [-separator <string>] [-tol <delay>]
[-tolLead <delay>] [-tolTrail <delay>] [-track] [-notrack]
[-vhdlmatches {<ref-logic-value>=<test-logic-value>:...}]
[-wavepane <n>] [-wavewin <name>]
Arguments
-addwave
Specifies that new comparison objects are added automatically to the Wave window.
Optional. Default. You can specify that objects aren’t added automatically using the
-noaddwave argument. Related Tcl variable is PrefCompare(defaultAddToWave).
-hide
Hides all comparisons except those that have at least one difference. Optional. Related
Tcl variable is PrefCompare(defaultHideIfNoDiffs).
-noaddwave
Specifies that new comparison objects are not added automatically to the Wave window.
Optional. The default is to add comparison objects automatically. Related Tcl variable is
PrefCompare(defaultAddToWave).
-show
Shows all comparisons even if they don’t have any differences. Optional. Default.
Related Tcl variable is PrefCompare(defaultHideIfNoDiffs).
-ignoreVlogStrengths
Specifies that Verilog net strengths should be ignored when comparing two Verilog nets.
Optional. Default. Related Tcl variable is PrefCompare(defaultIgnoreVerilogStrengths).
-noignoreVlogStrengths
Specifies that Verilog net strengths should not be ignored when comparing two Verilog
nets. Optional. Related Tcl variable is PrefCompare(defaultIgnoreVerilogStrengths).
-listwin <name>
Causes specified comparisons to be displayed in the specified List window. Optional.
Related Tcl variable is PrefCompare(defaultListWindow).

compare options CR-109
-maxsignal <n>
Specifies an upper limit for the total differences encountered on any one signal. When
that limit is reached, ModelSim stops computing differences on that signal. Optional. The
default is 100. Related Tcl variable is PrefCompare(defaultMaxSignalErrors).
-maxtotal <n>
Specifies an upper limit for the total differences encountered. When that limit is reached,
ModelSim stops computing differences. Optional. The default is 1000. Related Tcl
variable is PrefCompare(defaultMaxTotalErrors).
-<mode>
Specifies the default mode of signal types that are compared with the compare add
command (CR-94). Optional. The actual values the option may take are -in, -out, -inout,
-internal, -ports, and -all. More than one mode option may be used in the same compare
options command.
-separator <string>
Used with the -rebuild option of the compare add command (CR-94). When a bus has
been broken into bits (bit blasted) by a synthesis tool, ModelSim expects a separator
between the base bus name and the bit indication. This option identifies that separator.
The default is "_". For example, the signal "mybus" might be broken down into
"mybus_0", "mybus_1", etc. Optional. Related Tcl variable is
PrefCompare(defaultRebuildSeparator).
-tol <delay>
Specifies the default maximum time the test signal edge is allowed to trail or lead the
reference edge in an asynchronous comparison. Optional. The default is 0. If a unit is
used (e.g., ps) with the time value, the time must be in curly braces.
You can specify different values for the leading and trailing tolerances using -tolLead
and -tolTrail.
-tolLead <delay>
Specifies the default maximum time the test signal edge is allowed to lead the reference
edge in an asynchronous comparison. Optional. The default is 0. If a unit (e.g., ps) is used
with the time value, the time must be in curly braces. Related Tcl variables are
PrefCompare(defaultLeadTolerance) and PrefCompare(defaultLeadUnits).
-tolTrail <delay>
Specifies the default maximum time the test signal edge is allowed to trail the reference
edge in an asynchronous comparison. Optional. The default is 0. If a unit is used
(e.g., ps) with the time value, the time must be in curly braces. Related Tcl variables are
PrefCompare(defaultTrailTolerance) and PrefCompare(defaultTrailUnits).

CR-110 compare options
Graphical representation of tolLead and tolTrail
Reference Signal
Test Signal
tolLead
tolTrail
-track
Specifies that the waveform comparison should track the current simulation. Optional.
Default. The differences will be updated at the end of each run command, so if you want
to see differences soon after they occur, use many relatively short run commands.
Related Tcl variable is PrefCompare(defaultTrackLiveSim).
-notrack
Specifies that the waveform comparison should not track the current simulation.
Optional. Related Tcl variable is PrefCompare(defaultTrackLiveSim).
example:
Default is {U=UWX-:X=UWXD:0=0LD:1=1HD:Z=ZD:W=UWXD:L=0LD:H=1HD:
-=UX01ZWLHD}. Related Tcl variable is PrefCompare(defaultVHDLMatches).
example:
Default is {0=0:1=1:Z=Z:X=X}. Related Tcl variable is

PrefCompare(defaultVLOGMatches).
-wavepane <n>
Specifies the default pane of the Wave window in which compare differences will be
viewed. Optional. Related Tcl variable is PrefCompare(defaultWavePane).
-wavewin <name>
Specifies the default name of the Wave window in which compare differences will be
viewed. Optional. Related Tcl variable is PrefCompare(defaultWaveWindow).

compare options CR-111
Examples
compare options
Returns the current value of all options.
compare options -maxtotal 2000
Sets the maxtotal option to 2000 differences.
compare options -maxtotal
Returns the current value of the maxtotal option.
compare options -ignoreVlogStrengths
Sets the option to ignore Verilog net strengths.
compare options -vlogxmatches {0=0:1=1:Z=Z:X=XZ0}
Verilog X will now match X, Z, or 0.
compare options -vhdlmatches {X=UXWD}
VHDL std_logic X will now match 'U', 'X', 'W', or 'D'.
compare options -tolLead {300 ps}
Sets the leading tolerance for asynchronous comparisons to 300 picoseconds.
compare options -tolTrail {250 ps}
Sets the trailing tolerance for asynchronous comparisons to 250 picoseconds.
See also
compare add (CR-94), compare clock (CR-99), "Waveform Compare" (UM-270)

CR-112 compare reload
compare reload
The compare reload command reloads comparison differences to allow their viewing
without recomputation. Prior to invoking compare reload, you must open the relevant
datasets with the same names that were used during the original comparison.
Syntax
compare reload
<rulesFilename> <diffsFilename>
Arguments
<rulesFilename>
Specifies the name of the file that was previously saved using the compare saverules
command. Required. Must be the first argument.
<diffsFilename>
Specifies the name of the file that was previously saved using the compare savediffs
command. Required.
See also
compare add (CR-94), compare savediffs (CR-115), compare saverules (CR-116),
compare run (CR-114), compare start (CR-119), "Waveform Compare" (UM-270)

compare reset CR-113
compare reset
Clears the current compare differences, allowing another compare run command to be
executed. Does not modify any of the compare options or any of the signals selected for
comparison. This allows you to re-run the comparison with different options or with a
modified signal list.
Syntax
compare reset
Arguments
None
See also
compare add (CR-94), compare run (CR-114), and "Waveform Compare" (UM-270)

CR-114 compare run
compare run
The compare run command runs the difference computation on the signals selected via a
compare add command. Reports in the Transcript pane the total number of errors found.
Syntax
compare run
[<startTime>] [<endTime>]
Arguments
<startTime>
Specifies when to start computing differences. Optional. Default is zero. If a unit (e.g.,
ps) is used with the time value, the time must be in curly braces. The default units are
determined by the simulation resolution. (Default simulation resolution is nanoseconds.
Simulation resolution can be changed with the -t argument of the vsim command (CR-
373)).
<endTime>
Specifies when to end computing differences. Optional. Default is the end of the dataset
simulation run that ends earliest. If a unit (e.g., ps) is used with the time value, the time
must be placed in curly braces.
Examples
compare run
Computes differences over the entire time range.
compare run {5.3 ns} {57 ms}
Computes differences from 5.3 nanoseconds to 57 milliseconds.
See also
compare add (CR-94), compare end (CR-105), compare start (CR-119), "Waveform
Compare" (UM-270)

compare savediffs CR-115
compare savediffs
The compare savediffs command saves the comparison results to a file that can be
reloaded later. To be able to reload the file later, you must also save the comparison setup
using the compare saverules command.
Syntax
compare savediffs
<diffsFilename>
Arguments
<diffsFilename>
Specifies the name of the file to create. Required. To load the file at a later time, use the
compare reload command (CR-112).
See also
compare add (CR-94), compare reload (CR-112), compare saverules (CR-116), "Waveform
Compare" (UM-270)

CR-116 compare saverules
compare saverules
The compare saverules command saves the comparison setup information (or "rules") to
a file that can be re-executed later. The command saves compare options, clock definitions,
and region and signal selections.
Syntax
compare saverules
[-expand] <rulesFilename>
Arguments
-expand
Expands groups specified by the compare add (CR-94) command to individual signals.
Optional. If you added a region with the compare add command and then deleted signals
from that region, you must use the -expand argument or the rules will not reflect the
signal deletions.
<rulesFilename>
Specifies the name of the file to which you want to save the rules. Required. To load the
file at a later time, use the compare reload command (CR-112).
See also
compare add (CR-94), compare reload (CR-112), compare savediffs (CR-115), "Waveform
Compare" (UM-270)

compare see CR-117
compare see
The compare see command displays the specified comparison difference in the Wave
window using whatever horizontal and vertical scrolling are necessary. The signal
containing the specified difference will be highlighted, and the active cursor will be
positioned at the starting time of the difference.
Syntax
compare see
[-first] [-last] [-next] [-nextanno] [-previous] [-prevanno]
[-wavepane <n>] [-wavewin <name>]
Arguments
-first
Shows the first difference, ordered by time. Optional. Performs the same action as the
Find First Difference button in the Wave window.
-last
Shows the last difference, ordered by time. Optional. Performs the same action as the
Find Last Difference button in the Wave window.
-next
Shows the next difference (in time) after the currently selected difference. Optional.
Performs the same action as the Find Next Difference button in the Wave window.
-nextanno
Shows the next annotated difference (in time) after the currently selected difference.
Optional. Performs the same action as the Next Annotated Difference button in the Wave
window.
-previous
Shows the previous difference (in time) before the currently selected difference.
Optional. Performs the same action as the Previous Difference button in the Wave
window.
-prevanno
Shows the previous annotated difference (in time) before the currently selected
difference. Optional. Performs the same action as the Previous Annotated Difference
button in the Wave window.
-wavepane <n>
Specifies the pane of the Wave window in which the difference should be shown.
Optional.
-wavewin <name>
Specifies the name of the Wave window in which the difference should be shown.
Optional.

CR-118 compare see
Examples
compare see -first
Shows the earliest difference (in time) in the default Wave window.
compare see -next
Shows the next difference (in time) in the default Wave window.
See also
compare add (CR-94), compare run (CR-114), "Waveform Compare" (UM-270)

compare start CR-119
compare start
The compare start command begins a new dataset comparison. The datasets that you’ll be
comparing must already be open.
Syntax
compare start
[-batch] [-hide] [-show] [-maxsignal <n>] [-maxtotal <n>]
[-refDelay <delay>] [-testDelay <delay>] <reference_dataset>
[<test_dataset>]
Arguments
-batch
Specifies that comparisons will not be automatically inserted into the Wave window.
Optional.
-hide
Hides all comparisons except those that have at least one difference. Optional. You can
change the default using the compare options command (CR-108) or by editing the
PrefCompare(defaultHideIfNoDiffs) variable in the pref.tcl file.
-show
Shows all comparisons even if they don’t have any differences. Optional. Default. You
can change the default using the compare options command (CR-108) or by editing the
PrefCompare(defaultHideIfNoDiffs) variable in the pref.tcl file.
-maxsignal <n>
Specifies an upper limit for the total differences encountered on any one signal. When
that limit is reached, ModelSim stops computing differences on that signal. Optional. The
default limit is 100. You can change the default using the compare options command
(CR-108) or by editing the PrefCompare(defaultMaxSignalErrors) variable in the pref.tcl
file.
-maxtotal <n>
Specifies an upper limit for the total differences encountered. When that limit is reached,
ModelSim stops computing differences. Optional. The default limit is 1000. You can
change the default using the compare options command (CR-108) or by editing the
PrefCompare(defaultMaxTotalErrors) variable in the pref.tcl file.
-refDelay <delay>
Delays the reference dataset relative to the test dataset. Optional. If <delay> contains a
unit, it must be enclosed in curly braces. Delays are applied to signals specified with the
compare add command (CR-94). For each signal compared, a delayed virtual signal is
created with "_d" appended to the signal name, and these are the signals viewed in the
Wave window comparison objects. The delay is not applied to signals specified in
compare "when" expressions.

CR-120 compare start
-testDelay <delay>
Delays the test dataset relative to the reference dataset. Optional. If <delay> contains a
unit, it must be enclosed in curly braces. Delays are applied to signals specified with the
compare add command (CR-94). For each signal compared, a delayed virtual signal is
created with "_d" appended to the signal name, and these are the signals viewed in the
Wave window comparison objects. The delay is not applied to signals specified in
compare "when" expressions.
<reference_dataset>
The dataset to be used as the comparison reference. Required.
<test_dataset>
The dataset to be tested against the reference. Optional. If not specified, ModelSim uses
the current simulation. The reference and test datasets may be the same.
Examples
compare start gold
Begins a waveform comparison between a dataset named "gold" and the current
simulation. Assumes the gold dataset was already opened.
dataset open gold_typ.wlf gold
dataset open bad_typ.wlf test
compare start -maxtotal 5000 -maxsignal 1000 gold test
This command sequence opens two datasets and starts a comparison between the two
using greater than default limits for total differences encountered.
See also
compare add (CR-94), compare options (CR-108), compare stop (CR-121), "Waveform
Compare" (UM-270)

compare stop CR-121
compare stop
This command is used internally by the compare stop button to suspend comparison
computations in progress. If a compare run execution has returned to the VSIM prompt,
compare stop has no effect. Under Unix, entering a Control-C character in the window that
invoked ModelSim has the same effect as compare stop.
Syntax
compare stop
Arguments
None
See also
compare run (CR-114), compare start (CR-119), "Waveform Compare" (UM-270)

CR-122 compare update
compare update
This command is primarily used internally to update the comparison differences when
comparing a live simulation against a .wlf file. The compare update command is called
automatically at the completion of each simulation run if the "-track" compare option is in
effect.
The user can also call compare update periodically during a long simulation run to cause
difference computations to catch up with the simulation. This command does nothing if the
-track compare option was not in effect when the compare run command (CR-114) was
executed.
Syntax
compare update
Arguments
None
See also
compare run (CR-114), "Waveform Compare" (UM-270)

configure CR-123
configure
The configure command invokes the List or Wave widget configure command for the
current default List or Wave window. To change the default window, use the view
command (CR-332).
Syntax
configure
list|wave [-window <wname>] [<option> <value>]
[-delta [all | collapse | none]] [-gateduration [<duration_open>]]

[-gateexpr [<expression>]] [-usegating [<value>]]
[-strobeperiod [<period>]] [-strobestart [<start_time>]]
[-usesignaltriggers [<value>]] [-usestrobe [<value>]]
[-childrowmargin [<pixels>]] [-cursorlockcolor [<color>]]

[-gridcolor [<color>]] [-griddelta [<pixels>]] [-gridoffset [<time>]]
[-gridperiod [<time>]] [-namecolwidth [<width>]] [-rowmargin [<pixels>]]
[-signalnamewidth [<value>]] [-timecolor [<color>]]
[-timeline [<value>]] [-valuecolwidth [<width>]] [-vectorcolor [<color>]]
[-waveselectcolor [<color>]] [-waveselectenable [<value>]]
Description
The command works in three modes:
• without options or values it returns a list of all attributes and their current values
• with just an option argument (without a value) it returns the current value of that attribute
• with one or more option-value pairs it changes the values of the specified attributes to the
new values
The returned information has five fields for each attribute: the command-line switch, the
Tk widget resource name, the Tk class name, the default value, and the current value.
Arguments
list|wave
Specifies either the List or Wave widget to configure. Required.
-window <wname>
Specifies the name of the List or Wave window to target for the configure command.
(The view command (CR-332) allows you to create more than one List or Wave window).
Optional. If no window is specified the default window is used; the default window is
determined by the most recent invocation of the view command (CR-332).
<option> <value>
-bg <color>
Specifies the window background color. Optional.
-fg <color>
Specifies the window foreground color. Optional.
-selectbackground <color>
Specifies the window background color when selected. Optional.

CR-124 configure
-selectforeground <color>
Specifies the window foreground color when selected. Optional.
-font <font>
Specifies the font used in the widget. Optional.
-height <pixels>
Specifies the height in pixels of each row. Optional.
Arguments, List window only

-delta [all | collapse | none]
The all option displays a new line for each time step on which objects change; collapse
displays the final value for each time step; and none turns off the display of the delta
column. To use -delta, -usesignaltriggers must be set to 1 (on). Optional.
-gateduration [<duration_open>]
The duration for gating to remain open beyond when -gateexpr (below) becomes false,
expressed in x number of timescale units. Extends gating beyond the back edge (the last
list row in which the expression evaluates to true). Optional. The default value for normal
synchronous gating is zero. If -gateduration is set to a non-zero value, a simulation value
will be displayed after the gate expression becomes false (if you don’t want the values
displayed, set -gateduration to zero).
-gateexpr [<expression>]
Specifies the expression for trigger gating. Optional. (Use the -usegating argument to
enable trigger gating.) The expression is evaluated when the List window would
normally have displayed a row of data. See the "GUI_expression_format" (CR-22) for
information on expression syntax.
-usegating [<value>]
Enables triggers to be gated on (a value of 1) or off (a value of 0) by an overriding
expression. Default is off. Optional. (Use the -gatexpr argument to specify the
expression.) See "Using gating expressions to control triggering" (UM-266) for additional
information on using gating with triggers.
-strobeperiod [<period>]
Specifies the period of the list strobe. When using a time unit, the time value and unit
must be placed in curly braces. Optional.
-strobestart [<start_time>]
Specifies the start time of the list strobe. When using a time unit, the time value and unit
must be placed in curly braces. Optional.
-usesignaltriggers [<value>]
If 1, uses signals as triggers; if 0, not. Optional.
-usestrobe [<value>]
If 1, uses the strobe to trigger; if 0, not. Optional.

configure CR-125
Arguments, Wave window only

-childrowmargin [<pixels>]
Specifies the distance in pixels between child signals. Optional. Default is 2. Related Tcl
variable is PrefWave(childRowMargin).
-cursorlockcolor [<color>]
Specifies the color of a locked cursor. Default is red. Related Tcl variable is
PrefWave(cursorLockColor).
-gridcolor [<color>]
Specifies the background grid color; the default is grey50. Optional. Related Tcl variable
is PrefWave(gridColor).
-griddelta [<pixels>]
Specifies the closest (in pixels) two grid lines can be drawn before intermediate lines will
be removed. Optional. Default is 40. Related Tcl variable is PrefWave(gridDelta).
-gridoffset [<time>]
Specifies the time (in user time units) of the first grid line. Optional. Default is 0. Related
Tcl variable is PrefWave(gridOffset).
-gridperiod [<time>]
Specifies the time (in user time units) between subsequent grid lines. Optional. Default
is 1. Related Tcl variable is PrefWave(gridPeriod).
-namecolwidth [<width>]
Specifies in pixels the width of the name column. Optional. Default is 150. Related Tcl
variable is PrefWave(nameColWidth).
-rowmargin [<pixels>]
Specifies the distance in pixels between top-level signals. Default is 4. Related Tcl
variable is PrefWave(rowMargin).
-signalnamewidth [<value>]
Controls the number of hierarchical regions displayed as part of a signal name shown in
the pathname pane. Optional. Default of 0 displays the full path. 1 displays only the leaf
path element, 2 displays the last two path elements, and so on. Related Tcl variable is
PrefWave(SignalNameWidth). Can also be set with the WaveSignalNameWidth variable
-timecolor [<color>]
Specifies the time axis color. Default is green. Optional. Related Tcl variable is
PrefWave(timeColor).
-timeline [<value>]
Specifies whether the horizontal axis displays simulation time (default) or grid period
count. Default is zero. When set to 1, the grid period count is displayed. Related Tcl
variable is PrefWave(timeline).
-valuecolwidth [<width>]
Specifies in pixels the width of the value column. Default is 100. Related Tcl variable is
PrefWave(valueColWidth).
-vectorcolor [<color>]
Specifies the vector waveform color. Default is #b3ffb3. Optional. Related Tcl variable
is PrefWave(vectorColor).

CR-126 configure
-waveselectcolor [<color>]
Specifies the background highlight color of a selected waveform. Default is grey30.
Related Tcl variable is PrefWave(waveSelectColor).
-waveselectenable [<value>]
Specifies whether the waveform background highlights when an object is selected. 1
enables highlighting; 0 disables highlighting. Default is 0. Related Tcl variable is
PrefWave(waveSelectEnabled).
To get a more readable listing of all attributes and current values, use the lecho (CR-188)
command, which pretty-prints a Tcl list.
There are more options than are listed here. See the output of a configure list or configure
wave command for all options.
Examples
config list -strobeperiod
Displays the current value of the strobeperiod attribute.
config list -strobeperiod {50 ns} -strobestart 0 -usestrobe 1
Sets the period of the list strobe and turns it on.
config wave -vectorcolor blue
Sets the wave vector color to blue.
config wave -signalnamewidth 1
Sets the display in the current Wave window to show only the leaf path of each signal.
See also
view (CR-332), "Preference variables located in Tcl files" (UM-540)

context CR-127
context
The context command provides several operations on a context's name. The option you
specify determines the operation.
Syntax
context dataset | exists | isInst | isNet | isProc | isVar | join | parent |
split | tail | type
<name>
Arguments
context dataset <name>
Return the dataset name from the name.
context exists <name>
Returns 1 if the name is valid, 0 otherwise.
context isInst <name>
Returns 1 if the name is an instance pathname, 0 otherwise.
context isNet <name>
Returns 1 if the name is a Signal or Net pathname, 0 otherwise.
context isProc <name>
Returns 1 if the name is a Process pathname, 0 otherwise.
context join <name> <name> ...
Takes one or more names and combines them, using the correct path separator.
context parent <name>
Returns the parent path of the name by removing the tail (see context tail).
context path <name>
Returns the pathname portion of the name, removing the dataset name.
context split <name>
Returns a list whose elements are the path components in the name. The first element of
the list will be the dataset name if one is present in the name, including the dataset
separator. For example, context split /foo/bar/baz returns / foo bar baz .
context tail <name>
Returns all of the characters in the name after the last path separator. If the name contains
no separators then returns the name. Any trailing path separator is discarded.
context type <name>
Returns a string giving the acc type of the name.
<name>
Name of a context object or region. Required. Does not have to be a valid object name
unless the specified option requires this (i.e., exists or isInst).

CR-128 coverage clear
coverage clear
The coverage clear command clears all code coverage statement and branch counts
obtained during previous run commands and unloads the current exclusion filter file.
Syntax
coverage clear
[<filename>] [-all | -excluded [-user | -pragma | -instance]]
Arguments
<filename>
Specifies the name of the file you wish to clear. Optional.
-all
Clears all statement and branch counts and all user exclusion flags set with the coverage
exclude command. Optional.
-excluded
Unloads a currently loaded exclusion filter file. Exclusion filter files specify files and line
numbers that you wish to exclude from Code Coverage statistics. See "Excluding objects
from coverage" (UM-347) for more details.
-user
Clears only user exclusions.
-pragma
Clears only pragma exclusions.
-instance
Clears only instance-specific exclusions.
Example
coverage clear -excluded -pragma
Clears the statement exclusion flags that have been set by the coverage exclude
command. Only pragma exclusions are cleared.
See also
Chapter 13 - Measuring code coverage, coverage exclude (CR-129), coverage reload (CR-
131),
coverage report (CR-132), coverage save (CR-135)

coverage exclude CR-129
coverage exclude
The coverage exclude command loads an exclusion filter file or allows direct exclusion of
specific lines in a source file or rows within a table. Exclusion filter files specify files and
line numbers that you wish to exclude from Code Coverage statistics. (See "Excluding
objects from coverage" (UM-347) for more details).
Syntax
coverage exclude
<filename>or
[-add | -remove] <source> [-inst <path>] [<ln> | <ln> - <ln>] | all]

[(-c) | -e <ln> <rn> | (<rn>-<rn>) | all]
Arguments
<filename>
Specifies the file name of the exclusion filter you wish to load. Required if <source> is
not specified. See "Excluding objects from coverage" (UM-347) for filter file syntax.
-add
Adds another exclusion. Optional.
-remove
Removes an existing exclusion or part of one. Optional.
<source>
Designates the name of the design source file, not an exclusion file, from which
exclusions will be made. Required if <filename> is not specified.
-inst <path>
Designates the hierarchical path of an instance in the design. Required if you do not
specify <filename> or <source>.
<ln>
Specifies the line number to be excluded from code coverage in the design source file
<source>. Also can use line_number1 – line_number2 (ln1–ln2). Optional.
all
When used with <source>, specifies that all lines in the source file should be excluded.
When used with -inst <path>, specifies that all lines in the instance and all instances
contained within the specified instance should be excluded. Required if a range or line
number is not specified.
-c
Implies a condition truth table from which lines or rows will be excluded. Optional.
-e
Implies an expression truth table from which lines or rows will be excluded. Optional.
<rn>
Specifies the row number in the truth table to be excluded. Also row1 – row2 (rn1–rn2).
Optional

CR-130 coverage exclude
See also
Chapter 13 - Measuring code coverage, Excluding objects from coverage (UM-347),
coverage clear (CR-128), coverage reload (CR-131), coverage report (CR-132), coverage
save (CR-135)

coverage reload CR-131
coverage reload
The coverage reload command seeds the coverage statistics with the output of a previous
coverage save command. This allows you to gather statistics from multiple simulation
runs.
Syntax
coverage reload
-57<filename> [-incremental] [-install <path>] [-root <new_root_name>]
[-strip <n>]
Arguments
-57
Specifies that the file being reloaded was produced in ModelSim version 5.7x. Optional.
The coverage file format changed in version 5.8, so you must flag files that are from the
earlier version.
<filename>
Specifies the file(s) containing data to reload. Required. This file should be the output of
a previous coverage save command.
-incremental
Merges loaded coverage data with current coverage data. Optional. Without this
argument, loading coverage data overwrites existing data.
-install <path>
Adds <path> as additional hierarchy on the front end of instance and signal names in the
data file. Optional. This argument allows you to merge coverage results from simulations
that have different hierarchies.
-root <new_root_name>
Specifies the root name of the design for which you have a saved coverage report.
Optional. This argument has been superseded by the -strip and -install arguments. It is
included for backwards compatibility only.
-strip <n>
Removes <n> levels of hierarchy from instance and signal names in the data file.
Optional. This argument allows you to merge coverage results from simulations that have
different hierarchies.
See also
Chapter 13 - Measuring code coverage, coverage clear (CR-128), coverage exclude (CR-
129), coverage report (CR-132), coverage save (CR-135)

CR-132 coverage report
coverage report
The coverage report command produces textual output of coverage statistics. You can
choose from a number of report output options using the arguments listed below. To view
this data more interactively, right-click in the Files tab of the Workspace pane and select
Coverage > Coverage Reports from the popup context menu.
If you’d like to produce reports in an offline manner (i.e., without a simulation loaded), use
the vcover report command (CR-322).
Syntax
coverage report
[-above <percent> | -below <percent>] [-append]
[-byinstance] [-excluded [[-pragma] [-user]] | -totals | [-lines] [-zeros]]
[-file <filename>] [-instance <pathname>] [-library <libname>] [-package
<pkgname>] [-noannotate] [-recursive] [-select bces[t|x]] [-source
<filename>] [-xml]
Arguments
-above <percent>
Specifies that only objects with coverage values above this percentage be included in the
output. Optional.
-below <percent>
Specifies that only objects with coverage values below this percentage be included in the
output. Optional.
-append
Appends the current coverage statistics to the named output file (-file <filename>).
Optional. Can be used with the -excluded, -instance, -lines, -total, and -zeros arguments
to append specific reports to the output file.
-byinstance
Writes out a coverage summary for all instances and packages. Optional.
-excluded
Writes out the files and lines that are currently being excluded by the user from the
coverage analysis. Shows both pragma and user-based exclusions unless -pragma or
-user are specified. Optional. This is the same information that is shown in the "Current
Exclusions pane" (GR-121).
-pragma
When used with the -excluded argument, writes out only lines currently being
excluded by pragmas. Optional.
-user
When used with the -excluded argument, writes out files and lines currently being
excluded by the coverage exclude command. Optional.
-file <filename>
Specifies a file name for the report. Optional. Default is to write the report to the
Transcript pane. Environment variables may be used in the pathname.

coverage report CR-133
-instance <pathname>
Writes out the source file summary coverage data for the selected instance. Optional.
-library <libname>
Only needs to be used when you have packages of the same name in different libraries.
Optional.
-lines
Writes out the source file summary data and after each file it writes out the details for
each executable line in the file. Optional.
-noannotate
Produces the same report as -lines but removes source code from the output report.
Optional.
-package <pkgname>
Prints a report on the specified VHDL package body. Optional.
-recursive
Reports on the instance specified with -instance and every included instance, recursively.
Can also be used with -lines and -totals. Optional.
-select bces[t|x]
Specifies which coverage statistics to include in the report. Optional. By default the
report includes statistics for all categories you enabled at compile time.
The characters are as follows:
b–Include branch statistics.
c–Include condition statistics.
e–Include expression statistics.
s–Include statement statistics.
t–Include toggle statistics.
x–Include extended toggle statistics.
-source <filename>
Writes a summary of statement coverage data for a specific source file. Optional.
Environment variables may be used in the pathname.
-totals
Writes out a top-level summary of the number of files, statements, branches, hits, and
signal toggles for both file-based and instance-based views of the current analysis.
Optional. Useful for tracking changes.
-xml
Outputs report in XML format. Optional. See "Reporting coverage data" (UM-350) for
more information.
-zeros
Writes out a file-based summary of lines that have not been executed (zero hits),
annotates the source code, and supports the -source and -instance options. Optional. For
a detailed report that includes line numbers, use: coverage report -zeros -lines.

CR-134 coverage report
Examples
coverage report -totals -file myreport.txt
Writes a top-level summary of the number of files, statements, branches, hits, and signal
toggles to myreport.txt.
coverage report -lines -noannotate -select bcs
Writes detailed branch, condition, and statement statistics, without associated source
code, to the specified file.
coverage report -byinstance
Writes a summary of code coverage for all instances to the Transcript pane.
coverage report -lines -byinstance -file myreport.txt
Writes code coverage details of all instances in the design to myreport.txt. The -lines
option reports coverage statistics for each statement and branch. Branch coverage
statistics follow statement statistics and are presented in four columns: line, column, true
branch count, and false branch count.
coverage report -lines -instance /top/p
Writes code coverage details of one specific instance to the Transcript pane.
coverage report -excluded -file myexclusions.txt
Writes both pragma and user-based exclusions to myexclusions.txt.
coverage report -lines -below 90 -file myreport.txt
Writes a summary of coverage by source file for coverage less than or equal to 90%.
coverage report -zeros byinstance -file myzerocov.txt
Writes a list of statements with zero coverage to myzerocov.txt.
See also
129), coverage reload (CR-131), coverage save (CR-135), vsim (CR-373) -coverage option,
vcover report (CR-322).

coverage save CR-135
coverage save
The coverage save command saves current coverage statistics to a file that can be reloaded
later, preserving instance-specific information.
Syntax
coverage save
[-instance <path>] <filename> [-norecursive] [-xml]
Arguments
-instance <path>
Saves coverage data for only the specified instance and any of its children, recursively.
Use the -norecursive argument to exclude data from the instance’s children. <path> is a
path to the instance. Optional.
<filename>
Specifies a file name for the report. Required.
-norecursive
When saving coverage by instance, excludes data from children of the specified instance.
Optional.
-xml
Saves data in XML format. Optional. See "Reporting coverage data" (UM-350) for more
information.
Currently XML-formatted coverage files cannot be reloaded or merged.
See also
129), coverage reload (CR-131), coverage report (CR-132), "$coverage_save(<filename>,
[<instancepath>], [<xml_output>])" (UM-152) Verilog system task

CR-136 dataset alias
dataset alias
The dataset alias command assigns an additional name (alias) to a dataset. The dataset can
then be referenced by that alias. A dataset can have any number of aliases, but all dataset
names and aliases must be unique.
Syntax
dataset alias
<dataset_name> [<alias_name>]
Arguments
<dataset_name>
Specifies the name of the dataset to which to assign the alias. Required.
<alias_name>
Specifies the alias name to assign to the dataset. Optional. If you don’t specify an
alias_name, ModelSim lists current aliases for the specified dataset_name.
See also
dataset list (CR-140), dataset open (CR-141), dataset save (CR-143)

dataset clear CR-137
dataset clear
The dataset clear command removes all event data from the current simulation WLF file
while keeping all currently logged signals logged. Subsequent run commands will continue
to accumulate data in the WLF file.
Syntax
dataset clear
Example
add wave *
run 100000ns
dataset clear
run 100000ns
Clears data in the WLF file from time 0ns to 100000ns, then logs data into the WLF file
from time 100000ns to 200000ns.
See also
"WLF files (datasets)" (UM-226), log (CR-191)

CR-138 dataset close
dataset close
The dataset close command closes an active dataset. To open a dataset, use the dataset
open command.
Syntax
dataset close
<logicalname> | [-all]
Arguments
<logicalname>
Specifies the logical name of the dataset or alias you wish to close. Required if -all isn’t
used.
-all
Closes all open datasets including the simulation. Optional.
See also
dataset open (CR-141)

dataset info CR-139
dataset info
The dataset info command reports a variety of information about a dataset.
Syntax
dataset info
<option> <dataset_name>
Arguments
<option>
Identifies what information you want reported. Required. Only one option per command
is allowed. The current options include:
name - Returns the actual name of the dataset. Useful for identifying the real dataset name
of an alias.
file - Returns the name of the WLF file associated with the dataset.
exists - Returns "1" if the dataset exists; "0" if it doesn’t.
<dataset_name>
Specifies the name of the dataset or alias for which you want information. Optional. If
you do not specify a dataset name, ModelSim uses the dataset of the current environment
(see the environment command (CR-161)).
See also
dataset alias (CR-136), dataset list (CR-140), dataset open (CR-141)

CR-140 dataset list
dataset list
The dataset list command lists all active datasets.
Syntax
dataset list
[-long]
Arguments
-long
Lists the filename corresponding to each dataset’s logical name. Optional.
See also
dataset alias (CR-136), dataset save (CR-143)

dataset open CR-141
dataset open
The dataset open command opens a WLF file (representing a prior simulation) and assigns
it the logical name that you specify. To close a dataset, use dataset close.
Syntax
dataset open
<filename> [<logicalname>]
Arguments
<filename>
Specifies the WLF file to open as a view-mode dataset. Required.
<logicalname>
Specifies the logical name for the dataset. Optional. This is a prefix that will identify the
dataset in the current session. By default the dataset prefix will be the name of the
specified WLF file.
Examples
dataset open last.wlf test
Opens the dataset file last.wlf and assigns it the logical name test.
See also
dataset alias (CR-136), dataset list (CR-140), dataset save (CR-143), vsim (CR-373) -view
option

CR-142 dataset rename
dataset rename
The dataset rename command changes the logical name of a dataset to the new name you
specify.
Syntax
dataset rename
<logicalname> <newlogicalname>
Arguments
<logicalname>
Specifies the existing logical name of the dataset. Required.
<newlogicalname>
Specifies the new logical name for the dataset. Required.
Examples
dataset rename test test2
Renames the dataset file "test" to "test2".
See also
dataset alias (CR-136), dataset list (CR-140), dataset open (CR-141)

dataset save CR-143
dataset save
The dataset save command writes data from the current simulation to the specified file.
This lets you save simulation data while the simulation is still in progress.
Syntax
dataset save
<datasetname> <filename>
Arguments
<datasetname>
Specifies the name of the dataset you want to save. Required.
<filename>
Specifies the name of the file to save. Required.
Examples
dataset save sim gold.wlf
Saves all current log data in the sim dataset to the file "gold.wlf".
See also
dataset snapshot (CR-144)

CR-144 dataset snapshot
dataset snapshot
The dataset snapshot command saves data from the current WLF file (vsim.wlf by default)
at a specified interval. This lets you take sequential or cumulative "snapshots" of your
simulation data.
Syntax
dataset snapshot
[-dir <directory>] [-disable] [-enable] [-file <filename>] [-filemode
overwrite | increment] [-mode cumulative | sequential] [-report] [-reset]
-size <file size> | -time <simulation time>
Arguments
-dir <directory>
Specifies a directory into which the files should be saved. Optional. Default is to save into
the directory where ModelSim is writing the current WLF file.
-disable
Turns snapshotting off. Optional. All other options are ignored if you specify -disable.
-enable
Turns snapshotting on. Optional. Default.
-file <filename>
Specifies the name of the file to save. Optional. Default is "vsim_snapshot". ".wlf" will
be appended to the file and possibly an incrementing suffix if -filemode is set to
"increment".
-filemode overwrite | increment
Specifies whether to overwrite the snapshot file each time a snapshot occurs. Optional.
Default is "overwrite". If you specify "increment", a new file is created for each snapshot.
An incrementing suffix (1 to n) is added to each new file (e.g., vsim_snapshot_1.wlf).
-mode cumulative | sequential
Specifies whether to keep all data from the time signals are first logged. Optional. Default
is "cumulative". If you specify "sequential", the current WLF file is cleared every time a
snapshot is taken. See the examples for further details.
-report
Lists current snapshot settings in the Transcript pane. Optional. All other options are
ignored if you specify -report.
-reset
Resets values back to defaults. Optional. The behavior is to reset to the default, then
apply the remainder of the arguments on the command line. See examples below. If
specified by itself without any other arguments, -reset disables dataset snapshot.
-size <file size>
Specifies that a snapshot occurs based on WLF file size. You must specify either -size or
-time. See examples below.
-time <simulation time>
Specifies that a snapshot occurs based on simulation time. You must specify either -time
or -size. See examples below.

dataset snapshot CR-145
Examples
dataset snapshot -size 10
Creates the file vsim_snapshot.wlf that is written to every time the current WLF file
reaches a multiple of 10 MB (i.e., at 10 MB, 20 MB, 30 MB, etc.).
dataset snapshot -size 10 -mode sequential
Similar to the previous example but in this case the current WLF file is cleared every time
it reaches 10 MB.
dataset snapshot -time 1000000 -file gold.wlf -mode sequential -filemode
increment
Assuming simulator time units are ps, this command saves a file called gold_n.wlf every
1000000 ps. If you ran for 3000000 ps, you’d have three files: gold_1.wlf with data from
0 to 1000000 ps, gold_2.wlf with data from 1000001 to 2000000, and gold_3.wlf with
data from 2000001 to 3000000.
Note: Because this example uses "sequential" mode, if you ran the simulation for
3500000 ps, the resulting vsim.wlf (the default log file) file will contain data only from
3000001 to 3500000 ps.
dataset snapshot -reset -time 10000

Enables snapshotting with time=10000 and default mode (cumulative) and default
filemode (overwrite).
See also
dataset save (CR-143)

CR-146 delete
delete
The delete command removes objects from either the List or Wave window.
Syntax
delete
list|wave [-window <wname>] <object_name>
Arguments
list|wave
Specifies the target window for the delete command. Required.
-window <wname>
Specifies the name of the List or Wave window to target for the delete command (the
view command (CR-332) allows you to create more than one List or Wave window).
Optional. If no window is specified the default window is used; the default window is
determined by the most recent invocation of the view command (CR-332).
<object_name>
Specifies the name of an object. Required. Must match an object name used in an add
list (CR-48) or add wave (CR-52) command. Multiple object names may be specified.
Wildcard characters are allowed.
Examples
delete list -window list2 vec2
Removes the object vec2 from the list2 window.
See also
add list (CR-48), add wave (CR-52), and "Wildcard characters" (CR-17)

describe CR-147
describe
The describe command displays information about the specified HDL object, C variable,
or design region. The description is displayed in the Transcript pane. The following kinds
of objects can be described:
• Design region
• VHDL
signals, variables, and constants
• Verilog
nets and registers
• C
variables
• SystemC
signals, ports, FIFOs, and member variables of modules
VHDL signals, Verilog nets and registers, and SystemC signals and ports may be specified
as hierarchical names.
C variables can be described if you are running "C Debug" (UM-399), and the variables are
local to the active call frame for the line in the function in the C source file where you are
stopped.
For specific information related to viewing SystemC objects see "SystemC object and type
display in ModelSim" (UM-180).
Syntax
describe
<name>
Arguments
<name>
The name of an HDL object, SystemC signal, or C variable for which you want a
description. HDL object names can be full hierarchical names or relative names.
Examples
describe x
Prints the type of C variable x.
describe *p
Prints the type of what p points to.
describe clk prw prdy
Prints the types of the three specified signals.

CR-148 disablebp
disablebp
The disablebp command turns off breakpoints and when commands. To turn the
breakpoints or when statements back on again, use the enablebp command.
Syntax
disablebp
[<id#>]
Arguments
<id#>
Specifies a breakpoint or when command id to disable. Optional. If you don’t specify an
id#, all breakpoints are disabled. Note that C breakpoint id#s (see "C Debug" (UM-399))
are prefixed with "c.".
See also
bd (CR-70), bp (CR-75), enablebp command (CR-158), onbreak (CR-214), resume (CR-249),
when (CR-407)

disable_menu CR-149
disable_menu
The disable_menu command disables the specified menu within the specified window.
The disabled menu will become grayed-out and nonresponsive. Returns nothing.
Syntax
disable_menu
Arguments
<window_name>
must be expressed as "". All other window pathnames begin with a period (.) as shown
in the example below.
<menu_path>
Name of the Tk menu-widget path. Required.
Examples
disable_menu "" File
Disables the file menu of the Main window.
disable_menu .mywindow File
Disables the file menu of the mywindow window.
See also
add_menu (CR-56), enable_menu (CR-159)

CR-150 disable_menuitem
disable_menuitem
The disable_menuitem command disables a specified menu item within the specified
menu path of the specified window. The menu item will become grayed-out and
nonresponsive. Returns nothing.
Syntax
disable_menuitem
<window_name> <menu_path> <label>
Arguments
<window_name>
Tk path of the window containing the menu. Required.
pathnames begin with a period (.) as shown in the example below.
<menu_path>
Name of the Tk menu-widget path. The path may include a submenu as shown in the
example below. Required.
<label>
Menu item text. Required.
Examples
disable_menuitem .mywindow file.save "Save Results As..."
This command locates the mywindow window, and disables the Save Results As... menu
item in the save submenu of the file menu.
See also
add_menuitem (CR-59), enable_menuitem (CR-160)

do CR-151
do
The do command executes commands contained in a macro file. A macro file can have any
name and extension. An error encountered during the execution of a macro file causes its
execution to be interrupted, unless an onerror command (CR-216), onbreak command (CR-
214), or the OnErrorDefaultAction Tcl variable has specified the resume command (CR-
249).
Syntax
do
<filename> [<parameter_value>]
Arguments
<filename>
Specifies the name of the macro file to be executed. Required. The name can be a
pathname or a relative file name.
Pathnames are relative to the current working directory if the do command is executed
from the command line. If the do command is executed from another macro file,
pathnames are relative to the directory of the calling macro file. This allows groups of
macro files to be moved to another directory and still work.
<parameter_value>
Specifies values that are to be passed to the corresponding parameters $1 through $9 in
the macro file. Optional. Multiple parameter values must be separated by spaces.
If you want to make the parameters optional (i.e., specify fewer parameter values than
the number of parameters actually used in the macro), you must use the argc (UM-542)
simulator state variable in the macro. See "Making macro parameters optional" (UM-488).
Note that there is no limit on the number of parameters that can be passed to macros, but
only nine values are visible at one time. You can use the shift command (CR-266) to see
the other parameters.
Examples
do macros/stimulus 100
This command executes the file macros/stimulus, passing the parameter value 100 to $1
in the macro file.
do testfile design.vhd 127
If the macro file testfile contains the line bp $1 $2, this command would place a
breakpoint in the source file named design.vhd at line 127.
See also
Chapter 20 - Tcl and macros (DO files), "ModelSim modes of operation" (UM-27), "Using
a startup file" (UM-538), DOPATH (UM-521)

CR-152 down
down
The down command searches for object transitions or values in the specified List window.
It executes the search on objects currently selected in the window, starting at the time of the
active cursor. The active cursor moves to the found location.
Use this command to move to consecutive transitions or to find the time at which an object
takes on a particular value, or an expression of multiple objects evaluates to true. See the
up command (CR-290) for related functionality.
The procedure for using down includes three steps: click on the desired object; click on the
desired starting location; issue the down command. (The seetime command (CR-264) can
initially position the cursor from the command line, if desired.)
Returns: <number_found> <new_time> <new_delta>
Syntax
down
[-expr {<expression>}] [-falling] [-noglitch] [-rising]
[-value <sig_value>] [-window <wname>] [<n>]
Arguments
-expr {<expression>}
The List window will be searched until the expression evaluates to a boolean true
condition. Optional. The expression may involve more than one object, but is limited to
objects that have been logged in the referenced List window. An object may be specified
either by its full path or by the shortcut label displayed in the List window.
See "GUI_expression_format" (CR-22) for the format of the expression. The expression
must be placed within curly braces.
-falling
Searches for a falling edge on the specified object if that object is a scalar object. If it is
not a scalar object, the option will be ignored. Optional.
-noglitch
Specifies that delta-width glitches are to be ignored. Optional.
-rising
Searches for a rising edge on the specified object if that object is a scalar object. If it is
not a scalar object, the option will be ignored. Optional.
-value <sig_value>
Specifies a value of the object to match. Optional. Must be specified in the same radix
that the selected object is displayed. Case is ignored, but otherwise the value must be an
exact string match -- don't-care bits are not yet implemented.
-window <wname>
Specifies an instance of the List window that is not the default. Optional. Otherwise, the
default List window is used. Use the view command (CR-332) to change the default
window.

down CR-153
<n>
Specifies to find the nth match. Optional. If less than n are found, the number found is
returned with a warning message, and the marker is positioned at the last match.
Examples
down -noglitch -value FF23
Finds the next time at which the selected vector transitions to FF23, ignoring glitches.
down
Goes to the next transition on the selected object.
The following examples illustrate search expressions that use a variety of object attributes,
paths, array constants, and time variables. Such expressions follow the
"GUI_expression_format" (CR-22).
down -expr {clk’rising && (mystate == reading) && (/top/u3/addr ==
32’habcd1234)}
Searches down for an expression that evaluates to a boolean 1 when object clk just
changed from low to high and object mystate is the enumeration reading and object
/top/u3/addr is equal to the specified 32-bit hex constant.
down -expr {(/top/u3/addr and 32’hff000000) == 32’hac000000}
Searches down for an expression that evaluates to a boolean 1 when the upper 8 bits of
the 32-bit object /top/u3/addr equals hex ac.
down -expr {((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode ==
writing)}
Searches down for an expression that evaluates to a boolean 1 when logfile time is
between 23 and 54 microseconds, clock just changed from low to high, and object mode
is enumeration writing.
See also
"GUI_expression_format" (CR-22), view (CR-332), seetime (CR-264), up (CR-290)

CR-154 drivers
drivers
The drivers command displays the names of all drivers of the specified object. The driver
list is expressed relative to the top-most design signal/net connected to the specified object.
If the object is a record or array, each subelement is displayed individually.
Syntax
drivers
<object_name>
Arguments
<object_name>
Specifies the name of the signal or net whose drivers are to be shown. Required. All
signal or net types are valid. Multiple names and wildcards are accepted.
See also
readers (CR-242) command

dumplog64 CR-155
dumplog64
The dumplog64 command dumps the contents of the specified WLF file in a readable
format to stdout. The WLF file cannot be opened for writing in a simulation when you use
this command.
The dumplog64 command cannot be used in a DO file.
Syntax
dumplog64
<filename>
Arguments
<filename>
The name of the WLF file to be read. Required.

CR-156 echo
echo
The echo command displays a specified message in the Transcript pane.
Syntax
echo
[<text_string>]
Arguments
<text_string>
Specifies the message text to be displayed. Optional. If the text string is surrounded by
quotes, blank spaces are displayed as entered. If quotes are omitted, two or more adjacent
blank spaces are compressed into one space.
Examples
echo “The time is $now ns.”
If the current time is 1000 ns, this command produces the message:
The time is 1000 ns.
If the quotes are omitted, all blank spaces of two or more are compressed into one space.
echo The time is $now ns.
If the current time is 1000ns, this command produces the message:
The time is 1000 ns.
echo can also use command substitution, such as:
echo The hex value of counter is [examine -hex counter].
If the current value of counter is 21 (15 hex), this command produces:
The hex value of counter is 15.

edit CR-157
edit
The edit command invokes the editor specified by the EDITOR environment variable. By
default the specified filename will open in ModelSim Source editor.
Syntax
edit
[<filename>]
Arguments
<filename>
Specifies the name of the file to edit. Optional. If the <filename> is omitted, the editor
opens the current source file. If you specify a non-existent filename, it will open a new
file.
See also
notepad (CR-211), EDITOR (UM-521) environment variable

CR-158 enablebp
enablebp
The enablebp command turns on breakpoints and when commands that were previously
disabled.
Syntax
enablebp
[<id#>]
Arguments
<id#>
Specifies a breakpoint or when statement id to enable. Optional. If you don’t specify an
id#, all breakpoints are enabled. Note that C breakpoint id#s (see "C Debug" (UM-399))
are prefixed with "c.".
See also
bd (CR-70), bp (CR-75), disablebp command (CR-148), onbreak (CR-214), resume (CR-249),
when (CR-407), Chapter 16 - C Debug (UM-399)

enable_menu CR-159
enable_menu
The enable_menu command enables a previously-disabled menu. The menu will be
changed from grayed-out to normal and will become responsive. Returns nothing.
Syntax
enable_menu
Arguments
<window_name>
<menu_path>
Name of the Tk menu-widget path. Required.
Examples
enable_menu "" File
Enables the previously-disabled File menu of the Main window.
enable_menu .mywindow File
Enables the previously-disabled File menu of the mywindow window.
See also
add_menu (CR-56), disable_menu (CR-149)

CR-160 enable_menuitem
enable_menuitem
The enable_menuitem command enables a previously-disabled menu item. The menu
item will be changed from grayed-out to normal, and will become responsive. Returns
nothing.
Syntax
enable_menuitem
<window_name> <menu_path> <label>
Arguments
<window_name>
<menu_path>
Name of the Tk menu-widget path. The path may include a submenu as shown in the
example below. Required.
<label>
Menu item text. Required.
Examples
enable_menuitem .mywindow file.save "Save Results As..."
This command locates the mywindow window and enables the previously-disabled Save
Results As... menu item in the save submenu of the file menu.
See also
add_menuitem (CR-59), disable_menuitem (CR-150)

environment CR-161
environment
The environment, or env command, allows you to display or change the current dataset
and region/signal environment.
Syntax
environment
[-dataset] [-nodataset] [<pathname>]
Arguments
-dataset
Displays the specified environment pathname with a dataset prefix. Optional. Dataset
prefixes are displayed by default if more than one dataset is open during a simulation
session.
-nodataset
Displays the specified environment pathname without a dataset prefix. Optional.
<pathname>
Specifies the pathname to which the current region/signal environment is to be changed.
See "Object name syntax" (CR-12) for information on specifying pathnames. Optional.
If omitted the command causes the pathname of the current region/signal environment to
be displayed.
Examples
env
Displays the pathname of the current region/signal environment.
env-dataset test
Changes all unlocked windows to the context of the "test" dataset.
env test:/top/foo
Changes all unlocked windows to the context "test: /top/foo".
env blk1/u2
Moves down two levels in the design hierarchy.
env /
Moves to the top level of the design hierarchy.

CR-162 examine
examine
The examine command examines one or more objects and displays current values (or the
values at a specified previous time) in the Transcript pane. It optionally can compute the
value of an expression of one or more objects. If you are using C Debug (UM-399), examine
can display the value of a C variable as well.
The following objects can be examined:
• VHDL
signals, shared variables, process variables, constants, and generics
• Verilog
nets, registers, and variables
• C
variables
• SystemC
signals, FIFOs, ports, and member variables of modules
When stopped in C code, examine (with no arguments) displays the values of the local
variables and arguments of the current C function. For specific information related to
viewing SystemC objects see "SystemC object and type display in ModelSim" (UM-180).
To display a previous value, specify the desired time using the -time option. To compute
an expression, use the -expr option. The -expr and the -time options may be used together.
Virtual signals and functions may also be examined within the GUI (actual signals are
examined in the kernel).
The following rules are used by the examine command to locate an HDL object:
• If the name does not include a dataset name, then the current dataset is used.
• If the name does not start with a path separator, then the current context is used.
• If the name is a path separator followed by a name that is not the name of a top-level
design unit, then the first top-level design unit in the design is used.
• For a relative name containing a hierarchical path, if the first object name cannot be found
in the current context, then an upward search is done up to the top of the design hierarchy
to look for a matching object name.
• If no objects of the specified name can be found in the specified context, then an upward
search is done to look for a matching object in any visible enclosing scope up to an
instance boundary. If at least one match is found within a given context, no (more)
upward searching is done; therefore, some objects that may be visible from a given
context will not be found when wildcards are used if they are within a higher enclosing
scope.
• The wildcards '*' and '?' can be used at any level of a name except in the dataset name and
inside of a slice specification.
• A wildcard character will never match a path separator. For example, /dut/* will match
/dut/siga and /dut/clk. However, /dut* won’t match either of those.
See "Design object names" (CR-12) for more information on specifying names.

examine CR-163
Syntax
examine
[-delta <delta>] [-env <path>] [-in] [-out] [-inout] [-internal] [-ports]
[-expr <expression>] [-name] [-<radix>] [-time <time>] [-value] <name>...
Arguments
-delta <delta>
Specifies a simulation cycle at the specified time from which to fetch the value. Optional.
The default is to use the last delta of the time step. The objects to be examined must be
logged via the add list, add wave, or log command in order for the examine command to
be able to return a value for a requested delta. This option can be used only with objects
that have been logged via the add list, add wave, or log command.
-env <path>
Specifies a path in which to look for an object name. Optional.
-expr <expression>
Specifies an expression to be evaluated. Optional. The objects to be examined must be
logged via the add list, add wave, or log command in order for the examine command to
be able to evaluate the specified expression. If the -time argument is present, the
expression will be evaluated at the specified time, otherwise it will be evaluated at the
current simulation time. See "GUI_expression_format" (CR-22) for the format of the
expression. The expression must be placed within curly braces.
-in
Specifies that <name> include ports of mode IN. Optional.
-out
Specifies that <name> include ports of mode OUT. Optional.
-inout
Specifies that <name> include ports of mode INOUT. Optional.
-internal
Specifies that <name> include internal (non-port) signals. Optional.
-ports
Specifies that <name> include all ports. Optional. Has the same effect as specifying -in,
-inout, and -out together.
-name
Displays object name(s) along with the value(s). Optional. Default is -value behavior
(see below).
The lecho command (CR-188) will return the output of an examine command in
"pretty-print" format. For example,
lecho [examine -name clk prw pstrb]
-<radix>
Specifies the radix for the objects that follow in the command. Valid entries (or any
unique abbreviations) are: binary, ascii, unsigned, decimal, octal, hex, symbolic, and
default. If no radix is specified for an enumerated type, the default representation is used.
You can change the default radix for the current simulation using the radix command

CR-164 examine
(CR-241). You can change the default radix permanently by editing the DefaultRadix (UM-
-time <time>
Specifies the time value between 0 and $now for which to examine the objects. Optional.
If an expression is specified it will be evaluated at that time. The objects to be examined
must be logged via the add list, add wave, or log command in order for the examine
command to be able to return a value for a requested time. This option can be used only
with objects that have been logged via the add list, add wave, or log command.
If the <time> field uses a unit, the value and unit must be placed in curly braces. For
example, the following are equivalent for ps resolution:
exa -time {3.6 ns} signal_a
exa -time 3600 signal_a
-value
Returns value(s) as a curly-braces separated Tcl list. Default. Use to toggle off a previous
use of -name.
<name>...
Specifies the name of any HDL or SystemC object. Required (except when the -expr
option is used). All object types are allowed, except those of the type file. Multiple names
and wildcards are accepted. Spaces, square brackets, and extended identifiers require
curly braces; see examples below for more details. To examine a VHDL variable you can
add a process label to the name. For example (make certain to use two underscore
characters):
exa line__36/i
Examples
examine /top/bus1
Returns the value of /top/bus1.
examine {rega[16]}
Returns the value of the subelement of rega that is specified by the index (i.e., 16). Note
that you must use curly braces when examining subelements.
examine {foo[20:22]}
Returns the value of the contiguous subelements of foo specified by the slice (i.e., 20:22).
Note the curly braces.
examine {/top/\My extended id\ }
Note that when specifying an object that contains an extended identifier as the last part
of the name, there must be a space after the closing '\' and before the closing '}'.
examine -time {3450 us} -expr {/top/bus and $bit_mask}
In this example the -expr option specifies a signal path and user-defined Tcl variable.
The expression will be evaluated at 3450us.
examine -time $t -name $fifo "${fifo}(1 to 3)" ${fifo}(1)
Using the ${fifo} syntax limits the variable to the simple name fifo, instead of
interpreting the parenthesis as part of the variable. Quotes are needed when spaces are
involved; and by using quotes (") instead of braces, the Tcl interpreter will expand
variables before calling the command.

examine CR-165
examine -expr {clk’event && (/top/xyz == 16’hffae)}

Because -time is not specified, this expression will be evaluated at the current simulation
time. Note the signal attribute and array constant specified in the expression.
Commands like find (CR-176) and examine return their results as a Tcl list (just a blank-
separated list of strings). You can do things like:
foreach sig [find ABC*] {echo "Signal $sig is [exa $sig]" ...}
if {[examine -bin signal_12] == “11101111XXXZ”} {...}
examine -hex [find *]
The Tcl variable array, $examine (), can also be used to return values. For example,
$examine (/clk). You can also examine an object in the "Source window" (GR-199) by
selecting it with the right mouse button.
examine x
Prints the value of C variable x.
examine *p
Prints the value *p (de-references p).
examine ip->in1
Prints the structure member in1 pointed to by ip.
See also
"Design object names" (CR-12), "Wildcard characters" (CR-17), "GUI_expression_format"
(CR-22), Chapter 16 - C Debug (UM-399)

CR-166 exit
exit
The exit command exits the simulator and the ModelSim application.
If you want to stop the simulation using a when command (CR-407), you must use a stop
command (CR-273) within your when statement. DO NOT use an exit command or a quit
command (CR-240). The stop command acts like a breakpoint at the time it is evaluated.
Syntax
exit
[-force]
Argument
-force
Quits without asking for confirmation. Optional; if this argument is omitted, ModelSim
asks you for confirmation before exiting.

fcover clear CR-167
fcover clear
The fcover clear command removes all functional coverage count data and comment
meta-data from the current simulation. It doesn’t affect the configuration of coverage
directives.
Syntax
fcover clear
See also
Chapter 15 - Functional coverage with PSL and ModelSim, "Clearing functional coverage
data" (UM-397), fcover configure command (CR-169)

CR-168 fcover comment
fcover comment
The fcover comment command adds comment meta-data to the current functional
coverage database.
Use the command to encode the characteristics (arguments, randomization seed, etc.) of the
set of tests that produced the current functional coverage so that there is some traceability
from coverage to tests.
When coverage databases are merged, comment meta-data is accumulated, so that a merged
database has a set of multiple comments associated with it.
Syntax
fcover comment
[-append "<text_string>"] [-clear]
Arguments
-append "<text_string>"
Adds the specified <text_string> to the current functional coverage database. Optional.
-clear
Clears all comments from the current functional coverage database. Optional.
Examples
fcover comment -append "Test1 +2 +seed=1023 +op=add"
Adds the test description to the current comments.
fcover comment
Displays all comments in the current database.
fcover comment -clear
Clears all comments from the current database.
See also
Chapter 15 - Functional coverage with PSL and ModelSim

fcover configure CR-169
fcover configure
The fcover configure command enables, disables, and sets coverage targets for PSL
functional coverage directives.
If you invoke it without any optional arguments, the command reports the current settings
for the specified directive(s).
Syntax
fcover configure
[-at_least <count>] <coverage_directive> [-disable] [-enable]
[-exclude] [-include] [-include] [-log on|off] [-recursive] [-weight
<integer>]
Arguments
-at_least <count>
Specifies a target count for the selected coverage point(s). The <count> value must be a
positive integer value. A directive is considered 100% covered when the AtLeast count
is reached. Optional. The default value is 1. You can change the permanent default by
editing the CoverAtLeast (UM-531) variable in the modelsim.ini file.
<coverage_directive>
Identifies the functional coverage directive(s) to which the configuration parameters
should be applied. Multiple directives may be specified. Wildcards are allowed.
Required.
-disable
Disables incrementing on the specified directive(s). Optional. Disabled directives still
count toward overall coverage if they had coverage events prior to being disabled. You
can change the permanent default by editing the CoverEnable (UM-531) variable in the
modelsim.ini file.
-enable
Enables incrementing on the specified directive(s). Optional. Default. You can change
the permanent default by editing the CoverEnable (UM-531) variable in the modelsim.ini
file.
-exclude
Removes the specified directive(s) from the current functional coverage database.
Excluded directives will still show up in the Functional Coverage pane but they do not
count toward coverage totals nor do they show up in reports. Optional.
-include
Adds the specified directive(s) to the current functional coverage database. Optional.
Default.
-limit <count>
Specifies the number of cover directive hits before the directive is "auto disabled."
Optional. The default value is 1. You can change the permanent default by editing the
CoverLimit (UM-531) variable in the modelsim.ini file.
This argument is useful if you have a directive that is already covered but is evaluated
frequently. Disabling such directives improves simulation performance.

CR-170 fcover configure
-log on|off
Specifies whether to log directive counts to the transcript. Even with logging off,
coverage counts are incremented in the underlying database.This option applies to all
directives that follow it in the command line.
One of the following values is required:
on–Enable logging. Default.
off–Disable logging.
You can change the permanent default by setting the CoverLog (UM-531) variable in the
modelsim.ini file.
-recursive
recursively into subregions. If omitted, the search is limited to the selected region.
Optional.
-weight <integer>
Specifies a relative weighting for the specified coverage directive. A directive with a
weight of 2 will have twice the impact on the aggregated coverage numbers as will a
directive with a weight of 1. The weight must be a natural integer (>= 0). If its weight is
set to 0 but a directive is otherwise enabled, its coverage will not count toward the
aggregated coverage statistics. The default value is 1. Optional.
Examples
fcover configure *
Reports the current configuration settings for the functional coverage directives in the
current scope.
fcover configure -enable -at_least 20 /top/reset_trigger
Enables coverage counting for /top/reset_trigger with an AtLeast count of 20.
fcover configure -r -disable /top/*
Disables all functional coverage directives in the region /top and all regions below /top.
See also
Chapter 15 - Functional coverage with PSL and ModelSim, "Configuring functional
coverage directives" (UM-386)

fcover reload CR-171
fcover reload
The fcover reload command seeds functional coverage statistics with results from a
previous coverage analysis. This allows you to gather statistics from multiple simulation
runs and aggregate them into a single set of statistics.
Note that this command must be run on an elaborated simulation database. To merge
coverage databases in offline mode, use the vcover merge command (CR-320).
Syntax
fcover reload
<filename> [-install <path>] [-merge] [-strip <n>]
Arguments
<filename>
Specifies the functional coverage database to reload. Required. This file should be the
output of a previous fcover save command (CR-175).
-install <path>
Adds <path> as additional hierarchy on the front end of instance and signal names in the
data file. Optional. This argument allows you to merge coverage results from simulations
that have different hierarchies.
-merge
Merges loaded coverage data with current coverage data. Optional. Without this
argument, loading coverage data overwrites existing data.
-strip <n>
Removes <n> levels of hierarchy from instance and signal names in the data file.
Examples
fcover reload run2
Replaces functional coverage results from the current simulation with results loaded
from run2.
fcover reload -merge -install /top/dut/mac ./mac128_test_stats.fcdb
Merges the current coverage results with those in mac128_test_stats.fcdb. The signals
and instances in the database are given the new path /top/dut/mac. This methodology can
be useful for merging statistics derived from a block simulation into the statistics of an
overall chip simulation.
fcover reload -merge -strip 2 ./system_test_stats.fcdb
Merges the current coverage results with those in system_test_stats.fcdb. The signals and
instances in the database have the top 2 levels of hierarchy removed from their names
(e.g., /systop/unit1). This methodology can be useful for merging statistics derived from
a system simulation into the statistics of an individual chip simulation.

CR-172 fcover reload
See also
Chapter 15 - Functional coverage with PSL and ModelSim, "Reloading/merging functional
coverage data" (UM-396), fcover save command (CR-175)

fcover report CR-173
fcover report
The fcover report command produces an ASCII report of the current functional coverage
results.
For each directive instance, the report includes by default the full instance path, the
coverage count or percentage, the design unit, the source file name, and the source line
number. The report is sorted by design unit. For each design unit, the report includes a
coverage percentage computed from each coverage directive in that design unit.
Note that a report response of "No match" indicates that the report was empty. For example,
"fcover report -du foo -r *" where there is no design unit "foo" will result in "No match."
Syntax
fcover report
[-above <percent>] [-aggregated] [-append] [-below <percent>] [-comment]
[-config] <coverage_directive> [-details] [-du <name>]
[-noaggregated] [-nocomment] [-nodetails] [-output <filename>]
[-recursive] [-xml] [-zero]
Arguments
-above <percent>
report. Optional.
-aggregated
Includes aggregated statistics in the output. Optional. Default.
-append
Appends this report to the named report file. Optional.
-below <percent>
report. Optional.
-comment
Specifies that comments should be included with the report. Comments are excluded by
default. Optional.
-config
Specifies that the current configuration of each directive be included in the report. Has
no effect unless you also specify the -details argument. Optional.
<coverage_directive>
Identifies the functional coverage directive(s) to include in the report. Multiple directives
may be specified. Wildcards are allowed. Required if -du <name> isn’t specified.
-details
Includes details associated with each cover directive (e.g., count) in the output. Optional.
Default.
-du <name>
Specifies that only objects belonging to the given design unit be included in the report.
Optional.

CR-174 fcover report
-noaggregated
Excludes aggregated statistics from the output. The statistics are included by default.
Optional.
-nocomment
Specifies that comments should be excluded from the report. Optional. Default.
-nodetails
Excludes details associated with each cover directive (e.g., count) from the output.
Details are included by default. Optional.
-output <filename>
Specifies a file name for the report. The default is to write the report to the Transcript
(GUI mode) or stdout (batch mode). Environment variables may be used in the
pathname. Optional.
-recursive
For use with wildcard matching and reporting aggregated statistics by design unit.
Specifies that the scope of the matching is to descend recursively into subregions. If
omitted, the search is limited to the selected region.
-xml
Formats the report data in XML. Optional.
-zero
Specifies that only objects with coverage counts of exactly zero be included in the report.
Takes precedence over the -above and -below values. This is a useful option for locating
coverage "holes" (i.e., coverage events that never happened during simulation). Optional.
Examples
fcover report -r /*
Reports all cover directives to the Transcript pane.
fcover report -r /* -du memory -file report.txt -xml
Saves an XML report to file report.txt for design unit memory only.
fcover report -aggregated -r /top/module1/*
Reports on directives in and beneath /top/module1 including aggregated statistics.
See also
Chapter 15 - Functional coverage with PSL and ModelSim, "Reporting functional coverage
statistics" (UM-391), vcover report command (CR-322)

fcover save CR-175
fcover save
The fcover save command saves the current functional coverage database to a re-loadable
file.
Syntax
fcover save
<filename>
Arguments
<filename>
Specifies the file to be created. If the file already exists, it is replaced. Required.
See also
Chapter 15 - Functional coverage with PSL and ModelSim, "Saving functional coverage
data" (UM-395), fcover reload command (CR-171)

CR-176 find
find
The find command locates objects in the design whose names match the name specification
you provide. You must specify the type of object you want to find. When searching for nets
and signals, the find command returns the full pathname of all nets, signals, registers,
variables, and named events that match the name specification.
When searching for nets and signals, the order in which arguments are specified is
unimportant. When searching for virtuals, however, all optional arguments must be
specified before any object names.
The following rules are used by the find command to locate an object:
• If the name does not include a dataset name, then the current dataset is used.
• If the name does not start with a path separator, then the current context is used.
• If the name is a path separator followed by a name that is not the name of a top-level
design unit, then the first top-level design unit in the design is used.
• For a relative name containing a hierarchical path, if the first object name cannot be found
in the current context, then an upward search is done up to the top of the design hierarchy
to look for a matching object name.
• If no objects of the specified name can be found in the specified context, then an upward
search is done to look for a matching object in any visible enclosing scope up to an
instance boundary. If at least one match is found within a given context, no (more)
upward searching is done; therefore, some objects that may be visible from a given
context will not be found when wildcards are used if they are within a higher enclosing
scope.
• The wildcards '*' and '?' can be used at any level of a name except in the dataset name and
inside of a slice specification. Square bracket ’[]’ wildcards can also be used.
• A wildcard character will never match a path separator. For example, /dut/* will match
/dut/siga and /dut/clk. However, /dut* won’t match either of those.
• Because square brackets are wildcards in the find command, only parentheses ’()’ can be
used to index or slice arrays.
• The WildcardFilter Tcl preference variable is used by the find command to exclude the
specified types of objects when performing the search.
See "Design object names" (CR-12) for more information on specifying names.
Syntax
find nets | signals
[-in] [-inout] [-internal] <object_name> ... [-nofilter] [-out] [-ports]
[-recursive]
find instances
[-recursive] <object_name> ...
find virtuals
[-kind <kind>] [-unsaved] <object_name> ...
find classes
[<class_name>]

find CR-177
find objects
[-class <class_name>] [-isa <class_name>] [<object_name>]
Arguments for nets and signals

-in
Specifies that the scope of the search is to include ports of mode IN. Optional.
-inout
Specifies that the scope of the search is to include ports of mode INOUT. Optional.
-internal
Specifies that the scope of the search is to include internal (non-port) objects. Optional.
<object_name> ...
Specifies the net or signal for which you want to search. Required. Multiple nets and
signals and wildcard characters are allowed. Wildcards cannot be used inside of a slice
specification. Spaces, square brackets, and extended identifiers require special syntax;
see the examples below for more details.
-nofilter
Specifies that the WildcardFilter Tcl preference variable be ignored when finding signals
or nets. Optional.
-out
Specifies that the scope of the search is to include ports of mode OUT. Optional.
-ports
Specifies that the scope of the search is to include all ports. Optional. Has the same effect
as specifying -in, -out, and -inout together.
-recursive
Specifies that the scope of the search is to descend recursively into subregions. Optional.
If omitted, the search is limited to the selected region.
Arguments for instances

-recursive
<object_name> ...
Specifies the instance for which you want to search. Required. Multiple instances and
wildcard characters are allowed.
Arguments for virtuals

-kind <kind>
Specifies the kind of virtual object for which you want to search. Optional. <kind> can
be one of designs, explicits, functions, implicits, or signals.
-unsaved
Specifies that ModelSim find only virtuals that have not been saved to a format file.
<object_name> ...
Specifies the virtual object for which you want to search. Required. Multiple virtuals and
wildcard characters are allowed.

CR-178 find
Arguments for classes

<class_name>
Specifies the incrTcl class for which you want to search. Optional. Wildcard characters
are allowed. The options for class_name include nets, objects, signals, and virtuals. If you
do not specify a class name, the command returns all classes in the current namespace
context. See "incrTcl commands" in the Tcl Man Pages for more information.
Arguments for objects

-class <class_name>
Restricts the search to objects whose most-specific class is class_name. Optional.
-isa <class_name>
Restricts the search to those objects that have class_name anywhere in their heritage.
Optional.
<object_name>
Specifies the incrTcl object for which you want to search. Optional. Wildcard characters
are allowed. If you do not specify an object name, the command returns all objects in the
current namespace context. See "incrTcl commands" in the Tcl Man Pages for more
information.
Examples
find signals -r /*
Finds all signals in the entire design.
find nets -in /top/xy*
Finds all input signals in region /top that begin with the letters "xy".
find signals -r u1/u2/cl*
Finds all signals in the design hierarchy at or below the region <current_context>/u1/u2
whose names begin with "cl".
find signals {s[1]}
Finds a signal named s1. Note that you must enclose the object in curly braces because
of the square bracket wildcard characters.
find signals {s[123]}
Finds signals s1, s2, or s3.
find signals s(1)
Finds the element of signal s that is indexed by the value 1. Note that the find command
uses parentheses, not square brackets, to specify a subelement index.
find signals {/top/data(3 downto 0)}
Finds a 4-bit array named data. Note that you must use curly braces due to the spaces in
the array slice specification.
find signals {/top/\My extended id\ }
Note that when specifying an object that contains an extended identifier as the last part
of the name, there must be a space after the closing '\' and before the closing '}'.

find CR-179
if {[find signals /dut/core/pclk] != ""} {

echo "pclk does exist"
}
If /dut/core/pclk exists, prints the message "pclk does exist" in the transcript. This would
typically be run in a Tcl script.
Additional search options

To search for HDL objects within a specific display window, use the search command (CR-
260)or select Edit > Find.
See also
"Design object names" (CR-12), "Wildcard characters" (CR-17)

CR-180 force
force
The force command allows you to apply stimulus interactively to VHDL signals and
Verilog nets. Since force commands (like all commands) can be included in a macro file,
it is possible to create complex sequences of stimuli.
You can force Virtual signals (UM-233) if the number of bits corresponds to the signal value.
You cannot force virtual functions. In VHDL and mixed models, you cannot force an input
port that is mapped at a higher level or that has a conversion function on the input.
You cannot force bits or slices of a register; you can force only the entire register. You
cannot force VHDL or Verilog variables (reg, integer, time, real (or realtime)); these must
be changed. See the change command (CR-81).
You cannot force a VHDL alias of a VHDL signal.
You cannot force any objects within SystemC modules.
Syntax
force
[-freeze | -drive | -deposit] [-cancel <time>] [-repeat <time>]
<object_name> <value> [<time>] [, <value> <time> ...]
Arguments
-freeze
Freezes the object at the specified value until it is forced again or until it is unforced with
a noforce command (CR-208). Optional.
-drive
Attaches a driver to the object and drives the specified value until the object is forced
again or until it is unforced with a noforce command (CR-208). Optional.
This option is illegal for unresolved signals.
-deposit
Sets the object to the specified value. The value remains until there is a subsequent driver
transaction, or until the object is forced again, or until it is unforced with a noforce
command (CR-208). Optional.
If one of the -freeze, -drive, or -deposit options is not used, then -freeze is the default
for unresolved objects and -drive is the default for resolved objects.
If you prefer -freeze as the default for resolved and unresolved VHDL signals, change
the default force kind in the DefaultForceKind (UM-531) preference variable.
-cancel <time>
Cancels the force command at the specified <time>. The time is relative to the current
time unless an absolute time is specified by preceding the value with the character @.
Cancellation occurs at the last simulation delta cycle of a time unit. A value of zero
cancels the force at the end of the current time period. Optional.

force CR-181
-repeat <time>
Repeats the force command, where <time> is the time at which to start repeating the
cycle. The time is relative to the current time. A repeating force command will force a
value before other non-repeating force commands that occur in the same time step.
Optional.
<object_name>
Specifies the name of the HDL object to be forced. Required. A wildcard is permitted
only if it matches one object. See "Design object names" (CR-12) for the full syntax of an
object name. The object name must specify a scalar type or a one-dimensional array of
character enumeration. You may also specify a record subelement, an indexed array, or
a sliced array, as long as the type is one of the above. Required.
<value>
Specifies the value to which the object is to be forced. The specified value must be
appropriate for the type. Required.
A VHDL one-dimensional array of character enumeration can be forced as a sequence of
character literals or as a based number with a radix of 2, 8, 10 or 16. For example, the
following values are equivalent for a signal of type bit_vector (0 to 3):
Value Description
1111 character literal sequence
2#1111 binary radix
10#15 decimal radix
16#F hexadecimal radix
Note: For based numbers in VHDL, ModelSim translates each 1 or 0 to the appropriate
value for the number’s enumerated type. The translation is controlled by the translation
table in the pref.tcl file. If ModelSim cannot find a translation for 0 or 1, it uses the left
bound of the signal type (type’left) for that value.
<time>
Specifies the time to which the value is to be applied. The time is relative to the current
time unless an absolute time is specified by preceding the value with the character @. If
the time units are not specified, then the default is the resolution units selected at
simulation start-up. Optional.
A zero-delay force command causes the change to occur in the current (rather than the
next) simulation delta cycle.

CR-182 force
Examples
force input1 0
Forces input1 to 0 at the current simulator time.
force bus1 01XZ 100 ns
Forces bus1 to 01XZ at 100 nanoseconds after the current simulator time.
force bus1 16#f @200
Forces bus1 to 16#F at the absolute time 200 measured in the resolution units selected at
simulation start-up.
force input1 1 10, 0 20 -r 100
Forces input1 to 1 at 10 time units after the current simulation time and to 0 at 20 time
units after the current simulation time. This cycle repeats starting at 100 time units after
the current simulation time, so the next transition is to 1 at 100 time units after the current
simulation time.
force input1 1 10 ns, 0 {20 ns} -r 100ns
Similar to the previous example, but also specifies the time units. Time unit expressions
preceding the "-r" must be placed in curly braces.
force s 1 0, 0 100 -repeat 200 -cancel 1000
Forces signal s to alternate between values 1 and 0 every 100 time units until time 1000.
Cancellation occurs at the last simulation delta cycle of a time unit. So,
force s 1 0 -cancel 0
will force signal s to 1 for the duration of the current time period.
when {/mydut/siga = 10#1} {
force -deposit /mydut/siga 10#85
}
Forces siga to decimal value 85 whenever the value on the signal is 1.
See also
noforce (CR-208), change (CR-81)
Note: You can configure defaults for the force command by setting the
DefaultForceKind variable in the modelsim.ini file. See "Force command defaults" (UM-
539).

gdb dir CR-183
gdb dir
The gdb dir command sets the source directory search path for the C debugger. See
"Setting up C Debug" (UM-402) for more information.
Invoking this command starts the C debugger if it is not already running.
Syntax
gdb dir
[<src_directory_path_1>[:<src_directory_path_2>[:<...>]]]
Argument
<src_directory_path_1>[:<src_directory_path_2>[:<...>]]
Specifies one or more directories for C source code. Optional. If no directory is specified,
the source directory search path is set to the gdb default–$cdir:$cwd.
Examples
gdb dir /a/b/c:~/foo
Sets the source directory search path to /a/b/c:~/foo:$cdir:$cwd
See also
Chapter 16 - C Debug (UM-399)

CR-184 getactivecursortime
getactivecursortime
The getactivecursortime command gets the time of the active cursor in the Wave window.
Returns the time value.
Syntax
getactivecursortime
[-window <wname>]
Arguments
-window <wname>
Specifies an instance of the Wave window that is not the default. Otherwise, the default
Wave window is used. Optional. Use the view command (CR-332) to change the default
window.
Examples
getactivecursortime
Returns:
980 ns
See also
left (CR-189), right (CR-250)

getactivemarkertime CR-185
getactivemarkertime
The getactivemarkertime command gets the time of the active marker in the List window.
Returns the time value. If -delta is specified, returns time and delta.
Syntax
getactivemarkertime
[-window <wname>] [-delta]
Arguments
-window <wname>
Specifies an instance of the List window that is not the default. Otherwise, the default List
window is used. Optional. Use the view command (CR-332) to change the default
window.
-delta
Returns the delta value. Optional. Default is to return only the time.
Examples
getactivemarkertime -delta
Returns:
980 ns, delta 0
See also
down (CR-152), up (CR-290)

CR-186 help
help
The help command displays in the Transcript pane a brief description and syntax for the
specified command.
Syntax
help
[<command> | <topic>]
Arguments
<command>
Specifies the command for which you want help. The entry is case and space sensitive.
Optional.
<topic>
Specifies a topic for which you want help. The entry is case and space sensitive. Optional.
Specify one of the following six topics:
Topic Description
commands Lists all available commands and topics
debugging Lists debugging commands
execution Lists commands that control execution of

your simulation.
Tcl Lists all available Tcl commands.
Tk Lists all available Tk commands
incrTCL Lists all available incrTCL commands

history CR-187
history
The history command lists the commands you have executed during the current session.
History is a Tcl command. For more information, consult the Tcl Man Pages.
Syntax
history
[clear] [keep <value>]
Arguments
clear
Clears the history buffer. Optional.
keep <value>
Specifies the number of executed commands to keep in the history buffer. Optional. The
default is 50.

CR-188 lecho
lecho
The lecho command takes one or more Tcl lists as arguments and pretty-prints them to the
Transcript pane. Returns nothing.
Syntax
lecho
<args> ...
Arguments
<args> ...
Any Tcl list created by a command or user procedure.
Examples
lecho [configure wave]
Prints the Wave window configuration list to the Transcript pane.

left CR-189
left
The left command searches left (previous) for signal transitions or values in the specified
Wave window. It executes the search on signals currently selected in the window, starting
at the time of the active cursor. The active cursor moves to the found location.
Use this command to move to consecutive transitions or to find the time at which a
waveform takes on a particular value, or an expression of multiple signals evaluates to true.
See the right command (CR-250) for related functionality.
The procedure for using left entails three steps: click on the desired waveform; click on the
desired starting location; issue the left command. (The seetime command (CR-264) can
Syntax
left
Arguments
The waveform display will be searched until the expression evaluates to a boolean true
condition. Optional. The expression may involve more than one signal, but is limited to
signals that have been logged in the referenced Wave window. A signal may be specified
either by its full path or by the shortcut label displayed in the Wave window.
-falling
Searches for a falling edge on the specified signal if that signal is a scalar signal. If it is
not a scalar signal, the option will be ignored. Optional.
-noglitch
Looks at signal values only on the last delta of a time step. For use with the -value option
only. Optional.
-rising
Searches for a rising edge on the specified signal if that signal is a scalar signal. If it is
-value <sig_value>
Specifies a value of the signal to match. Must be specified in the same radix in which the
selected waveform is displayed. Case is ignored, but otherwise the value must be an exact
string match — don't-care bits are not yet implemented. Only one signal may be selected,
but that signal may be an array. Optional.
-window <wname>
Specifies an instance of the Wave window that is not the default. Optional. Otherwise,
the default Wave window is used. Use the view command (CR-332) to change the default
window.

CR-190 left
<n>
Specifies to find the nth match. If less than n are found, the number found is returned with
a warning message, and the cursor is positioned at the last match. Optional. The default
is 1.
Examples
left -noglitch -value FF23 2
Finds the second time to the left at which the selected vector transitions to FF23, ignoring
glitches.
left
Goes to the previous transition on the selected signal.
The following examples illustrate search expressions that use a variety of signal attributes,
left -expr {clk’rising && (mystate == reading) && (/top/u3/addr ==
32’habcd1234)}
Searches left for an expression that evaluates to a boolean 1 when signal clk just changed
from low to high and signal mystate is the enumeration reading and signal /top/u3/addr
is equal to the specified 32-bit hex constant; otherwise is 0.
left -expr {(/top/u3/addr and 32’hff000000) == 32’hac000000}
Searches left for an expression that evaluates to a boolean 1 when the upper 8 bits of the
32-bit signal /top/u3/addr equals hex ac.
left -expr {((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode ==
writing)}
Searches left for an expression that evaluates to a boolean 1 when logfile time is between
23 and 54 microseconds, clock just changed from low to high, and signal mode is
enumeration writing.
Note: "Wave window mouse and keyboard shortcuts" (UM-609) are also available for
next and previous edge searches. Tab searches right (next) and shift-tab searches left
(previous).
See also
"GUI_expression_format" (CR-22), right (CR-250), seetime (CR-264), view (CR-332)

log CR-191
log
The log command creates a wave log format (WLF) file containing simulation data for all
HDL objects whose names match the provided specifications. Objects that are displayed
using the add list (CR-48) and add wave (CR-52) commands are automatically recorded in
the WLF file. The log is stored in a WLF file in the working directory. By default the file
is named vsim.wlf. You can change the default name using the -wlf option of the vsim (CR-
373) command.
If no port mode is specified, the WLF file contains data for all objects in the selected region
whose names match the object name specification.
The WLF file is the source of data for the List and Wave windows. An object that has been
logged and is subsequently added to the List or Wave window will have its complete
history back to the start of logging available for listing and waving.
Limitations: Verilog memories and VHDL variables can be logged using the variable’s full
name only.
Syntax
log
[-depth <level>] [-flush] [-howmany] [-in] [-inout] [-internal]
[-optcells] [-out] [-ports] [-recursive] <object_name> ...
Arguments
-depth <level>
-flush
Adds region data to the WLF file after each individual log command. Optional. Default
is to add region data to the log file only when a command that advances simulation time
is executed (e.g., run, step, etc.) or when you quit the simulation.
-howmany
Returns an integer indicating the number of signals found. Optional.
-in
Specifies that the WLF file is to include data for ports of mode IN whose names match
the specification. Optional.
-inout
Specifies that the WLF file is to include data for ports of mode INOUT whose names
match the specification. Optional.
-internal
Specifies that the WLF file is to include data for internal (non-port) objects whose names
match the specification. Optional.
-optcells
pattern.

CR-192 log
-out
Specifies that the WLF file is to include data for ports of mode OUT whose names match
-ports
Specifies that the scope of the search is to include all ports. Optional.
-recursive
If omitted, the search is limited to the selected region. You can use the -depth argument
to specify how far down the hierarchy to descend.
<object_name>
Specifies the object name which you want to log. Required. Multiple object names may
be specified. Wildcard characters are allowed. (Note that the WildcardFilter Tcl
preference variable identifies types to ignore when matching objects with wildcard
patterns.)
Examples
log -r /*
Logs all objects in the design.
log -out *
Logs all output ports in the current design unit.
See also
add list (CR-48), add wave (CR-52), nolog (CR-209), Chapter 8 - WLF files (datasets) and
virtuals (UM-225), and "Wildcard characters" (CR-17)
Note: The log command is also known as the "add log" command.

lshift CR-193
lshift
The lshift command takes a Tcl list as an argument and shifts it in-place, one place to the
left, eliminating the left-most element. The number of shift places may also be specified.
Returns nothing.
Syntax
lshift
<list> [<amount>]
Arguments
<list>
Specifies the Tcl list to target with lshift. Required.
<amount>
Specifies the number of places to shift. Optional. Default is 1.
Examples
proc myfunc args {
# throws away the first two arguments
lshift args 2
...
See also
See the Tcl man pages (Help > Tcl Man Pages) for details.

CR-194 lsublist
lsublist
The lsublist command returns a sublist of the specified Tcl list that matches the specified
Tcl glob pattern.
Syntax
lsublist
<list> <pattern>
Arguments
<list>
Specifies the Tcl list to target with lsublist. Required.
<pattern>
Specifies the pattern to match within the <list> using Tcl glob-style matching. Required.
Examples
In the example below, variable ‘t’ returns "structure signals source".
set window_names "structure signals variables process source wave list
dataflow"
set t [lsublist $window_names s*]
See also
The set command is a Tcl command. See the Tcl man pages (Help > Tcl Man Pages) for
details.

macro_option CR-195
macro_option
This command is available for UNIX only (excluding Linux).
The macro_option command controls the speed and delay of macro (DO file) playback,
plus the level of debugging feedback. If invoked without any options, macro_option
returns all current settings; returns a specific setting if invoked with an option and no
argument; returns the previous setting if invoked with both an option and an argument.
Syntax
macro_option
[speed fast | demo] | [delay <delay_time>] | [debug <level>]
Arguments
speed fast | demo
Set the macro playback speed to fast or demo. Optional.
delay <delay_time>
Set the delay time in milliseconds; delay is the time between events in demo mode.
Optional.
debug <level>
Set the debug level from 1 to 9; 9 giving the most feedback. Optional.
See also
play (CR-218), run (CR-252)

CR-196 mem display
mem display
The mem display command prints to the Transcript pane the memory contents of the
specified instance. As a shorthand, if the given instance path contains only a single array
signal or variable, the signal or variable name need not be specified.
Address radix, data radix, and address range for the output can also be specified, as well as
special output formats.
You can redirect the output of the mem display command into a file for later use with the
mem load command. The output file can also be read by the Verilog $readmem system
tasks if the memory module is a Verilog module and Verilog memory format (hex or
binary) is specified. The format settings are stored at the top of this file as a pseudo
comment so that subsequent mem load commands can correctly interpret the data. Do not
edit this data when manipulating a saved file.
By default, identical data lines are printed. To replace identical lines with a single line
containing the asterisk character, you can enable compression with the -compress
argument.
Syntax
mem display
[-format [bin | hex | mti]] [-addressradix <radix>] [-dataradix <radix>]
[-wordsperline <Nwords>] [-startaddress <st>] [-endaddress <end>]
[-noaddress] [-compress] [<path>]
Arguments
-format [bin | hex | mti]
Specifies the output format of the contents. Optional. The default format is mti. For
details on mti format, see the description contained in mem load (CR-199).
-addressradix <radix>
Specifies the address radix for the default (mti) formatted files. The <radix> can be
specified as: d (decimal) or h (hex). Optional. If the output format is mti, the default is d.
-dataradix <radix>
Specifies the data radix for the default (mti) formatted files. Optional. If unspecified, the
global default radix is used. Valid entries (or any unique abbreviations) are: binary,
decimal, unsigned, octal, hex, symbolic, and default. If no radix is specified for an
enumerated type, the symbolic representation is used. You can change the default radix
for the current simulation using the radix command (CR-241). You can change the default
radix permanently by editing the DefaultRadix (UM-531) variable in the modelsim.ini file.
-wordsperline <Nwords>
Specifies how many words are to be printed on each line, with the default assuming an
80 column display width. <Nwords> is an unsigned integer. Optional.
-startaddress <st>
Specifies the start address for a range of addresses to be displayed. The <st> can be
specified as any valid address in the memory. Optional. If unspecified, the default is the
start of the memory.

mem display CR-197
-endaddress <end>
Specifies the end address for a range of addresses to be displayed. The <end> can be
specified as any valid address in the memory. Optional. If unspecified, the default is the
end of the memory.
-noaddress
Specifies that addresses not be printed. Optional.
-compress
Specifies that identical lines not be printed. Optional. Reduces the file size by replacing
exact matches with a single line containing an asterisk. These compressed files are
automatically expanded during a mem load operation.
<path>
Specifies the full path to the memory instance. Optional. The default is the current
context, as shown in the Structure tab of the Workspace. Indexes can be specified.
Examples
mem display -startaddress 5 -endaddress 10/top/c/mru_mem
This command displays the memory contents of instance /top/m/mru_mem, addresses 5
to 10 to the screen as follows:
# 5: 110 110 110 110 110 000
mem display -format hex -startaddress 5 -endaddress 10 /top/c/mru_mem

Displays the memory contents of the same instance to the screen in hex format, as
follows:
# 5: 6 6 6 6 6 0
See Also
mem load (CR-199)

CR-198 mem list
mem list
The mem list command displays a flattened list of all memory instances in the current or
specified context after a design has been elaborated. Each instance line is prefixed by
"VHDL:" or "Verilog:", depending on the type of model.
Returns the signal/variable name, address range, and depth and width of the memory.
Syntax
mem list
[-recursive] [<path>]
Arguments
-recursive
Recursively descends into sub-modules when listing memories. Optional.
<path>
The hierarchical path to the location the search should start. Optional. The default is the
current context, as shown in the Structure tab of the Workspace pane.
Examples
mem list -r /
Recursively lists all memories at the top level of the design. Returns:
# Verilog: /top/m/mem[0:255](256d x 16w)
#
mem list /top2/uut -r

Recursively lists all memories in /top2/uut. Returns:
# Verilog: /top2/uut/mem[0:255] x 16w

mem load CR-199
mem load
The mem load command updates the simulation memory contents of a specified instance.
You can upload contents either from a memory data file, a memory pattern, or both. If both
are specified, the pattern is applied only to memory locations not contained in the file.
A relocatable memory file is one that has been saved without address information. You can
load a relocatable memory file into the instance of a memory core by specifying an address
range on the mem load command line. If no address range (starting and ending address) is
specified, the memory is loaded starting at the first location.
The order in which the data is placed into the memory depends on the format specified by
the -format option. If you choose bin or hex format, the memory is filled low to high, to be
compatible with $readmem commands. This is in contrast to the default mti format, which
fills the memory according to the memory declaration, from left index to right index.
For Verilog objects and VHDL integers and std_logic types: if the word width in a file is
wider than the word width of the memory, the leftmost bits (msb’s) in the data words are
ignored. To allow wide words use the -truncate option which will ignore the msb bits that
exceed the memory word size. If the word width in the file is less than the width of the
memory, and the left-most digit of the file data is not ’X’, then the left-most bits are zero
filled. Otherwise, they are X-filled.
The type of data required for the -filldata argument is dependent on the -filltype specified:
a fixed value, or one that governs an incrementing, decrementing, or random sequence.
• For fixed pattern values, the fill pattern is repeatedly tiled to initialize the memory block
specified. The pattern can contain multiple word values for this option.
• For incrementing or decrementing patterns, each memory word is treated as an unsigned
quantity, and each successive memory location is filled in with a value one higher or
lower than the previous value. The initial value must be specified.
• For a random pattern, a random data sequence will be generated to fill in the memory
values. The data type in the sequence will match the type stored in the memory. For
std_logic and associated types, unsigned integer sequences are generated. A seed value
may be specified on the command line. For any given seed, the generated sequence is
identical.
The interpretation of the pattern data is performed according to the default system radix
setting. However, this can be overridden with a standard Verilog-style
‘<radix_char><data> specification.
Syntax
mem load
[-infile <infile> -format [bin | hex | mti]]
[-filltype <filltype>] [-filldata <patterndata>] [-fillradix <radix>]
[-skip <Nwords>] [-truncate] [-startaddress <st>] [-endaddress <end>]
[<path>]

CR-200 mem load
Arguments
-infile <infile>
Updates memory data from the specified file. Required unless the -filltype argument is
used.
-endaddress <end>
Specifies the end address for a range of addresses to be loaded. The <end> can be
specified as any valid address in the memory. Optional.
-format [bin | hex | mti]
Specifies the format of the file to be loaded. The <formtype> can be specified as: bin,
hex, or mti. bin and hex are the standard Verilog hex and binary memory pattern file
formats. These can be used with Verilog memories, and with VHDL memories composed
of std_logic types. mti is the "MTI memory data file format" (GR-178).
In the MTI memory data file format, internal file address and data radix settings are
stored within the file itself. Thus, there is no need to specify these settings on the mem
load command line. If a format specified on the command line and the format signature
stored internally within the file do not agree, the file cannot be loaded.
-filltype <filltype>
Fills in memory data patterns algorithmically. The <filltype> can be specified as: value,
inc, dec, or rand. Required unless the -infile argument is used, in which case it is optional.
Default is value.
-filldata <patterndata>
Specifies the pattern parameters, value for fixed-value fill operations, and seed or starting
point for random, increment, or decrement fill operations. Required if -filltype is used.
A fill pattern covers any of the selected address range that is not populated from file
values. If a fill pattern is used without a file option, the entire memory or specified
address range is initialized with the fill pattern.
-fillradix <radix>
Specifies radix of the data specified by "-filldata" option. Valid entries (or any unique
abbreviations) are: binary, decimal, unsigned, octal, hex, symbolic, and default.
-skip <Nwords>
Specifies the number of words to be skipped between each fill pattern value. <Nwords>
is specified as an unsigned integer. Optional. Used with -filltype and -filldata.
-truncate
Ignores any most significant bits (msb) in a memory word which exceed the memory
word size. By default, when memory word size is exceeded, an error results.
-startaddress <st>
Specifies the start address for a range of addresses to be loaded. The <st> can be specified
as any valid address in the memory. Optional.

mem load CR-201
<path>
The hierarchical path to the memory instance. If the memory instance name is unique,
shorthand instance names can be used. Optional. The default is the current context, as
shown in the Structure tab of the Workspace pane.
Memory address indexes can be specified in the instance name also. If addresses are
specified both in the instance name and the file, only the intersection of the two address
ranges is populated with memory data.
Examples
mem load -infile vals.mem -format bin -filltype value -filldata 1‘b0
/top/m/mem
Loads the memory pattern from the file vals.mem to the memory instance /top/m/mem,
filling the rest of the memory with the fixed-value 1‘b0. When you enter the mem
display command on memory addresses 0 through 12, you see the following:
mem display -startaddress 0 -endaddress 12 /top/m/mem
# 0: 0000000000000000 0000000000000001 0000000000000010 0000000000000011
# 4: 0000000000000100 0000000000000101 0000000000000110 0000000000000111
# 8: 0000000000001000 0000000000001001 0000000000000000 0000000000000000
# 12: 0000000000000000
mem load -infile vals.mem -format hex -st 0 -end 12 -filltype value -filldata
16’Hbeef /top/m/mru_mem
Loads the memory pattern from the file vals.mem to the memory instance
/top/m/mru_mem, filling the rest of the memory with the fixed-value 16’Hbeef.
mem load -filltype value -filldata "16’hab 16’hcd" /top/mem2 -skip 3
Loads memory instance /top/mem2 with two words of memory data using the Verilog
Hex format, skipping 3 words after each fill pattern sequence.
mem load -format h -truncate -infile data_files/data.out /top/m_reg_inc/mem
Truncates the msb bits that exceed the maximum word size (specified in HDL code).
See also
mem save (CR-202)

CR-202 mem save
mem save
The mem save command saves the contents of a memory instance to a file in any of the
supported formats: Verilog binary, Verilog hex, and MTI memory pattern data.
This command works identically to the mem display command, except that its output is
written to a file rather than a display.
The order in which the data is placed into the saved file depends on the format specified by
the -format argument. If you choose bin or hex format, the file is populated from low to
high, to be compatible with $readmem commands. This is in contrast to the default mti
format, which populates the file according to the memory declaration, from left index to
right index.
You can use the mem save command to generate relocatable memory data files. The
-noaddress option omits the address information from the memory data file. You can later
load the generated memory data file using the memory load command.
Syntax
mem save
[-format bin | hex | mti] [-addressradix <radix>] [-dataradix <radix>]
[-wordsperline <Nwords>] [-startaddress <st> -endaddress <end>]
[-noaddress] [-compress] [<path>] -outfile <filename>
Arguments
-format bin | hex | mti
Specifies the output format. The <format_spec> can be specified as bin, hex, or mti.
Optional. The default format is mti. The MTI memory pattern data format is described in
mem load (CR-199).
Specifies the address radix for the default mti formatted files. Optional. The <radix> can
be specified as: dec or hex. The default is the decimal representation.
-dataradix <radix>
Specifies the data radix for the default mti formatted files. Optional. The <radix> can be
specified as symbolic, binary, octal, decimal, unsigned, or hex. You can change the
default radix for the current simulation using the radix command (CR-241). You can
change the default radix permanently by editing the DefaultRadix (UM-531) variable in
the modelsim.ini file.
-wordsperline <Nwords>
Specifies how many memory values are to be printed on each line. Optional. The default
assumes an 80 character display width. The <Nwords> is specified as an unsigned
integer.
-startaddress <st>
Specifies the start address for a range of addresses to be saved. The <st> can be specified
-endaddress <end>
Specifies the end address for a range of addresses to be saved. The <end> can be specified

mem save CR-203
-noaddress
Prevents addresses from being printed. Optional. Mutually exclusive with the
-compress option.
-compress
Specifies that only unique lines are printed, identical lines are not printed. Optional.
Mutually exclusive with the -noaddress option.
-outfile <filename>
Specifies that the memory contents be stored in <filename>. Required.
<path>
The hierarchical path to the location of the memory instance. Optional. The default is the
current context, as shown in the Structure tab of the Workspace pane.
Examples
mem save -format mti -outfile memfile -start 0 -end 10 /top/m/mem
Saves the memory contents of the instance /top/m/mem(0:10) to memfile, written in the
mti radix. The contents of memfile are as follows:
// memory data file (do not edit the following line - required for mem load
use)
// format=mti addressradix=d dataradix=s version = 1.0
0: 0000000000000000 0000000000000001 0000000000000010 0000000000000011
4: 0000000000000100 0000000000000101 0000000000000110 0000000000000111
8: 0000000000001000 0000000000001001 xxxxxxxxxxxxxxxx
See also
mem display (CR-196), mem load (CR-199)

CR-204 mem search
mem search
The mem search command finds and prints to the screen the first occurring match of a
specified memory pattern in the specified memory instance. Shorthand instance names are
accepted. Optionally, you can instruct the command to print all occurrences. The search
pattern can be one word or a sequence of words.
Syntax
mem search
[-addressradix <radix>] [-dataradix <radix>] [-all]
[-replace <word>[ <word>...]] [-startaddress <address>]
[-endaddress <address>] [<path>] -pattern <word>[ <word>...]
Arguments
Specifies the radix for the address being displayed. The <radix> can be specified as
decimal or hexadecimal. Default is decimal. Optional.
-dataradix <radix>
Specifies the radix for the memory data being displayed. The <radix> can be specified as
symbolic, binary, octal, decimal, unsigned, or hex. Optional. By default the radix
displayed is the system default.
-all
Searches the specified memory range and prints out all matching occurrences to the
screen. Optional. By default only the first matching occurrence is printed.
-replace <word>[ <word>...]
Replaces the found patterns with a designated pattern. Optional. If this option is used,
each pattern specified by the -pattern argument must have a corresponding pattern
specified by the -replace argument. Multiple word patterns are accepted, separated by a
single white space. No wildcards are allowed in the replaced pattern.
-startaddress <address>
Specifies the start address for a range of addresses to search. The <address> can be
-endaddress <address>
Specifies the end address for a range of addresses to search. The <address> can be
<path>
Specifies the hierarchical path to the location of the memory instance. Optional. The
default is the current context value, as shown in the Structure tab of the Workspace pane.
-pattern <word>[ <word>...]
Specifies the value of the pattern for the search. Required. Multiple word patterns are
accepted, separated by a single white space. Wildcards are accepted in the pattern.

mem search CR-205
Examples
mem search -pattern 16‘Hbeef -dataradix hex /uut/u0/mem3
Searches for and prints to the screen all occurrences of the pattern 16‘Hbeef in /uut/u0/
mem3. Returns:
#7845: beef
#7846: beef
#100223: beef
mem search -p 16‘Hbeef -d hex -replace 16‘Hcafe -st 7846 -end 150000 /uut/
u1/mem3
Searches for and prints only the first occurrence of 16‘Hbeef in the address range
7845:150000, replacing it with 16‘Hcafe in /uut/u1/mem3. Returns:
#7846: cafe
mem search -p 16‘Hbeef -r 16‘Habe -addressadix hex -all /uut/u1/mem3

Replaces all occurrences of 16‘Hbeef with 16‘Habe in /uut/u1/mem3. Returns:
#1ea5: 2750
#1ea6: 2750
#1877f: 2750
mem search -p "*f"

Searches for and prints the first occurrence any pattern ending in f.
mem search -p "abe cafe" /uut/u1/mem3
Searches for and prints the first occurrence of this multiple word pattern.

CR-206 modelsim
modelsim
The modelsim command starts the ModelSim GUI without prompting you to load a design.
This command is valid only for Windows platforms, and may be invoked in one of three
ways:
from the DOS prompt
from a ModelSim shortcut
from the Windows Start > Run menu
To use modelsim arguments with a shortcut, add them to the target line of the shortcut’s
properties. (Arguments work on the DOS command line too, of course.)
The simulator may be invoked from either the MODELSIM prompt after the GUI starts or
from a DO file called by modelsim.
Syntax
modelsim
[-do <macrofile>] [-project <project file>]
Arguments
-do <macrofile>
Specifies the DO file to execute when modelsim is invoked. Optional.
Note: In addition to the macro called by this argument, if a DO file is specified by the
STARTUP variable in modelsim.ini, it will be called when the vsim command (CR-373)
is invoked.
-project <project file>

Specifies the .mpf file to load for this session. Optional.
See also
vsim (CR-373), do (CR-151), and "Using a startup file" (UM-538)

next CR-207
next
The next command continues a search after you have invoked the search command. See
the search command (CR-260) for more information.
Syntax
next
<window_name> [-window <wname>]
Arguments
<window_name>
Specifies the window in which to continue searching. Can be one of Signals, Objects,
Variables, Locals, Source, List, Wave, Process, Structure, or a unique abbreviation
thereof. Required.
-window <wname>
Specifies an instance of the window that is not the default. Optional. Otherwise, the
default window is used. Use the view command (CR-332) to change the default window.

CR-208 noforce
noforce
The noforce command removes the effect of any active force (CR-180) commands on the
selected HDL objects. The noforce command also causes the object’s value to be re-
evaluated.
Syntax
noforce
<object_name> ...
Arguments
<object_name>
Specifies the name of an object. Required. Must match an object name used in a previous
force command (CR-180). Multiple object names may be specified. Wildcard characters
are allowed.
See also
force (CR-180) and "Wildcard characters" (CR-17)

nolog CR-209
nolog
The nolog command suspends writing of data to the wave log format (WLF) file for the
specified signals. A flag is written into the WLF file for each signal turned off, and the GUI
displays "-No Data-" for the signal(s) until logging (for the signal(s)) is turned back on.
Logging can be turned back on by issuing another log command (CR-191) or by doing a
nolog -reset.
Because use of the nolog command adds new information to the WLF file, WLF files
created when using the nolog command cannot be read by older versions of the simulator.
If you are using dumplog64.c, you will need to get an updated version.
Syntax
nolog
[-all] [-depth <level>] [-howmany] [-in] [-inout] [-internal] [-out]
[-ports] [-recursive] [-reset] [<object_name>...]
Arguments
-all
Turns off logging for all signals currently logged. Optional.
-depth <level>
-howmany
Returns an integer indicating the number of signals found. Optional.
-in
Turns off logging only for ports of mode IN whose names match the specification.
Optional.
-inout
Turns off logging only for ports of mode INOUT whose names match the specification.
Optional.
-internal
Turns off logging only for internal (non-port) objects whose names match the
specification. Optional.
-out
Turns off logging only for ports of mode OUT whose names match the specification.
Optional.
-ports
Specifies that the scope of the search is to include all ports. Optional.
-recursive
If omitted, the search is limited to the selected region. You can use the -depth argument
to specify how far down the hierarchy to descend.

CR-210 nolog
-reset
Turns logging back on for all unlogged signals. Optional.
<object_name>...
Specifies the object name which you want to unlog. Optional. Multiple object names may
be specified. Wildcard characters are allowed.
Examples
nolog -r /*
Unlogs all objects in the design.
nolog -reset
Turns logging back on for all unlogged signals.
See also
add list (CR-48), add wave (CR-52), log (CR-191)

notepad CR-211
notepad
The notepad command opens a simple text editor. It may be used to view and edit ASCII
files or create new files. This mode can be changed from the Notepad Edit menu.
Returns nothing.
Syntax
notepad
[<filename>] [-r | -edit]
Arguments
<filename>
Name of the file to be displayed. Optional.
-r | -edit
Selects the notepad editing mode: -r for read-only, and -edit for edit mode. Optional. Edit
mode is the default.

CR-212 noview
noview
The noview command closes a window/pane in the ModelSim GUI. To open a window/
pane, use the view command.
Syntax
noview
<window_name>...
Arguments
<window_name>...
Specifies the window/pane to close. Wildcards and multiple window/pane types may be
used. At least one type (or wildcard) is required. Available window types are:
assertions, dataflow, fcovers, list, locals, memory, objects, process, profile,
profile_details, signals, structure, variables, wave, watch, and workspace
Examples
noview wave1
Closes the Wave window named "wave1".
noview l*
Closes all List windows.
See also
view (CR-332)

nowhen CR-213
nowhen
The nowhen command deactivates selected when (CR-407) commands.
Syntax
nowhen
[<label>]
Arguments
<label>
Specifies an individual when command. Optional. Wildcards may be used to select more
than one when command.
Examples
when -label 99 b {echo “b changed”}
…
nowhen 99
This nowhen command deactivates the when (CR-407) command labeled 99.
nowhen *
This nowhen command deactivates all when (CR-407) commands.

CR-214 onbreak
onbreak
The onbreak command is used within a macro, placed before a run command. It specifies
one or more commands to be executed when running a macro that encounters a breakpoint
in the source code. Using the onbreak command without arguments will return the current
onbreak command string. Use an empty string to change the onbreak command back to
its default behavior (i.e., onbreak ""). In that case, the macro will be interrupted after a
breakpoint occurs (after any associated bp command (CR-75) string is executed).
onbreak commands can contain macro calls.
Syntax
onbreak
{[<command> [; <command>] ...]}
Arguments
<command>
Any command can be used as an argument to onbreak. If you want to use more than one
command, use a semicolon to separate the commands, or place them on multiple lines.
The entire command string must be placed in curly braces. You must use the onbreak
command before a run (CR-252), run -continue, or step (CR-272) command. It is an error
to execute any commands within an onbreak command string following any of the run
commands. This restriction applies to any macros or Tcl procedures used in the onbreak
command string. Optional.
Examples
onbreak {exa data ; cont}
Examine the value of the HDL object data when a breakpoint is encountered. Then
continue the run command (CR-252).
onbreak {resume}
Resume execution of the macro file on encountering a breakpoint.
set broken 0
onbreak {
set broken 1
resume
}
run -all
if { $broken } {
puts "failure"
} else {
puts "success"
}
This set of commands test for assertions. Assertions are treated as breakpoints if the
severity level is greater than or equal to the current BreakOnAssertion variable setting
(see "[vsim] simulator control variables" (UM-529)). By default a severity level of failure
or above causes a breakpoint; a severity level of error or below does not.
See also
abort (CR-44), bd (CR-70), bp (CR-75), do (CR-151), onerror (CR-216), resume (CR-249),
status (CR-271)

onElabError CR-215
onElabError
The onElabError command specifies one or more commands to be executed when an error
is encountered during elaboration. The command is used by placing it within the
modelsim.tcl file or a macro. During initial design load onElabError may be invoked from
within the modelsim.tcl file; during a simulation restart onElabError may be invoked from
a macro.
Use the onElabError command without arguments to return to a prompt.
Syntax
onElabError
Arguments
<command>
Any command can be used as an argument to onElabError. If you want to use more than
one command, use a semicolon to separate the commands, or place them on multiple
lines. The entire command string must be placed in curly braces. Optional.
See also
do (CR-151)

CR-216 onerror
onerror
The onerror command is used within a macro, placed before a run command; it specifies
one or more commands to be executed when a running macro encounters an error. Using
the onerror command without arguments will return the current onerror command string.
Use an empty string to change the onerror command back to its default behavior (i.e.,
onerror ""). Use onerror with a resume command (CR-249) to allow an error message to be
printed without halting the execution of the macro file.
Syntax
onerror
Arguments
<command>
Any command can be used as an argument to onerror. If you want to use more than one
command, use a semicolon to separate the commands, or place them on multiple lines.
The entire command string must be placed in curly braces. Optional.
Example
onerror {quit -f}
Forces the simulator to quit if an error is encountered while the macro is running.
See also
abort (CR-44), do (CR-151), onbreak (CR-214), resume (CR-249), status (CR-271)
Note: You can also set the global OnErrorDefaultAction Tcl variable in the pref.tcl file
to dictate what action ModelSim takes when an error occurs. The onerror command is
invoked only when an error occurs in the macro file that contains the onerror command.
Conversely, OnErrorDefaultAction will run even if the macro does not contain a local
onerror command. This can be useful when you run a series of macros from one script,
and you want the same behavior across all macros.

pause CR-217
pause
The pause command placed within a macro interrupts the execution of that macro.
Syntax
pause
Arguments
None.
Description
When you execute a macro and that macro gets interrupted, the prompt will change to:
VSIM(paused)>
This “pause” prompt reminds you that a macro has been interrupted.
When a macro is paused, you may invoke another macro, and if that one gets interrupted,
you may even invoke another — up to a nesting level of 50 macros.
If the status of nested macros gets confusing, use the status command (CR-271). It will show
you which macros are interrupted, at what line number, and show you the interrupted
command.
To resume the execution of the macro, use the resume command (CR-249). To abort the
execution of a macro use the abort command (CR-44).
See also
abort (CR-44), do (CR-151), resume (CR-249), run (CR-252)

CR-218 play
play
The play command replays a sequence of keyboard and mouse actions that were previously
saved to a file with the record command (CR-243). Returns nothing.
Play returns immediately; the playback proceeds in the background. Caution must be used
when putting play commands in do (macro) files.
Syntax
play
<filename>
Arguments
<filename>
Specifies the recorded file to replay. Required.
Playback controls
The following Tcl set commands control the playback type and speed by setting the
play_macro() global variables. The commands are invoked from the ModelSim command
line.
set play_macro(speed)
Specify the playback speed: either demo (with the delay specified below), or fast (no
delays).
set play_macro(delay)
Specifies the delay time in milliseconds. Controls the speed of playback in demo mode.
See also
macro_option (CR-195), record (CR-243)

pop CR-219
pop
This command is used with C Debug. See Chapter 16 - C Debug (UM-399) for more
information.
The pop command moves the specified number of call frames up the C callstack.
Syntax
pop
<#_of_levels>
Arguments
<#_of_levels>
Specifies the number of call frames to move up the C callstack. Optional. If unspecified,
1 level is assumed.
Examples
pop
Moves up 1 call frame.
pop 4
Moves up 4 call frames.
See also
push (CR-237), Chapter 16 - C Debug (UM-399)

CR-220
power add
The power add command specifies the signals or nets to track for power information. Data
produced by these commands can be translated (by a Synopsys utility) to drive the
Synopsys power analysis tools.
The power add command is intended to be used as follows:
1 Add the objects of interest with the power add command.
2 Run the simulation with the run command (CR-252).
3 Produce a report with the power report command (CR-221).
Syntax
power add
[-in] [-inout] [-internal] [-out] [-ports] [-r] <signalsOrNets> ...
Arguments
-in
Specifies only inputs. Optional.
-inout
Specifies only inouts. Optional.
-internal
Specifies only design internal signals or nets. Optional.
-out
Specifies only outputs. Optional.
-ports
Specifies only design ports. Optional.
-r
Searches recursively on a wildcard specified for the signal or net. Optional.
<signalsOrNets> ...
Specifies the signal or net to track. Required. Multiple names or wildcards may be used.
Must refer to VHDL signals of type bit, std_logic, or std_logic_vector, or to Verilog nets.
When using wildcards, the -in, -inout, -internal, -out, and -ports arguments filter the
qualifying signals. If you specify more than one of these arguments, the logical OR of the
arguments is performed.
See also
power report (CR-221), power reset (CR-222)
See the Synopsys Power documentation for more information.

power report CR-221
power report
The power report command reports power information for the specified signals or nets.
The report can be written to a file or to the Transcript pane. Data produced by these
commands can be translated (by a Synopsys utility) to drive the Synopsys power analysis
tools.
The power report command is intended to be used as follows:
1 Add the objects of interest with the power add command (CR-220).
3 Produce the report with the power report command.
Syntax
power report
[-all] [-noheader] [-file <filename>]
Arguments
-all
Writes information on all objects logged. Optional.
-noheader
Suppresses the header to aid in post processing. Optional.
-file <filename>
Specifies a filename for the power report. Optional. Default is to write the report to the
Transcript pane.
Description
The report format for each line is:
signal path, toggle count, hazard count, time at a 1, time at a 0, time at an X
• toggle count is the number of 0->1 and 1->0 transitions

• hazard count is the number of 0/1->X, and X->0/1 transitions
Note that if a signal is initialized at X, and later transitions to 0 or 1, it is not counted as
a hazard.
• times are the times spent at each of the three respective states
You will also need to know the total simulation time.
See also
power add (CR-220), power reset (CR-222)

CR-222 power reset
power reset
The power reset command selectively resets power information to zero for the signals or
nets specified with the power add command (CR-220). Returns nothing.
Syntax
power reset
[-all] [-in] [-inout] [-out] [-internal] [-ports] [-r]
<signalsOrNets> ...
Arguments
-all
Resets all signals/nets. Optional.
-in
Resets only inputs. Optional.
-inout
Resets only inouts. Optional.
-out
Resets only outputs. Optional.
-internal
Resets only design internal signals or nets. Optional.
-ports
Resets only design ports. Optional.
-r
Searches recursively on a wildcard specified for the signal or net. Optional.
<signalsOrNets> ...
Specifies the signal or net to reset. Required. Multiple names or wildcards may be used.
See also
power add (CR-220), power report (CR-221)

precision CR-223
precision
The precision command determines how real numbers display in the graphic interface
(e.g., Objects, Wave, Locals, and List windows). It does not affect the internal
representation of a real number and therefore precision values over 17 are not allowed.
Using the precision command without any arguments displays the current precision
setting.
Syntax
precision
[<digits>[#]]
Arguments
<digits>[#]
Specifies the number of digits to display. Optional. Default is 6. Trailing zeros are not
displayed unless you append the ’#’ sign. See examples for more details.
Examples
precision 4
Results in 4 digits of precision. For example:
1.234 or 6543
precision 8#
Results in 8 digits of precision including trailing zeros. For example:
1.2345600 or 6543.2100
precision 8
Results in 8 digits of precision but doesn’t print trailing zeros. For example:
1.23456 or 6543.21

CR-224 printenv
printenv
The printenv command prints to the Transcript pane the current names and values of all
environment variables. If variable names are given as arguments, prints only the names and
values of the specified variables.
Syntax
printenv
[<var>...]
Arguments
<var>...
Specifies the name(s) of the environment variable(s) to print. Optional.
Examples
printenv
Prints all environment variable names and their current values. For example,
# CC = gcc
# DISPLAY = srl:0.0
...
printenv USER HOME

Prints the specified environment variables:
# USER = vince
# HOME = /scratch/srl/vince

profile clear CR-225
profile clear
The profile clear command clears any performance data that has been gathered during
previous run commands. After this command is executed, all profiling data will be reset.
This command has no effect on the current profiling session. The last profile on or profile
off command will still be in effect.
Syntax
profile clear
Arguments
None
See also
Chapter 12 - Profiling performance and memory use (UM-317), profile interval (CR-226),
profile off (CR-227), profile on (CR-228), profile option (CR-229), profile reload (CR-230),
profile report (CR-231)
Note: Profiling must be active when this command is invoked. Use the profile on
command (CR-228) to begin profiling.

CR-226 profile interval
profile interval
The profile interval command selects the frequency with which the profiler collects
samples during a run command. To use this command, first enable profiling with the
profile on command.
Syntax
profile interval
[<sample_frequency>]
Arguments
<sample_frequency>
An integer value from 1 to 999 that represents how many milliseconds to wait between
each sample collected during a profiled simulation run. Default is 10 ms.
If the sample-frequency is not supplied, the profile interval command returns the current
sample frequency.
See also
Chapter 12 - Profiling performance and memory use (UM-317), profile clear (CR-225),
profile off (CR-227), profile on (CR-228), profile option (CR-229), profile reload (CR-230),

profile off CR-227
profile off
The profile off command disables runtime memory allocation and statistical performance
profiling.
Syntax
profile off
[-m] [-p]
Arguments
-m
Disables memory allocation profiling only. Optional.
-p
Disables statistical performance profiling only. Optional.
See also
profile interval (CR-226), profile on (CR-228), profile option (CR-229), profile reload (CR-
230), profile report (CR-231)

CR-228 profile on
profile on
The profile on command enables runtime memory allocation and statistical performance
profiling. After this command is executed, every subsequent run command will be
profiled.
Syntax
profile on
[-m] [-p] [-file <filename> | -fileonly <filename>]]
Arguments
-m
Enables memory allocation profiling only. Optional.
-p
Enables statistical performance profiling only. Optional.
-file <filename>
Allows creation of a raw profile data file that can be post-processed later. Saves memory
profile data into both an external file and internal data structures. Optional
-fileonly <filename>
Allows creation of a raw profile data file that can be post-processed later. Saves memory
profile data into an external file only, not to internal data structures. Optional
See also
profile interval (CR-226), profile off (CR-227), profile option (CR-229), profile reload (CR-
230), profile report (CR-231)
Example
profile on
run 1000 ns
profile report -hier -file perf.rpt
This set of commands enables the profiler, runs the simulation for 1000 nanoseconds, and
outputs the profiling data to perf.rpt.

profile option CR-229
profile option
The profile option command changes how profiling data are reported. The command acts
like a toggle: invoking it once turns on the option; invoking it a second time turns the option
back off. To use this command, first enable profiling with the profile on command (CR-
228).
Syntax
profile option
collapse_sections [on | off | status]
Arguments
collapse_sections
Groups profiling data by section. A section consists of regions of code such as VHDL
processes, functions, or Verilog always blocks. By default all profiling data are reported
on a per line basis.
on | off | status
Specifies whether to enable, disable, or report the status of the profile options. Optional.
If omitted, the profile option command acts as a toggle.
See also
profile interval (CR-226), profile off (CR-227), profile on (CR-228), profile reload (CR-230),

CR-230 profile reload
profile reload
The profile reload command reads in raw profile data from an external file created during
memory allocation profiling. The profile report command (CR-231) and the Profile and
Profile Details panes of the user interface can be used to view the data. The intent of the
raw profile files is to allow analysis of memory profile data in cases where the memory
required for the design plus the memory required for internal profiling data exceeds the
memory capacity of the machine. To use this command, you must first use the -m -file
<filename> or the -m -fileonly <filename> arguments with the profile on command (CR-
228).
The profile reload command will clear all performance and memory profiling data
collected to that point (implicit profile clear). Any currently loaded design will be
unloaded (implicit quit -sim), and run-time profiling will be turned off (implicit profile off
-m -p). If a new design is loaded after you have read the raw profile data, then all internal
profile data is cleared (implicit profile clear), but run-time profiling is not turned back on.
Syntax
profile reload
<filename>
Arguments
<filename>
Designates the name of the external file where raw profile data will be saved. Required.
See also
profile interval (CR-226), profile off (CR-227), profile on (CR-228), profile option (CR-229),

profile report CR-231
profile report
The profile report command outputs profiling data that have been gathered up to the point
that you execute the command. To use this command, first enable profiling using the
profile on command (CR-228).
Syntax
profile report
[-cutoff <percentage>] [-file <filename>] [-m] [-p]
[-ranked | -calltree | -structural [-level <positive_integer>]
[<rootname>] [-showcalls] | -functoinst <func>]
Arguments
-calltree
Reports a hierarchical callstack list of statistical performance and memory allocation
data. Optional. Default.
-cutoff <percentage>
Filters out entries in the report that had less than <percentage> of time spent in them.
Optional. Default is to report all entries (i.e., 0%).
-file <filename>
Specifies a file name for the report. Optional. Default is to write the report to the
Transcript pane.
-functoinst <func>
Creates a ranked profile report of all uses of the specified function, where <func>
indicates a function name (for PLI, FLI, or SystemC) or a <.v/.vhd-filename>:<line#>.
Optional.
-instofdef <inst>
Creates a ranked report of all instances with the same definition as the specified instance,
showing profile results for each. <inst> is the hierarchical pathname of the desired
instance. Optional.
-level <positive_integer>
Determines how far to expand instance hierarchy in a structural report. If omitted, the
report includes all levels. Optional.
-m
Displays memory allocation data in the report. Optional. If -m is not specified, the profile
report will include memory allocation data if the memory profiler was previously
enabled.
-p
Displays statistical performance samples in the report. Optional. If -p is not specified, the
profile report will include performance statistics if the performance profiler was
previously enabled.
-ranked
Reports a ranked list of statistical performance and memory allocation data. Optional.

CR-232 profile report
<rootname>
Causes a structural report to be rooted at the specified instance. If not specified, the report
contains all roots and any orphan samples. Optional.
-showcalls
Shows function callstacks beneath instances in a structural report. If omitted, functional
callstacks are not shown in the report. Optional.
-structural
Reports a structural list of statistical performance and memory allocation data. Optional.
See also
profile interval (CR-226), profile off (CR-227), profile on (CR-228), profile option (CR-229),
profile reload (CR-230)
Example
profile on
run 1000 ns
profile report -c -file perf.rpt
This set of commands enables the statistical sampling profiler, runs the simulation for
1000 nanoseconds, and outputs the call-tree profiling data to a file named perf.rpt.

project CR-233
project
The project commands are used to perform common operations on projects. Some of the
project commands must be used outside of a simulation session.
Syntax
project
[addfile <filename>] | [close] | [compileall] | [delete <project>] | [env]
| [history] | [new <home_dir> <proj_name> [<defaultlibrary>]
[<use_current>]] | [open <project>] | [removefile <filename>]
Arguments
addfile <filename>
Adds the specified file to the current open project. Optional.
close
Closes the current project. Optional. Must be used outside of a simulation session.
compileall
Compiles all files in the current project. Optional.
delete <project>
Deletes a specified project file. Optional.
env
Returns the current project file. Optional.
history
Lists a history of manipulated projects. Optional. Must be used outside of a simulation
session.
new <home_dir> <proj_name> [<defaultlibrary>] [<use_current>]
Creates a new project under a specified home directory with a specified name and
optionally a default library. Optional. If use_current is set to 1, then ModelSim uses the
current modelsim.ini file when creating the project rather than the default. You must
specify a default library if you want to specify use_current. A new project cannot be
created while a project is currently open or a simulation is in progress.
open <project>
Opens a specified project file, making it the current project. Changes the current working
directory to the project's directory. Optional. Must be used outside of a simulation
session.
removefile <filename>
Removes the specified file from the current project. Optional.
Examples
project open /user/george/design/test3/test3.mpf
Makes /user/george/design/test3/test3.mpf the current project and changes the current
working directory to /user/george/design/test3.
project compileall
Executes current project library build scripts.

CR-234 property list
property list
The property list command changes one or more properties of the specified signal, net, or
register in the List window. The properties correspond to those you can set by selecting
View > Signal Properties (List window). At least one argument must be used.
Syntax
property list
[-window <wname>] [-label <label>] [-radix <radix>]
[-trigger <setting>] [-width <number>] <pattern>
Arguments
-window <wname>
Specifies a particular List window when multiple instances of the window exist (e.g.,
list2). Optional. If no window is specified the default window is used; the default window
is determined by the most recent invocation of the view command (CR-332).
-label <label>
Specifies the label to appear at the top of the List window column. Optional.
-radix <radix>
Specifies the radix for List window objects. Optional.
Valid entries (or any unique abbreviations) are: binary, ascii, unsigned, decimal, octal,
hex, symbolic, and default. If no radix is specified for an enumerated type, the default
representation is used. You can change the default radix for the current simulation using
the radix command (CR-241). You can change the default radix permanently by editing
the DefaultRadix (UM-531) variable in the modelsim.ini file.
-trigger <setting>
Valid settings are 0 or 1. Setting trigger to 1 will enable the List window to be triggered
by changes in the objects matching the specified pattern. Optional.
-width <number>
Valid numbers are 1 through 256. Specifies the desired column width for the objects
matching the specified pattern. Optional.
<pattern>
Specifies a name or wildcard pattern to match the full pathnames of the signals, nets, or
registers for which you are defining the property change. Required.

property wave CR-235
property wave
The property wave command changes one or more properties of the specified signal, net,
or register in the Wave window. The properties correspond to those you can set by selecting
View > Signal Properties (Wave window). At least one argument must be used.
Syntax
property wave
[-window <wname>] [-color <color>] [-format <format>] [-height <number>]
[-offset <number>] [-radix <radix>] [-scale <float>] <pattern>
Arguments
-window <wname>
Specifies a particular Wave window when multiple instances of the window exist (e.g.,
wave2). Optional. If no window is specified the default window is used; the default
window is determined by the most recent invocation of the view command (CR-332).
-color <color>
Specifies the color to be used for the waveform. Optional.
-format <format>
The waveform <format> can be expressed as:
analog
Displays a waveform whose height and position is determined by the -scale and -offset
values (shown below). Optional.
literal
Displays the waveform as a box containing the object value (if the value fits the space
available). Optional.
logic
Displays values as 0, 1, X, or Z. Optional.
-height <number>
Specifies the height (in pixels) of the waveform. Optional.
-offset <number>
Specifies the waveform position offset in pixels. Valid only when -format is specified as
analog. Optional.
-radix <radix>
Specifies the radix for Wave window objects. Optional.
Valid entries (or any unique abbreviations) are: binary, ascii, unsigned, decimal, octal,
hex, symbolic, and default. If no radix is specified for an enumerated type, the default
representation is used. You can change the default radix for the current simulation using
the radix command (CR-241). You can change the default radix permanently by editing
the DefaultRadix (UM-531) variable in the modelsim.ini file.

CR-236 property wave
-scale <float>
Specifies the waveform scale relative to the unscaled size value of 1. Valid only when
-format is specified as analog. Optional.
<pattern>
Specifies a name or wildcard pattern to match the full path names of the signals, nets, or
registers for which you are defining the property change. Required.

push CR-237
push
This command is used with C Debug. See Chapter 16 - C Debug (UM-399) for more
information.
The push command moves the specified number of call frames down the C callstack.
Syntax
push
<#_of_levels>
Arguments
<#_of_levels>
Specifies the number of call frames to move down the C callstack. Optional. If
unspecified, 1 level is assumed.
Examples
push
Moves down 1 call frame.
push 4
Moves down 4 call frames.
See also
pop (CR-219), Chapter 16 - C Debug (UM-399)

CR-238 pwd
pwd
The Tcl pwd command displays the current directory path in the Transcript pane.
Syntax
pwd
Arguments
None.

quietly CR-239
quietly
The quietly command turns off transcript echoing for the specified command.
Syntax
quietly
<command>
Arguments
<command>
Specifies the command for which to disable transcript echoing. Required. Any results
normally echoed by the specified command will not be written to the Transcript pane. To
disable echoing for all commands use the transcript command (CR-286) with the -quietly
option.
See also
transcript (CR-286)

CR-240 quit
quit
The quit command exits the simulator. If you want to stop the simulation using a when
command (CR-407), you must use a stop command (CR-273) within your when statement.
DO NOT use an exit command (CR-166) or a quit command. The stop command acts like
a breakpoint at the time it is evaluated.
Syntax
quit
[-f | -force] [-sim]
Arguments
-f | -force
Quits without asking for confirmation. Optional. If omitted, ModelSim asks you for
confirmation before exiting. (The -f and -force arguments are equivalent.)
-sim
Unloads the current design in the simulator without exiting ModelSim. All files opened
by the simulation will be closed including the WLF file (vsim.wlf).

radix CR-241
radix
The radix command specifies the default radix to be used for the current simulation. The
command can be used at any time. The specified radix is used for all commands (force (CR-
180), examine (CR-162), change (CR-81), etc.) as well as for displayed values in the Objects,
Locals, Dataflow, List, and Wave windows. You can change the default radix permanently
by editing the DefaultRadix (UM-531) variable in the modelsim.ini file.
Syntax
radix
[-symbolic | -binary | -octal | -decimal | -hexadecimal |
-unsigned | -ascii]
Arguments
Entries may be truncated to any length. For example, -symbolic could be expressed as
-s or -sy, etc. Optional.
Also, -signed may be used as an alias for -decimal. The -unsigned radix will display as
unsigned decimal. The -ascii radix will display a Verilog object as a string equivalent
using 8 bit character encoding.
If no arguments are used, the command returns the current default radix.

CR-242 readers
readers
The readers command displays the names of all readers of the specified object. The reader
list is expressed relative to the top-most design signal/net connected to the specified object.
Syntax
readers
<object_name>
Arguments
<object_name>
Specifies the name of the signal or net whose readers are to be shown. Required. All
signal or net types are valid. Multiple names and wildcards are accepted.
See also
drivers (CR-154) command

record CR-243
record
The record command starts recording a replayable trace of all keyboard and mouse actions.
Record and play operations may also be run from the macro-helper menu object of the
macro menu. Returns nothing.
Syntax
record
[<filename>]
Arguments
<filename>
Specifies the file for the saved recording. If <filename> is not specified, the recording
terminates.
See also
macro_option (CR-195), play (CR-218)

CR-244 report
report
The report command displays the value of all simulator control variables, or the value of
any simulator state variables relevant to the current simulation.
Syntax
report
simulator control | simulator state
Arguments
simulator control
Displays the current values for all simulator control variables.
simulator state
Displays the simulator state variables relevant to the current simulation.
Examples
report simulator control
Displays all simulator control variables.
# UserTimeUnit = ns
# RunLength = 100
# IterationLimit = 5000
# BreakOnAssertion = 3
# DefaultForceKind = default
# IgnoreNote = 0
# IgnoreWarning = 0
# IgnoreError = 0
# IgnoreFailure = 0
# CheckpointCompressMode = 1
# NumericStdNoWarnings = 0
# StdArithNoWarnings = 0
# PathSeparator = /
# DefaultRadix = symbolic
# DelayFileOpen = 0
# WLFFilename = vsim.wlf
report simulator state

Displays all simulator state variables. Only the variables that relate to the design being
simulated are displayed:
# now = 0.0
# delta = 0
# library = work
# entity = type_clocks
# architecture = full
# resolution = 1ns

report CR-245
Viewing preference variables

Preference variables have more to do with the way things look (but not entirely) rather than
controlling the simulator. You can view preference variables from the Preferences dialog
box. Select Tools > Edit Preferences (Main window).
See also
"Preference variables located in INI files" (UM-524), and "Preference variables located in
Tcl files" (UM-540)

CR-246 restart
restart
The restart command reloads the design elements and resets the simulation time to zero.
Only design elements that have changed are reloaded. (Note that SDF files are always
reread during a restart.) Shared libraries are handled as follows during a restart:
• Shared libraries that implement VHDL foreign architectures only are reloaded at each
restart when the architecture is elaborated (unless the -keeploaded option to the vsim
command (CR-373) is used).
• Shared libraries loaded from the command line (-foreign and -pli options) and from the
Veriuser entry in the modelsim.ini file are reloaded (unless you specify the -keeploaded
argument to vsim).
• Shared libraries that implement VHDL foreign subprograms remain loaded (they are not
reloaded) even if they also contain code for a foreign architecture.
You can configure defaults for the restart command by setting the DefaultRestartOptions
variable in the modelsim.ini file. See "Restart command defaults" (UM-539).
To handle restarts with Verilog PLI applications, you need to define a Verilog user-defined
task or function, and register a misctf class of callback. To handle restarts with Verilog VPI
applications, you need to register reset callbacks. To handle restarts with VHDL FLI
applications, you need to register restart callbacks. See Appendix D - Verilog PLI / VPI /
DPI for more information on the Verilog PLI/VPI/DPI and the ModelSim FLI Reference
for more information on the FLI.
Syntax
restart
[-force] [-noassertions] [-nobreakpoint] [-nolist] [-nolog] [-nowave]
Arguments
-force
Specifies that the simulation will be restarted without requiring confirmation in a popup
window. Optional.
-noassertions
Specifies that current assertion and functional coverage configurations will not be
maintained after the simulation is restarted. Optional. The default is for assertion and
functional coverage settings to be maintained after the simulation is restarted.
-nobreakpoint
Specifies that all breakpoints will be removed when the simulation is restarted. Optional.
The default is for all breakpoints to be reinstalled after the simulation is restarted.
-nolist
Specifies that the current List window environment will not be maintained after the
simulation is restarted. Optional. The default is for all currently listed HDL objects and
their formats to be maintained.
-nolog
Specifies that the current logging environment will not be maintained after the
simulation is restarted. Optional. The default is for all currently logged objects to
continue to be logged.

restart CR-247
-nowave
Specifies that the current Wave window environment will not be maintained after the
simulation is restarted. Optional. The default is for all objects displayed in the Wave
window to remain in the window with the same format.
See also
checkpoint (CR-93), restore (CR-248), vsim (CR-373), "Checkpointing and restoring
simulations" (UM-86), "The difference between checkpoint/restore and restart" (UM-87)

CR-248 restore
restore
The restore command restores the state of a simulation that was saved with a checkpoint
command (CR-93) during the current invocation of VSIM (called a "warm restore").
The items restored are: simulation kernel state, vsim.wlf file, HDL objects listed in the List
and Wave windows, file pointer positions for files opened under VHDL and under Verilog
$fopen, and the saved state of foreign architectures.
If you want to restore while running VSIM, use this command. If you want to start up
VSIM and restore a previously-saved checkpoint, use the -restore switch with the vsim
command (CR-373) (called a "cold restore").
Checkpoint/restore allows a cold restore, followed by simulation activity, followed by a
warm restore back to the original cold-restore checkpoint file. Warm restores to checkpoint
files that were not created in the current run are not allowed except for this special case of
an original cold restore file.
Checkpoint files are platform dependent–you cannot checkpoint on one platform and
restore on another.
Syntax
restore
<filename>
Arguments
<filename>
Specifies the name of the checkpoint file. Required.
See also
checkpoint (CR-93), vsim (CR-373), "The difference between checkpoint/restore and
restart" (UM-87)

resume CR-249
resume
The resume command is used to resume execution of a macro file after a pause command
(CR-217) or a breakpoint. It may be input manually or placed in an onbreak (CR-214)
command string. (Placing a resume command in a bp (CR-75) command string does not
have this effect.) The resume command can also be used in an onerror (CR-216) command
string to allow an error message to be printed without halting the execution of the macro
file.
Syntax
resume
Arguments
None.
See also
abort (CR-44), do (CR-151), onbreak (CR-214), onerror (CR-216), pause (CR-217)

CR-250 right
right
The right command searches right (next) for signal transitions or values in the specified
Wave window. It executes the search on signals currently selected in the window, starting
at the time of the active cursor. The active cursor moves to the found location.
Use this command to move to consecutive transitions or to find the time at which a
waveform takes on a particular value, or an expression of multiple signals evaluates to true.
See the left command (CR-189) for related functionality.
The procedure for using right entails three steps: click on the desired waveform; click on
the desired starting location; issue the right command. (The seetime command (CR-264)
can initially position the cursor from the command line, if desired.)
Syntax
right
Arguments
The waveform display will be searched until the expression evaluates to a boolean true
condition. Optional. The expression may involve more than one signal, but is limited to
signals that have been logged in the referenced Wave window. A signal may be specified
either by its full path or by the shortcut label displayed in the Wave window.
-falling
Searches for a falling edge on the specified signal if that signal is a scalar signal. If it is
-noglitch
Looks at signal values only on the last delta of a time step. For use with the -value option
only. Optional.
-rising
Searches for a rising edge on the specified signal if that signal is a scalar signal. If it is
-value <sig_value>
Species a value of the signal to match. Must be specified in the same radix that the
selected waveform is displayed. Case is ignored, but otherwise the value must be an exact
string match -- don't-care bits are not yet implemented. Only one signal may be selected,
but that signal may be an array. Optional.
-window <wname>
window.

right CR-251
<n>
Specifies to find the nth match. If less than n are found, the number found is returned with
a warning message, and the cursor is positioned at the last match. Optional. The default
is 1.
Examples
right -noglitch -value FF23 2
Finds the second time to the right at which the selected vector transitions to FF23,
ignoring glitches.
right
Goes to the next transition on the selected signal.
right -expr {clk’rising && (mystate == reading) && (/top/u3/addr ==
32’habcd1234)}
Searches right for an expression that evaluates to a boolean 1 when signal clk just
changed from low to high and signal mystate is the enumeration reading and signal
/top/u3/addr is equal to the specified 32-bit hex constant; otherwise is 0.
right -expr {(/top/u3/addr and 32’hff000000) == 32’hac000000}
Searches right for an expression that evaluates to a boolean 1 when the upper 8 bits of the
right -expr {((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode ==
writing)}
Searches right for an expression that evaluates to a boolean 1 when logfile time is
between 23 and 54 microseconds, and clock just changed from low to high and signal
mode is enumeration writing.
Note: "Wave window mouse and keyboard shortcuts" (UM-609) are also available for
next and previous edge searches. Tab searches right (next) and shift-tab searches left
(previous).
See also
"GUI_expression_format" (CR-22), left (CR-189), seetime (CR-264), view (CR-332)

CR-252 run
run
The run command advances the simulation by the specified number of timesteps.
Syntax
run
[<timesteps>[<time_units>]] | [-all] | [-continue] | [-finish] | [-next] |
[-step] | [-over]
Arguments
<timesteps>[<time_units>]
Specifies the number of timesteps for the simulation to run. The number may be
fractional, or may be specified absolute by preceding the value with the character @.
Optional. In addition, optional <time_units> may be specified as:
fs, ps, ns, us, ms, or sec
The default <timesteps> and <time_units> specifications can be changed during a
ModelSim session by selecting Simulate > Simulation Options (Main window). Time
steps and time units may also be set with the RunLength (UM-533) and UserTimeUnit (UM-
534) variables in the modelsim.ini file.
-all
Causes the simulator to run the current simulation forever, or until it hits a breakpoint or
specified break event. Optional.
-continue
Continues the last simulation run after a step (CR-272) command, step -over command or
a breakpoint. A run -continue command may be input manually or used as the last
command in a bp (CR-75) command string. Optional.
-finish
In "C Debug" (UM-399) only, continues the simulation run and returns control to the
calling function. Optional.
-next
Causes the simulator to run to the next event time. Optional.
-step
Steps the simulator to the next HDL statement. Optional.
-over
Specifies that VHDL procedures, functions and Verilog tasks are to be executed but
treated as simple statements instead of entered and traced line by line. Optional.

run CR-253
Examples
run 1000
Advances the simulator 1000 timesteps.
run 10.4 ms
Advances the simulator the appropriate number of timesteps corresponding to 10.4
milliseconds.
run @8000
Advances the simulator to timestep 8000.
See also
step (CR-272)

CR-254 sccom
sccom
The sccom command is actually two commands in one: sccom interacts with a C/C++
compiler to compile SystemC source code into the work library, and sccom -link takes the
compiled source code and links the design.
This command may be invoked from within ModelSim or from the operating system
command prompt. This command may also be invoked during simulation.
Compiled libraries are platform dependent. If you move between platforms, you need to run
vdel -allsystemc on the working library and then recompile your SystemC source.
Compiled libraries are version dependent. For example, you cannot use a library compiled
with 5.8 in a simulation using 5.8a vsim. You have to re-compile your design with the
updated version of sccom.
Certain restrictions apply when compiling SystemC modules with HP aCC. See
"Restrictions on compiling with HP aCC" (UM-169) for details.
During the linking of the design (with sccom -link) the order in which you specify archives
(.a) and object files is very important. Any dependent .a or .o must be specified before the
.a or .o on which it depends.
Compile syntax
sccom
[<CPP compiler options>] [-error <msg_number>[,<msg_number>,...]]
[-f <filename>] [-help] [-log <logfile>] [-nologo][-note
<msg_number>[,<msg_number>,...]] [-scv] [-scms]
[-suppress <msg_number>[,<msg_number>,...]] [-vv] [-verbose] [-version]
[-version] [-warning <msg_number>[,<msg_number>,...]] <filename>
Link syntax
sccom -link
[<CPP linker options>] [-f <filename>] [-help] [-lib <compiled library>]
[-log <logfile>] [-nologo] [-scv] [-vv] [-verbose] [-version]
[-work <library_name>]
Arguments
<CPP compiler options>
Any normal C++ compiler option can be used, with the exception of the -o and -c options.
By default, sccom compiles without debugging information. Specify the -g argument to
compile for debugging. You can specify arguments for all sccom compiles by editing the
CppOptions variable in the modelsim.ini file.
<CPP linker options>
Any normal C++ compiler option can be used, with the exception of the -o option. You
can specify arguments for all sccom compiles by editing the CppOptions variable in the
modelsim.ini file.
-error <msg_number>[,<msg_number>,...]
Changes the severity level of the specified message(s) to "error." Optional. Edit the error
(UM-536) variable in the modelsim.ini file to set a permanent default. See "Changing
message severity level" (UM-546) for more information.

sccom CR-255
-f <filename>
Specifies a file with more command-line arguments. Optional. Allows complex
argument strings to be reused without retyping. Nesting of -f options is allowed.
The file syntax basically follows what you type on the command line with the exception
that newline characters are ignored. Environment variable expansion (for example in a
pathname) does not occur in -f files.
-help
Displays the command’s options and arguments. Optional.
-lib <compiled library>
Only used for sccom -link invocations. Specifies the default working library where the
SystemC linker can find the object files for compiled SystemC modules.
-link
sccom’s -link argument performs the final link of all previously compiled SystemC
source code. Required before running simulation. Any dependent .a or .o must be
specified before the .a or .o on which it depends. Two types of dependencies are possible,
and where you place the -link argument is different based on which type of dependency
the files have.
If your archive or object is dependent on the .o files created by sccom (i.e. your code
references symbols in the generated SystemC .o files), then you must specify the -link
argument after the list of files, as shown below:
sccom a.o b.o libtemp.a -link
Under the covers, the C++ linker’s command and argument order looks like this:
ld a.o b.o libtemp.a <internal list of SC .o files> libsystemc.a
However, if the .o files created by sccom are dependent on the object or archive you
provided, then the -link argument must be placed before the object files or archive:
sccom -link a.o b.o libtemp.a
In this case, the "undercover" command and argument order look like this:
ld <internal list of SC .o files> libsystemc.a a.o b.o libtemp.a
-log <logfile>
Specifies the logfile in which to collect output. Optional. Related modelsim.ini variable
is SccomLogfile.
-nologo
Disables the startup banner. Optional.
-note <msg_number>[,<msg_number>,...]
Changes the severity level of the specified message(s) to "note." Optional. Edit the note
-scv
Includes the SystemC verification library. Optional. If you specify this argument when
compiling your C code with sccom, you must also specify it when linking the object files
with sccom -link. Related modelsim.ini variable is UseScv.

CR-256 sccom
-scms
Includes the SystemC master slave library. Optional. If you specify this argument when
compiling your C code with sccom, you must also specify it when linking the object files
with sccom -link.
-suppress <msg_number>[,<msg_number>,...]
Prevents the specified message(s) from displaying. Optional. You cannot suppress Fatal
or Internal messages. Edit the suppress (UM-536) variable in the modelsim.ini file to set a
permanent default. See "Changing message severity level" (UM-546) for more
information.
-vv
Prints all subprocess invocation information. Optional. An example is the call to gcc
along with the command-line arguments.
-verbose
Prints the name of each sc_module encountered during compilation. Optional. Related
modelsim.ini variable SccomVerbose.
-version
Displays the version of sccom used to compile the design. Optional.
-warning <msg_number>[,<msg_number>,...]
Changes the severity level of the specified message(s) to "warning." Optional. Edit the
warning (UM-536) variable in the modelsim.ini file to set a permanent default. See
"Changing message severity level" (UM-546) for more information.
-work <library_name>
For the compiler:
Specifies a logical name or pathname of a library that is to be mapped to the logical
library work. Optional; by default, the compiled object files (.so) are added to the work
library. The specified pathname overrides the pathname specified for work in the project
file.
For the linker:

Specifies a logical name or pathname of a library where the final linked object file (.so)
is to be stored. Optional; by default, the linked object files are added to the work library.
<filename>
Specifies the name of a file containing the SystemC/C++ source to be compiled.
Required. Multiple filenames separated by spaces can be entered, or wildcards can be
used (e.g., *.cpp).
Examples
sccom -g example.cpp
Compiles example.cpp with debugging information.
sccom -link
Links example.o.
sccom -work lib1 a.cpp
sccom -work lib2 b.cpp
sccom -link -lib lib1 -lib lib2 -work lib3
vsim -scwork lib3 -lib lib1 -lib lib2
These three commands compile a.cpp into a first library lib1, and b.cpp into a second
library called lib2. The compiled object files created in those two libraries are then linked

sccom CR-257
and compiled into a third shared library, lib3. When vsim is invoked, the -scwork
argument is required in order to point to the location of the shared library. The -lib
arguments are required to specify the locations of the SystemC design units.
sccom -I/home/systemc/include -DSC_INCLUDE_FX -g a.cpp b.cpp
Compiles the SystemC code with an include directory and the compile time macro
(SC_INCLUDE_FX) to compile the source with support for fixed point types. For more
information, see "Fixed point types" (UM-182).
sccom -02 a.cpp
Compiles with the g++ -02 optimization argument.
sccom -L home/libs/ -l mylib -link
Links in the library libmylib.a when creating the .so file. The -L argument specifies the
search path for the libraries.
See also
Chapter 6 - SystemC simulation, scgenmod command (CR-258), vdel -allsystemc
command (CR-327)

CR-258 scgenmod
scgenmod
Once a Verilog or VHDL module is compiled into a library, you can use the scgenmod
command to write its equivalent SystemC foreign module declaration to standard output.
Optional arguments allow you to generate sc_bit, sc_bv, or resolved port types; sc_logic
and sc_lv port types are generated by default.
Syntax
scgenmod
[-help] [-lib <library_name>] [-sc_logic] [-sc_bit] [-bool]
[-sc_resolved] [-sc_bv] [-sc_lv] [-sc_rv] [-sc_int] [-sc_uint]
<module_name>
Arguments
-help
-lib <library_name>
Specifies the pathname of the working library. If not specified, the default library work
is used. Optional.
<module_name>
Specifies the name of the Verilog/VHDL module to be accessed. Required.
Scalar type options:

-sc_bit
Causes scgenmod to generate sc_bit scalar port types.
-bool
Causes scgenmod to generate bool scalar port types.
-sc_logic
Causes scgenmod to generate sc_logic scalar port types.
-sc_resolved
Causes scgenmod to generate resolved scalar port types.
Vector type options:

-sc_bv
Causes scgenmod to generate sc_bv<N> vector port types.
-sc_int
Causes scgenmod to generate sc_int<N> vector port types.
-sc_lv
Causes scgenmod to generate sc_lv<N> vector port types.
-sc_rv
Causes scgenmod to generate resolved vector port types.
-sc_uint
Causes scgenmod to generate sc_uint<N> port types.

scgenmod CR-259
Examples
This example uses a Verilog module that is compiled into the work library. The module
begins as Verilog source code:
module vcounter (clock, topcount, count);
input clock;
input topcount;
output count;
reg count;
...
endmodule
After compiling using vlog (CR-358), you invoke scgenmod on the compiled module with
the following command:
scgenmod vcounter
The SystemC foreign module declaration for the above Verilog module is:
class vcounter : public sc_foreign_module
{
public:
sc_in<sc_logic> clock;
sc_in<sc_logic> topcount;
sc_out<sc_logic> count;
vcounter(sc_module_name nm, const char* hdl_name)

: sc_foreign_module(nm, hdl_name),
clock("clock"),
topcount("topcount"),
count("count")
{}
~vcounter()
{}
};
See also
Chapter 6 - SystemC simulation, sccom command (CR-254)

CR-260 search
search
The search command searches the specified window for one or more objects matching the
specified pattern(s). The search starts at the object currently selected, if any; otherwise it
starts at the window top. The default action is to search downward until the first match, then
move the selection to the object found, and return the index of the object found. The search
can be continued using the next command.
Returns the index of a single match, or a list of matching indices. Returns nothing if no
matches are found.
Syntax
search
<window_name> [-window <wname>] [-all] [-field <n>] [-toggle]
[-forward | -backward] [-wrap | -nowrap] [-exact] [-regexp] [-nocase]
[-count <n>] <pattern>
Arguments for all windows

<window_name>
Specifies the window in which to search. Can be one of Signals, Objects, Variables,
Locals, Source, List, Wave, Process, Structure, or a unique abbreviation thereof.
Required.
-window <wname>
Specifies an instance of the window that is not the default. Optional. Otherwise, the
default window is used. Use the view command (CR-332) to change the default window.
-forward
Search in the forward direction. Optional. This is the default.
-backward
Search in the reverse direction. Optional. Default is forward.
<pattern>
String or glob-style wildcard pattern. Required. Must be the last argument specified.
Arguments, for all EXCEPT the Source window

-all
Finds all matches and returns a list of the indices of all objects that match. Optional.
-field <n>
Selects different fields to test, depending on the window type:
Window n=1 n=2 n=3 default
structure instance entity/ architecture instance

module
signals name - cur. value name
process status process fullpath fullpath

label

search CR-261
Window n=1 n=2 n=3 default
variables name - cur. value name
wave name - cur. value name

list label fullname - label
Default behavior for the List window is to attempt to match the label and if that fails, try
to match the full signal name.
-toggle
Adds objects found to the selection. Does not do an initial clear selection. Optional.
Otherwise deselects all and selects only one object.
-wrap
Specifies that the search continue from the top of the window after reaching the bottom.
Optional. This is the default.
-nowrap
Specifies that the search stop at the bottom of the window and not continue searching at
the top. Optional. The default is to wrap.
Arguments, Source window only

-exact
Search for an exact match. Optional.
-regexp
Use the pattern as a Tcl regular expression. Optional.
-nocase
Ignore case. Optional. Default is to use case.
-count <n>
Search for the nth match. Optional. Default is to search for the first match.
Description
With the -all option, the entire window is searched, the last object matching the pattern is
selected, and a Tcl list of all corresponding indices is returned.
With the -toggle option, objects found are selected in addition to the current selection.
For the List window, the search is done on the names of the objects listed, that is, across the
header. To search for values of objects in the List window, use the down command (CR-
152) and up command (CR-290). Likewise, in the Wave window, the search is done on object
names and values in the values column. To search for object values in the waveform pane
of the Wave window, use the right command (CR-250) and the left command (CR-189). You
can also select Edit > Search in both windows.
See also
find (CR-176), next (CR-207), view (CR-332)

CR-262 searchlog
searchlog
The searchlog command searches one or more of the currently open logfiles for a specified
condition. It can be used to search for rising or falling edges, for signals equal to a specified
value, or for when a generalized expression becomes true.
Syntax
searchlog
[-count <n>] [-deltas] [-env <path>] [-expr {<expr>}] [-reverse]
[-rising | -falling | -anyedge] [-startDelta <num>] [-value <string>]
<startTime> <pattern>
If at least one match is found, it returns the time (and optionally delta) at which the last
match occurred and the number of matches found, in a Tcl list:
{{<time>} <matchCount>}
where <time> is in the format <number> <unit>. If the -deltas option is specified, the
delta of the last match is also returned:
{{<time>} <delta> <matchCount>}
If no matches are found, a TCL_ERROR is returned. If one or more matches are found,
but less than the number requested, it is not considered an error condition, and the time
of the farthest match is returned, with the count of the matches found.
Arguments
-count <n>
Specifies to search for the nth occurrence of the match condition, where <n> is a positive
integer. Optional.
-deltas
Indicates to test for a match on simulation delta cycles. Otherwise, matches are only
tested for at the end of each simulation time step. Optional.
-env <path>
Provides a design region in which to look for the signal names. Optional.
-expr {<expr>}
Specifies a general expression of signal values and simulation time. Optional. searchlog
will search until the expression evaluates to true. The expression must have a boolean
result type. See "GUI_expression_format" (CR-22) for the format of the expression.
-reverse
Specifies to search backwards in time from <startTime>. Optional.
-rising | -falling | -anyedge
Specifies an edge to look for on a scalar signal. Optional. This option is ignored for
compound signals. If no options are specified, the default is -anyedge.
-startDelta <num>
Indicates a simulation delta cycle on which to start. Optional.
-value <string>
Specifies to search until a single scalar or compound signal takes on this value. Optional.

searchlog CR-263
<startTime>
Specifies the simulation time at which to start the search. Required. The time may be
specified as an integer number of simulation units, or as {<num> <timeUnit>}, where
<num> can be integer or with a decimal point, and <timeUnit> is one of the standard
VHDL time units (fs, ps, ns, us, ms, sec).
<pattern>
Specifies one or more signal names or wildcard patterns of signal names to search on.
Required unless the -expr argument is used.
See also
virtual signal (CR-351), virtual log (CR-343), virtual nolog (CR-346)

CR-264 seetime
seetime
The seetime command scrolls the List or Wave window to make the specified time visible.
For the List window, a delta can be optionally specified as well.
Returns nothing
Syntax
seetime
list|wave [-window <wname>] [-select] [-delta <num>] <time>
Arguments
list|wave
Specifies the target window type. Required.
-window <wname>
Specifies an instance of the Wave or List window that is not the default. Optional.
Otherwise, the default Wave or List window is used. Use the view command (CR-332) to
change the default window.
-select
Also moves the active cursor or marker to the specified time (and optionally, delta).
Optional. Otherwise, the window is only scrolled.
-delta <num>
For the List window when deltas are not collapsed, this option specifies a delta. Optional.
Otherwise, delta 0 is selected.
<time>
Specifies the time to be made visible. Required.

setenv CR-265
setenv
The setenv command changes or reports the current value of an environment variable. The
setting is not persistent–it is valid only for the current ModelSim session.
Syntax
setenv
<varname> [<value>]
Arguments
<varname>
The name of the environment variable you wish to set or check. Required.
<value>
The value for the environment variable. Optional. If you don’t specify a value, ModelSim
reports the variable’s current value.
See also
unsetenv (CR-289), printenv (CR-224)

CR-266 shift
shift
The shift command shifts macro parameter values left one place, so that the value of
parameter $2 is assigned to parameter $1, the value of parameter $3 is assigned to $2, etc.
The previous value of $1 is discarded.
The shift command and macro parameters are used in macro files. If a macro file requires
more than nine parameters, they can be accessed using the shift command.
To determine the current number of macro parameters, use the argc (UM-542) variable.
Syntax
shift
Arguments
None.
Description
For a macro file containing nine macro parameters defined as $1 to $9, one shift command
shifts all parameter values one place to the left. If more than nine parameters are named,
the value of the tenth parameter becomes the value of $9 and can be accessed from within
the macro file.
See also
do (CR-151)

show CR-267
show
The show command lists HDL objects and subregions visible from the current
environment. The objects listed include:
• VHDL
signals, processes, constants, variables, and instances
• Verilog
nets, registers, tasks, functions, instances, variables, and memories
If using "C Debug" (UM-399), show displays the names and types of the local variables and
arguments of the current C function.
The show command returns formatted results to stdout. To eliminate formatting (to use the
output in a Tcl script), use the Show command instead.
Syntax
show
[-all] [<pathname>]
Arguments
-all
Displays all names at and below the specified path recursively. Optional.
<pathname>
Specifies the pathname of the environment for which you want the objects and
subregions to be listed. Optional; if omitted, the current environment is assumed.
Examples
show
Lists the names of all the objects and subregion environments visible in the current
environment.
show /uut
Lists the names of all the objects and subregions visible in the environment named /uut.
show sub_region
Lists the names of all the objects and subregions visible in the environment named
sub_region which is directly visible in the current environment.
See also
environment (CR-161), find (CR-176)

CR-268 simstats
simstats
The simstats command returns performance-related statistics about elaboration and
simulation. The statistics measure the simulation kernal process (vsimk) for a single
invocation of vsim. If you invoke vsim a second time, or restart the simulation, the current
statistics are discarded and new values are collected.
If executed without arguments, the command returns a list of pairs like the following:
{{elab memory} 0} {{elab working set} 7245824} {{elab time} 0.942645}
{{elab cpu time} 0.190274} {{elab context} 0} {{elab page faults} 1549}
{memory 0} {{working set} 0} {time 0} {{cpu time} 0} {context 0}
{{page faults} 0}
The elaboration statistics are measured one time at the end of elaboration. The simulation
memory statistics are measured at the time you invoke simstats. The simulation time
statistics are updated at the end of each run command. See the arguments below for
descriptions of each statistic.
Units for time values are in seconds. Units for memory values vary by platform:
• For SunOS and Linux, the memory size is reported in Kbytes
• For HP-UX, the memory size is reported in the number of pages
• For Windows, the memory size is reported in bytes.
Some of the values may not be available on all platforms and other values may be
approximates. Different operating systems report these numbers differently.
Syntax
simstats
[memory | working | time | cpu | context | faults]
Arguments
memory
Returns the amount of virtual memory that the OS has allocated for vsimk. Optional.
working
Returns the portion of allocated virtual memory that is currently being used by vsimk.
Optional. If this number exceeds the actual memory size, you will encounter performance
degradation.
time
Returns the cumulative "wall clock time" of all run commands. Optional.
cpu
Returns the cumulative processor time of all run commands. Optional. Processor time
differs from wall clock time in that processor time is only counted when the cpu is
actually running vsimk. If vsimk is swapped out for another process, cpu time does not
increase.
context
Returns the number of context swaps (vsimk being swapped out for another process) that
occurred during all run commands. Optional.

simstats CR-269
faults
Returns the number of page faults that occurred during all run commands. Optional.

CR-270 splitio
splitio
The splitio command operates on a VHDL inout or out port to create a new signal having
the same name as the port suffixed with "__o". The new signal mirrors the output driving
contribution of the port.
Note: In ModelSim versions prior to 5.5c, splitio was used to split the VHDL inout or
output ports so you could re-simulate your design from a vcd file using
vsim -vcdread. In later versions, addition of the vcd dumpports command (CR-295)
eliminated the need for splitio.
Syntax
splitio
[-outalso | -outonly] [-r] <signal_name>...
Arguments
-outalso
Allows splitio to work on out ports as well as inout ports. Optional.
-outonly
Allows splitio to work only on out ports. Optional.
-r
Specifies that the port selection occurs recursively into subregions. Optional. If omitted,
included ports are limited to the current region.
<signal_name>...
Specifies the VHDL port. Operates only on inout ports by default; out ports may be
specified with the options above. Separate multiple port names with spaces. Required.
Wildcards can be used.
Examples
The splitio command operates on inout or out ports and silently ignores any other signals
specified. The new signals created may be specified in any vsim (CR-373) commands that
operate on signals. These signals appear to be out ports to the signal selection options on
vsim commands. For example,
splitio /data
Creates a signal data__o if data is an inout port.

status CR-271
status
The status command lists summary information about currently interrupted macros. If
invoked without arguments, the command lists the filename of each interrupted macro, the
line number at which it was interrupted, and prints the command itself. It also displays any
onbreak (CR-214) or onerror (CR-216) commands that have been defined for each
interrupted macro.
Syntax
status
[file | line]
Arguments
file
Reports the file pathname of the current macro.
line
Reports the line number of the current macro.
Examples
The transcript below contains examples of resume (CR-249), and status commands.
VSIM(paused)> status
# Macro resume_test.do at line 3 (Current macro)
# command executing: “pause”
# is Interrupted
# ONBREAK commands: “resume”
# Macro startup.do at line 34
# command executing: “run 1000"
# processing BREAKPOINT
# is Interrupted
# ONBREAK commands: “resume”
VSIM(paused)> resume
# Resuming execution of macro resume_test.do at line 4
See also
abort (CR-44), do (CR-151), pause (CR-217), resume (CR-249)

CR-272 step
step
The step command steps to the next HDL or C statement. Current values of local HDL
variables may be observed at this time using the Locals window. VHDL procedures and
functions, Verilog tasks and functions, and C functions can optionally be skipped over.
When a wait statement or end of process is encountered, time advances to the next
scheduled activity. The Process and Source windows will then be updated to reflect the next
activity.
Syntax
step
[-over] [<n>]
Arguments
-over
Specifies that VHDL procedures and functions, Verilog tasks and functions, and C
functions should be executed but treated as simple statements instead of entered and
traced line by line. Optional.
<n>
Any integer. Optional. Will execute ‘n’ steps before returning.
See also
run (CR-252)

stop CR-273
stop
The stop command is used with the when command (CR-407) to stop simulation in batch
files. The stop command has the same effect as hitting a breakpoint. The stop command
may be placed anywhere within the body of the when command.
Syntax
stop
Arguments
None.
Use the run command (CR-252) with the -continue option to continue the simulation run,
or the resume command (CR-249) to continue macro execution. If you want macro
execution to resume automatically, put the resume command at the top of your macro file:
onbreak {resume}
Note: If you want to stop the simulation using a when command (CR-407), you must use
a stop command within your when statement. DO NOT use an exit command (CR-166)
or a quit command (CR-240). The stop command acts like a breakpoint at the time it is
evaluated.
See also
bp (CR-75), resume (CR-249), run (CR-252), when (CR-407)

CR-274 tb
tb
The tb (traceback) command displays a stack trace for the current process in the Transcript
pane. This lists the sequence of HDL function calls that have been entered to arrive at the
current state for the active process.
If you are using "C Debug" (UM-399), tb displays a stack trace of the C call stack.
Syntax
tb
[<#_of_levels>]
Arguments
<#_of_levels>
Specifies the number of call frames in the C stack to display. Optional. If you don’t
specify a level, the entire C stack is displayed. This argument is available only for "C
Debug" (UM-399).

tcheck_set CR-275
tcheck_set
The tcheck_set command works in tandem with tcheck_status (CR-277) to report on and
enable/disable individual timing checks. tcheck_set modifies either a check's reporting or
X-generation status and reports the new setting in the Transcript pane.
Disabling a timing check's reporting prevents generation of associated violation messages.
For Verilog modules this means ModelSim disables message reporting. For VHDL design
units this means ModelSim sets the MsgOn parameter in a VITAL timing check procedure
(TCP) to FALSE. Disabling a timing check's X generation removes a timing check’s ability
to affect the outputs of the simulation. For Verilog modules this means ModelSim toggles
the timing check's notifier. For VHDL design units this means ModelSim sets the Xon
parameter in a VITAL TCP to FALSE.
tcheck_set does not override the effects of invoking vlog (CR-358) or vsim (CR-373) with
the +nospecify, +notimingchecks, or +no_neg_tchk argument. tcheck_set can override
the effects of invoking vsim (CR-373) with the +no_notifier, +no_tchk_msg, -g, or -G
argument. These latter arguments establish initial values for the simulation, and those
values can be modified by tcheck_set.
Keep in mind the following if you are using VHDL VITAL:
• VITAL does not provide the granularity to set individual period or width checks. These
checks are part of a single VITAL TCP, and tcheck_set toggles MsgOn and Xon for all
checks in the TCP. See "Examples" below for further information.
• If an instance is not Level-1 optimized, you cannot set values for individual TCPs. You
can set values only for the entire instance. tcheck_status reports "ALL" for instances that
aren’t Level-1 optimized. See "Examples" below for further information.
Syntax
tcheck_set
<instance> [-quiet] [-r | <tcheck>] [<Stat> | <MsgStat> <XStat>]
Arguments
<instance>
Specifies the instance for which you want to change the reporting or X-generation status.
Required.
-quiet
Suppresses printing the new setting to the Transcript pane. Optional.
-r
Attempts to change all checks on this instance and instances below this instance.
Optional.
<tcheck>
Specifies a specific timing check to change. Optional. If you don’t specify <tcheck> or
-r, or you specify ALL for <tcheck>, ModelSim attempts to apply the change to all
timing checks in the instance.
You can specify either the integer that is assigned to each timing check (and reported via
tcheck_status) or the actual timing check name enclosed in double quotes (see
"Examples" below). Note that the integer number may change between library compiles.

CR-276 tcheck_set
<Stat>
Enables/disables both X generation and violation message reporting for the specified
timing check(s). Optional. Specify either ON (enable) or OFF (disable).
<MsgStat>
Enables/disables violation message reporting for the specified timing check(s). Optional.
Specify either ON (enable) or OFF (disable).
<XStat>
Enables/disables X generation for the specified timing check(s). Optional. Specify either
ON (enable) or OFF (disable).
Examples
tcheck_set top.y1.u2 "( WIDTH (negedge CLK) )" OFF
Turns off message reporting and X generation for the "( WIDTH (negedge CLK) )" check
in instance top.y1.u2. Creates the following output in the Transcript pane:
#0 ( WIDTH (negedge CLK) ) MsgOff XOff
tcheck_set top.y1.u2 1 OFF ON

Turns off message reporting for timing check number 1 in instance top.y1.u2. Creates the
following output in the Transcript pane:
#1 ( WIDTH (posedge CLK) ) MsgOff XOn
VSIM 2> tcheck_status dff1

# 1 ( PERIOD CLK ) MsgOn, XOn
# ( WIDTH (posedge CLK) ) MsgOn, XOn
# ( WIDTH (negedge CLK) ) MsgOn, XOn
VSIM 3> tcheck_set dff1 "( WIDTH (posedge CLK) )" off on
# 1 ( PERIOD CLK ) MsgOff, XOn
# ( WIDTH (posedge CLK) ) MsgOff, XOn
# ( WIDTH (negedge CLK) ) MsgOff, XOn
Shows how period and hold checks work with VHDL VITAL. In this case, specifying
"off on" for ( WIDTH (posedge CLK) ) also sets ( PERIOD CLK ) and ( WIDTH (negedge
CLK) ) to the same values.
VSIM 3> tcheck_status dff5

# ALL MsgOn XOn
VSIM 4> tcheck_set dff5 on off

# ALL MsgOn XOff
Instance dff5 is from an unaccelerated model so tcheck_set can only toggle message
reporting and X generation for all checks on the instance.
See also
tcheck_status (CR-277), "VITAL compliance warnings" (UM-94), Chapter 18 - Standard
Delay Format (SDF) Timing Annotation, "Disabling timing checks" (UM-451), -g, -G,
no_notifier, +no_tchk_msg, +nospecify, +no_neg_tchk, and +notimingchecks
arguments to the vsim command (CR-373)

tcheck_status CR-277
tcheck_status
The tcheck_status command works in tandem with tcheck_set (CR-275) to report on and
enable/disable individual timing checks. tcheck_status prints in the Transcript pane the
current status of all timing checks in the instance or a specific timing check specified with
the optional <tcheck> argument.
Disabling a timing check's reporting prevents generation of associated violation messages.
For Verilog modules this means ModelSim disables message reporting. For VHDL design
units this means ModelSim sets the MsgOn parameter in a VITAL timing check procedure
(TCP) to FALSE. Disabling a timing check's X generation removes a timing check’s ability
to affect the outputs of the simulation. For Verilog modules this means ModelSim toggles
the timing check's notifier. For VHDL design units this means ModelSim sets the Xon
parameter in a VITAL TCP to FALSE.
Syntax
tcheck_status
[-lines] <instance> [<tcheck>]
Arguments
-lines
Specifies that the HDL source file and line numbers of the check(s) be displayed.
Optional. Has no effect on VHDL instances. Note that line information may not always
be available.
<instance>
Specifies the instance for which you want timing check status reported. Required.
<tcheck>
Specifies a specific timing check within the instance on which to report status. Optional.
By default ModelSim reports all timing checks within the specified instance. You can
specify either the integer that is assigned to each timing check (and reported via
tcheck_status) or the actual timing check name enclosed in double quotes (see
"Examples" below). Note that the integer number may change between library compiles.
Output
The output of the tcheck_status command looks as follows:
#<Number> <SDF_Description> [<src_line>] <MsgStat> <XStat>
Field Description
<Number> an integer that can be used as shorthand to specify the check in the
tcheck_status or tcheck_set commands (as the <tcheck>
argument); this number can change with compiler optimizations,
and you can’t assume it will stay the same between library compiles
<SDF_Description> an SDF specification of the timing check including enclosing

parentheses ’( )'

CR-278 tcheck_status
Field Description
<src_line> the source file and line number for the timing check specification;
output if you specify the -lines argument; the format of the object is
<source_file_name>:<line_number>.
<MsgStat> violation message reporting status indicator

MsgON/MsgOFF - violation reporting is enabled/disabled and
unchangeable
MsgOn/MsgOff - violation reporting is enabled/disabled and
modifiable
<XStat> violation X generation status indicator

XON/XOFF - X generation is enabled/disabled and
unchangeable
XOn/XOff - X generation is enabled/disabled and modifiable
Examples
tcheck_status top.y1.u2
Creates the following output:
#0 ( WIDTH (negedge CLK) ) MsgOn XOn
#1 ( WIDTH (posedge CLK) ) MsgOn XOn
#2 ( SETUP (negedge D) (posedge CLK) ) MsgOFF XOFF
#3 ( HOLD (posedge CLK) (negedge D) ) MsgOn XOff
tcheck_status -lines top.y1.u2 1

Creates the following output:
#1 ( WIDTH (posedge CLK) ) 'cell.v:224' MsgOn XOn
See also
tcheck_set (CR-275), Chapter 18 - Standard Delay Format (SDF) Timing Annotation

toggle add CR-279
toggle add
The toggle add command enables collection of toggle statistics for the specified nodes. The
allowed nodes are Verilog nets and registers and VHDL signals of type bit, bit_vector,
std_logic, and std_logic_vector (other types are silently ignored).
You can also collect and view toggle statistics in the ModelSim GUI. See Chapter 13 -
Measuring code coverage for details.
Syntax
toggle add
[-full] [-in] [-inout] [-internal] [-out] [-ports] [-r] <node_name>-unique
Returns
Command result Return value
no signals are added and no signals are Nothing added.

found to be already in the toggle set
no signals are added and some signals 0

are found to be already in the toggle set
some signals are added the number of bits added
Arguments
-full
Enables extended mode toggle coverage, which tracks the following six transitions:
1) 1 or H --> 0 or L
2) 0 or L --> 1 or H
3) X or Z --> 1 or H
4) X or Z --> 0 or L
5) 1 or H --> X or Z
6) 0 or L --> X or Z
Optional. By default only transitions to 0 and 1 are counted.
-in
Enables toggle statistics collection on nodes of mode IN. Optional.
-inout
Enables toggle statistics collection on nodes of mode INOUT. Optional.
-internal
Enables toggle statistics collection on internal (non-port) objects. Optional.
-out
Enables toggle statistics collection on nodes of mode OUT. Optional.

CR-280 toggle add
-ports
Enables toggle statistics collection on nodes of modes IN, OUT, or INOUT. Optional.
-r
Specifies that toggle statistics collection is enabled recursively into subregions. Optional.
If omitted, toggle statistic collection is limited to the current region.
<node_name>
Enables toggle statistics collection for the named node(s). Required. Multiple names and
wildcards are accepted.
-unique
Reports an attempt to add a signal that is an alias to a signal already added. The alias will
not be added. Optional.
Examples
toggle add /dut/data/a
Enables toggle statistics collection for signal /dut/data/a.
toggle add {/dut/data_in[5]}
Enables toggle statistics collection for bit 6 of bus /dut/data_in. The curly braces must be
added in order to escape the square brackets (’[]’).
See also
"Toggle coverage" (UM-343), toggle report (CR-283), toggle reset (CR-284)

toggle disable CR-281
toggle disable
The toggle disable command disables toggle statistics collection on the specified nodes.
The command provides a method of implementing coverage exclusions for toggle
coverage.
The command is intended to be used as follows:
1 Enable toggle statistics collection for all signals using the -cover t/x argument to vcom
(CR-311) or vlog (CR-358).
2 Exclude certain signals by disabling them with the toggle disable command.
Syntax
toggle disable
[-all] | [-in] [-out] [-inout] [-internal] [-ports] [-r] <node_name>
Arguments
-all
Disables toggle statistics collection for all nodes that have toggle checking enabled.
Optional. Must be used alone without other arguments.
-in
Disables toggle statistics collection on nodes of mode IN. Optional.
-out
Disables toggle statistics collection on nodes of mode OUT. Optional.
-inout
Disables toggle statistics collection on nodes of mode INOUT. Optional.
-internal
Disables toggle statistics collection on internal (non-port) objects. Optional.
-ports
Disables toggle statistics collection on nodes of modes IN, OUT, or INOUT. Optional.
-r
Specifies that toggle statistics collection is disabled recursively into subregions.
Optional. If omitted, the disable is limited to the current region.
<node_name>
Disables toggle statistics collection for the named node(s). Required. Multiple names and
See also
"Toggle coverage" (UM-343), toggle add (CR-279), toggle enable (CR-282)

CR-282 toggle enable
toggle enable
The toggle enable command re-enables toggle statistics collection on nodes whose toggle
coverage had previously been disabled via the toggle disable command.
Syntax
toggle enable
Arguments
-all
Enables toggle statistics collection for all nodes that have toggle checking disabled.
-in
Enables toggle statistics collection on disabled nodes of mode IN. Optional.
-out
Enables toggle statistics collection on disabled nodes of mode OUT. Optional.
-inout
Enables toggle statistics collection on disabled nodes of mode INOUT. Optional.
-internal
Enables toggle statistics collection on disabled internal (non-port) objects. Optional.
-ports
Enables toggle statistics collection on disabled nodes of modes IN, OUT, or INOUT.
Optional.
-r
Specifies that toggle statistics collection is enabled recursively into subregions. Optional.
If omitted, the enable is limited to the current region.
<node_name>
Enables toggle statistics collection for the named node(s). Required. Multiple names and
See also
"Toggle coverage" (UM-343), toggle disable (CR-281)

toggle report CR-283
toggle report
The toggle report command displays a list of all nodes that have not transitioned to both 0
and 1 at least once. Also displayed is a summary of the number of nodes checked, the
number that toggled, the number that didn't toggle, and a percentage that toggled.
You can also collect and view toggle statistics in the ModelSim GUI. See Chapter 13 -
Measuring code coverage for details.
The toggle report command is intended to be used as follows:
1 Enable statistics collection with the toggle add command (CR-279).
3 Produce the report with the toggle report command.
Note: If you want to ensure that you are reporting all signals in the design, use the
-nocollapse argument to vsim when you load your design. Without this argument, the
simulator collapses certain ports that are connected to the same signal in order to improve
performance, and those collapsed signals will not appear in the report. The -nocollapse
argument degrades simulator performance, so it should be used only when it is absolutely
necessary to see all signals in a toggle report.
Syntax
toggle report
[-all] [-file <filename>] [<signal>...] [-summary]
Arguments
-all
Lists all nodes checked along with their individual transition to 0 and 1 counts. Optional.
-file <filename>
Specifies a file to which to write the report. By default the report is displayed in the
Transcript pane. Optional.
<signal>...
Specifies the name of a signal whose toggle statistics are to be displayed. Multiple signal
names, separated by spaces, may be specified. Wildcards may be used.
-summary
Selects only the summary portion of the report. Optional.
See also
"Toggle coverage" (UM-343), toggle add (CR-279), toggle reset (CR-284)

CR-284 toggle reset
toggle reset
The toggle reset command resets the toggle counts to zero for the specified nodes.
Syntax
toggle reset
Arguments
-all
Resets toggle statistics collection for all nodes that have toggle checking enabled.
-in
Resets toggle statistics collection on nodes of mode IN. Optional.
-out
Resets toggle statistics collection on nodes of mode OUT. Optional.
-inout
Resets toggle statistics collection on nodes of mode INOUT. Optional.
-internal
Resets toggle statistics collection on internal (non-port) objects. Optional.
-ports
Resets toggle statistics collection on nodes of modes IN, OUT, or INOUT. Optional.
-r
Specifies that toggle statistics collection is reset recursively into subregions. Optional. If
omitted, the reset is limited to the current region.
<node_name>
Resets toggle statistics collection for the named node(s). Required. Multiple names and
See also
"Toggle coverage" (UM-343), toggle add (CR-279), toggle report (CR-283)

transcribe CR-285
transcribe
The transcribe command displays a command in the Transcript pane, and then executes
the command. The transcribe command is normally used to direct commands to the
Transcript pane from an external event such as a menu pick or button selection. The add
button (CR-45) and add_menuitem (CR-59) commands can utilize transcribe. Returns
nothing.
Syntax
transcribe
<command>
Arguments
<command>
Specifies the command to execute. Required.
Examples
add button pwd {transcribe pwd} NoDisable
Creates a button labeled "pwd" that invokes transcribe with the pwd Tcl command, and
echoes the command and its results to the Transcript pane. The button remains active
during a run.
See also
add button (CR-45), add_menuitem (CR-59)

CR-286 transcript
transcript
The transcript command controls echoing of commands executed in a macro file. If no
option is specified, the current setting is reported.
Syntax
transcript
[on | off | -q | quietly]
Arguments
on
Specifies that commands in a macro file will be echoed to the Transcript pane as they are
executed. Optional.
off
Specifies that commands in a macro file will not be echoed to the Transcript pane as they
are executed. Optional. The transcribe command (CR-285) can be used to force a
command to be echoed.
-q
Returns "0" if transcripting is turned off or "1" if transcripting is turned on. Useful in a
Tcl conditional expression. Optional.
quietly
Turns off the transcript echo for all commands. To turn off echoing for individual
commands see the quietly command (CR-239). Optional.
Examples
transcript on
Commands within a macro file will be echoed to the Transcript pane as they are executed.
transcript
If issued immediately after the previous example, the message:
Macro transcripting is turned ON.
appears in the Transcript pane.
See also
echo (CR-156), transcribe (CR-285)

transcript file CR-287
transcript file
The transcript file command sets or queries the pathname for the transcript file. You can
use this command to clear a transcript in batch mode or to limit the size of a transcript file.
It offers an alternative to setting the PrefMain(file) Tcl preference variable.
Syntax
transcript file
[<filename>]
Arguments
<filename>
Specifies the full path and filename for the transcript file. Optional. If you specify a new
file, the existing transcript file is closed and a new transcript file opened. If you specify
an empty string (""), the existing file is closed and no new file is opened. If you don’t
specify this argument, the current setting is returned.
Examples
transcript file ""
Closes the current transcript file and stops writing data to the file. This is a method for
reducing the size of your transcript.
transcript file ""
run 1 ms
transcript file transcript
run 1 ms
This series of commands results in the transcript containing only data from the second
millisecond of the simulation. The first transcript file command closes the transcript so
no data is being written to it. The second transcript file command opens a new transcript
and records data from 1 ms to 2 ms.
See also
"Transcript" (GR-16)

CR-288 tssi2mti
tssi2mti
The tssi2mti command is used to convert a vector file in Fluence Technology (formerly
TSSI) Standard Events Format into a sequence of force (CR-180) and run (CR-252)
commands. The stimulus is written to the standard output.
The source code for tssi2mti is provided in the file tssi2mti.c in the examples directory.
Syntax
tssi2mti
<signal_definition_file> [<sef_vector_file>]
Arguments
<signal_definition_file>
Specifies the name of the Fluence Technology signal definition file describing the format
and content of the vectors. Required.
<sef_vector_file>
Specifies the name of the file containing vectors to be converted. If none is specified,
standard input is used. Optional.
Examples
tssi2mti trigger.def trigger.sef > trigger.do
The command will produce a do file named trigger.do from the signal definition file
trigger.def and the vector file trigger.sef.
tssi2mti trigger.def < trigger.sef > trigger.do
This example is the same as the previous one, but uses the standard input instead.
See also
force (CR-180), run (CR-252), write tssi (CR-429)

unsetenv CR-289
unsetenv
The unsetenv command deletes an environment variable. The deletion is not permanent–it
is valid only for the current ModelSim session.
Syntax
unsetenv
<varname>
Arguments
<varname>
The name of the environment variable you wish to delete. Required.
See also
setenv (CR-265), printenv (CR-224)

CR-290 up
up
The up command searches for object transitions or values in the specified List window. It
executes the search on objects currently selected in the window, starting at the time of the
active cursor. The active cursor moves to the found location.
Use this command to move to consecutive transitions or to find the time at which an object
takes on a particular value, or an expression of multiple objects evaluates to true. See the
down command (CR-152) for related functionality.
The procedure for using up includes three steps: click on the desired object; click on the
desired starting location; issue the up command. (The seetime command (CR-264) can
Syntax
up
Arguments
The List window will be searched until the expression evaluates to a boolean true
condition. Optional. The expression may involve more than one object, but is limited to
objects that have been logged in the referenced List window. An object may be specified
either by its full path or by the shortcut label displayed in the List window.
-falling
Searches for a falling edge on the specified object if that object is a scalar. If it is not a
scalar, the option will be ignored. Optional.
-noglitch
Specifies that delta-width glitches are to be ignored. Optional.
-rising
Searches for a rising edge on the specified object if that object is a scalar. If it is not a
scalar, the option will be ignored. Optional.
-value <sig_value>
Specifies a value of the object to match. Optional. Must be specified in the same radix in
which the selected object is displayed. Case is ignored, but otherwise must be an exact
string match -- don't-care bits are not yet implemented.
-window <wname>
window.

up CR-291
<n>
Specifies to find the nth match. Optional. If less than n are found, the number found is
returned with a warning message, and the marker is positioned at the last match.
Examples
up -noglitch -value FF23
Finds the last time at which the selected vector transitions to FF23, ignoring glitches.
up
Goes to the previous transition on the selected object.
up -expr {clk’rising && (mystate == reading) && (/top/u3/addr ==
32’habcd1234)}
Searches up for an expression that evaluates to a boolean 1 when signal clk just changed
from low to high and signal mystate is the enumeration reading and signal /top/u3/addr
is equal to the specified 32-bit hex constant.
up -expr {(/top/u3/addr and 32’hff000000) == 32’hac000000}
Searches up for an expression that evaluates to a boolean 1 when the upper 8 bits of the
up -expr {((NOW > 23 us) && (NOW < 54 us)) && clk’rising && (mode == writing)}
Searches up for an expression that evaluates to a boolean 1 when logfile time is between
23 and 54 microseconds, clock just changed from low to high, and signal mode is
enumeration writing.
See also
"GUI_expression_format" (CR-22), view (CR-332), seetime (CR-264), down (CR-152)

CR-292 vcd add
vcd add
The vcd add command adds the specified objects to a VCD file. The allowed objects are
Verilog nets and variables and VHDL signals of type bit, bit_vector, std_logic, and
std_logic_vector (other types are silently ignored).
All vcd add commands must be executed at the same simulation time. The specified
objects are added to the VCD header and their subsequent value changes are recorded in
the specified VCD file.
By default all port driver changes and internal variable changes are captured in the file. You
can filter the output using arguments detailed below.
Related Verilog tasks: $dumpvars, $fdumpvars
Syntax
vcd add
[-r] [-in] [-out] [-inout] [-internal] [-ports] [-file <filename>]
<object_name>
Arguments
-r
Specifies that signal and port selection occurs recursively into subregions. Optional. If
omitted, included signals and ports are limited to the current region.
-in
Includes only port driver changes from ports of mode IN. Optional.
-out
Includes only port driver changes from ports of mode OUT. Optional.
-inout
Includes only port driver changes from ports of mode INOUT. Optional.
-internal
Includes only internal variable or signal changes. Excludes port driver changes. Optional.
-ports
Includes only port driver changes. Excludes internal variable or signal changes. Optional.
-file <filename>
Specifies the name of the VCD file. This option should be used only when you have
created multiple VCD files using the vcd files command (CR-304).
<object_name>
Specifies the Verilog or VHDL object to add to the VCD file. Required. Multiple objects
may be specified by separating names with spaces. Wildcards are accepted.
See also
See Chapter 19 - Value Change Dump (VCD) Files for more information on VCD files.
Verilog tasks are documented in the IEEE 1364 standard.

vcd checkpoint CR-293
vcd checkpoint
The vcd checkpoint command dumps the current values of all VCD variables to the
specified VCD file. While simulating, only value changes are dumped.
Related Verilog tasks: $dumpall, $fdumpall
Syntax
vcd checkpoint
[<filename>]
Arguments
<filename>
Specifies the name of the VCD file. Optional. If omitted the command is executed on the
file designated by the vcd file command (CR-302) or "dump.vcd" if vcd file was not
invoked.
See also

CR-294 vcd comment
vcd comment
The vcd comment command inserts the specified comment in the specified VCD file.
Syntax
vcd comment
<comment string> [<filename>]
Arguments
<comment string>
Comment to be included in the VCD file. Required. Must be quoted by double quotation
marks or curly braces.
<filename>
file designated by the vcd file command (CR-302) or "dump.vcd" if vcd file was not
invoked.
See also

vcd dumpports CR-295
vcd dumpports
The vcd dumpports command creates a VCD file that includes port driver data.
By default all port driver changes are captured in the file. You can filter the output using
arguments detailed below.
Related Verilog task: $dumpports
Syntax
vcd dumpports
[-compress] [-file <filename>] [-in] [-inout] [-out] [-unique]
[-vcdstim ] <object_name>
Arguments
-compress
Produces a compressed VCD file. Optional. ModelSim uses the gzip compression
algorithm. If you specify a .gz extension on the -file <filename> argument, ModelSim
compresses the file even if you don’t use the -compress argument.
-file <filename>
Specifies the path and name of a VCD file to create. Optional. Defaults to the current
working directory and the filename dumpports.vcd. Multiple filenames can be opened
during a single simulation.
-in
Includes ports of mode IN. Optional.
-inout
Includes ports of mode INOUT. Optional.
-out
Includes ports of mode OUT. Optional.
-unique
Generates unique VCD variable names for ports, even if those ports are connected to the
same collapsed net. Optional.
-vcdstim
Ensures that port name order in the VCD file matches the declaration order in the
instance’s module or entity declaration. Optional. See "Port order issues" (UM-460) for
further information.
<object_name>
Specifies the Verilog or VHDL object to add to the VCD file. Required. Multiple objects
may be specified by separating names with spaces. Wildcards are accepted.

CR-296 vcd dumpports
Examples
vcd dumpports -in -file counter.vcd /test_counter/dut/*
Creates a VCD file named counter.vcd of all IN ports in the region /test_counter/dut/.
vcd dumpports -file addern.vcd /testbench/uut/*
vsim -vcdstim addern.vcd addern -gn=8 -do "add wave /*; run 1000"
These two commands resimulate a design from a VCD file. See "Simulating with input
values from a VCD file" (UM-458) for further details.
vcd dumpports -vcdstim -file proc.vcd /top/p/*
vcd dumpports -vcdstim -file cache.vcd /top/c/*
run 1000
vsim top -vcdstim /top/p=proc.vcd -vcdstim /top/c=cache.vcd

This series of commands creates VCD files for the instances proc and cache and then re-
simulates the design using the VCD files in place of the instance source files. See
"Replacing instances with output values from a VCD file" (UM-459) for more information.

vcd dumpportsall CR-297
vcd dumpportsall
The vcd dumpportsall command creates a checkpoint in the VCD file which shows the
value of all selected ports at that time in the simulation, regardless of whether the port
values have changed since the last timestep.
Related Verilog task: $dumpportsall
Syntax
vcd dumpportsall
[<filename>]
Arguments
<filename>
Specifies the name of the VCD file. Optional. If omitted the command is executed on all
open VCD files.
See also

CR-298 vcd dumpportsflush
vcd dumpportsflush
The vcd dumpportsflush command flushes the contents of the VCD file buffer to the
specified VCD file.
Related Verilog task: $dumpportsflush
Syntax
vcd dumpportsflush
[<filename>]
Arguments
<filename>
open VCD files.
See also

vcd dumpportslimit CR-299
vcd dumpportslimit
The vcd dumpportslimit command specifies the maximum size of the VCD file (by
default, limited to available disk space). When the size of the file exceeds the limit, a
comment is appended to the file and VCD dumping is disabled.
Related Verilog task: $dumpportslimit
Syntax
vcd dumpportslimit
<dumplimit> [<filename>]
Arguments
<dumplimit>
Specifies the maximum VCD file size in bytes. Required.
<filename>
open VCD files.
See also

CR-300 vcd dumpportsoff
vcd dumpportsoff
The vcd dumpportsoff command turns off VCD dumping and records all dumped port
values as x.
Related Verilog task: $dumpportsoff
Syntax
vcd dumpportsoff
[<filename>]
Arguments
<filename>
open VCD files.
See also

vcd dumpportson CR-301
vcd dumpportson
The vcd dumpportson command turns on VCD dumping and records the current values of
all selected ports. This command is typically used to resume dumping after invoking vcd
dumpportsoff.
Related Verilog task: $dumpportson
Syntax
vcd dumpportson
[<filename>]
Arguments
<filename>
open VCD files.
See also

CR-302 vcd file
vcd file
The vcd file command specifies the filename and state mapping for the VCD file created
by a vcd add command (CR-292). The vcd file command is optional. If used, it must be
issued before any vcd add commands.
Related Verilog task: $dumpfile
Note: vcd file is included for backward compatibility. Use the vcd files command (CR-
304) if you want to use multiple VCD files during a single simulation.
Syntax
vcd file
[-dumpports] [<filename>] [-map <mapping pairs>] [-nomap]
Arguments
-dumpports
Capture detailed port driver data for Verilog ports and VHDL std_logic ports. Optional.
This option works only on ports, and any subsequent vcd add command (CR-292) will
accept only qualifying ports (silently ignoring all other specified objects).
<filename>
Specifies the name of the VCD file that is created (the default is dump.vcd). Optional.
-map <mapping pairs>
Affects only VHDL signals of type std_logic. Optional. It allows you to override the
default mappings. The mapping is specified as a list of character pairs. The first character
in a pair must be one of the std_logic characters UX01ZWLH- and the second character
is the character you wish to be recorded in the VCD file. For example, to map L and H
to z:
vcd file -map "L z H z"
Note that the quotes in the example above are a Tcl convention for command strings that
include spaces.
-nomap
Affects only VHDL signals of type std_logic. Optional. It specifies that the values
recorded in the VCD file shall use the std_logic enumeration characters of UX01ZWLH-.
This option results in a non-standard VCD file because VCD values are limited to the
four state character set of x01z. By default, the std_logic characters are mapped as
follows.
VHDL VCD VHDL VCD
U x W x
X x L 0
0 0 H 1

vcd file CR-303
VHDL VCD VHDL VCD
1 1 - x
Z z
See also

CR-304 vcd files
vcd files
The vcd files command specifies a filename and state mapping for a VCD file created by a
vcd add command (CR-292). The vcd files command is optional. If used, it must be issued
before any vcd add commands.
Related Verilog task: $fdumpfile
Syntax
vcd files
[-compress] <filename> [-map <mapping pairs>] [-nomap]
Arguments
-compress
Produces a compressed VCD file. Optional. ModelSim uses the gzip compression
algorithm. If you specify a .gz extension on the -file <filename> argument, ModelSim
compresses the file even if you don’t use the -compress argument.
<filename>
Specifies the name of a VCD file to create. Required. Multiple files can be opened during
a single simulation; however, you can create only one file at a time. If you want to create
multiple files, invoke vcd files multiple times.
-map <mapping pairs>
Affects only VHDL signals of type std_logic. Optional. It allows you to override the
default mappings. The mapping is specified as a list of character pairs. The first character
in a pair must be one of the std_logic characters UX01ZWLH- and the second character
is the character you wish to be recorded in the VCD file. For example, to map L and H
to z:
vcd files -map "L z H z"
Note that the quotes in the example above are a Tcl convention for command strings that
include spaces.
-nomap
Affects only VHDL signals of type std_logic. Optional. It specifies that the values
recorded in the VCD file shall use the std_logic enumeration characters of UX01ZWLH-.
This option results in a non-standard VCD file because VCD values are limited to the
four state character set of x01z. By default, the std_logic characters are mapped as
follows.
VHDL VCD VHDL VCD
U x W x
X x L 0
0 0 H 1
1 1 - x
Z z

vcd files CR-305
Examples
The following example shows how to "mask" outputs from a VCD file until a certain time
after the start of the simulation. The example uses two vcd files commands and the vcd on
(CR-309) and vcd off (CR-308) commands to accomplish this task.
vcd files in_inout.vcd
vcd files output.vcd
vcd add -in -inout -file in_inout.vcd /*
vcd add -out -file output.vcd /*
vcd off output.vcd
run 1us
vcd on output.vcd
run -all
See also

CR-306 vcd flush
vcd flush
The vcd flush command flushes the contents of the VCD file buffer to the specified VCD
file. This command is useful if you want to create a complete VCD file without ending your
current simulation.
Related Verilog tasks: $dumpflush, $fdumpflush
Syntax
vcd flush
[<filename>]
Arguments
<filename>
file designated by the vcd file command (CR-302) or dump.vcd if vcd file was not
invoked.
See also

vcd limit CR-307
vcd limit
The vcd limit command specifies the maximum size of a VCD file (by default, limited to
available disk space). When the size of the file exceeds the limit, a comment is appended
to the file and VCD dumping is disabled.
Related Verilog tasks: $dumplimit, $fdumplimit
Syntax
vcd limit
<filesize> [<filename>]
Arguments
<filesize>
Specifies the maximum VCD file size in bytes. Required.
<filename>
invoked.
See also

CR-308 vcd off
vcd off
The vcd off command turns off VCD dumping to the specified file and records all VCD
variable values as x.
Related Verilog tasks: $dumpoff, $fdumpoff
Syntax
vcd off
[<filename>]
Arguments
<filename>
invoked.
See also

vcd on CR-309
vcd on
The vcd on command turns on VCD dumping to the specified file and records the current
values of all VCD variables. By default, vcd on is automatically performed at the end of
the simulation time that the vcd add (CR-292) commands are performed.
Related Verilog tasks: $dumpon, $fdumpon
Syntax
vcd on
[<filename>]
Arguments
<filename>
invoked.
See also
Verilog system tasks are documented in the IEEE 1364 standard.

CR-310 vcd2wlf
vcd2wlf
vcd2wlf is a utility that translates a VCD (Value Change Dump) file into a WLF file that
can be displayed in ModelSim using the vsim -view argument.
Syntax
vcd2wlf
[-splitio] [-splitio_in_ext <extension>] [-splitio_out_ext <extension>]
<vcd filename> <wlf filename>
Arguments
-splitio
Specifies that extended VCD port values are to be split into their corresponding input and
output components by creating 2 signals instead of just 1 in the resulting .wlf file.
Optional. By default the new input-component signal keeps the same name as the original
port name while the output-component name is the original name with "__o" appended
to it.
-splitio_in_ext <extension>
Specifies an extension to add to input-component signal names created by using -splitio.
Optional.
-splitio_out_ext <extension>
Specifies an extension to add to output-component signal names created by using
-splitio. Optional.
<vcd filename>
Specifies the name of the VCD file you want to translate into a WLF file. Required.
<wlf filename>
Specifies the name of the output WLF file. Required.

vcom CR-311
vcom
The vcom command compiles VHDL source code into a specified working library (or to
the work library by default).
This command may be invoked from within ModelSim or from the operating system
command prompt. This command may also be invoked during simulation.
Compiled libraries are major-version dependent. For example you cannot use a library
compiled with 5.7 in a simulation using 5.8 vsim. You would have to refresh the libraries
using the -refresh argument to vcom. This is not true for minor versions (e.g., 5.7a libraries
work in 5.7d).
Syntax
vcom
[-87] [-93] [-2002] [+acc[=<spec>][+<entity>[(architecture)]]]
[-bindAtCompile] [-bindAtLoad] [-check_synthesis] [-cover <stat>]
[-debugVA] [-error <msg_number>[,<msg_number>,...]] [-explicit]
[-f <filename>] [-force_refresh] [-help] [-ignoredefaultbinding]
[-ignorevitalerrors] [-just abcep] [-line <number>] [-lint] [-no1164]
[-noaccel <package_name>] [-nocasestaticerror] [-nocheck] [-nocoverage]
[-nodebug[=ports]] [-noindexcheck] [-nologo] [-nonstddriverinit]
[-noothersstaticerror] [-nopsl] [-norangecheck]
[-note <msg_number>[,<msg_number>, ...]] [-novital] [-novitalcheck]
[-nowarn <number>] [-O0 | -O1 | -O4 | -O5] [-pedanticerrors]
[-performdefaultbinding] [-pslfile <filename>] [-quiet] [-rangecheck]
[-refresh] [-s] [-skip abcep] [-source]
[-suppress <msg_number>[,<msg_number>,...]]
[-time] [-version] [-warning <msg_number>[,<msg_number>,...]]
[-work <library_name>] <filename>
Arguments
-87
Disables support for VHDL-1993 and 2002. Optional. Default is -2002. See additional
discussion in the examples. You can modify the VHDL93 variable in the modelsim.ini
file to set this permanently (see "Preference variables located in INI files" (UM-524)).
-93
Disables support for VHDL-1987 and 2002. Optional. Default is -2002. See additional
discussion in the examples. You can modify the VHDL93 variable in the modelsim.ini
file to set this permanently (see "Preference variables located in INI files" (UM-524)).
-2002
Specifies that the compiler is to support VHDL-2002. Optional. This is the default.
+acc[=<spec>][+<entity>[(architecture)]]
Enables access to design objects that would otherwise become unavailable due to
optimizations. Optional. Note that using this option may reduce optimizations.
<spec> currently has only one choice:
v–Enable access to variables, constants, and aliases in processes that would otherwise be
merged due to optimizations.

CR-312 vcom
<entity> and (<architecture>) specify the design unit(s) in which to allow the access. If
(<architecture>) is not specified, then all architectures of a given <entity> are enabled for
access.
-bindAtCompile
Forces ModelSim to perform default binding at compile time rather than at load time.
Optional. See "Default binding" (UM-79) for more information. You can change the
permanent default by editing the BindAtCompile (UM-527) variable in the modelsim.ini.
-bindAtLoad
Forces ModelSim to perform default binding at load time rather than at compile time.
Optional. Default. See "Default binding" (UM-79) for more information.
-check_synthesis
Turns on limited synthesis rule compliance checking. Specifically, it checks to see that
signals read by a process are in the sensitivity list. Optional. The checks understand only
combinational logic, not clocked logic. Edit the CheckSynthesis (UM-527) variable in the
modelsim.ini file to set a permanent default.
-cover <stat>
Enables various coverage statistics collection. Optional.
<stat> is one or more of the following characters:
b–Collect branch statistics.
c–Collect condition statistics.
e–Collect expression statistics.
s–Collect statement statistics. Default.
t–Collect toggle statistics. Cannot be used if ’x’ is specified.
x–Collect extended toggle statistics (see "Toggle coverage" (UM-343) for details).
Cannot be used if ’t’ is specified.
By default only statement coverage is enabled when you invoke vsim with the -coverage
option.
-debugVA
Prints a confirmation if a VITAL cell was optimized, or an explanation of why it was not,
during VITAL level-1 acceleration. Optional.
-explicit
Directs the compiler to resolve ambiguous function overloading by favoring the explicit
function definition over the implicit function definition. Optional. Strictly speaking, this
behavior does not match the VHDL standard. However, the majority of EDA tools
choose explicit operators over implicit operators. Using this switch makes ModelSim
compatible with common industry practice.

vcom CR-313
-f <filename>
Specifies a file with more command-line arguments. Optional. Allows complex
argument strings to be reused without retyping. Allows gzipped input files. Nesting of
-f options is allowed.
-force_refresh
Forces the refresh of a design unit. Optional. When the compiler refreshes a design unit,
it checks each dependency to ensure its source has not been changed and recompiled. If
a dependency has been changed and recompiled, the compiler will not refresh the
dependent design unit (unless you use -force_refresh). To avoid potential errors or
mismatches caused by the dependency recompilation, you should recompile the
dependent design unit’s source rather than use this switch.
-help
-ignoredefaultbinding
Instructs the compiler not to generate a default binding during compilation. Optional.
You must explicitly bind all components in the design to use this switch.
-ignorevitalerrors
Directs the compiler to ignore VITAL compliance errors. Optional. The compiler still
reports that VITAL errors exist, but it will not stop the compilation. You should exercise
caution in using this switch; as part of accelerating VITAL packages, we assume that
compliance checking has passed.
-just abcep
Directs the compiler to “just” include:
a - architectures
b - bodies
c - configurations
e - entities
p - packages
Any combination in any order can be used, but one choice is required if you use this
optional switch.
-line <number>
Starts the compiler on the specified line in the VHDL source file. Optional. By default,
the compiler starts at the beginning of the file.
-lint
Enables warning messages for two situations: 1) the result of the built-in concatenation
operator ("&") is the actual for a subprogram formal parameter of an unconstrained array
type; and 2) the entity to which a component instantiation is bound has a port that is not
on the component, and for which there is no error otherwise. Optional.
-no1164
Causes the source files to be compiled without taking advantage of the built-in version
of the IEEE std_logic_1164 package. Optional. This will typically result in longer
simulation times for VHDL programs that use variables and signals of type std_logic.

CR-314 vcom
-noaccel <package_name>
Turns off acceleration of the specified package in the source code using that package.
-nocasestaticerror
Suppresses case statement static warnings. Optional. VHDL standards require that case
statement alternative choices be static at compile time. However, some expressions
which are globally static are allowed. This switch prevents the compiler from warning on
such expressions. If the -pedanticerrors switch is specified, this switch is ignored.
-nocheck
Disables index and range checks. Optional. You can disable these individually using the
-noindexcheck and -norangecheck arguments, respectively.
-nocoverage
Disables collection of statement coverage statistics, which is on by default. Optional.
-nodebug[=ports]
Hides the internal data of the compiled design unit. Optional. The design unit’s source
code, internal structure, signals, processes, and variables will not display in ModelSim’s
windows. In addition, none of the hidden objects may be accessed through the Dataflow
window or with commands. This also means that you cannot set breakpoints or single
step within this code. Don’t compile with this switch until you’re done debugging.
Note that this is not a speed switch like the “nodebug” option on many other products.
The optional =ports switch hides the ports for the lower levels of your design; it should
only be used to compile the lower levels of the design. If you hide the ports of the top
level you will not be able to simulate the design.
Design units or modules compiled with -nodebug can only instantiate design units or
modules that are also compiled -nodebug.
-noindexcheck
Disables checking on indexing expressions to determine whether indices are within
declared array bounds. Optional.
-nologo
Disables display of the startup banner. Optional.
-nonstddriverinit
Forces ModelSim to match pre-5.7c behavior in initializing drivers in a particular case.
Optional. Prior to 5.7c, VHDL ports of mode out or inout could have incorrectly
initialized drivers if the port did not have an explicit initialization value and the actual
signal connected to the port had explicit initial values. Depending on a number of factors,
ModelSim could incorrectly use the actual signal's initial value when initializing lower
level drivers. Note that the argument does not cause all lower-level drivers to use the
actual signal's initial value. It does this only in the specific cases where older versions
used the actual signal's initial value.
-noothersstaticerror
Disables warnings that result from array aggregates with multiple choices having
"others" clauses that are not locally static. Optional. If the -pedanticerrors switch is
specified, this switch is ignored.

vcom CR-315
-nopsl
Instructs the compiler to ignore embedded PSL assertions. By default vcom parses any
PSL assertion statements it finds in the specified files. See "Compiling and simulating
assertions" (UM-375) for more information.
-norangecheck
Disables run time range checking. In some designs, this results in a 2X speed increase.
Range checking is enabled by default or, once disabled, can be enabled using
-rangecheck. See "Range and index checking" (UM-74) for additional information.
-note <msg_number>[,<msg_number>, ...]
-novital
Causes vcom to use VHDL code for VITAL procedures rather than the accelerated and
optimized timing and primitive packages built into the simulator kernel. Optional.
Allows breakpoints to be set in the VITAL behavior process and permits single stepping
through the VITAL procedures to debug your model. Also all of the VITAL data can be
viewed in the Locals or Objects windows.
-novitalcheck
Disables Vital level 1 checks and also Vital level 0 checks defined in section 4 of the
Vital-95 Spec (IEEE Std 1076.4-1995). Optional.
-nowarn <number>
Selectively disables a category of warning message. Optional. Multiple -nowarn
switches are allowed. Warnings may be disabled for all compiles via the Main window
Compile > Compile Options menu command or the modelsim.ini file (see the "[vcom]
VHDL compiler control variables" (UM-527)).
The warning message categories are:
1 = unbound component
2 = process without a wait statement
3 = null range
4 = no space in time literal
5 = multiple drivers on unresolved signal
6 = VITAL compliance checks
7 = VITAL optimization messages
8 = lint checks
9 = signal value used in expression evaluated at elaboration
10 = VHDL-1993 constructs in VHDL-1987 code
11 = PSL checks
-O0 | -O1 | -O4 | -O5
Lower the optimization to a minimum with -O0 (capital oh zero). Optional. Use this to
work around bugs, increase your debugging visibility on a specific cell, or when you
want to place breakpoints on source lines that have been optimized out.
Enable PE-level optimization with -O1. Optional. Note that changing from the default
-O4 to -O1 may cause event order differences in your simulation.

CR-316 vcom
Enable standard SE optimizations with -O4. Default. The main differences between -O4
and -O1 are that ModelSim attempts to improve memory management for vectors and
accelerate VITAL Level 1 modules with -O4.
Enable maximum optimization with -O5. Optional. We recommend use of this switch
with large sequential blocks only; other uses may significantly increase compile times.
-O5 attempts to optimize loops and prevents variable assignments in situations where a
variable is assigned but is not actually used. Using the +acc argument to vcom will cancel
this latter optimization.
-pedanticerrors
Forces ModelSim to error (rather than warn) on three conditions: 1) when a choice in a
case statement is not a locally static expression; 2) when an array aggregate with multiple
choices doesn’t have a locally static "others" choice; 3) when a generate statement
without a BEGIN keyword exists between the declarative objects and the concurrent
statements. Optional. This argument overrides -nocasestaticerror and
-noothersstaticerror (see above).
-performdefaultbinding
Enables default binding when it has been disabled via the
RequireConfigForAllDefaultBinding option in the modelsim.ini file. Optional.
-pslfile <filename>
Identifies an external PSL assertion file to compile along with the VHDL source files.
See "Compiling and simulating assertions" (UM-375) for more information.
-quiet
Disables ’Loading’ messages. Optional.
-rangecheck
Enables run time range checking. Default. Range checking can be disabled using the
-norangecheck argument. See "Range and index checking" (UM-74) for additional
information.
-refresh
Regenerates a library image. Optional. By default, the work library is updated; use -work
<library> to update a different library. See vcom "Examples" (CR-317) for more
information.
-s
Instructs the compiler not to load the standard package. Optional. This argument should
only be used if you are compiling the standard package itself.
-skip abcep
Directs the compiler to skip all:
a - architectures
b - bodies
c - configurations
e - entities
p - packages
Any combination in any order can be used, but one choice is required if you use this
optional switch.

vcom CR-317
-source
Displays the associated line of source code before each error message that is generated
during compilation. Optional. By default, only the error message is displayed.
information.
-time
Reports the "wall clock time" vcom takes to compile the design. Optional. Note that if
many processes are running on the same system, wall clock time may differ greatly from
the actual "cpu time" spent on vcom.
-version
Returns the version of the compiler as used by the licensing tools, such as "Model
Technology ModelSim SE vcom 5.5 Compiler 2000.01 Jan 29 2000".
library work. Optional; by default, the compiled design units are added to the work
file.
<filename>
Specifies the name of a file containing the VHDL source to be compiled. One filename
is required; multiple filenames can be entered separated by spaces or wildcards may be
used (e.g., *.vhd).
If you don’t specify a filename, and you are using the GUI, a dialog box pops up allowing
you to select the options and enter a filename.
Examples
vcom example.vhd
Compiles the VHDL source code contained in the file example.vhd.
vcom -87 o_units1.vhd o_units2.vhd
vcom -93 n_unit91.vhd n_unit92.vhd
ModelSim supports designs that use elements conforming to the 1987, 1993, and 2002
standards. Compile the design units separately using the appropriate switches.
vcom -nodebug example.vhd
Hides the internal data of example.vhd. Models compiled with -nodebug cannot use any
of the ModelSim debugging features; any subsequent user will not be able to see into the
model.
vcom -nodebug=ports level3.vhd level2.vhd
vcom -nodebug top.vhd
The first line compiles and hides the internal data, plus the ports, of the lower-level
design units, level3.vhd and level2.vhd. The second line compiles the top-level unit,

CR-318 vcom
top.vhd, without hiding the ports. It is important to compile the top level without =ports
because top-level ports must be visible for simulation.
vcom -noaccel numeric_std example.vhd
When compiling source that uses the numeric_std package, this command turns off
acceleration of the numeric_std package, located in the ieee library.
vcom -explicit example.vhd
Although it is not obvious, the = operator is overloaded in the std_logic_1164 package.
All enumeration data types in VHDL get an “implicit” definition for the = operator. So
while there is no explicit = operator, there is an implicit one. This implicit declaration can
be hidden by an explicit declaration of = in the same package (LRM Section 10.3).
However, if another version of the = operator is declared in a different package than that
containing the enumeration declaration, and both operators become visible through use
clauses, neither can be used without explicit naming.
ARITHMETIC.”=”(left, right)
To eliminate that inconvenience, the VCOM command has the -explicit option that
allows the explicit = operator to hide the implicit one. Allowing the explicit declaration
to hide the implicit declaration is what most VHDL users expect.
vcom -work mylib -refresh
The -work option specifies mylib as the library to regenerate. -refresh rebuilds the
library image without using source code, allowing models delivered as compiled libraries
without source code to be rebuilt for a specific release of ModelSim (4.6 and later only).

vcover convert CR-319
vcover convert
The vcover convert command converts a code coverage file created in ModelSim 5.7 to a
ModelSim 5.8 format. You can also use the command with the -strip or -install arguments
to create a new data file with different levels of hierarchy. The command can be invoked
within the ModelSim GUI or at the command line.
Syntax
vcover convert
[-57] [-install <path>] [-log <filename>] [-strip <n>] <outfile> <file>
Arguments
-57
Converts the specified file to a 5.8 format. Optional.
-install <path>
Adds <path> as additional hierarchy on the front end of instance and object names in the
input file. Optional. This argument allows you to create a new coverage file with a
different level of hierarchy.
-log <filename>
Specifies the file for outputting progress messages. Optional. By default these messages
are output to vcover.log.
-strip <n>
Removes <n> levels of hierarchy from instance and object names in the data files.
Optional. This argument allows you to create a new coverage file with a different level
of hierarchy.
<outfile>
Specifies the name of the new file you want to output. Required.
<file>
Specifies the file you want to convert. Required.
See also
vcover merge command (CR-320), vcover stats command (CR-325), Chapter 13 -
Measuring code coverage

CR-320 vcover merge
vcover merge
The vcover merge command merges multiple code or functional coverage data files that
were created with the coverage save command (CR-135) or the fcover save command (CR-
175), respectively. The command adjusts its functionality to the type of coverage files
(functional coverage or code coverage) given on its command line. The command can be
invoked within the ModelSim GUI or at the system prompt.
Important: Code coverage databases and functional coverage databases are not
interoperable. It is illegal to mix code coverage and functional coverage files in the same
invocation of vcover merge.
Syntax
vcover merge
[-and] [-append] [-inputs <pathname>] [-install <path>] [-log <filename>]
[-strip <n>] [-verbose] <outfile> <file1> <file2> <filen>...
Arguments
-and
Excludes statements in the output file only if they are excluded in all input files. Optional.
By default a statement is excluded in the output merge file if the statement is excluded in
any of the input files. Not a valid option when merging functional coverage databases.
-append
Specifies that progress messages are to be appended to the current log file. Optional. By
default a new log file is created each time you invoke the command. Not a valid option
when merging functional coverage databases.
-inputs <pathname>
Specifies a text file containing input filenames that you want to merge. Optional.
-install <path>
data files. Optional. This argument allows you to merge coverage results from
simulations that have different hierarchies.
-log <filename>
-strip <n>
-verbose
Enables summary code coverage statistics to be computed and directed to the log file
each time a file is merged into the base. The statistics are instance-based. Optional. Not
a valid option when merging functional coverage databases.
<outfile>
Specifies the name of the file that will contain the merged output. Required.

vcover merge CR-321
<file1> <file2> <filen>...

Specifies the file(s) you want to merge. Required. Multiple pathnames and wildcards are
allowed.
Example
vcover merge myresult myfile1 myfile2
Merges coverage statistics for myfile1 and myfile2 and writes them to myresult.
vcover merge myresult2 /dut/*.cov
Uses wildcards to merge all files with a .cov extension in a particular directory. You must
enter this command at a UNIX shell prompt. This example does not work currently on
Windows platforms.
eval vcover merge summary [glob *.cov]
Allows the above vcover merge example using wildcards to work on all platforms.
"glob" returns a list of the fields whose names end in .cov.
See also
vcover convert command (CR-319), vcover stats command (CR-325), fcover save
command (CR-175), Chapter 13 - Measuring code coverage, Chapter 15 - Functional
coverage with PSL and ModelSim

CR-322 vcover report
vcover report
The vcover report command produces textual output of coverage statistics from a
previously saved code or functional coverage run. This allows you to produce reports in an
"offline" manner (i.e., without having to load a simulation.) You can choose from a number
of report output options using the arguments listed below.
Syntax
vcover report
[-above <percent> | -below <percent>] [-aggregated] [-append] [-comment]
[-details] [-lines | -totals] [-instance <pathname> [-recursive]]
[-noaggregated] [-nocomment] [-nodetails] [-output <pathname>] [-package
<pkgname>] [-select bces[t|x]]
[-toggles [-all]] [-xml] <file>
Arguments
-above <percent>
output. Optional.
-below <percent>
output. Optional.
-aggregated
Includes aggregated statistics in the output. Not a valid option when reporting on a code
coverage database. Optional. Default.
-all
When used with -toggles, creates a report that lists both toggled and untoggled signals.
Not a valid option when reporting on a functional coverage database. Optional.
-append
Appends the report data to the named output file. Optional.
-comment
Specifies that comments should be included with the report. Comments are excluded by
default. Not a valid option when reporting on a code coverage database. Optional.
-details
Includes details associated with each cover directive (e.g., count) in the output. Not a
valid option when reporting on a code coverage database. Optional. Default.
-instance <pathname>
Writes out the source file summary coverage data for the selected instance. Optional.
-lines
Writes out the source file summary data and after each file it writes out the details for
each executable line in the file. Not a valid option when reporting on a functional
coverage database. Optional.
-noaggregated
Excludes aggregated statistics from the output. The statistics are included by default. Not
a valid option when reporting on a code coverage database. Optional.

vcover report CR-323
-nocomment
Excludes comments from the report. Not a valid option when reporting on a code
coverage database. Optional. Default.
-nodetails
Excludes details associated with each cover directive (e.g., count) from the output.
Details are included by default. Not a valid option when reporting on a code coverage
database. Optional.
-package <pkgname>
Creates a report on the specified VHDL package body. Not a valid option when reporting
on a functional coverage database. Optional.
-recursive
Reports on the instance specified with -instance and every included instance, recursively.
Can also be used with -lines and -totals. Optional.
-output <pathname>
Specifies the name of the file that will contain the report. Optional. The report will print
to stdout if you do not specify an output file.
-select bces[t|x]
Specifies which code coverage statistics to include in the report. Not a valid option when
reporting on a functional coverage database. Optional. By default the report includes
statistics for all categories you enabled at compile time.
The characters are as follows:
b–Include branch statistics.
c–Include condition statistics.
e–Include expression statistics.
s–Include statement statistics.
t–Include toggle statistics.
x–Include extended toggle statistics.
Note that "t" and "x" are mutually exclusive.
-toggles
Creates a report of untoggled signals. If you also specify -all, all signals (both toggled
and untoggled) are listed in the report. Not a valid option when reporting on a functional
coverage database. Optional.
-totals
Writes out a top-level summary of the number of files, statements, branches, hits, and
signal toggles for both file-based and instance-based views of the current analysis. Useful
for tracking changes. Not a valid option when reporting on a functional coverage
database. Optional.
-xml
Outputs report in XML format. Optional. See "Reporting coverage data" (UM-350) for
more information.
<file>
Specifies the previously saved code or functional coverage file on which you want to
report. Required.

CR-324 vcover report
Examples
vcover report -totals -output myreport.cov
Writes a top-level summary of the number of instances, statements, branches, hits, and
signal toggles to myreport.cov.
vcover report -lines -select bcs save.cov
Writes detailed branch, condition, and statement statistics, without associated source
code, to save.cov.
vcover report save.cov
Writes a summary of code coverage for all instances to save.cov.
vcover report -lines myreport.cov
Writes code coverage details of all instances in the design to myreport.cov. The -lines
option reports coverage statistics for each statement and branch. Branch coverage
statistics will following statement statistics and will be presented in four columns: line,
column, true branch count, false branch count.
vcover report -lines -instance /top/p save.cov
Writes code coverage details of one specific instance to save.cov.
vcover report -lines -below 90 -file myreport.cov
Writes a summary of coverage by source file for coverage less than or equal to 90%.
vcover report -zeros -output myzerocov.txt
Writes a list of statements with zero coverage to myzerocov.txt.
See also
Chapter 13 - Measuring code coverage, coverage save (CR-135), fcover save (CR-175),
coverage report command (CR-132), fcover report command (CR-173)

vcover stats CR-325
vcover stats
The vcover stats command computes and prints to stdout summary statistics for previously
saved code or functional coverage databases. It can be invoked within the ModelSim GUI
or at the command line.
For functional coverage databases, vcover stats creates coverage statistics output that is
roughly equivalent to the output from this command:
fcover report -config -details -aggregated -r *
The format and filtering of the report output produced by vcover stats is not as flexible as
that of the fcover report command (CR-173).
Syntax
vcover stats
[-and] [-append] [-incremental] [-inputs <pathname>] [-install <path>]
[-log <filename>] [-strip <n>] [-verbose] <file1> [<file2> <filen>...]
Arguments
-and
Excludes statements in the output merge file only if they are excluded in all input files.
Optional. By default statements are excluded in the output file if the statement is
excluded in any of the input files. Not a valid option when merging functional coverage
databases.
-append
Specifies that progress messages are to be appended to the current log file. Optional. By
default a new log file is created each time you invoke the command. Not a valid option
when merging functional coverage databases.
-inputs <pathname>
Specifies a text file containing input filenames for which you want to produce statistics.
Optional.
-incremental
Prints statistics for the specified files as if the files were merged one after the other in the
listed order. Optional. For example, using this argument will cause vcover stats to print
the statistics for <file1>, then any incremental coverage after merging <file2>, and then
any incremental coverage after merging <file3> into the merge of <file1> and <file2>,
and so forth. At the end it prints the total statistics for the full merge. The statistics are
written to both stdout and vcover.log. Not a valid option when merging functional
coverage databases.
-install <path>
data files. Optional. This argument allows you to merge coverage results from
simulations that have different hierarchies.
-log <filename>

CR-326 vcover stats
-strip <n>
-verbose
Enables summary code coverage statistics to be computed and directed to the log file
each time a file is merged into the base. The statistics are instance-based. Not a valid
option when merging functional coverage databases.
<file1> [<file2> <filen>...]
Specifies the file(s) for which you want summary statistics. Required. Multiple
pathnames and wildcards are allowed.
See also
coverage save command (CR-135), fcover save command (CR-175), vcover merge
command (CR-320), fcover report command (CR-173), Chapter 13 - Measuring code
coverage, Chapter 15 - Functional coverage with PSL and ModelSim

vdel CR-327
vdel
The vdel command deletes a design unit from a specified library.
Syntax
vdel
[-help] [-lib <library_name>] [-verbose]
[-all | <design_unit> [<arch_name>] | -allsystemc]
Arguments
-all
Deletes an entire library. Optional. BE CAREFUL! Libraries cannot be recovered once
deleted, and you are not prompted for confirmation.
-allsystemc
Deletes all SystemC modules in a design from the working directory. Optional.
<arch_name>
Specifies the name of an architecture to be deleted. Optional. If omitted, all of the
architectures for the specified entity are deleted. Invalid for a configuration or a package.
<design_unit>
Specifies the entity, package, configuration, or module to be deleted. Required unless -all
is used. This option is not supported for SystemC modules.
-help
-lib <library_name>
Specifies the logical name or pathname of the library that holds the design unit to be
deleted. Optional. By default, the design unit is deleted from the work library.
-verbose
Displays progress messages. Optional.
Examples
vdel -all
Deletes the work library.
vdel -lib synopsys -all
Deletes the synopsys library.
vdel xor
Deletes the entity named xor and all its architectures from the work library.
vdel xor behavior
Deletes the architecture named behavior of the entity xor from the work library.
vdel base
Deletes the package named base from the work library.

CR-328 vdir
vdir
The vdir command lists the contents of a design library.
This command can also be used to check compatibility of a vendor library. If vdir cannot
read a vendor-supplied library, the library may not be ModelSim compatible. SystemC
modules are listed with this command.
Syntax
vdir
[-help] [-l] [-r] [-all] | [-lib <library_name>] [<design_unit>]
Arguments
-help
-l
Prints the version of vcom, vlog, or sccom with which each design unit was compiled.
Also prints the object-code version number that indicates which versions of vcom/vlog/
sccom and ModelSim are compatible. This example was printed by vdir -l for the counter
module in the work library:
# Library Vendor : Model Technology
# MODULE ram_tb
# Verilog Version: DPV:j32Jc=Q?7<3><C;OK0
# Version number: CRW2<UhheaW;LIL2_B5o31
# Source modified time: 1064511064
# Source file: ram_tb.v
# Opcode format: 5.8 Beta 2; VLOG SE Object version 172
# Optimized Verilog design root: 1
# Language standard: 1
# Source directory: C:\modelsim_examples\memory\vlog_memory
-r
Prints architecture information for each entity in the output.
-all
Lists the contents of all libraries listed in the [Library] section of the active modelsim.ini
file. Optional. See "[Library] library path variables" (UM-525) for more information.
-lib <library_name>
Specifies the logical name or the pathname of the library to be listed. Optional. By
default, the contents of the work library are listed.
<design_unit>
Indicates the design unit to search for within the specified library. If the design unit is a
VHDL entity, its architectures are listed. Optional. By default all entities, configurations,
modules, packages, and optimized design units in the specified library are listed.
Examples
vdir -lib design my_asic
Lists the architectures associated with the entity named my_asic that reside in the HDL
design library called design.

verror CR-329
verror
The verror command prints a detailed description about a message number. It may also
point to additional documentation related to the error.
Syntax
verror
[-all [-kind <tool>]] [-fmt] [-ranges] <msgNum>...
Arguments
-all [-kind <tool>]
Prints all error messages. Optional. If you specify -kind <tool>, it prints just those error
messages associated with the specified tool.
-fmt
Prints the format string that is used in the actual error message. Optional.
-ranges
Prints the numeric ranges of error message numbers by tool. Optional.
<msgNum>
Specifies the message number of a ModelSim message. Required unless you specify the
-all argument. The message number can be obtained from messages that have the format:
** <Level>: ([<Tool>-[<Group>-]]<MsgNum>) <FormattedMsg>
Example
Say you see the following message in the transcript:
** Error (vsim-3061) foo.v(22): Too many Verilog port connections.
You would type:

verror 3061
and receive the following output:

Message # 3061:
Too many Verilog ports were specified in a mixed VHDL/Verilog instantiation.

Verify that the correct VHDL/Verilog connection is being made and that the
number of ports matches.
[DOC: ModelSim User's Manual - Mixed VHDL and Verilog Designs Chapter]

CR-330 vgencomp
vgencomp
Once a Verilog module is compiled into a library, you can use the vgencomp command to
write its equivalent VHDL component declaration to standard output. Optional switches
allow you to generate bit or vl_logic port types; std_logic port types are generated by
default.
Syntax
vgencomp
[-help] [-lib <library_name>] [-b] [-s] [-v] <module_name>
Arguments
-help
-lib <library_name>
Specifies the pathname of the working library. If not specified, the default library work
is used. Optional.
-b
Causes vgencomp to generate bit port types. Optional.
-s
Used for the explicit declaration of default std_logic port types. Optional.
-v
Causes vgencomp to generate vl_logic port types. Optional.
<module_name>
Specifies the name of the Verilog module to be accessed. Required.
Examples
This example uses a Verilog module that is compiled into the work library. The module
begins as Verilog source code:
module top(i1, o1, o2, io1);
parameter width = 8;
parameter delay = 4.5;
parameter filename = "file.in";
input i1;
output [7:0] o1;
output [4:7] o2;
inout [width-1:0] io1;
endmodule
After compiling, vgencomp is invoked on the compiled module:

vgencomp top
and writes the following to stdout:

component top
generic(

vgencomp CR-331
width : integer := 8;
delay : real := 4.500000;
filename : string := "file.in"
);
port(
i1 : in std_logic;
o1 : out std_logic_vector(7 downto 0);
o2 : out std_logic_vector(4 to 7);
io1 : inout std_logic_vector
);
end component;

CR-332 view
view
The view command displays a stand-alone window or Main window pane and shifts focus
to that window or pane. If multiple instances of a stand-alone window exist, view will
change the default window of that type to the specified window. Using the -new option,
view will create an additional instance of the specified stand-alone window type and set it
to be the default window for that type.
Names for windows are generated as follows:
• The first window name (automatically created without using -new) has the same name as
the window type.
• Additional window names created by -new append an integer to the window type, starting
with 1.
To remove a window, use the noview command (CR-212).
The view command returns the name(s) of the viewed window(s).
Syntax
view
[*] [-height <n>] [-icon] [-new] [-title {New Window Title}] [-undock | -
dock] [-width <n>] [-x <n>] [-y <n>] <window_type>...
Arguments
*
Specifies that all windows be opened. Optional.
-height <n>
Specifies the window height in pixels. Valid only for stand-alone windows, not panes in
the Main window. Optional.
-icon
Toggles the view between window and icon. Valid only for stand-alone windows, not
panes in the Main window. Optional.
-new
Creates a new instance of the window type specified with the <window_type> argument.
Valid only for stand-alone windows, not panes in the Main window. Optional. New
window names are created by appending an integer to the window type, starting with 1,
then incrementing the integer.
-title {New Window Title}
Specifies the window title of the designated window. Curly braces are only needed for
titles that include spaces. Double quotes can be used in place of braces, for example
"New Window Title". If the new window title does not include spaces, no braces or
quotes are needed. For example: -title new_wave wave assigns the title new_wave to the
Wave window.
-undock
Opens the specified pane as a standalone window, undocked from the Main window.
Optional.

view CR-333
-dock
Docks the specified standalone window into the Main window.
-width <n>
Specifies the window width in pixels. Valid only for stand-alone windows, not panes in
<window_type>...
Specifies the window/pane type to view. Required. You do not need to type the full type
(see examples below); implicit wildcards are accepted; multiple window types may be
used. Available window/pane types are:
assertions, dataflow, fcovers, list, locals, mdiwave, memory, objects, process, profile,
profile_details, signals, source, structure, variables, watch, wave, and workspace
Also creates a new instance of the specified stand-alone window type when used with the
-new option. You may also specify the window(s) to view when multiple instances of
that window type exist (e.g., wave2). This works only with ModelSim-generated window
names, not with window titles specified with the -title argument.
-x <n>
Specifies the window upper-left-hand x-coordinate in pixels. Valid only for stand-alone
windows, not panes in the Main window. Optional.
-y <n>
Specifies the window upper-left-hand y-coordinate in pixels. Valid only for stand-alone
windows, not panes in the Main window. Optional.
Examples
view -undock wave.
Undocks the Wave pane from the Main window and makes it a standalone window.
view w
Displays the Watch and Wave panes.
view ob pr
Displays the Objects and Active Process panes.
view -title {My Wave Window} wave
Opens a new Wave window with My Wave Window as its title.
view wave
view -new wave
The first command creates a window named ’wave’. The second command creates a
window named ‘wave1’. Its full Tk path is ‘.wave1’. Wave1 is now the default Wave
window. Any add wave command (CR-52) would add objects to wave1.
view wave
Changes the default Wave window back to ‘wave’.
add wave -win .wave1 mysig
Will override the default Wave window and add mysig to wave1.
See also
noview (CR-212)

CR-334 virtual count
virtual count
The virtual count command counts the number of currently defined virtuals that were not
read in using a macro file.
Syntax
virtual count
[-kind <kind>] [-unsaved]
Arguments
-kind <kind>
Specifies a subset of virtuals to look at. Optional. <kind> can be any of the following:
signals, functions, designs, implicits, and explicits. Unique abbreviations are accepted.
-unsaved
Specifies that the count include only those virtuals that have not been saved to a macro
file. Optional.
See also
virtual define (CR-335), virtual save (CR-349), virtual show (CR-350), "Virtual Objects
(User-defined buses, and more)" (UM-233)

virtual define CR-335
virtual define
The virtual define command prints to the Transcript pane the definition of the virtual
signal or function in the form of a command that can be used to re-create the object.
Syntax
virtual define
[-kind <kind>] <pathname>
Arguments
-kind <kind>
<pathname>
Specifies the path to the virtual(s) for which you want definitions. Required. Wildcards
can be used.
Examples
virtual define -kind explicits *
Shows the definitions of all the virtuals you have explicitly created.
See also
virtual describe (CR-337), virtual show (CR-350), "Virtual Objects (User-defined buses,
and more)" (UM-233)

CR-336 virtual delete
virtual delete
The virtual delete command removes the matching virtuals.
Syntax
virtual delete
Arguments
-kind <kind>
<pathname>
Specifies the path to the virtual(s) you want to delete. Required. Wildcards can be used.
Examples
virtual delete -kind explicits *
Deletes all of the virtuals you have explicitly created.
See also
virtual signal (CR-351), virtual function (CR-339), "Virtual Objects (User-defined buses,
and more)" (UM-233)

virtual describe CR-337
virtual describe
The virtual describe command prints to the Transcript pane a complete description of the
data type of one or more virtual signals. Similar to the existing describe command.
Syntax
virtual describe
Arguments
-kind <kind>
<pathname>
Specifies the path to the virtual(s) for which you want descriptions. Required. Wildcards
can be used.
Examples
virtual describe -kind explicits *
Describes the data type of all virtuals you have explicitly created.
See also
virtual define (CR-335), virtual show (CR-350), "Virtual Objects (User-defined buses, and
more)" (UM-233)

CR-338 virtual expand
virtual expand
The virtual expand command produces a list of all the non-virtual objects contained in the
specified virtual signal(s). This can be used to create a list of arguments for a command that
does not accept or understand virtual signals.
Syntax
virtual expand
[-base] <pathname>
Arguments
-base
Causes the root signal parent to be output in place of a subelement. Optional. For
example:
vcd add [virtual expand -base myVirtualSignal]
the resulting command after substitution would be:

vcd add signala signalb signalc
<pathname>
Specifies the path to the signals and virtual signals to expand. Required. Wildcards can
be used. Any number of paths can be specified.
Examples
vcd add [virtual expand myVirtualSignal]
Adds the elements of a virtual signal to the VCD file.
In the Tcl language, the square brackets specify that the enclosed command should be
executed first ("virtual expand ..."), then the result substituted into the surrounding
command. So if myVirtualSignal is a concatenation of signala, signalb.rec1 and signalc(5
downto 3), the resulting command after substitution would be:
vcd add signala signalb.rec1 {signalc(5 downto 3)}
The slice of signalc is quoted in curly braces, because it contains spaces.
See also
virtual signal (CR-351), "Virtual Objects (User-defined buses, and more)" (UM-233)

virtual function CR-339
virtual function
The virtual function command creates a new signal, known only by the GUI (not the
kernel), that consists of logical operations on existing signals and simulation time, as
described in <expressionString>. It cannot handle bit selects and slices of Verilog
registers. Please see "Syntax and conventions" (CR-9) for more details on syntax.
If the virtual function references more than a single scalar signal, it will display as an
expandable object in the Wave and Objects windows. The children correspond to the inputs
of the virtual function. This allows the function to be "expanded" in the Wave window to
see the values of each of the input waveforms, which could be useful when using virtual
functions to compare two signal values.
Virtual functions can also be used to gate the List window display.
Syntax
virtual function
[-env <path>] [-install <path>] [-delay <time>] {<expressionString>}
<name>
Arguments
Arguments for virtual function are the same as those for virtual signal, except for the
contents of the expression string.
-env <path>
Specifies a hierarchical context for the signal names in <expressionString> so they don't
all have to be full paths. Optional.
-install <path>
Causes the newly-created signal to become a child of the specified region. If -install is
not specified, the newly-created signal becomes a child of the nearest common ancestor
of all objects appearing in <expressionString>. If the expression references more than
one WLF file (dataset), the virtual signal will automatically be placed in region
virtuals:/Functions. Optional.
-delay <time>
Specifies a value by which the virtual function will be delayed. Optional. You can use
negative values to look forward in time. If units are specified, the <time> option must be
enclosed in curly braces. See the examples below for more details.
{<expressionString>}
A text string expression in the MTI GUI expression format. Required. See
"GUI_expression_format" (CR-22) for more information.
<name>
The name you define for the virtual signal. Required. Case is ignored unless installed in
a Verilog region. Use alpha, numeric, and underscore characters only, unless you are
using VHDL extended identifier notation. If using VHDL extended identifier notation,
<name> needs to be quoted with double quotes or with curly braces.

CR-340 virtual function
Examples
virtual function { not /chip/section1/clk } clk_n
Creates a signal /chip/section1/clk_n that is the inverse of /chip/section1/clk.
virtual function -install /chip { (std_logic_vector) chip.vlog.rega }
rega_slv
Creates a std_logic_vector equivalent of a Verilog register rega and installs it as /chip/
rega_slv.
virtual function { /chip/addr[11:0] == 0xfab } addr_eq_fab
Creates a boolean signal /chip/addr_eq_fab that is true when /chip/addr[11:0] is equal
to hex "fab", and false otherwise. It is acceptable to mix VHDL signal path notation with
Verilog part-select notation.
virtual function { gate:/chip/siga XOR rtl:/chip/siga } siga_diff
Creates a signal that is high only during times when signal /chip/siga of the gate-level
version of the design does not match /chip/siga of the rtl version of the design. Because
there is no common design region for the inputs to the expression, siga_diff is installed
in region virtuals:/Functions. The virtual function siga_diff can be added to the Wave
window, and when expanded will show the two original signals that are being compared.
virtual function -delay {10 ns} {/top/signalA AND /top/signalB} myDelayAandB
Creates a virtual signal consisting of the logical "AND" function of /top/signalA with
/top/signalB, and delays it by 10 ns.
virtual function { | (gate:/chip/outbus XOR rtl:/chip/outbus) } outbus_diff
Creates a one-bit signal outbus_diff which is non-zero during times when any bit of /chip/
outbus in the gate-level version doesn’t match the corresponding bit in the rtl version.
This expression uses the "OR-reduction" operator, which takes the logical OR of all the
bits of the vector argument.

virtual function CR-341
Commands fully compatible with virtual functions

add list (CR-48) add log /log (CR-191) add wave (CR-52)
checkpoint (CR-93) and restore (CR- delete (CR-146) describe (CR-147) ("virtual describe" is
248) a little faster)
down (CR-152) / up (CR-290) examine (CR-162) find (CR-176)

restart (CR-246) left (CR-189) / right (CR-250) search (CR-260)
searchlog (CR-262) show (CR-267)
Commands not currently compatible with virtual functions

check contention add (CR-84) check contention config (CR-86) check contention off (CR-87)
check float add (CR-88) check float config (CR-89) check float off (CR-90)
check stable on (CR-92) check stable off (CR-91) drivers (CR-154)
force (CR-180) noforce (CR-208) power add (CR-220)
power report (CR-221) power reset (CR-222) toggle add (CR-279)
toggle reset (CR-284) toggle report (CR-283) vcd add (CR-292)
when (CR-407)
See also
virtual count (CR-334) virtual define (CR-335) virtual delete (CR-336)
virtual describe (CR-337) virtual expand (CR-338) virtual hide (CR-342)
virtual log (CR-343) virtual nohide (CR-345) virtual nolog (CR-346)
virtual region (CR-348) virtual save (CR-349) virtual show (CR-350)
virtual signal (CR-351) virtual type (CR-354) Virtual Objects (User-defined

buses, and more) (UM-233)

CR-342 virtual hide
virtual hide
The virtual hide command causes the specified real or virtual signals to not be displayed
in the Objects window. This is used when you want to replace an expanded bus with a user-
defined bus. You make the signals reappear using the virtual nohide command.
Syntax
virtual hide
[-kind <kind>]|[-region <path>] <pattern>
Arguments
-kind <kind>
-region <path>
Used in place of -kind to specify a region of design space in which to look for the signal
names. Optional.
<pattern>
Indicates which signal names or wildcard patterns should be used in finding the signals
to hide. Required. Any number of names or wildcard patterns may be used.
See also
virtual nohide (CR-345), "Virtual Objects (User-defined buses, and more)" (UM-233)

virtual log CR-343
virtual log
The virtual log command causes the simulation-mode dependent signals of the specified
virtual signals to be logged by the kernel. If wildcard patterns are used, it will also log any
normal signals found, unless the -only option is used. You unlog the signals using the
virtual nolog command.
Syntax
virtual log
[-kind <kind>]|[-region <path>] [-recursive] [-only] [-in] [-out] [-inout]
[-internal] [-ports] <pattern>
Arguments
-kind <kind>
-region <path>
Used in place of -kind to specify a region of design space in which to look for signals to
log. Optional.
-recursive
-only
Can be used with a wildcard to specify that only virtual signals (as opposed to all signals)
found by the wildcard should be logged. Optional.
-in
Specifies that the kernel log data for ports of mode IN whose names match the
-out
Specifies that the kernel log data for ports of mode OUT whose names match the
-inout
Specifies that the kernel log data for ports of mode INOUT whose names match the
-internal
Specifies that the kernel log data for internal (non-port) objects whose names match the
-ports
Specifies that the kernel log data for all ports. Optional.
<pattern>
to log. Required. Any number of names or wildcard patterns may be used.

CR-344 virtual log
See also
virtual nolog (CR-346), "Virtual Objects (User-defined buses, and more)" (UM-233)

virtual nohide CR-345
virtual nohide
The virtual nohide command reverses the effect of a virtual hide command, causing the
specified real or virtual signals to reappear the Objects window.
Syntax
virtual nohide
[-kind <kind>]|[-region <path>] <pattern>
Arguments
-kind <kind>
-region <path>
Used in place of -kind to specify a region of design space in which to look for the signal
names. Optional.
<pattern>
to expose. Required. Any number of names or wildcard patterns may be used.
See also
virtual hide (CR-342), "Virtual Objects (User-defined buses, and more)" (UM-233)

CR-346 virtual nolog
virtual nolog
The virtual nolog command reverses the effect of a virtual log command. It causes the
simulation-dependent signals of the specified virtual signals to be excluded ("unlogged")
by the kernel. If wildcard patterns are used, it will also unlog any normal signals found,
unless the -only option is used.
Syntax
virtual nolog
[-kind <kind>]|[-region <path>] [-recursive] [-only] [-in] [-out] [-inout]
[-internal] [-ports] <pattern>
Arguments
-kind <kind>
-region <path>
Used in place of -kind to specify a region of design space in which to look for signals to
unlog. Optional.
-recursive
-only
Can be used with a wildcard to specify that only virtual signals (as opposed to all signals)
found by the wildcard should be unlogged. Optional.
-in
Specifies that the kernel exclude data for ports of mode IN whose names match the
-out
Specifies that the kernel exclude data for ports of mode OUT whose names match the
-inout
Specifies that the kernel exclude data for ports of mode INOUT whose names match the
-internal
Specifies that the kernel exclude data for internal (non-port) objects whose names match
-ports
Specifies that the kernel exclude data for all ports. Optional.
<pattern>
Indicates which signal names or wildcard pattern should be used in finding the signals to
unlog. Required. Any number of names or wildcard patterns may be used.

virtual nolog CR-347
See also
virtual log (CR-343), "Virtual Objects (User-defined buses, and more)" (UM-233)

CR-348 virtual region
virtual region
The virtual region command creates a new user-defined design hierarchy region.
Syntax
virtual region
<parentPath> <regionName>
Arguments
<parentPath>
The full path to the region that will become the parent of the new region. Required.
<regionName>
The name you want for the new region. Required.
See also
virtual function (CR-339), virtual signal (CR-351), "Virtual Objects (User-defined buses,
and more)" (UM-233)
Note: Virtual regions cannot be used in the when (CR-407) command.

virtual save CR-349
virtual save
The virtual save command saves the definitions of virtuals to a file.
Syntax
virtual save
[-kind <kind>] [-append] [<filename>]
Arguments
-kind <kind>
-append
Specifies to save only virtuals that are not already saved or weren’t read in from a macro
file. These unsaved virtuals are then appended to the specified or default file. Optional.
<filename>
Used for writing the virtual definitions. Optional. If you don’t specify <filename>, the
default virtual filename (virtuals.do) will be used. You can specify a different default in
the pref.tcl file.
See also
virtual count (CR-334), "Virtual Objects (User-defined buses, and more)" (UM-233)

CR-350 virtual show
virtual show
The virtual show command lists the full path names of all explicitly defined virtuals.
Syntax
virtual show
[-kind <kind>]
Arguments
-kind <kind>
See also
virtual define (CR-335), virtual describe (CR-337), "Virtual Objects (User-defined buses,
and more)" (UM-233)

virtual signal CR-351
virtual signal
The virtual signal command creates a new signal, known only by the GUI (not the kernel),
that consists of concatenations of signals and subelements as specified in
<expressionString>. It cannot handle bit selects and slices of Verilog registers. Please see
"Concatenation of signals or subelements" (CR-27) for more details on syntax.
Syntax
virtual signal
[-env <path>] [-install <path>] [-delay <time>] {<expressionString>}
<name>
Arguments
-env <path>
Specifies a hierarchical context for the signal names in <expressionString>, so they
don't all have to be full paths. Optional.
-install <path>
Causes the newly-created signal to become a child of the specified region. If -install is
not specified, the newly-created signal becomes a child of the nearest common ancestor
of all objects appearing in <expressionString>. If the expression references more than
one WLF file (dataset), the virtual signal will automatically be placed in region virtuals:/
Signals. Optional.
-delay <time>
Specifies a value by which the virtual signal will be delayed. Optional. You can use
negative values to look forward in time. If units are specified, the <time> option must be
enclosed in curly braces. See the examples below for more details.
{<expressionString>}
A text string expression in the MTI GUI expression format that defines the signal and
subelement concatenation. Can also be a literal constant or computed subexpression.
Required. For details on syntax, please see "Syntax and conventions" (CR-9).
<name>
The name you define for the virtual signal. Required. Case is ignored unless installed in
a Verilog region. Use alpha, numeric, and underscore characters only, unless you are
using VHDL extended identifier notation. If using VHDL extended identifier notation,
<name> needs to be quoted with double quotes or with curly braces.

CR-352 virtual signal
Examples
virtual signal -env sim:/chip/alu { (concat_range (4 downto 0))(a_04 & a_03
& a_02 & a_01 & a_00) } a
Reconstructs a bus sim:/chip/alu/a(4 downto 0), using VHDL notation, assuming that
a_ii are all scalars of the same type.
virtual signal -env sim:chip.alu { (concat_range [4:0])&{a_04, a_03, a_02,
a_01, a_00} } a
Reconstructs a bus sim:chip.alu.a[4:0], using Verilog notation. Note that the
concatenation notation starts with "&{" rather than "{".
virtual signal -install sim:/testbench { /chipa/alu/a(19 downto 13) &
/chipa/decode/inst & /chipa/mode } stuff
Creates a signal sim:/testbench/stuff which is a record type with three fields
corresponding to the three specified signals. The example assumes /chipa/mode is of type
integer, /chipa/alu/a is of type std_logic_vector, and /chipa/decode/inst is a user-defined
enumeration.
virtual signal -delay {10 ps} {/top/signalA} myDelayedSignalA
Creates a virtual signal that is the same as /top/signalA except it is delayed by 10 ps.
virtual signal { chip.instruction[23:21] } address_mode
Creates a three-bit signal, chip.address_mode, as an alias to the specified bits.
virtual signal {a & b & c & 3'b000} myextendedbus
Concatenates signals a, b, and c with the literal constant ’000’.
virtual signal {num & "000"} fullbus
add wave -unsigned fullbus
Adds three missing bits to the bus num, creates a virtual signal fullbus, and then adds that
signal to the Wave window.
virtual signal { num31 & num30 & num29 & ... & num4 & num3 & "000" } fullbus
add wave -unsigned fullbus
Reconstructs a bus that was fragmented by synthesis and is missing the lower three bits.
Note that you would have to type in the actual bit names (i.e. num28, num27, etc.)
represented by the ... in the syntax above.
virtual signal {(aold == anew) & (bold == bnew)} myequalityvector
Creates a two-bit signal (with an enumerated type) based on the results of the
subexpressions. For example, if aold equals anew, then the first bit is true (1).
Alternatively, if bold does not equal bnew, the second bit is false (0). Each subexpression
is evaluated independently.
virtual signal {(concat_reverse)(bus1 & bus2[7:4])} newbus
Creates signal newbus that is a concatenation of bus1 (bit-reversed) and bus2[7:4] (bit-
reversed). Assuming bus1 has indices running 7 downto 0, the result will be
newbus[11:0] with the upper 8 bits being bus1[0:7] and the lower 4 bits being bus2[4:7].
See "Concatenation directives" (CR-28) for further details.

virtual signal CR-353
Commands fully compatible with virtual signals

add list (CR-48) add log / log (CR-191) add wave (CR-52)
checkpoint (CR-93) and restore (CR- delete (CR-146) describe (CR-147) ("virtual
248) describe" is a little faster)
down (CR-152) / up (CR-290) examine (CR-162) find (CR-176)

force (CR-180)/noforce (CR-208) restart (CR-246) left (CR-189) / right (CR-250)
search (CR-260) searchlog (CR-262) show (CR-267)
Commands compatible with virtual signals using [virtual expand <signal>]

check contention add (CR-84) check contention config (CR-86) check contention off (CR-87)
check float add (CR-88) check float config (CR-89) check float off (CR-90)
check stable on (CR-92) check stable off (CR-91) drivers (CR-154)
power add (CR-220) power report (CR-221) power reset (CR-222)
toggle add (CR-279) toggle reset (CR-284) toggle report (CR-283)
vcd add (CR-292)
Commands not currently compatible with virtual signals

when (CR-407)
See also
virtual count (CR-334) virtual define (CR-335) virtual delete (CR-336)
virtual describe (CR-337) virtual expand (CR-338) virtual function (CR-339)

virtual hide (CR-342) virtual log (CR-343) virtual nohide (CR-345)
virtual nolog (CR-346) virtual region (CR-348) virtual save (CR-349)
virtual show (CR-350) virtual type (CR-354) Virtual Objects (User-defined

buses, and more) (UM-233)

CR-354 virtual type
virtual type
The virtual type command creates a new enumerated type, known only by the GUI, not the
kernel. Virtual types are used to convert signal values to character strings. The command
works with signed integer values up to 64 bits.
Virtual types cannot be used in the when (CR-407) command.
Syntax
virtual type
-delete <name> | {<list_of_strings>} <name>
Arguments
-delete <name>
Deletes a previously defined virtual type. <name> is the name you gave the virtual type
when you originally defined it. Required if not defining a type.
{<list_of_strings>}
A list of values and their associated character strings. Required if -delete is not used.
Values can be expressed in decimal or based notation and can include "don’t-cares" (see
examples below). Three kinds of based notation are supported: Verilog, VHDL, and C-
language styles. The values are interpreted without regard to the size of the bus to be
mapped. Bus widths up to 64 bits are supported.
There is currently no restriction on the contents of each string, but if strings contain
spaces they would need to be quoted, and if they contain characters treated specially by
Tcl (square brackets, curly braces, backslashes...), they would need to be quoted with
curly braces.
See the examples below for further syntax.
<name>
The user-defined name of the virtual type. Required if -delete is not used. Case is not
ignored. Use alpha, numeric, and underscore characters only, unless you are using VHDL
extended identifier notation. If using VHDL extended identifier notation, <name> needs
to be quoted with double quotes or with curly braces.
Examples
virtual type {state0 state1 state2 state3} mystateType
virtual function {(mystateType)mysignal} myConvertedSignal
add wave myConvertedSignal
Using positional notation, associates each string with an enumeration index, starting at
zero and increasing by one in the positive direction.When myConvertedSignal is
displayed in the Wave, List, or Objects window, the string "state0" will appear when
mysignal == 0, "state1" when mysignal == 1, "state2" when
mysignal == 2, etc.

virtual type CR-355
virtual type {{0 NULL_STATE} {1 st1} {2 st2} {0x04 st3} {16'h08 st4} \
{'h10 st5} {16#20 st6} {0b01000000 st7} {0x80 st8} \
{default BAD_STATE}} myMappedType
virtual function {(myMappedType)mybus} myConvertedBus
add wave myConvertedBus
Uses sparse mapping of bus values to alphanumeric strings for an 8-bit, one-hot
encoding. It shows the variety of syntax that can be used for values. The value "default"
has special meaning and corresponds to any value not explicitly specified.
virtual type -delete mystateType
Deletes the virtual type "mystateType".
virtual type {{0x01-- add}{0x02-- sub}{default bad}} mydecodetype
Creates a virtual type that includes "don’t-cares" (the ’-’ character).
virtual type {{0x0100 0xff add}{0x0200 0xff sub}{default bad}} mydecodetype
Creates a virtual type using a mask for "don’t-cares." The middle field is the mask, and
the mask should have bits set to 1 for the bits that are don't care.
See also
virtual function (CR-339), "Virtual Objects (User-defined buses, and more)" (UM-233)

CR-356 vlib
vlib
The vlib command creates a design library. You must use vlib rather than operating system
commands to create a library directory or index file. If the specified library already exists
as a valid ModelSim library, the vlib command will exit with a warning message without
touching the library.
Syntax
vlib
[-archive [-compact <percent>]] [-help] [-dos | -short | -unix | -long]
[-unnamed_designs <value>] <name>
Arguments
-archive [-compact <percent>]
Causes design units that are compiled into the created library to be stored in archives
rather than in subdirectories. Optional. See "Archives" (UM-59) for more details.
You may optionally specify a decimal number between 0 and 1 that denotes the allowed
percentage of wasted space before archives are compacted. By default archives are
compacted when 50% (.5) of their space is wasted. See an example below.
-help
-dos
Specifies that subdirectories in a library have names that are compatible with DOS. Not
recommended if you use the vmake (CR-369) utility. Optional.
-short
Interchangeable with the -dos argument. Optional.
-unix
Specifies that subdirectories in a library may have long file names that are NOT
compatible with DOS. Optional. Default for ModelSim SE.
-long
Interchangeable with the -unix argument. Optional.
-unnamed_designs <value>
Specifies how many unnamed, optimized versions of a design the vopt command (CR-
371) will save within the library. Once <value> is reached, vopt deletes the oldest
unnamed, optimized version. Optional.
<name>
Specifies the pathname or archive name of the library to be created. Required.
Examples
vlib design
Creates the design library design. You can define a logical name for the library using the
vmap command (CR-370) or by adding a line to the library section of the modelsim.ini file
that is located in the same directory.

vlib CR-357
vlib -archive -compact .3 uut

Creates the design library uut and specifies that any design units compiled into the library
are created as archives. Also specifies that each archive be compacted when 30% of its
space is wasted.

CR-358 vlog
vlog
The vlog command compiles Verilog source code into a specified working library (or to the
work library by default).
vlog may be invoked from within ModelSim or from the operating system command
prompt. It may also be invoked during simulation.
Compiled libraries are major-version dependent. For example you cannot use a library
compiled with 5.7 in a simulation using 5.8 vsim. You would have to refresh the libraries
using the -refresh argument to vlog. This is not true for minor versions (e.g., 5.7a libraries
work in 5.7d).
Syntax
vlog
[-93] [-help] [-compat] [-compile_uselibs[=<directory_name>]]
[-cover <stat>] [-debugCellOpt] [+define+<macro_name>[=<macro_text>]]
[+delay_mode_distributed] [+delay_mode_path] [+delay_mode_unit]
[+delay_mode_zero] [-dpiheader] [-error <msg_number>[,<msg_number>,...]]
[-f <filename>] [-fast[=<secondary_name>] [+acc[=<spec>] [+<module>[.]]]]
[-forcecode] [-hazards] [+incdir+<directory>] [-incr]
[-instantiateReadOnly] [-isymfile] [-keep_delta] [-L <libname>]
[-Lf <libname>] [+libext+<suffix>] [-libmap <pathname>] [-libmap_verbose]
[+librescan] [-line <number>] [-lint] [+maxdelays] [+mindelays]
[+nocheckALL] [+nocheckCLUP] [+nocheckDELAY] [+nocheckDNET] [+nocheckOPRD]
[+nocheckSUDP] [-nocoverage] [-nodebug[=ports | =pli]] [-noincr]
[+nolibcell] [-nologo] [-nopsl] [+nospecify]
[-note <msg_number>[,<msg_number>,...]] [+notimingchecks] [-novopt]
[+nowarn<CODE>][-O0 | -O1 | -O4 | -O5] [+opt+[<lib>.]<module>]
[-pslfile <filename>] [-quiet] [-R [<simargs>]] [-refresh] [-source] [-sv]
[-suppress <msg_number>[,<msg_number>,...]] [-time] [+typdelays] [-u]
[-v <library_file>] [-version] [-vlog95compat] [-vopt]
[-warning <msg_number>[,<msg_number>,...]] [-work <library_name>]
[-y <library_directory>] <filename>
Arguments
-93
Specifies that the VHDL interface to Verilog modules use VHDL 1076-1993 extended
identifiers to preserve case in Verilog identifiers that contain uppercase letters. Optional.
-help
-compat
Disables optimizations that result in different event ordering than Verilog-XL. Optional.
ModelSim Verilog generally duplicates Verilog-XL event ordering, but there are cases
where it is inefficient to do so. Using this option does not help you find event order
dependencies, but it allows you to ignore them. Keep in mind that this option does not
account for all event order discrepancies, and that using this option may degrade
performance. See "Event ordering in Verilog designs" (UM-132) for additional
information.

vlog CR-359
-compile_uselibs[=<directory_name>]
Locates source files specified in a ùselib directive (see "Verilog-XL ùselib compiler
directive" (UM-120)), compiles those files into automatically created libraries, and updates
the modelsim.ini file with the logical mappings to the new libraries. Optional. If a
directory_name is not specified, ModelSim uses the name specified in the
MTI_USELIB_DIR environment variable. If that variable is not set, ModelSim creates
the directory mti_uselibs in the current working directory.
-cover <stat>
Specifies type(s) of coverage statistics to collect. Optional.
<stat> is one or more of the following characters:
b–Collect branch statistics.
c–Collect condition statistics.
e–Collect expression statistics.
s–Collect statement statistics.
t–Collect toggle statistics. Cannot be used if ’x’ is specified.
x–Collect extended toggle statistics (see "Toggle coverage" (UM-343) for details).
Cannot be used if ’t’ is specified.
By default only statement coverage is enabled when you invoke vsim with the -coverage
option.
-debugCellOpt
Produces Transcript pane output that identifies why certain cells within the design were
not optimized. Used only when compiling gate-level Verilog libraries with -fast (see
below). Optional.
+define+<macro_name>[=<macro_text>]
Allows you to define a macro from the command line that is equivalent to the following
compiler directive:
`define <macro_name> <macro_text>
Optional. You can specify more than one macro with a single +define. For example:
vlog +define+one=r1+two=r2+three=r3 test.v
A command line macro overrides a macro of the same name defined with the `define
compiler directive.
+delay_mode_distributed
Disables path delays in favor of distributed delays. Optional. See "Delay modes" (UM-
144)for details.
+delay_mode_path
Sets distributed delays to zero in favor of using path delays. Optional. See "Delay modes"
(UM-144) for details.
+delay_mode_unit
Sets path delays to zero and non-zero distributed delays to one time unit. Optional. See
"Delay modes" (UM-144) for details.

CR-360 vlog
+delay_mode_zero
Sets path delays and distributed delays to zero. Optional. See "Delay modes" (UM-144) for
details.
-dpiheader
Generates a header file that may then be included in C source code for DPI import
functions.
-f <filename>
Specifies a file with more command line arguments. Optional. Allows complex
arguments to be reused without retyping. Allows gzipped input files. Nesting of -f
options is allowed.
-fast[=<secondary_name>] [+acc[=<spec>] [+<module>[.]]]
Increases simulation speed on gate-level designs by allowing parameter propagation and
global optimizations. If you are simulating RTL, use the vopt command (CR-371) instead
of -fast. Please see "Optimizing Verilog designs" (UM-124). The following options are
available:
=<secondary_name>
Allows you to specify a different secondary name for the optimized code. The compiler
automatically assigns a secondary name to distinguish optimized code from
un-optimized code that may exist in the same library. The default secondary name for
optimized code is "fast"; the default secondary name for un-optimized code is "verilog".
+acc[=<spec>][+<module>[.]]
Allows you to maintain design object visibility. Note that using this option may reduce
simulation speed.
<spec> is one or more of the following characters:
b–Enable access to bits of vector nets. This is necessary for PLI applications that
require handles to individual bits of vector nets. Also, some user interface commands
require this access if you need to operate on net bits.
c–Enable access to library cells. By default any Verilog module containing a
non-empty specify block may be optimized, and debug and PLI access may be limited.
This option keeps module cell visibility.
l–Enable access to line number directives and process names.
n–Enable access to nets.
p–Enable access to ports. This disables the module inlining optimization, and is
necessary only if you have PLI applications that require access to port handles.
r–Enable access to registers (including memories, integer, time, and real types).
s–Enable access to system tasks.
t–Enable access to tasks and functions.

vlog CR-361
If <spec> is omitted, access is enabled for all objects.

<module> is a module name, optionally followed by "." to indicate all children of the
module. Multiple modules are allowed, with each separated by a "+". If no modules are
specified, then all modules are affected.
-forcecode
Forces code generation for optimized inlined modules when using the -fast switch.
Should be used only when compiling vendor-supplied cell libraries that will be placed in
a read-only location. Optional.
-hazards
Detects event order hazards involving simultaneous reading and writing of the same
register in concurrently executing processes. Optional. You must also specify this
argument when you simulate the design with vsim (CR-373). See "Hazard detection" (UM-
135) for more details.
Important: Enabling -hazards implicitly enables the -compat argument. As a result,

using this argument may affect your simulation results.
+incdir+<directory>
Specifies directories to search for files included with ìnclude compiler directives.
Optional. By default, the current directory is searched first and then the directories
specified by the +incdir options in the order they appear on the command line. You may
specify multiple +incdir options as well as multiple directories separated by "+" in a
single +incdir option.
-incr
Performs an incremental compile. Optional. Compiles only code that has changed. For
example, if you change only one module in a file containing several modules, only the
changed module will be recompiled. Note however that if the compile options change,
all modules are recompiled regardless if you use -incr or not.
-instantiateReadOnly
Enables a -fast optimized design to instantiate modules or UDPs from a work library that
has read-only permission. The instantiations will not be in-lined or further optimized.
Recommended usage is to always have write access to the work library.
-isymfile
Generates a complete list of all imported TFs. Used with DPI to determine all imported
TFs that are expected by ModelSim. Valid only for Windows, RS6000 and RS64
platforms only.
-keep_delta
Disables optimizations that remove delta delays. Optional.
Delta delays result from zero delay events. Those events are normally processed in the
next iteration or "delta" of the current timestep. -fast and +opt implement optimizations
that can remove delta delays and process an event earlier.
-L <libname>
Searches the specified resource library for precompiled modules. The library search
options you specify here must also be specified when you run the vsim command (CR-
373). Optional.

CR-362 vlog
-Lf <libname>
Same as -L but the specified library is searched before any ’uselib directives. (See
"Library usage" (UM-117) and "Verilog-XL compatible compiler arguments" (UM-119) for
more information). Optional.
+libext+<suffix>
Works in conjunction with the -y option. Specifies file extensions for the files in a source
library directory. Optional. By default the compiler searches for files without extensions.
If you specify the +libext option, then the compiler will search for a file with the suffix
appended to an unresolved name. You may specify only one +libext option, but it may
contain multiple suffixes separated by "+". The extensions are tried in the order they
appear in the +libext option.
-libmap <pathname>
Specifies a Verilog 2001 library map file. Optional. You can omit this argument by
placing the library map file as the first option on the vlog invocation (e.g., vlog top.map
top.v top_cfg.v).
-libmap_verbose
Displays library map pattern matching information during compilation. Optional. Use to
troubleshoot problems with matching filename patterns in a library file.
+librescan
Scans libraries in command-line order for all unresolved modules. Optional.
-line <number>
Starts the compiler on the specified line in the Verilog source file. Optional. By default,
the compiler starts at the beginning of the file.
-lint
Instructs ModelSim to perform three lint-style checks: 1) warn when Module ports are
NULL; 2) warn when assigning to an input port; 3) warn when referencing undeclared
variables/nets in an instantiation. The warnings are reported as WARNING[8]. Can also
be enabled using the Show_Lint (UM-526) variable in the modelsim.ini file.
+maxdelays
Selects maximum delays from the "min:typ:max" expressions. Optional. If preferred,
you can defer delay selection until simulation time by specifying the same option to the
simulator.
+mindelays
Selects minimum delays from the "min:typ:max" expressions. Optional. If preferred, you
can defer delay selection until simulation time by specifying the same option to the
simulator.
+nocheckALL
Enables all +nocheck arguments described below. Optional. Argument has an effect only
when compiling gate-level cell libraries with -fast (see above). The +nocheck switches
increase the optimizations of -fast.
+nocheckCLUP
Allows connectivity loops in a cell to be optimized. Optional. Argument has an effect
only when compiling gate-level cell libraries with -fast (see above).

vlog CR-363
+nocheckDELAY
When used in conjunction with +delay_mode_path (see above), allows inlined Verilog
modules with distributed delays and no path delays to be optimized. Optional. Argument
has an effect only when compiling gate-level cell libraries with -fast (see above).
+nocheckDNET
Allows both the port and the delayed port (created for negative setup/hold) to be used in
the functional section of the cell. Optional. Argument has an effect only when compiling
gate-level cell libraries with -fast (see above).
+nocheckOPRD
Allows an output port to be read internally by the cell. Optional. Argument has an effect
only when compiling gate-level cell libraries with -fast (see above). Note that if the value
read is the only value contributed to the output by the cell, and if there's a driver on the
net outside the cell, the value read will not reflect the resolved value.
+nocheckSUDP
Allows a sequential UDP to drive another sequential UDP. Optional. Argument has an
effect only when compiling gate-level cell libraries with -fast (see above).
-nocoverage
Disables collection of statement coverage statistics, which are on by default. Optional.
-nodebug[=ports | =pli]
Hides the internal data of the compiled design unit. Optional. The design unit’s source
code, internal structure, registers, nets, etc. will not display in ModelSim’s windows. In
addition, none of the hidden objects may be accessed through the Dataflow window or
with commands. This also means that you cannot set breakpoints or single step within
this code. Don’t compile with this switch until you’re done debugging.
Note that this is not a speed switch like the “nodebug” option on many other products.
Use the vopt command (CR-371) to increase simulation speed.
The optional =ports switch hides the ports for the lower levels of your design; it should
be used only to compile the lower levels of the design. If you hide the ports of the top
level you will not be able to simulate the design.
The optional =pli switch prevents the use of pli functions to interrogate individual
modules for information; this switch may be used at any level of the design. Combine
both switches with =ports+pli or =pli+ports.
-nodebug encrypts entire files. The `protect compiler directive allows you to encrypt
regions within a file. See "ModelSim compiler directives" (UM-155) for details.
-noincr
Disables incremental compile previously turned on with -incr. Optional.
+nolibcell
By default all modules compiled from a source library are treated as though they contain
a `celldefine compiler directive. This option disables this default. The `celldefine
directive only affects the PLI access routines acc_next_cell and acc_next_cell_load.
Optional.
-nologo
Disables the startup banner. Optional.

CR-364 vlog
-nopsl
Instructs the compiler to ignore embedded PSL assertions. By default vlog parses any
PSL assertion statements it finds in the specified files. See "Compiling and simulating
assertions" (UM-375) for more information.
+nospecify
Disables specify path delays and timing checks. Optional.
+notimingchecks
Removes all timing check entries from the design as it is parsed. Optional. To disable
checks on individual instances, use the tcheck_set command (CR-275).
-novopt
Forces vlog to produce code if you have set the VoptFlow (UM-534) variable in the
modelsim.ini to 1. You can use this argument in tandem with vsim -novopt to run
ModelSim in debug mode when the default behavior is optimized.
+nowarn<CODE>
Disables warning messages in the category specified by <CODE>. Optional. Warnings
that can be disabled include the <CODE> name in square brackets in the warning
message. For example,
** Warning: test.v(15): [RDGN] - Redundant digits in numeric literal.
This warning message can be disabled by specifying +nowarnRDGN.
-O0 | -O1 | -O4 | -O5
Lower the optimization to a minimum with -O0 (capital oh zero). Optional. Use this to
work around bugs, increase your debugging visibility on a specific cell, or when you
want to place breakpoints on source lines that have been optimized out.
Enable PE-level optimization with -O1. Optional.
Enable standard SE optimizations with -O4. Default.
Enable maximum optimization with -O5. Optional. -O5 attempts to optimize loops and
prevents variable assignments in situations where a variable is assigned but is not
actually used. Using the +acc argument to vlog will cancel this latter optimization.
Use caution with the -O5 argument. We recommend use of this argument with large
sequential blocks only; other uses may significantly increase compile times.
+opt+[<lib>.]<module>
Generates optimized code for designs that have been previously compiled un-optimized
(without the -fast option; see above). Optional. The <module> specification is the name
of the top-level design module, and <lib>, which is optional, is the library in which it
resides. By default, the top-level module is searched for in the work library. If the design
has multiple top-level modules, then provide the names in a list separated by plus signs.
For example,
vlog +opt+testbench+globals
Any options that are appropriate with -fast are also appropriate with +opt. Specifically,
use the +acc option to enable PLI access, and use the -L and -Lf options to specify the
libraries to be searched.

vlog CR-365
+protect
Enables `protect ... èndprotect directives. Optional. See "ModelSim compiler
directives" (UM-155) for more information.
-pslfile <filename>
Identifies an external PSL assertion file to compile along with the Verilog source files.
See "Compiling and simulating assertions" (UM-375) for more information.
-quiet
Disables 'Loading' messages. Optional.
-R [<simargs>]
Instructs the compiler to invoke vsim (CR-373) after compiling the design. The compiler
automatically determines which top-level modules are to be simulated. The command
line arguments following -R are passed to the simulator, not the compiler. Place the -R
option at the end of the command line or terminate the simulator command line
arguments with a single "-" character to differentiate them from compiler command line
arguments.
The -R option is not a Verilog-XL option, but it is used by ModelSim to combine the
compile and simulate phases together as you may be used to doing with Verilog-XL. It
is not recommended that you regularly use this option because you will incur the
unnecessary overhead of compiling your design for each simulation run. Mainly, it is
provided to ease the transition to ModelSim.
-refresh
Regenerates a library image. Optional. By default, the work library is updated; use -work
<library_name> to update a different library. See vlog examples for more information.
-source
Displays the associated line of source code before each error message that is generated
during compilation. Optional; by default, only the error message is displayed.
-sv
Enables System Verilog keywords. Optional. By default ModelSim follows the rules of
IEEE Std 1364-2001 and ignores System Verilog keywords. If a source file has a ".sv"
extension, ModelSim will automatically parse System Verilog keywords.
information.
-time
Reports the "wall clock time" vlog takes to compile the design. Optional. Note that if
many processes are running on the same system, wall clock time may differ greatly from
the actual "cpu time" spent on vlog.
+typdelays
Selects typical delays from the "min:typ:max" expressions. Default. If preferred, you can
defer delay selection until simulation time by specifying the same option to the simulator.
-u
Converts regular Verilog identifiers to uppercase. Allows case insensitivity for module
names. Optional.

CR-366 vlog
-v <library_file>
Specifies a source library file containing module and UDP definitions. Optional. See
"Verilog-XL compatible compiler arguments" (UM-119) for more information.
After all explicit filenames on the vlog command line have been processed, the compiler
uses the -v option to find and compile any modules that were referenced but not yet
defined. Modules and UDPs within the file are compiled only if they match previously
unresolved references. Multiple -v options are allowed. See additional discussion in the
examples.
-version
Returns the version of the compiler as used by the licensing tools, such as "Model
Technology ModelSim SE vlog 5.5 Compiler 2000.01 Jan 28 2000".
-vlog95compat
Disables Verilog 2001 keywords, which ensures that code that was valid according to the
1364-1995 spec can still be compiled. By default ModelSim follows the rules of IEEE
Std 1364-2001. Some requirements in 1364-2001 conflict with requirements in 1364-
1995. Optional. Edit the vlog95compat (UM-526) variable in the modelsim.ini file to set a
permanent default.
-vopt
Notifies vlog that the vopt command (CR-371) will be run. As a result, vlog will not
produce code. Optional.
library work. Optional; by default, the compiled design units are added to the work
file.
-y <library_directory>
Specifies a source library directory containing module and UDP definitions. Optional.
See "Verilog-XL compatible compiler arguments" (UM-119) for more information.
After all explicit filenames on the vlog command line have been processed, the compiler
uses the -y option to find and compile any modules that were referenced but not yet
defined. Files within this directory are compiled only if the file names match the names
of previously unresolved references. Multiple -y options are allowed. You will need to
specify a file suffix by using -y in conjunction with the +libext+<suffix> option if your
filenames differ from your module names. See additional discussion in the examples.
Important: Any -y arguments that follow a -refresh argument on a vlog command line
are ignored. Any -y arguments that come before the -refresh argument on a vlog
command line are processed.
<filename>
Specifies the name of the Verilog source code file to compile. One filename is required.
Multiple filenames can be entered separated by spaces. Wildcards can be used.

vlog CR-367
Examples
vlog example.vlg
Compiles the Verilog source code contained in the file example.vlg.
vlog -nodebug example.v
Hides the internal data of example.v. Models compiled with -nodebug cannot use any of
the ModelSim debugging features; any subsequent user will not be able to see into the
model.
vlog -nodebug=ports level3.v level2.v
vlog -nodebug top.v
The first line compiles and hides the internal data, plus the ports, of the lower-level
design units, level3.v and level2.v. The second line compiles the top-level unit, top.v,
without hiding the ports. It is important to compile the top level without =ports because
top-level ports must be visible for simulation.
vlog -nodebug=ports+pli level3.v level2.v
vlog -nodebug=pli top.v
The first command hides the internal data, and ports of the design units, level3.v and
level2.v. In addition it prevents the use of PLI functions to interrogate the compiled
modules for information (either =ports+pli or =pli+ports works fine for this command).
The second line compiles the top-level unit without hiding the ports but restricts the use
of PLI functions as well.
Note that the =pli switch may be used at any level of the design but =ports should only
be used on lower levels since you can’t simulate without visible top-level ports.
vlog -L work -L libA -L libB top.v
This command demonstrates how to compile hierarchical modules organized into
separate libraries that have sub-module names that overlap among the libraries. Assume
you have a top-level module top that instantiates module modA from library libA and
module modB from library libB. Furthermore, modA and modB both instantiate modules
named cellA, but the definition of cellA compiled into libA is different from that compiled
into libB. In this case, you can’t just specify -L libA - L libB because instantiations of
cellA from modB resolve to the libA version of cellA. See "Library usage" (UM-117) for
further information.
vlog top.v -v und1
After compiling top.v, vlog will scan the file und1 for modules or primitives referenced
but undefined in top.v. Only referenced definitions will be compiled.
vlog top.v +libext+.v+.u -y vlog_lib
After compiling top.v, vlog will scan the vlog_lib library for files with modules with the
same name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u
implies filenames with a .v or .u suffix (any combination of suffixes may be used). Only
referenced definitions will be compiled.
vlog -work mylib -refresh
The -work option specifies mylib as the library to regenerate. -refresh rebuilds the
library image without using source code, allowing models delivered as compiled libraries
without source code to be rebuilt for a specific release of ModelSim.
If your library contains VHDL design units be sure to regenerate the library with the
vcom command (CR-311) using the -refresh option as well. See "Regenerating your
design libraries" (UM-66) for more information.

CR-368 vlog
vlog module1.v -u -O0 -incr

The -incr option determines whether or not the module source or compile options have
changed as module1.v is parsed. If no change is found, the code generation phase is
skipped. Differences in compile options are determined by comparing the compiler
options stored in the _info file with the compiler options given. They must match exactly.

vmake CR-369
vmake
The vmake utility allows you to use a UNIX or Windows MAKE program to maintain
libraries. You run vmake on a compiled design library, and the utility outputs a makefile.
You can then run the makefile with a version of MAKE (not supplied with ModelSim) to
reconstruct the library. A MAKE program is included with Microsoft Visual C/C++, as
well as many other program development environments.
After running the vmake utility, MAKE recompiles only the design units (and their
dependencies) that have changed. You run vmake only once; then you can simply run
MAKE to rebuild your design. If you add new design units or delete old ones, you should
re-run vmake to generate a new makefile.
The vmake utility ignores library objects compiled with -nodebug. Also, the vmake utility
is not supported for use with SystemC.
This command must be invoked from either the UNIX or the Windows/DOS prompt.
Syntax
vmake
[-fullsrcpath] [-help] [<library_name>] [><makefile>]
Arguments
-fullsrcpath
Produces complete source file paths within generated makefiles. Optional. By default
source file paths are relative to the directory in which compiles originally occurred. This
argument makes it possible to copy and evaluate generated makefiles within directories
that are different from where compiles originally occurred.
-help
<library_name>
Specifies the library name; if none is specified, then work is assumed. Optional.
><makefile>
Specifies the makefile name. Optional.
Examples
To produce a makefile for the work library:
vmake >makefile
You can also run vmake on libraries other than work:

vmake mylib >mylib.mak
To rebuild mylib, specify its makefile when you run MAKE:

make -f mylib.mak

CR-370 vmap
vmap
The vmap command defines a mapping between a logical library name and a directory by
modifying the modelsim.ini file. With no arguments, vmap reads the appropriate
modelsim.ini file(s) and prints the current logical library to physical directory mappings.
Returns nothing.
Syntax
vmap
[-help] [-c] [-del] [<logical_name>] [<path>]
Arguments
-help
-c
Copies the default modelsim.ini file from the ModelSim installation directory to the
current directory. Optional.
This argument is intended only for making a copy of the default modelsim.ini file to the
current directory. Do not use it while making your library mappings or the mappings may
end up in the incorrect copy of the modelsim.ini.
-del
Deletes the mapping specified by <logical_name> from the current project file. Optional.
<logical_name>
Specifies the logical name of the library to be mapped. Optional.
<path>
Specifies the pathname of the directory to which the library is to be mapped. Optional. If
omitted, the command displays the mapping of the specified logical name.

vopt CR-371
vopt
The vopt command performs global optimizations on Verilog and mixed-HDL designs
after they have been compiled with vcom or vlog.
The vopt command produces an optimized version of your design in the working directory.
You provide a name for this optimized version using the -o argument. You can then invoke
vsim directly on that new design unit name.
In the course of optimizing a design, vopt will remove objects that are deemed unnecessary
for simulation. For example, line numbers are removed, processes are merged, nets and
registers may be removed, etc. If you need visibility into your design for debugging
purposes, use the +acc argument to conditionally enable visibility for parts of your design.
Note, however, that using +acc may reduce simulation speed.
Syntax
vopt
[+acc[=<spec>][+<module>[.]]] -work <library_name> <design_unit> -o <name>
Arguments
+acc[=<spec>][+<module>[.]]
Allows you to maintain design object visibility. Note that using this option may reduce
simulation speed. Optional.
<spec> is one or more of the following characters:
a–Preserve PSL assertion and functional coverage browser data. Note that if a PSL
construct is being driven by a port signal, vopt may replace that signal name with its
higher-level driver. So in this case, if you prefer the local port name, the +acc "p"
option should also be specified (i.e., +acc=ap).
b–Enable access to bits of vector nets. This is necessary for PLI applications that
require handles to individual bits of vector nets. Also, some user interface commands
require this access if you need to operate on net bits.
c–Enable access to library cells. By default any Verilog module containing a
non-empty specify block may be optimized, and debug and PLI access may be limited.
This option keeps module cell visibility.
l–Enable access to line number directives and process names.
n–Enable access to nets.
p–Enable access to ports. This disables the module inlining optimization, and is
necessary only if you have PLI applications that require access to port handles.
r–Enable access to registers (including memories, integer, time, and real types).
s–Enable access to system tasks.
t–Enable access to tasks and functions.
If <spec> is omitted, access is enabled for all objects.
<module> is a module name, optionally followed by "." to indicate all children of the
module. Multiple modules are allowed, with each separated by a "+". If no modules are
specified, then all modules are affected.

CR-372 vopt
library work. Optional; by default, the optimized output for the design is added to the
work library. The specified pathname overrides the pathname specified for work in the
project file.
<design_unit>
One or more top-level design units that you want to optimize. Required.
-o <name>
Specifies a name for the optimized version of the design. Required.
Examples
vopt top -o mydesign
vsim mydesign
Runs optimizations on top-level design unit top and produces an optimized design unit
named "mydesign". The simulator vsim is then invoked on design unit mydesign.
vopt top +acc -o mydesign
Runs optimizations on top-level design unit top but preserves all visibility. Names the
optimized design "mydesign."
vopt top +acc+foo -o mydesign
Runs optimizations on top-level design unit top but preserves visibility on sub-module
foo. Names the optimized design "mydesign."
vopt top +acc+foo. -o mydesign
Runs optimizations on top-level design unit top but preserves visibility on sub-module
foo and all its children.
vopt top +acc=rn -o mydesign
Runs optimizations on top-level design unit top but enables net and register access in all
modules in the design. Names the optimized design "mydesign."
See also
"Optimizing Verilog designs" (UM-124),

vsim CR-373
vsim
The vsim command is used to invoke the VSIM simulator, or to view the results of a
previous simulation run (when invoked with the -view switch). You can simulate a VHDL
configuration or an entity/architecture pair; a Verilog module or configuration; a SystemC
module; or an optimized design. If you specify a VHDL configuration, it is invalid to
specify an architecture. During elaboration vsim determines if the source has been
modified since the last compile.
To manually interrupt design elaboration use the Break key or <Ctrl-c> from a shell.
You can invoke vsim from a command prompt or in the Transcript pane of the Main
window. You can also invoke it from the GUI by selecting Simulate > Start Simulation.
Syntax
vsim
[-assertfile <filename>] [-assume] [-c] [-csupv2] [-compress_elab]
[-coverage] [-do “<command_string>” | <macro_file_name>]
[+dumpports+direction] [+dumpports+unique]
[-elab <filename>] [-elab_cont <filename>]
[-elab_defer_fli] [-error <msg_number>[,<msg_number>,...]] [-f <filename>]
[-filemap_elab <HDLfilename>=<NEWfilename>]
[-g<Name>=<Value> ...] [-G<Name>=<Value> ...] [-gblso <filename>]
[-help] [-i] [-installcolormap] [-keeploaded] [-keeploadedrestart]
[-keepstdout] [-l <filename>] [-lib <libname>] [<license_option>]
[-load_elab <filename>] [-memprof] [-memprof+file=<filename>]
[-memprof+fileonly=<filename>] [-multisource_delay min | max | latest]
[+multisource_int_delays] [-noassume] [-nocompress] [+no_notifier]
[-nopsl] [+no_tchk_msg] [-note <msg_number>[,<msg_number>,...]]
[+notimingchecks]
[-novopt] [+pulse_int_e/<percent>] [+pulse_int_r/<percent>] [-quiet]
[-restore <filename>] [+sdf_iopath_to_prim_ok]
[-sdfmin | -sdftyp | -sdfmax[@<delayScale>] [<instance>=]<sdf_filename>]
[-sdfmaxerrors <n>] [-sdfnoerror] [-sdfnowarn] [+sdf_verbose]
[-suppress <msg_number>[,<msg_number>,...]]
[-t [<multiplier>]<time_unit>] [-tag <string>] [-title <title>]
[-trace_foreign <int>] [+transport_int_delays]
[-vcdstim [<instance>=]<filename>] [-version]
[-view [<dataset_name>=]<WLF_filename>] [-vopt] [-voptargs="<args>"]
[-warning <msg_number>[,<msg_number>,...]] [-wlf <filename>]
[-wlfcollapsedelta] [-wlfcollapsetime] [-wlfcompress]
[-wlfopt] [-wlfnocollapse] [-wlfnocompress] [-wlfnoopt]
[-wlfslim <size>] [-wlftlim <duration>]
[-absentisempty] [-foreign <attribute>] [-nocollapse] [-nofileshare]
[-noglitch] [+no_glitch_msg] [-std_input <filename>]
[-std_output <filename>] [-strictvital] [-vcdread <filename>]
[-vital2.2b]
[+alt_path_delays] [+delayed_timing_checks]
[-dpiexportobj <objfile>] [-extend_tcheck_data_limit <percent>]
[-extend_tcheck_ref_limit <percent>]
[-hazards] [+int_delays] [-L <library_name> ...] [-Lf <library_name> ...]
[+maxdelays] [+mindelays] [+no_cancelled_e_msg] [+no_neg_tchk]
[+no_notifier] [+no_path_edge] [+no_pulse_msg] [-no_risefall_delaynets]
[+no_show_cancelled_e] [+no_tchk_msg] [+nosdferror] [+nosdfwarn]
[+nospecify] [+nowarn<CODE>] [+ntc_warn] [-pli "<object list>"]
[+<plusarg>] [+pulse_e/<percent>] [+pulse_e_style_ondetect]
[+pulse_e_style_onevent] [+pulse_r/<percent>] [+sdf_nocheck_celltype]

CR-374 vsim
[+show_cancelled_e] [-sv_lib <shared_obj>] [-sv_liblist <filename>]

[-sv_root <dirname>] [+transport_path_delays] [+typdelays]
[-v2k_int_delays]
[-sclib] [-sc_arg <string> ...]
[<library_name>.<design_unit>]
VSIM arguments are grouped by language:
• Arguments, all languages (CR-374)
• Arguments, VHDL (CR-384)
• Arguments, Verilog (CR-385)
• Arguments, SystemC (CR-389)
• Arguments, object (CR-390)
Arguments, all languages

-assertfile <filename>
Designates an alternative file for recording assertion messages. Optional. By default
assertion messages are output to the file specified by the TranscriptFile variable in the
modelsim.ini file (see "Creating a transcript file" (UM-537)).
-assume
Simulates PSL assume directives as though they were assert directives. Optional.
Default. This option may also be specified with the SimulateAssumeDirectives (UM-533)
variable in the modelsim.ini file. See "Processing assume directives in simulation" (UM-
363) for more information.
-c
Specifies that the simulator is to be run in command-line mode. Optional. Also see
"ModelSim modes of operation" (UM-27) for more information.
-csupv2
Instructs vsim to use /usr/lib/libCsup_v2.sl for shared object loading. Optional. Use this
argument only on HP-UX 11.00 when you have compiled FLI/PLI/VPI C++ code with
aCC's -AA option. This option may also be specified with the UseCsupV2 (UM-534)
-compress_elab
Compresses an elaboration file when it is created. Optional. See "Simulating with an
elaboration file" (UM-138) for more information.
-coverage
Enables Code Coverage statistics collection during simulation. Optional. See Chapter 13
- Measuring code coverage for more information.
-do “<command_string>” | <macro_file_name>
Instructs vsim to use the command(s) specified by <command_string> or the macro file
named by <macro_file_name> rather than the startup file specified in the .ini file, if any.
Optional. Multiple commands should be separated by semi-colons (;).
+dumpports+direction
Modifies the format of extended VCD files to contain direction information. Optional.

vsim CR-375
+dumpports+unique
Generates unique VCD variable names for ports in a VCD file, even if those ports are
connected to the same collapsed net. Optional.
-elab <filename>
Creates an elaboration file for use with -load_elab. Optional. See "Simulating with an
-elab_cont <filename>
Creates an elaboration file for use with -load_elab and then continues the simulation.
Optional.
-elab_defer_fli
Defers the initialization of FLI models until the load of the elaboration file. Use this
argument along with -elab to create elaboration files for designs with FLI models that
don't support checkpoint/restore. Note that FLI models sensitive to design load ordering
may still not work correctly even if you use this argument. See "Simulating with an
-f <filename>
Specifies a file with more command line arguments. Optional. Allows complex argument
strings to be reused without retyping. Environment variable expansion (for example in a
-filemap_elab <HDLfilename>=<NEWfilename>
Defines a file mapping during -load_elab that lets you change the stimulus. Optional.
See "Simulating with an elaboration file" (UM-138) for more information.
-g<Name>=<Value> ...
Assigns a value to all specified VHDL generics and Verilog parameters that have not
received explicit values in generic maps, instantiations, or via defparams (such as top-
level generics/parameters and generics/parameters that would otherwise receive their
default values). Optional. Note there is no space between -g and <Name>=<Value>.
"Name" is the name of the generic/parameter, exactly as it appears in the VHDL source
(case is ignored) or Verilog source. "Value" is an appropriate value for the declared data
type of a VHDL generic or any legal value for a Verilog parameter. Make sure the Value
you specify for a VHDL generic is appropriate for VHDL declared data types. VHDL
type mismatches will cause the specification to be ignored (including no error messages).
No spaces are allowed anywhere in the specification, except within quotes when
specifying a string value. Multiple -g options are allowed, one for each generic/
parameter.
Name may be prefixed with a relative or absolute hierarchical path to select generics in
an instance-specific manner. For example,
Specifying -g/top/u1/tpd=20ns on the command line would affect only the tpd generic on
the /top/u1 instance, assigning it a value of 20ns.
Specifying -gu1/tpd=20ns affects the tpd generic on all instances named u1.
Specifying -gtpd=20ns affects all generics named tpd.

CR-376 vsim
If more than one -g option selects a given generic the most explicit specification takes
precedence. For example,
vsim -g/top/ram/u1/tpd_hl=10ns -gtpd_hl=15ns top
This command sets tpd_hl to 10ns for the /top/ram/u1 instance. However, all other tpd_hl
generics on other instances will be set to 15ns.
Limitation: In general, generics/parameters of composite type (arrays and records)
cannot be set from the command line. However, you can set string arrays, std_logic
vectors, and bit vectors if they can be set using a quoted string. For example,
-gstrgen="This is a string"
-gslv="01001110"
The quotation marks must make it into vsim as part of the string because the type of the
value must be determinable outside of any context. Therefore, when entering this
command from a shell, put a forward tick around the string. For example:
-gstrgen=’"This is a string"’
If working within the ModelSim GUI, you would enter the command as follows:
{-gstrgen="This is a string"}
-G<Name>=<Value> ...
Same as -g (see above) except that it will also override generics/parameters that received
explicit values in generic maps, instantiations, or via defparams. Optional. Note there is
no space between -G and <Name>=<Value>.
-gblso <filename>
On UNIX platforms, loads PLI/FLI shared objects with global symbol visibility.
Essentially all data and functions are exported from the specified shared object and are
available to be referenced and used by other shared objects. This option may also be
specified with the GlobalSharedObjectsList (UM-532) variable in the modelsim.ini file.
Optional.
-gui
Starts the ModelSim GUI without loading a design. Optional.
-help
-i
Specifies that the simulator is to be run in interactive mode. Optional.
-installcolormap
For UNIX only. Causes vsim to use its own colormap so as not to hog all the colors on
the display. This is similar to the -install switch on Netscape. Optional.
-keeploaded
Prevents the simulator from unloading/reloading any FLI/PLI/VPI shared libraries when
it restarts or loads a new design. Optional. The shared libraries will remain loaded at their
current positions. User application code in the shared libraries must reset its internal state
during a restart in order for this to work effectively.
-keeploadedrestart
Prevents the simulator from unloading/reloading any FLI/PLI/VPI shared libraries
during a restart. Optional. The shared libraries will remain loaded at their current

vsim CR-377
positions. User application code in the shared libraries must reset its internal state during
a restart in order for this to work effectively.
We recommend using this option if you’ll be doing warm restores after a restart and the
user application code has set callbacks in the simulator. Otherwise, the callback function
pointers might not be valid if the shared library is loaded into a new position.
-keepstdout
For use with foreign programs. Instructs the simulator to not redirect the stdout stream to
-l <filename>
Saves the contents of the Transcript pane to <filename>. Optional. Default is taken from
the TranscriptFile (UM-534) variable (initially set to transcript) in the modelsim.ini.
-lib <libname>
Specifies the default working library where vsim will look for the design unit(s).
Optional. Default is "work".
<license_option>
Restricts the search of the license manager. Optional. Use one of the following options.
<license_option> Description
-lic_nomgc exclude any MGC licenses from the search
-lic_nomti exclude any MTI licenses from the search
-lic_noqueue do not wait in queue when license is unavailable
-lic_plus checks out ModelSim PLUS (VHDL and Verilog)

license immediately after invocation
-lic_vhdl checks out ModelSim VHDL license immediately after

invocation
-lic_vlog checks out ModelSim VLOG license immediately after
invocation
The options may also be specified with the License (UM-532) variable in the modelsim.ini
file. Note that settings made from the command line are additive to options set in the
License variable.
-load_elab <filename>
Loads an elaboration file that was created with -elab. Optional. See "Simulating with an
-memprof
Causes memory allocation data to be collected during elaboration and simulation.
Optional.
-memprof+file=<filename>
Saves memory profile data to the named file and makes the data available for viewing
and reporting during the current simulation. The file can be used for archival or
comparison purposes. Optional.

CR-378 vsim
-memprof+fileonly=<filename>
Saves memory profile data to the named file only. The file can be read in later with the
profile reload command (CR-230) for analysis. This mode is useful for large designs,
when the design plus internal profiling data would use up too much memory. Optional.
-multisource_delay min | max | latest
Controls the handling of multiple PORT or INTERCONNECT constructs that terminate
at the same port. Optional. By default, the Module Input Port Delay (MIPD) is set to the
max value encountered in the SDF file. Alternatively, you may choose the min or latest
of the values. If you have a Verilog design and want to model multiple interconnect paths
independently, use the +multisource_int_delays argument.
+multisource_int_delays
Enables multisource interconnect delay with pulse handling and transport delay
behavior. Works for both Verilog and VITAL cells. Optional.
Use this argument when you have interconnect data in your SDF file and you want the
delay on each interconnect path modeled independently. Pulse handling is configured
using the +pulse_int_e and +pulse_int_r switches (described below).
The +multisource_int_delays argument cannot be used if you compiled using the
-novital argument to vcom. The -novital argument instructs vcom to implement VITAL
functionality using VHDL code instead of accelerated code, and multisource
interconnect delays cannot be implemented purely within VHDL.
-noassume
Prevents PSL assume directives from being simulated. Optional. This option may also be
specified with the SimulateAssumeDirectives (UM-533) variable in the modelsim.ini file.
See "Processing assume directives in simulation" (UM-363) for more information.
-nocompress
Causes VSIM to create uncompressed checkpoint files. Optional. This option may also
be specified with the CheckpointCompressMode (UM-531) variable in the modelsim.ini
file.
+no_notifier
Disables the toggling of the notifier register argument of all timing check system tasks.
Optional. By default, the notifier is toggled when there is a timing check violation, and
the notifier usually causes a UDP to propagate an X. This argument suppresses X
propagation in both Verilog and VITAL for the entire design. You can suppress X
propagation on individual instances using the tcheck_set command (CR-275).
-nopsl
Instructs ModelSim to ignore any PSL assertions that were compiled with the design. By
default vsim automatically invokes the PSL assertion engine at runtime if any assertions
were compiled with the design.
+no_tchk_msg
Disables error messages generated when timing checks are violated. Optional. For
Verilog, it disables messages issued by timing check system tasks. For VITAL, it
overrides the MsgOn arguments and generics.
Notifier registers are still toggled and may result in the propagation of Xs for timing
check violations. You can disable individual messages using the tcheck_set command
(CR-275).

vsim CR-379
+notimingchecks
Disables Verilog and VITAL timing checks for faster simulation. Optional. By default,
Verilog timing check system tasks ($setup, $hold,...) in specify blocks are enabled. For
VITAL, the timing check default is controlled by the ASIC or FPGA vendor, but most
default to enabled. You can disable individual checks using the tcheck_set command
(CR-275).
-novopt
Prevents ModelSim from running the vopt command (CR-371) automatically. If you have
set the VoptFlow (UM-534) variable to 1 in the modelsim.ini file, vsim will automatically
run vopt if you didn’t invoke it manually. This argument allows you to run ModelSim in
debug mode when the default mode is optimized.
+pulse_int_e/<percent>
Controls how pulses are propagated through interconnect delays, where <percent> is a
number between 0 and 100 that specifies the error limit as a percentage of the
interconnect delay. Optional. Used in conjunction with +multisource_int_delays (see
above). This option works for both Verilog and VITAL cells, though the destination of
the interconnect must be a Verilog cell. The source may be VITAL or Verilog.
A pulse greater than or equal to the error limit propagates to the output in transport mode
(transport mode allows multiple pending transitions on an output). A pulse less than the
error limit and greater than or equal to the rejection limit (see +pulse_int_r/<percent>
below) propagates to the output as an X. If the rejection limit is not specified, then it
defaults to the error limit. For example, consider an interconnect delay of 10 along with
a +pulse_int_e/80 option. The error limit is 80% of 10 and the rejection limit defaults to
80% of 10. This results in the propagation of pulses greater than or equal to 8, while all
other pulses are filtered.
+pulse_int_r/<percent>
Controls how pulses are propagated through interconnect delays, where <percent> is a
number between 0 and 100 that specifies the rejection limit as a percentage of the
interconnect delay. Optional. This option works for both Verilog and VITAL cells,
though the destination of the interconnect must be a Verilog cell. The source may be
VITAL or Verilog.
A pulse less than the rejection limit is filtered. If the error limit is not specified by
+pulse_int_e then it defaults to the rejection limit.
-quiet
Disable 'Loading' messages during batch-mode simulation. Optional.
-restore <filename>
Specifies that vsim is to restore a simulation saved with the checkpoint command (CR-
93).
Optional.
You must restore vsim under the same environment in which you did the checkpoint.
This means not only the same type of machine and OS and at least the same memory size,
but also the same vsim environment such as GUI vs. command line mode.

CR-380 vsim
+sdf_iopath_to_prim_ok
Prevents vsim from issuing an error when it cannot locate specify path delays to annotate.
If you specify this argument, IOPATH statements are annotated to the primitive driving
the destination port if a corresponding specify path is not found. Optional. See "SDF to
Verilog construct matching" (UM-445) for additional information.
-sdfmin | -sdftyp | -sdfmax[@<delayScale>] [<instance>=]<sdf_filename>
Annotates VITAL or Verilog cells in the specified SDF file (a Standard Delay Format
file) with minimum, typical, or maximum timing. Optional.
The optional argument @<delayScale> scales all values by the specified value. For
example, if you specify -sdfmax@1.5..., all maximum values in the SDF file will be
scaled to 150% of their original value.
The use of [<instance>=] with <sdf_filename> is also optional; it is used when the
backannotation is not being done at the top level. See "Specifying SDF files for
simulation" (UM-440).
-sdfmaxerrors <n>
Controls the number of Verilog SDF missing instance messages that will be emitted
before terminating vsim. Optional. <n> is the maximum number of missing instance
error messages to be emitted. The default number is 5.
-sdfnoerror
Errors issued by the SDF annotator while loading the design prevent the simulation from
continuing, whereas warnings do not. Changes SDF errors to warnings so that the
simulation can continue. Optional.
-sdfnowarn
Disables warnings from the SDF reader. Optional. See Chapter 4 - VHDL simulation for
an additional discussion of SDF.
+sdf_verbose
Turns on the verbose mode during SDF annotation. The Transcript pane provides
detailed warnings and summaries of the current annotation. Optional.
information.
-t [<multiplier>]<time_unit>
Specifies the simulator time resolution. Optional. <time_unit> must be one of the
following:
fs, ps, ns, us, ms, sec
The default is 1ns; the optional <multiplier> may be 1, 10 or 100. Note that there is no
space between the multiplier and the unit (i.e., 10fs, not 10 fs).
If you omit the -t argument, the default time resolution depends on design type: in a
Verilog design with ‘timescale directives, the minimum time precision is used (see
"Simulator resolution limit" (UM-129) for further details); in Verilog designs without any
timescale directives, or in a VHDL or mixed design, the value specified for the
Resolution (UM-533) variable in the modelsim.ini file is used.

vsim CR-381
Once you’ve begun simulation, you can determine the current simulator resolution by
invoking the report command (CR-244) with the simulator state option.
-tag <string>
Specifies a string tag to append to foreign trace filenames. Optional. Used with the
-trace_foreign <int> option. Used when running multiple traces in the same directory.
See the ModelSim FLI Reference for more information.
-title <title>
Specifies the title to appear for the ModelSim Main window. Optional. If omitted the
current ModelSim version is the window title. Useful when running multiple
simultaneous simulations. Text strings with spaces must be in quotes (e.g., "my title").
-trace_foreign <int>
Creates two kinds of foreign interface traces: a log of what functions were called, with
the value of the arguments, and the results returned; and a set of C-language files to
replay what the foreign interface side did.
The purpose of the logfile is to aid the debugging of your FLI/PLI/VPI code. The primary
purpose of the replay facility is to send the replay file to MTI support for debugging co-
simulation problems, or debugging problems for which it is impractical to send the FLI/
PLI/VPI code. See the ModelSim FLI Reference for more information.
+transport_int_delays
Selects transport mode with pulse control for single-source nets (one interconnect path).
Optional. By default interconnect delays operate in inertial mode (pulses smaller than the
delay are filtered). In transport mode, narrow pulses are propagated through interconnect
delays.
This option works for both Verilog and VITAL cells, though the destination of the
interconnect must be a Verilog cell. The source may be VITAL or Verilog. This option
works independently from +multisource_int_delays.
-vcdstim [<instance>=]<filename>
Specifies a VCD file from which to re-simulate the design. Optional. The VCD file must
have been created in a previous ModelSim simulation using the vcd dumpports
command (CR-295). See "Using extended VCD as stimulus" (UM-458) for more
information.
-version
Returns the version of the simulator as used by the licensing tools, such as "Model
Technology ModelSim SE vsim 5.5 Simulator 2000.01 Jan 28 2000".
-view [<dataset_name>=]<WLF_filename>
Specifies a wave log format (WLF) file for vsim to read. Allows you to use vsim to view
the results from an earlier simulation. The Structure, Objects, Wave, and List windows
can be opened to look at the results stored in the WLF file (other ModelSim windows will
not show any information when you are viewing a dataset). See additional discussion in
"Examples" (CR-391).
-vopt
Instructs vsim to run the vopt command (CR-371) automatically if vopt wasn’t manually
invoked. Optional. You can make this the default behavior. See "Making the optimized
flow the default" (UM-125) for more information.

CR-382 vsim
-voptargs="<args>"
Specifies arguments that vsim should pass to vopt (CR-371) when running vopt
automatically (see "Making the optimized flow the default" (UM-125)). The primary
purpose of this argument is to pass +acc arguments. Optional.
-wlf <filename>
Specifies the name of the wave log format (WLF) file to create. The default is vsim.wlf.
Optional. Corresponding .ini file entry is WLFFilename.
-wlfcollapsedelta
Instructs ModelSim to record values in the WLF file only at the end of each simulator
delta step. Any sub-delta values are ignored. May dramatically reduce WLF file size.
This option may also be specified with the WLFCollapseMode (UM-534) variable in the
modelsim.ini file. Default.
-wlfcollapsetime
Instructs ModelSim to record values in the WLF file only at the end of each simulator
time step. Any delta or sub-delta values are ignored. May dramatically reduce WLF file
size. This option may also be specified with the WLFCollapseMode (UM-534) variable in
the modelsim.ini file. Optional.
-wlfcompress
Creates compressed WLF files. Default. Use -wlfnocompress to turn off compression.
-wlfopt
Optimizes the display of waveforms in the Wave window. Default. Optional. WLF files
created prior to ModelSim version 5.8 cannot take advantage of the optimization. This
option may also be specified with the WLFOptimize (UM-535) variable in the
modelsim.ini file.
-wlfnocollapse
Instructs ModelSim to preserve all events and event order. May result in relatively larger
WLF files. This option may also be specified with the WLFCollapseMode (UM-534)
variable in the modelsim.ini file. Optional.
-wlfnocompress
Causes vsim to create uncompressed WLF files. Optional. Beginning with version 5.5,
WLF files are compressed by default in order to reduce file size. This may slow
simulation speed by one to two percent. You may want to disable compression to speed
up simulation or if you are experiencing problems with faulty data in the resulting WLF
file. This option may also be specified with the WLFCompress (UM-535) variable in the
modelsim.ini file.
-wlfnoopt
Disables optimization of waveform display in the Wave window. Optional.
Corresponding .ini file entry is WLFOptimize.
-wlfslim <size>
Specifies a size restriction in megabytes for the event portion of the WLF file. Optional.
The default is infinite size (0). The <size> must be an integer.

vsim CR-383
Note that a WLF file contains event, header, and symbol portions. The size restriction is
placed on the event portion only. When ModelSim exits, the entire header and symbol
portion of the WLF file is written. Consequently, the resulting file will be larger than the
size specified with -wlfslim.
If used in conjunction with -wlftlim, the more restrictive of the limits takes precedence.
This option may also be specified with the WLFSizeLimit (UM-535) variable in the
modelsim.ini file.

CR-384 vsim
-wlftlim <duration>
Specifies the duration of simulation time for WLF file recording. Optional. The default
is infinite time (0). The <duration> is an integer of simulation time at the current
resolution; you can optionally specify the resolution if you place curly braces around the
specification. For example,
{5000 ns}
sets the duration at 5000 nanoseconds regardless of the current simulator resolution.
The time range begins at the current simulation time and moves back in simulation time
for the specified duration. For example,
vsim -wlftlim 5000
writes at least the last 5000ns of the current simulation to the WLF file (the current
simulation resolution in this case is ns).
If used in conjunction with -wlfslim, the more restrictive of the limits will take effect.
This option may also be specified with the WLFTimeLimit (UM-535) variable in the
modelsim.ini file.
The -wlfslim and -wlftlim switches were designed to help users limit WLF file sizes for
long or heavily logged simulations. When small values are used for these switches, the
values may be overridden by the internal granularity limits of the WLF file format.
Arguments, VHDL
-absentisempty
Causes VHDL files opened for read that target non-existent files to be treated as empty,
rather than ModelSim issuing fatal error messages. Optional.
-foreign <attribute>
Specifies the foreign module to load. Optional. <attribute> is a quoted string consisting
of the name of a C function and a path to a shared library. For example,
vsim -foreign "c_init for.sl"
You can load up to ten foreign modules. Syntax for the attribute is further described in
the Introduction chapter of the ModelSim FLI Reference.
-nocollapse
Disables the optimization of internal port map connections. Optional.
-nofileshare
Turns off file descriptor sharing. Optional. By default ModelSim shares a file descriptor
for all VHDL files opened for write or append that have identical names.
-noglitch
Disables VITAL glitch generation. Optional.
See Chapter 4 - VHDL simulation for additional discussion of VITAL.
+no_glitch_msg
Disable VITAL glitch error messages. Optional.
-std_input <filename>
Specifies the file to use for the VHDL TextIO STD_INPUT file. Optional.

vsim CR-385
-std_output <filename>
Specifies the file to use for the VHDL TextIO STD_OUTPUT file. Optional.
-strictvital
Specifies to exactly match the VITAL package ordering for messages and delta cycles.
Optional. Useful for eliminating delta cycle differences caused by optimizations not
addressed in the VITAL LRM. Using this argument negatively impacts simulator
performance.
-vcdread <filename>
Simulates the VHDL top-level design from the specified VCD file. Optional. This
argument is included for backwards compatibility. Resimulations in ModelSim versions
5.5c and newer should use the -vcdstim argument. See "Simulating with input values
from a VCD file" (UM-458) for more details.
-vital2.2b
Selects SDF mapping for VITAL 2.2b (default is VITAL 2000). Optional.
Arguments, Verilog
+alt_path_delays
Configures path delays to operate in inertial mode by default. Optional. In inertial mode,
a pending output transition is cancelled when a new output transition is scheduled. The
result is that an output may have no more than one pending transition at a time, and that
pulses narrower than the delay are filtered. The delay is selected based on the transition
from the cancelled pending value of the net to the new pending value. The
+alt_path_delays option modifies the inertial mode such that a delay is based on a
transition from the current output value rather than the cancelled pending value of the net.
This option has no effect in transport mode (see +pulse_e/<percent> and
+pulse_r/<percent>).
+delayed_timing_checks
Causes timing checks to be performed on the delayed versions of input ports (used when
there are negative timing check limits). Optional.
-dpiexportobj <objfile>
Generate specified DPI export object file. Required only for Windows, RS6000, and
RS64 platforms.
-extend_tcheck_data_limit <percent>
-extend_tcheck_ref_limit <percent>
Causes a one-time extension of qualifying data or reference limits in an attempt to
provide a delay net solution prior to any limit zeroing. A limit qualifies if it bounds a
violation region which does not overlap a related violation region.
<percent> is the maximum percent of limit relaxation.
-hazards
Enables event order hazard checking in Verilog modules. Optional. You must also
specify this argument when you compile your design with vlog (CR-358). See "Hazard
detection" (UM-135) for more details.
Important: Enabling -hazards implicitly enables the -compat argument. As a result,

using this argument may affect your simulation results.

CR-386 vsim
+int_delays
Optimizes annotation of interconnect delays for designs that have been compiled using
-fast (see vlog command (CR-358)). Optional. This argument causes vsim to insert
"placeholder" delay elements at optimized cell inputs, resulting in faster backannotation
of interconnect delays from an SDF file.
-L <library_name> ...
Specifies the library to search for design units instantiated from Verilog. See "Library
usage" (UM-117) for more information. If multiple libraries are specified, each must be
preceded by the -L option. Libraries are searched in the order in which they appear on
the command line.
-Lf <library_name> ...
Same as -L but libraries are searched before ‘uselib directives. See "Library usage" (UM-
for more information. Optional.
117)
+maxdelays
Selects the maximum value in min:typ:max expressions. Optional. The default is the
typical value. Has no effect if you specified the min:typ:max selection at compile time.
+mindelays
Selects the minimum value in min:typ:max expressions. Optional. The default is the
typical value. Has no effect if you specified the min:typ:max selection at compile time.
+no_cancelled_e_msg
Disables negative pulse warning messages. Optional. By default vsim issues a warning
and then filters negative pulses on specify path delays. You can drive an X for a negative
pulse using +show_cancelled_e.
+no_neg_tchk
Disables negative timing check limits by setting them to zero. Optional. By default
negative timing check limits are enabled. This is just the opposite of Verilog-XL, where
negative timing check limits are disabled by default, and they are enabled with the
+neg_tchk option.
+no_notifier
Disables the toggling of the notifier register argument of all timing check system tasks.
Optional. By default, the notifier is toggled when there is a timing check violation, and
the notifier usually causes a UDP to propagate an X. This argument suppresses X
propagation on timing violations for the entire design. You can suppress X propagation
on individual instances using the tcheck_set command (CR-275).
+no_path_edge
Causes ModelSim to ignore the input edge specified in a path delay. Optional. The result
of this argument is that all edges on the input are considered when selecting the output
delay. Verilog-XL always ignores the input edges on path delays.
+no_pulse_msg
Disables the warning message for specify path pulse errors. Optional. A path pulse error
occurs when a pulse propagated through a path delay falls between the pulse rejection
limit and pulse error limit set with the +pulse_r and +pulse_e options. A path pulse error
results in a warning message, and the pulse is propagated as an X. The +no_pulse_msg
option disables the warning message, but the X is still propagated.

vsim CR-387
-no_risefall_delaynets
Disables the rise/fall delay net delay negative timing check algorithm. Optional. This
argument is provided to return ModelSim to its pre-6.0 behavior where violation regions
must overlap in order to find a delay net solution. In 6.0 versions and later, ModelSim
uses separate rise/fall delays, so violation regions need not overlap for a delay solution
to be found.
+no_show_cancelled_e
Filters negative pulses on specify path delays so they don’t show on the output. Default.
Use +show_cancelled_e to drive a pulse error state.
+no_tchk_msg
Disables error messages issued by timing check system tasks when timing check
violations occur. Optional. Notifier registers are still toggled and may result in the
propagation of Xs for timing check violations. You can disable individual messages
using the tcheck_set command (CR-275).
+nosdferror
Errors issued by the SDF annotator while loading the design prevent the simulation from
continuing, whereas warnings do not. Changes SDF errors to warnings so that the
simulation can continue. Optional.
+nosdfwarn
Disables warnings from the SDF annotator. Optional.
+nospecify
Disables specify path delays and timing checks. Optional.
+nowarn<CODE>
Disables warning messages in the category specified by <CODE>. Optional. Warnings
that can be disabled include the <CODE> name in square brackets in the warning
message. For example:
** Warning: (vsim-3017) test.v(2): [TFMPC] - Too few port connections.
Expected <m>, found <n>.
This warning message can be disabled with +nowarnTFMPC.
+ntc_warn
Enables warning messages from the negative timing constraint algorithm. Optional. By
default, these warnings are disabled.
This algorithm attempts to find a set of delays for the timing check delayed net arguments
such that all negative limits can be converted to non-negative limits with respect to the
delayed nets. If there is no solution for this set of limits, then the algorithm sets one of
the negative limits to zero and recalculates the delays. This process is repeated until a
solution is found. A warning message is issued for each negative limit set to zero.

CR-388 vsim
-pli "<object list>"

Loads a space-separated list of PLI shared objects. Optional. The list must be quoted if it
contains more than one object. This is an alternative to specifying PLI objects in the
Veriuser entry in the modelsim.ini file, see "Preference variables located in INI files"
(UM-524). You can use environment variables as part of the path.
+<plusarg>
Arguments preceded with "+" are accessible by the Verilog PLI routine
mc_scan_plusargs(). Optional.
+pulse_e/<percent>
Controls how pulses are propagated through specify path delays, where <percent> is a
number between 0 and 100 that specifies the error limit as a percentage of the path delay.
Optional.
A pulse greater than or equal to the error limit propagates to the output in transport mode
(transport mode allows multiple pending transitions on an output). A pulse less than the
error limit and greater than or equal to the rejection limit (see +pulse_r/<percent>)
propagates to the output as an X. If the rejection limit is not specified, then it defaults to
the error limit. For example, consider a path delay of 10 along with a +pulse_e/80 option.
The error limit is 80% of 10 and the rejection limit defaults to 80% of 10. This results in
the propagation of pulses greater than or equal to 8, while all other pulses are filtered.
Note that you can force specify path delays to operate in transport mode by using the
+pulse_e/0 option.
+pulse_e_style_ondetect
Selects the "on detect" style of propagating pulse errors (see +pulse_e). Optional. A
pulse error propagates to the output as an X, and the "on detect" style is to schedule the
X immediately, as soon as it has been detected that a pulse error has occurred. "on event"
style is the default for propagating pulse errors (see +pulse_e_style_onevent).
+pulse_e_style_onevent
Selects the "on event" style of propagating pulse errors (see +pulse_e). Default. A pulse
error propagates to the output as an X, and the "on event" style is to schedule the X to
occur at the same time and for the same duration that the pulse would have occurred if it
had propagated through normally.
+pulse_r/<percent>
Controls how pulses are propagated through specify path delays, where <percent> is a
number between 0 and 100 that specifies the rejection limit as a percentage of the path
delay. Optional.
A pulse less than the rejection limit is suppressed from propagating to the output. If the
error limit is not specified by +pulse_e then it defaults to the rejection limit.
+sdf_nocheck_celltype
Disables the error check a for mismatch between the CELLTYPE name in the SDF file
and the module or primitive name for the CELL instance. It is an error if the names do
not match. Optional.
+show_cancelled_e
Drives a pulse error state (’X’) for the duration of a negative pulse on a specify path
delay. Optional. By default ModelSim filters negative pulses.

vsim CR-389
-sv_lib <shared_obj>
Specifies the name of the DPI shared object with no extension. Required for use with DPI
import libraries.
-sv_liblist <filename>
Specifies the name of a bootstrap file containing names of DPI shared objects to load.
Optional.
-sv_root <dirname>
Specifies the directory name to be used as the prefix for DPI shared object lookups.
Optional.
+transport_path_delays
Selects transport mode for path delays. Optional. By default, path delays operate in
inertial mode (pulses smaller than the delay are filtered). In transport mode, narrow
pulses are propagated through path delays. Note that this option affects path delays only,
and not primitives. Primitives always operate in inertial delay mode.
+typdelays
Selects the typical value in min:typ:max expressions. Default. Has no effect if you
specified the min:typ:max selection at compile time.
-v2k_int_delays
Causes interconnect delays to be visible at the load module port per the IEEE 1364-2001
spec. Optional. By default ModelSim annotates INTERCONNECT delays in a manner
compatible with Verilog-XL. If you have $sdf_annotate() calls in your design that are not
getting executed, add the Verilog task $sdf_done() after your last $sdf_annotate() to
remove any zero-delay MIPDs that may have been created (see "ModelSim Verilog
system tasks and functions" (UM-152) for more information). May be used in tandem with
the +multisource_int_delays argument (see above).
Arguments, SystemC
-sclib
Specifies the design library where the SystemC shared library is created. By default, the
SystemC shared library is created in the logical work library. This option is only
necessary when the shared library is compiled in a design library other than the logical
work directory (via sccom -link -work <lib>). For more information on the sccom -link
and -work arguments, see sccom (CR-254).
-sc_arg <string> ...
Specifies a string representing a startup argument which is subsequently accessible from
within SystemC via the sc_argc() and sc_argv() functions (see "Accessing command-line
arguments" (UM-183).
If multiple SystemC startup arguments are specified, each must have a separate -sc_arg
argument. SystemC startup arguments returned via sc_argv() are in the order in which
they appear on the command line. White space within the <string> will not be treated
specially, and the string, white space and all, will be accessible as a single string among
the strings returned by sc_argv().

CR-390 vsim
Arguments, object
The object arguments may be a [<library_name>].<design_unit>, a .mpf file, a .wlf file, or
a text file. Multiple design units may be specified for Verilog modules and mixed VHDL/
Verilog configurations.
<library_name>.<design_unit>
Specifies a library and associated design unit; multiple library/design unit specifications
can be made. Optional. If no library is specified, the work library is used. Environment
variables can be used. <design_unit> may be one of the following:
<configuration> Specifies the VHDL configuration to simulate.

<module> ... Specifies the name of one or more top-level Verilog
modules to be simulated. Optional.
<entity> [(<architecture>)] Specifies the name of the top-level VHDL entity to be
simulated. Optional. The entity may have an
architecture optionally specified; if omitted the last
architecture compiled for the specified entity is
simulated. An entity is not valid if a configuration is
specified.a
<optimized_design_name> Specifies the name of an optimized design. See the
vopt command (CR-371). Optional.
a.Most UNIX shells require arguments containing () to be single-quoted to prevent

special parsing by the shell. See the examples below.
<MPF_file_name>
Opens the specified project. Optional.
<WLF_file_name>
Opens the specified dataset. Optional.
<text_file_name>
Opens the specified text file in a Source window. Optional.

vsim CR-391
Examples
vsim -gedge=’"low high"’ -gVCC=4.75 cpu
Invokes vsim on the entity cpu and assigns values to the generic parameters edge and
VCC. If working within the ModelSim GUI, you would enter the command as follows:
vsim {-gedge="low high"} -gVCC=4.75 cpu
vsim -view test=sim2.wlf

Instructs ModelSim to view the results of a previous simulation run stored in the WLF
file sim2.wlf. The simulation is displayed as a dataset named test. Use the -wlf option to
specify the name of the WLF file to create if you plan to create many files for later
viewing. For example:
vsim -wlf my_design.i01 my_asic structure
vsim -wlf my_design.i02 my_asic structure
vsim -sdfmin /top/u1=myasic.sdf

Annotates instance /top/u1 using the minimum timing from the SDF file myasic.sdf.
Use multiple switches to annotate multiple instances:
vsim -sdfmin /top/u1=sdf1 -sdfmin /top/u2=sdf2 top
vsim ’mylib.top(only)’ gatelib.cache_set

This example searches the libraries mylib for top(only) and gatelib for cache_set. If the
design units are not found, the search continues to the work library. Specification of the
architecture (only) is optional.
vsim -do "set PrefMain(forceQuit) 1; run -all" work.test_counter
Invokes vsim on test_counter and instructs the simulator to run until a break event and
quit when it encounters a $finish task.

CR-392 vsim<info>
vsim<info>
The vsim<info> commands return information about the current vsim executable.
vsimAuth
Returns the authorization level (PE/SE, VHDL/Verilog/PLUS).
vsimDate
Returns the date the executable was built, such as "Apr 10 2000".
vsimId
Returns the identifying string, such as "ModelSim 5.4".
vsimVersion
Returns the version as used by the licensing tools, such as "1999.04".
vsimVersionString
Returns the full vsim version string.
This same information can be obtained using the -version argument of the vsim command
(CR-373).

vsource CR-393
vsource
The vsource command specifies an alternative file to use for the current source file. This
command is used when the current source file has been moved. The alternative source
mapping exists for the current simulation only.
Syntax
vsource
[<filename>]
Arguments
<filename>
Specifies a relative or full pathname. Optional. If filename is omitted the source file for
the current design context is displayed.
Examples
vsource design.vhd
vsource /old/design.vhd

CR-394 wave
wave
A number of wave commands can be use to manipulate the Wave window. The following
tables summarize the available options for manipulating cursors, for zooming, and for
adjusting the wave display view in the Wave window:
Cursor Commands Description

wave activecursor Sets the active cursor to the specified cursor or, if no cursor is
specified, reports the active cursor
wave addcursor Adds a new cursor at specified time and returns the number of the
newly added cursor
wave cursortime Moves or reports the time of the specified cursor or, if no cursor
is specified, the time of the active cursor
wave deletecursor Deletes the specified cursor or, if no cursor is specified, the active
cursor
wave seecursor Positions the wave display such that the specified or active cursor
appears at the specified percent from the left edge of the display
– 0% is the left edge, 100% is the right edge.
Zooming Description
Commands
wave zoomin Zoom in the wave display by the specified factor. The default
factor is 2.0.
wave zoomout Zoom out the wave display by the specified factor. The default
factor is 2.0.
wave zoomfull Zoom the wave display to show the full simulation time.
wave zoomlast Return to last zoom range.
wave zoomrange Sets left and right edge of wave display to the specified start time
and end time. If times are not specified, reports left and right edge
times.
Display view Description

Commands
wave interrupt Immediately stops wave window drawing
wave refresh Cleans wave display and redraws waves
wave seecursor Positions the wave display such that the specified or active cursor
appears at the specified percent from the left edge of the display
– 0% is the left edge, 100% is the right edge.

wave CR-395
Display view Description

Commands
wave seetime Positions the wave display such that the specified time appears at
the specified percent from the left edge of the display – 0% is the
left edge, 100% is the right edge.
Syntax
wave activecursor
[-window <win>] [<cursor-num>]
wave addcursor
[-window <win>] [-time <time>]
wave cursortime
[-window <win>] [-time <time>] [<cursor-num>]
wave deletecursor
[-window <win>] [<cursor-num>]
wave interrupt
[-window <win>]
wave refresh
[-window <win>]
wave seecursor
[-window <win>] [-at <percent>] [<cursor-num>]
wave seetime
[-window <win>] [-at <percent>] <time>
wave zoomin
[-window <win>] [<factor>]
wave zoomout
[-window <win>] [<factor>]
wave zoomfull
[-window <win>]
wave zoomlast
[-window <win>]
wave zoomrange
[-window <win>] [<start-time>] [<end-time>]
Arguments
[-window <win>]
All commands default to the active Wave window unless this argument is used to specify
a different Wave window. Optional.
[<cursor-num>]
Specifies a cursor number. Optional.

CR-396 wave
[-time <time>]
Specifies a time. Optional.
[<factor>]
A number that specifies how much you want to zoom into or out of the wave display.
Optional. Default value is 2.0.
[<start-time>]
[<end-time>]
start-time and end-time are times that specify a zoom range. If neither number is
specified, the command returns the current zoom range. If only one time is specified, then
the zoom range is set to start at 0 and end at specified time.
[-at <percent>]
Positions the display such that the time or cursor is the specified <percent> from the left
edge of the wave display. 0% is the left edge; 100% is the right edge. Optional. Default
is 50%.
Examples
wave zoomrange 20ns 100ns
wave zoomrange 20 100
Either of these commands creates a zoom range with a start time of 20 ns and an end time
of 100 ns.

wave create CR-397
wave create
{The wave create command generates a waveform known only to the GUI. You can then
modify the waveform interactively and use the results to drive simulation. See Chapter 10
- Generating stimulus with Waveform Editor for more information.
Syntax
wave create
[-driver freeze|deposit|driver|expectedoutput] [-endtime <time>]
[-initialvalue <value>] [-language VHDL|Verilog]
-pattern clock|constant|random|repeater|counter|none
[-portmode in|out|inout|input|output|internal]
[-starttime <time>] <object_name>
-period <value> -dutycycle <value>
-value <value>
-period <value> -random_type <value>

[-seed <value>]
-sequence {val1 val2 val3 ...} -period <value>

-repeat forever|never|<#_of_times>
-direction <value> -type Binary|Range|Johnson|OneHot|ZeroHot|Gray

-endvalue <value> -period <value> -repeat forever|never|<#_of_times>
-startvalue <value> -step <value>
The arguments below are grouped according to waveform pattern. The first set applies to
all waveforms regardless of pattern.
Arguments for all waveforms

-driver freeze|deposit|driver|expectedoutput
Specifies that the signal is a driver of the specified type. Applies to signals of type inout
or internal. Optional.
-endtime <time>
The simulation time that the waveform should stop. If omitted, the waveform stops at
1000 simulation time units. Optional.
-initialvalue <value>
The initial value for the waveform. Value must be appropriate for the type of waveform
you are creating. Not applicable to counter patterns. Optional.
-language VHDL|Verilog
The language for the created wave. By default ModelSim uses VHDL to create the
waveform. Optional.
-pattern clock|constant|random|repeater|counter|none
The pattern for the created waveform. See "Creating waveforms from patterns" (GR-289)
for a description of the pattern types. Required.
-portmode in|out|inout|input|output|internal
The port type for the created waveform. ModelSim uses internal by default. Useful for
creating signals prior to loading a design. Optional.

CR-398 wave create
-starttime <time>
The simulation time at which the waveform should start. If omitted, the waveform starts
at 0 simulation time units. Optional.
<object_name>
The name of the created waveform. Required.
Arguments, clock patterns only

-dutycycle <value>
The duty cycle of the clock, which is the percentage of the period that the clock is high
or low. Acceptable values range from 0 to 100. Required.
-period <value>
The period of the signal. Required.
Arguments, constant patterns only

-value <value>
The value for the constant. Required.
Arguments, random patterns only

-period <value>
The period after which the value should change. Required.
-random_type <value>
The type of random pattern to generate. Required. Choices for <value> include Normal,
Uniform, Poisson, or Exponential.
-seed <value>
A seed value for the random generator. If omitted, ModelSim uses the value 5. Optional.
Arguments, repeater patterns only

-period <value>
The number of times to repeat. Required.
-sequence {val1 val2 val3 ...}
The set of values that you want repeated. Required.
Arguments, counter patterns only

-direction <value>
The direction which the counter should increment or decrement. Optional. The default is
Up. Choices for <value> include Up, Down, UpThenDown, and DownThenUp.
-type Binary|Range|Johnson|OneHot|ZeroHot|Gray
The type of counter to create. Default is Range. Optional.

wave create CR-399
-endvalue <value>
The ending value of the counter. This option applies to Range counter patterns only. All
other counter patterns start from 0 and go to the max value for that particular signal (e.g.,
for a 3-bit signal, the start value will be 000 and end value will be 111).
-period <value>
-startvalue <value>
The starting value of the counter. This option applies to Range counter patterns only. All
-step <value>
The step by which the counter is incremented/decremented. Required.
Examples
wave create -pattern /counter/clk
Creates a clock signal with the following default values: -period 100 -dutycycle 50
-starttime 0 -endtime 1000 -initialvalue 0
wave create -driver freeze -pattern constant -value 1111 -starttime 0ns -
endtime 1000ns sim:/andm/v_cont2
Creates a constant signal from 0 to 1000 ns with a value of 1111 and a drive type of
freeze.
See also
wave edit command (CR-400), wave modify command (CR-405), Chapter 10 - Generating
stimulus with Waveform Editor

CR-400 wave edit
wave edit
The wave edit command modifies waveforms created with the wave create command. See
the ModelSim Command Reference for syntax. The following table summarizes the
available editing options:
Command Description
wave edit cut Cut part of a waveform to the clipboard
wave edit copy Copy part of a waveform to the clipboard
wave edit paste Paste the waveform from the clipboard
wave edit invert Vertically flip part of a waveform

wave edit mirror Mirror part of a waveform
wave edit insert_pulse Insert a new edge on a waveform; doesn’t affect waveform
duration
wave edit delete Delete an edge from a waveform; doesn’t affect waveform
duration
wave edit stretch Move an edge by stretching the waveform
wave edit move Move an edge without moving other edges
wave edit change_value Change the value of part of a waveform

wave edit extend Extend all waves
wave edit driveType Change the driver type
wave edit undo Undo an edit
wave edit redo Redo a previously undone edit
Syntax
wave edit cut|copy|paste|invert|mirror
[-end <time>] -start <time> <object_name>
wave edit insert_pulse

[-duration <time>] -start <time> <object_name>
wave edit delete

-time <time> <object_name>
wave edit stretch|move

-backward <time>|-forward <time> -time <time> <object_name>
wave edit change_value

-end <time> -start <time> <value> <object_name>
wave edit extend

-extend to|by -time <time>

wave edit CR-401
wave edit extend

-extend to|by -time <time>
wave edit driveType

-driver freeze|deposit|driver|expectedoutput -end <time> -start <time>
The arguments below are grouped by editing operation. Many operations share similar
arguments.
Arguments for cut, copy, paste, invert, and mirror

-end <time>
The end of the section of waveform to perform the editing operation upon, denoted by a
simulation time. Optional for paste.
-start <time>
The beginning of the section of waveform to perform the editing operation upon, denoted
by a simulation time. Required.
<object_name>
The pathname of the waveform to edit. Required.
Arguments for insert_pulse

-duration <time>
The length of the pulse. Default is 10 time units. Optional.
-start <time>
The time at which the new pulse should be inserted. Required.
<object_name>
The pathname of the waveform on which you are inserting a pulse. Required.
Arguments for delete

-time <time>
The time at which the edge to delete occurs. Required.
<object_name>
The pathname of the waveform for which you are deleting an edge. Required.
Arguments for stretch and move

-backward <time>
The amount to stretch or move the edge backwards in simulation time. Required if
-forward <time> isn’t specified.
-forward <time>
The amount to stretch or move the edge forwards in simulation time. Required if
-backward <time> isn’t specified.
-time <time>
The time at which the edge to stretch or move occurs. Required.
<object_name>
The pathname of the waveform on which you are stretching or moving an edge.
Required.

CR-402 wave edit
Arguments for change_value

-end <time>
The end of the section of waveform of which you are changing the value. Required.
-start <time>
The beginning of the section of waveform of which you are changing the value.
Required.
<value>
The new value. Must match the type of the <object_name>. Required.
<object_name>
The pathname of the waveform on which you are changing a value. Required.
Arguments for extend

-extend to|by
Specify whether you are extending waves to a specific time or by a certain amount of
time. Required.
-time <time>
The time to extend waves to or the amount by which to extend the waves. Required.
Arguments for driveType

The type of driver to which you want the specified section of the waveform changed.
Required.
-end <time>
The end of the section of waveform of which you are changing the drive type. Required.
-start <time>
The beginning of the section of waveform of which you are changing the drive type.
Required.
Arguments for undo and redo

<number>
The number of editing operations to undo or redo. If omitted, only one editing operation
is undone or redone. Optional.
See also
wave create command (CR-397), Chapter 10 - Generating stimulus with Waveform Editor

wave export CR-403
wave export
The wave export command creates a stimulus file from waveforms created with the wave
create command.
Syntax
wave export
[-designunit <name>] [-end <time>] -file <name>
-format force|vcd|vhdl|verilog [-start <time>]
Arguments
-designunit <name>
The name of the design unit for which you want to export created waves. If omitted, the
command exports waves from the active design unit. Optional.
-end <time>
The simulation time at which you want to stop exporting. Required.
-file <name>
The filename for the saved stimulus file. Required.
-format force|vcd|vhdl|verilog
The format of the saved stimulus file. Required. The format options include:
force - A Tcl script that recreates the waveforms. The file should be sourced when
reloading the simulation.
vcd - An extended VCD file. Load using the -vcdstim argument to vsim.
vhdl - A VHDL testbench. Compile and load the file as your top-level design unit.
verilog - A Verilog testbench. Compile and load the file as your top-level design unit.
-start <time>
The simulation time at which you want to start exporting. Required.
See also
wave create command (CR-397), wave import command (CR-404), Chapter 10 -
Generating stimulus with Waveform Editor

CR-404 wave import
wave import
The wave import command imports an extended VCD file that was created with the wave
export command. It cannot read extended VCD file created by software other than
ModelSim. Use this command to apply a VCD file as stimulus to the current simulation.
Syntax
wave import
<VCD_file>
Arguments
<VCD_file>
The name of the extended VCD file to import. Required.
See also
wave create command (CR-397), wave export command (CR-403), Chapter 10 - Generating
stimulus with Waveform Editor

wave modify CR-405
wave modify
The wave modify command modifies waveform parameters set by a previous wave create
command.
Syntax
wave modify
<wave_name> [-driver freeze|deposit|driver|expectedoutput]
[-endtime <time>] [-initialvalue <value>]
-pattern clock|random|repeater|counter|none [-starttime <time>]
-period <value> -dutycycle <value>
-period <value> -random_type Normal|Uniform

[-seed <value>]
-period <value> -repeat forever|never|<#_of_times>

-direction down|up -type Binary|Range|Johnson|OneHot|ZeroHot|Gray

-endvalue <value> -period <value> -repeat forever|never|<#_of_times>
-startvalue <value> -step <value>
Arguments for all waveforms

<wave_name>
The name of an existing waveform created with the wave create command (CR-397).
Required.
Specifies that the signal is a driver of the specified type. Applies to signals of type inout
or internal. Optional.
-endtime <time>
The simulation time that the waveform should stop. If omitted, the waveform stops at
1000 simulation time units. Optional.
-initialvalue <value>
The initial value for the waveform. Value must be appropriate for the type of waveform
you are creating. Not applicable to counter patterns. Optional.
-pattern clock|random|repeater|counter|none
The pattern for the created waveform. See "Creating waveforms from patterns" (GR-289)
for a description of the pattern types. Required.
-starttime <time>
The simulation time that the waveform should start. If omitted, the waveform starts at 0
simulation time units. Optional.
Arguments, clock patterns only

-period <value>
The period of the signal. Required.

CR-406 wave modify
-dutycycle <value>
The duty cycle of the clock, which is the percentage of the period that the clock is high
or low. Acceptable values range from 0 to 100. Required.
Arguments, random patterns only

-period <value>
-random_type Normal|Uniform
The type of random pattern to generate. Required.
-seed <value>
A seed value for the random generator. If omitted, ModelSim uses the value 5. Optional.
Arguments, repeater patterns only

-period <value>
The set of values that you want repeated. Required.
Arguments, counter patterns only

-direction down|up
The direction which the counter should increment or decrement. Optional. The default is
up.
-type Binary|Range|Johnson|OneHot|ZeroHot|Gray
The type of counter to create. Default is Range. Optional.
-endvalue <value>
The ending value of the counter. This option applies to Range counter patterns only. All
-period <value>
-startvalue <value>
The starting value of the counter. This option applies to Range counter patterns only. All
-step <value>
The step by which the counter is incremented/decremented. Required.
See also
wave create command (CR-397), Chapter 10 - Generating stimulus with Waveform Editor

when CR-407
when
The when command instructs ModelSim to perform actions when the specified conditions
are met. For example, you can use the when command to break on a signal value or at a
specific simulator time (see "Time-based breakpoints" (CR-411)). Use the nowhen
command (CR-213) to deactivate when commands.
The when command uses a when_condition_expression to determine whether or not to
perform the action. Conditions can include the following HDL objects: VHDL signals, and
Verilog nets and registers. The when_condition_expression uses a simple restricted
language (that is not related to Tcl), which permits only four operators and operands that
may be either HDL object names, signame’event, or constants. ModelSim evaluates the
condition every time any object in the condition changes, hence the restrictions.
Here are some additional points to keep in mind about the when command:
• The when command creates the equivalent of a VHDL process or a Verilog always block.
It does not work like a looping construct you might find in other languages such as C.
• Virtual signals, functions, regions, types, etc. cannot be used in the when command.
Neither can simulator state variables other than $now.
• With no arguments, when will list the currently active when statements and their labels
(explicit or implicit).
Syntax
when
[[-label <label>] [-id <id#>] {<when_condition_expression>} {<command>}]
Arguments
-label <label>
Used to identify individual when commands. Optional.
-id <id#>
Attempts to assign this id number to the when command. Optional. If the id number you
specify is already used, ModelSim will return an error.
Note: Ids for when commands are assigned from the same pool as those used for the bp
command (CR-75). So, even if you haven’t used an id number for a when command, it’s
possible it is used for a breakpoint.
{<when_condition_expression>}
Specifies the conditions to be met for the specified <command> to be executed. Required
if a command is specified. The condition is evaluated in the simulator kernel and can be
an object name, in which case the curly braces can be omitted. The command will be
executed when the object changes value. The condition can be an expression with these
operators:
Name Operator
equals ==, =

CR-408 when
Name Operator
not equal !=, /=
greater than >

less than <
greater than or >=

equal
less than or equal <=

AND &&, AND
OR ||, OR
The operands may be object names, signame’event, or constants. Subexpressions in

parentheses are permitted. The command will be executed when the expression is
evaluated as TRUE or 1.
The formal BNF syntax is:
condition ::= Name | { expression }
expression ::= expression AND relation

| expression OR relation
| relation
relation ::= Name = Literal

| Name /= Literal
| Name ' EVENT
| ( expression )
Literal ::= '<char>' | “<bitstring>” | <bitstring>
The "=" operator can occur only between a Name and a Literal. This means that you
cannot compare the value of two signals, i.e., Name = Name is not possible.
Tcl variables can be used in the condition expression but you must replace the curly
braces ({}) with double quotes (""). This works like a macro substitution where the Tcl
variables are evaluated once and the result is then evaluated as the when condition.
Condition expressions are evaluated in the vsim kernel, which knows nothing about Tcl
variables. That's why the condition expression must be evaluated in the GUI before it is
sent to the vsim kernel. See below for an example of using a Tcl variable.
The ">", "<", ">=", and "<=" operators are the standard ones for vector types, not the
overloaded operators in the std_logic_1164 package. This may cause unexpected results
when comparing objects that contain values other than 1 and 0. ModelSim does a lexical
comparison (position number) for values other than 1 and 0. For example:
0000 < 1111 ## This evaluates to true
H000 < 1111 ## This evaluates to false
001X >= 0010 ## This also evaluates to false

when CR-409
{<command>}
The command(s) for this argument are evaluated by the Tcl interpreter within the
ModelSim GUI. Any ModelSim or Tcl command or series of commands are valid with
one exception—the run command (CR-252) cannot be used with the when command.
Required if a when expression is specified. The command sequence usually contains a
stop command (CR-273) that sets a flag to break the simulation run after the command
sequence is completed. Multiple-line commands can be used.
Note: If you want to stop the simulation using a when command, you must use a stop
command (CR-273) within your when statement. DO NOT use an exit command (CR-166)
or a quit command. The stop command acts like a breakpoint at the time it is evaluated.
See "Ending the simulation with the stop command" (CR-410) for examples.
Examples
The when command below instructs the simulator to display the value of object c in binary
format when there is a clock event, the clock is 1, and the value of b is 01100111. Finally,
the command tells ModelSim to stop.
when -label when1 {clk’event and clk=’1’ and b = “01100111”} {
echo “Signal c is [exa -bin c]"
stop
}
The commands below show an example of using a Tcl variable within a when command.
Note that the curly braces ({}) have been replaced with double quotes ("").
set clkb_path /tb/ps/dprb_0/udprb/ucar_reg/uint_ram/clkb;
when -label when1 "$clkb_path'event and $clkb_path ='1'" {

echo "Detected Clk edge at path $clkb_path"
}
This next example uses the Tcl set command to disable arithmetic package warnings at time
0. Note that the time unit (ns in this case) would vary depending on your simulation
resolution.
when {$now = @1ns } {set NumericStdNoWarnings 1}
run -all
The when command below is labeled a and will cause ModelSim to echo the message “b
changed” whenever the value of the object b changes.
when -label a b {echo “b changed”}
The multi-line when command below does not use a label and has two conditions. When
the conditions are met, an echo (CR-156) and a stop (CR-273) command will be executed.
when {b = 1
and c /= 0 } {
echo “b is 1 and c is not 0”
stop
}

CR-410 when
In the example below, for the declaration "wire [15:0] a;", the when command will activate
when the selected bits match a 7:
when {a(3:1) = 3'h7} {echo "matched at time " $now}
If you encounter a vectored net caused by optimizing with vopt (CR-371), use the ’event
qualifier to prevent the command from falsely evaluating when unrelated bits of ’a’ change:
when {a(3:1) = 3'h7 and a(3:1)'event} {echo "matched at time " $now}
In the example below, we want to sample the values of the address and data bus on the first
falling edge of clk after sstrb has gone high.
# ::strobe is our state variable
set ::strobe Zero
# This signal breakpoint only fires when sstrb changes to a '1'
when -label checkStrobe {/top/sstrb == '1'} {
# Our state Zero condition has been met, move to state One
set ::strobe One
}
# This signal breakpoint fires each time clk goes to '0'
when {/top/clk == '0'} {
if {$::strobe eq "One"} {
# Our state One condition has been met
# Sample the busses
echo Sample paddr=[examine -hex /top/paddr] :: sdata=[examine -hex
/top/sdata]
# reset our state variable until next rising edge of sstrb (back to
state Zero)
set ::strobe Zero
}
}
Ending the simulation with the stop command

Batch mode simulations are often structured as "run until condition X is true," rather than
"run for X time" simulations. The multi-line when command below sets a done condition
and executes an echo (CR-156) and a stop (CR-273) command when the condition is reached.
The simulation will not stop (even if a quit -f command is used) unless a stop command is
executed. To exit the simulation and quit ModelSim, use an approach like the following:
onbreak {resume}
when {/done_condition == ’1’} {
echo "End condition reached"
if [batch_mode] {
set DoneConditionReached 1
stop
}
}
run 1000 us
if {$DoneConditionReached == 1} {
quit -f
}
Here’s another example that stops 100ns after a signal transition:

when {a = 1} {
# If the 100ns delay is already set then let it go.
if {[when -label a_100] == ""} {
when -label a_100 { $now = 100 } {
# delete this breakpoint then stop

when CR-411
nowhen a_100
stop
}
}
}
Time-based breakpoints
You can build time-based breakpoints into a when statement with the following syntax.
For absolute time (indicated by @) use:
when {$now = @1750ns} {stop}
You can also use:

when {errorFlag = '1' OR $now = 2ms} {stop}
This example adds 2ms to the simulation time at which the when statement is first
evaluated, then stops.
You can also use variables, as shown in the following example:
set time 1000
when "\$now = $time" {stop}
The quotes instruct Tcl to expand the variables before calling the command. So, the when
command sees:
when "$now = 1000" stop
Note that "$now" has the ’$’ escaped. This prevents Tcl from expanding the variable,
because if it did, you would get:
when "0 = 1000" stop
See also
bp (CR-75), disablebp (CR-148), enablebp (CR-158), nowhen (CR-213)

CR-412 where
where
The where command displays information about the system environment. This command
is useful for debugging problems where ModelSim cannot find the required libraries or
support files.
The command displays two system settings:
current directory
This is the current directory that ModelSim was invoked from, or was specified on the
ModelSim command line.
current project file
This is the .mpf file ModelSim is using. All library mappings are taken from here when
a project is open.
Syntax
where
Arguments
None.

wlf2log CR-413
wlf2log
The wlf2log command translates a ModelSim WLF file (vsim.wlf) to a QuickSim II logfile.
The command reads the vsim.wlf WLF file generated by the add list, add wave, or log
commands in the simulator and converts it to the QuickSim II logfile format.
Important: This command should be invoked only after you have stopped the
simulation using quit -sim or dataset close sim.
Syntax
wlf2log
[-bits] [-fullname] [-help] [-inout] [-input] [-internal]
[-l <instance_path>] [-lower] [-o <outfile>] [-output] [-quiet] <wlffile>
Arguments
-bits
Forces vector nets to be split into 1-bit wide nets in the log file. Optional.
-fullname
Shows the full hierarchical pathname when displaying signal names. Optional.
-help
Displays a list of command options with a brief description for each. Optional.
-inout
Lists only the inout ports. Optional. This may be combined with the -input, -output, or
-internal switches.
-input
Lists only the input ports. Optional. This may be combined with the -output, -inout, or
-internal switches.
-internal
Lists only the internal signals. Optional. This may be combined with the -input, -output,
or -inout switches.
-l <instance_path>
Lists the signals at or below the specified HDL instance path within the design hierarchy.
Optional.
-lower
Shows all logged signals in the hierarchy. Optional. When invoked without the -lower
switch, only the top-level signals are displayed.
-o <outfile>
Directs the output to be written to the file specified by <outfile>. Optional. The default
destination for the logfile is standard out.
-output
Lists only the output ports. Optional. This may be combined with the -input, -inout, or
-internal switches.

CR-414 wlf2log
-quiet
Disables error message reporting. Optional.
<wlffile>
Specifies the ModelSim WLF file that you are converting. Required.
Additional information for QuickSim II users

In some cases your original QuickHDL/ModelSim simulation results (in your vsim.wlf file)
may contain signal values that do not directly correspond to qsim_12state values. The
resulting QuickSim II logfile generated by wlf2log may contain state values that are
surrounded by single quotes, e.g. '0' and '1'. To make this logfile compatible with QuickSim
models (that expect qsim_12state) you need to use a QuickSim II function named
$convert_wdb().
This function was created to convert logfiles resulting from VHDL simulation that used
std_logic and std_ulogic since these data types do not correlate to QuickSim's 12 simulation
states. Other VHDL data types such as qsim_state or bit (2 state) do not require conversion
as they are directly compatible with qsim_12state QuickSim II Waveform Databases
(WDB).
The following procedure can be used to convert a wlf2log-generated logfile into a
compatible QuickSim WDB. The procedure below shows how to convert the logfile while
loaded into memory in QuickSim II.
1 Load the logfile (the output from wlf2log) into a WDB other than "forces". "Forces" is
the default WDB, so you need to choose a unique name for the WDB when loading the
logfile (for example, "fred").
2 Enter the following at the command prompt from within QuickSim:

$convert_wdb("fred",0)
The first argument, which is "fred", is the name of the new WDB to be created. The
second argument, which is 0, specifies the type of conversion. At this time only one type
of conversion is supported. The value 0 specifies to convert std_logic or std_ulogic into
qsim_12state.
3 Do a connect_wdb (either through the pulldown menus, the "Connect WDB" palette icon
under "Stimulus", or a function invocation). You specify the name of the WDB that you
originally loaded the logfile into (in this case, "fred").
At this point you can issue the "run" command and the stimulus in the converted logfile will
be applied. Before exiting the simulation you should save the new WDB ("fred") as a WDB
or logfile so that it can be loaded again in the future. The new WDB or logfile will contain
the correct qsim_12state values eliminating the need to re-use $convert_wdb().

wlf2vcd CR-415
wlf2vcd
The wlf2vcd command translates a ModelSim WLF file to a standard VCD file. Complex
data types that are unsupported in the VCD standard (records, memories, etc.) are not
converted.
Important: This command should be invoked only after you have stopped the
simulation using quit -sim or dataset close sim.
Syntax
wlf2vcd
[-help] [-o <outfile>] [-quiet] <wlffile>
Arguments
-help
Displays a list of command options with a brief description for each. Optional.
-o <outfile>
Specifies a filename for the output. By default the VCD output goes to stdout. Optional.
-quiet
Disables warning messages that are produced when an unsupported type (e.g., records)
is encountered in the WLF file. Optional.
<wlffile>
Specifies the ModelSim WLF file that you are converting. Required.

CR-416 wlfman
wlfman
The wlfman command allows you to get information about and manipulate WLF files. The
command performs four functions depending on which mode you use:
• wlfman info generates file information, resolution, versions, etc.
• wlfman items generates a list of HDL objects (i.e., signals) from the source WLF file and
outputs it to stdout. When redirected to a file, the output is called an object_list_file, and
it can be read in by wlfman filter. The object_list_file is a list of objects, one per line.
Comments start with a '#' and continue to the end of the line. Wildcards are legal in the
leaf portion of the name. Here is an example:
/top/foo # signal foo
/top/u1/* # all signals under u1
/top/u1 # same as line above
-r /top/u2 # recursively, all signals under u2
Note that you can produce these files from scratch but be careful with syntax. wlfman
items always creates a legal object_list_file.
• wlfman filter reads in a WLF file and optionally an object_list_file and writes out
another WLF file containing filtered information from those sources. You determine the
filtered information with the arguments you specify.
• wlfman profile generates a report of the estimated percentage of file space that each
signal is taking in the specified WLF file. This command can identify signals that account
for a large percentage of the WLF file size (e.g., a logged memory that uses a zero-delay
integer loop to initialize the memory). You may be able to drastically reduce WLF file
size by not logging those signals.
• wlfman merge combines two WLF files with different signals into one WLF file. It does
not combine wlf files containing the same signals at different runtime ranges (i.e.,
mixedhdl_0ns_100ns.wlf & mixedhdl_100ns_200ns.wlf).
The different modes are intended to be used together. For example, you might run wlfman
profile and identify a signal that accounts for 50% of the WLF file size. If you don’t
actually need that signal, you can then run wlfman filter to remove it from the WLF file.
Syntax
wlfman info
<wlffile>
wlfman items
[-n] [-v] <wlffile>
wlfman filter
[-begin <time>] [-end <time>] [-f <object_list_file>] [-r <object>]
[-s <symbol>] [-t <resolution>] <sourcewlffile> <outwlffile>
wlfman profile
[-rank] [-top <number>] <wlffile>
wlfman merge
-noopt -opt -rank -top <number>

wlfman CR-417
Arguments for wlfman info

<wlffile>
Specifies the WLF file from which you want information. Required.
Arguments for wlfman items

-n
Lists regions only (no signals). Optional.
-v
Produces verbose output that lists the object type next to each object. Optional.
<wlffile>
Specifies the WLF file for which you want a profile report. Required.
Arguments for wlfman filter

-begin <time>
Specifies the simulation time at which you want to begin reading information from the
source WLF file. Optional. By default the output includes the entire time that is recorded
in the source WLF file.
-end <time>
Specifies the simulation time at which you want to end reading information from the
source WLF file. Optional.
-f <object_list_file>
Specifies an object_list_file created by wlfman items to include in the output WLF file.
Optional.
-r <object>
Specifies an object (region) to recursively include in the output. If <object> is a signal,
the output would be the same as using -s. Optional.
-s <symbol>
Specifies an object to include in the output. Optional. By default all objects are output.
-t <resolution>
Specifies the time resolution of the new WLF file. Optional. By default the resolution is
the same as the source WLF file.
<sourcewlffile>
Specifies the source WLF file from which you want objects. Required.
<outwlffile>
Specifies the name of the output WLF file. Required. The output WLF file will contain
all objects specified by -f <object_list_file>, -r <object>, and -s <symbol>. Output
WLF files are always written in the latest WLF version regardless of the source WLF file
version.

CR-418 wlfman
Arguments for wlfman profile

-rank
Sorts the report by percentage. Optional.
-top <number>
Filters the report so that only the top <number> signals in terms of file space percentage
are displayed. Optional.
<wlffile>
Specifies the WLF file from which you want object information. Required.
Arguments for wlfman merge

-noopt
Disables WLF file optimizations when writing output WLF file. Optional.
-opt
Forces WLF file optimizations when writing output WLF file. Optional. Default.
-o <outwlffile>
Specifies the name of the output WLF file. Required. The output WLF file will contain
all objects from <wlffile1> and <wlffile2>. Output WLF files are always written in the
latest WLF version regardless of the source WLF file version.
<wlffile1> <wlffile2>
Specifies the WLF files whose objects you want to copy into one WLF file. Optional.
Examples
wlfman profile -rank top_vh.wlf
The output from this command would look something like this:
#Repeated ID #'s mean those signals share the same
#space in the wlf file.
#
# ID Transitions File % Name
#----- ----------- ------ ----------------------------------------
1 2192 33 % /top_vh/pdata
1 /top_vh/processor/data
1 /top_vh/cache/pdata
1 /top_vh/cache/gen__0/s/data
2 1224 18 % /top_vh/ptrans
3 1216 18 % /top_vh/sdata
3 /top_vh/cache/sdata
3 /top_vh/memory/data
4 675 10 % /top_vh/strans
5 423 6 % /top_vh/cache/gen__3/s/data_out
6 135 3 % /top_vh/paddr.
.
.
.
wlfman profile -top 3 top_vh.wlf

The output from this command would look something like this:

wlfman CR-419
# ID Transitions File % Name

#----- ----------- ------ ----------------------------------------
1 2192 33 % /top_vh/pdata
1 /top_vh/processor/data
1 /top_vh/cache/pdata
2 1224 18 % /top_vh/ptrans
3 1216 18 % /top_vh/sdata
3 /top_vh/cache/sdata
3 /top_vh/memory/data
See also
Chapter 8 - WLF files (datasets) and virtuals (UM-225)

CR-420 wlfrecover
wlfrecover
The wlfrecover tool attempts to "repair" WLF files that are incomplete due to a crash or
the file being copied prior to completion of the simulation. The tool works only on WLF
files created by ModelSim versions 5.6 or later. You can run the tool from the VSIM> or
ModelSim> prompt or from a shell.
Syntax
wlfrecover
<filename> [-force] [-q]
Arguments
<filename>
Specifies the WLF file to repair. Required.
-force
Disregards file locking and attempts to repair the file. Optional.
-q
Hides all messages unless there is an error while repairing the file. Optional.

write cell_report CR-421
write cell_report
The write cell_report command writes to the Transcript pane or to a file a list of Verilog
modules which qualified for and received gate-level cell optimizations.
Gate-level cell optimizations are applied at the module level, in addition to normal Verilog
optimizations, to improve performance of gate-level simulations.
Syntax
write cell_report
[-filter <number>] [-infile <filename>] [-nonopt]
[[-outfile] <filename>]
Arguments
-filter <number>
Excludes cells with instance counts fewer than <number>. Optional.
-infile <filename>
Specifies a previously generated write report file to use as input. Optional. If not
specified then the write report command will be run.
-nonopt
Reports only non-optimized instances. Optional.
[-outfile] <filename>
Writes the report to the specified output file rather than the Transcript pane. Optional.

CR-422 write format
write format
The write format command records the names and display options of the HDL objects
currently being displayed in the List or Wave window. The file created is primarily a list of
add list (CR-48), add wave (CR-52), and configure (CR-123) commands, though a few other
commands are included (see "Output" below). This file may be invoked with the do
command (CR-151) to recreate the List or Wave window format on a subsequent simulation
run.
When you load a wave or list format file, ModelSim verifies the existence of the datasets
required by the format file. ModelSim displays an error message if the requisite datasets do
not all exist. To force the execution of the wave or list format file even if all datasets are
not present, use the -force switch with your do command. For example:
VSIM> do wave.do -force
Note that this will result in error messages for signals referencing nonexistent datasets.
Also, -force is recognized by the format file not the do command.
Syntax
write format
list | wave [-window <window_name>] <filename>
Arguments
list | wave
Specifies that the contents of either the List or the Wave window are to be recorded.
Required.
Specifies the window for which you want contents recorded. Optional. Use when you
have more than one instance of the List or Wave window.
<filename>
Specifies the name of the output file where the data is to be written. Required.
Examples
write format list alu_list.do
Saves the current data in the List window in a file named alu_list.do.
write format wave alu_wave.do
Saves the current data in the Wave window in a file named alu_wave.do.
Output
Below is an example of a saved Wave window format file.
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /cntr_struct/ld
add wave -noupdate -format Logic /cntr_struct/rst
add wave -noupdate -format Logic /cntr_struct/clk
add wave -noupdate -format Literal /cntr_struct/d
add wave -noupdate -format Literal /cntr_struct/q

write format CR-423
TreeUpdate [SetDefaultTree]
quietly WaveActivateNextPane
add wave -noupdate -format Logic /cntr_struct/p1
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {0 ns}
WaveRestoreZoom {0 ns} {1 us}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -signalnamewidth 0
configure wave -justifyvalue left
In the example above, five signals are added with the -noupdate argument to the default
window pane. The TreeUpdate command then refreshes all five waveforms. The second
WaveActivateNextPane command creates a second pane which contains three signals.The
WaveRestoreCursors command restores any cursors you set during the original
simulation, and the WaveRestoreZoom command restores the Zoom range you set. These
four commands are used only in saved Wave format files; therefore, they are not
documented elsewhere.
See also
add list (CR-48), add wave (CR-52)

CR-424 write list
write list
The write list command records the contents of the most recently opened or specified List
window in a list output file. This file contains simulation data for all HDL objects displayed
in the List window: VHDL signals and variables and Verilog nets and registers.
Syntax
write list
[-events] [-window <wname>] <filename>
Arguments
-events
Specifies to write print-on-change format. Optional. Default is tabular format.
-window <wname>
window.
<filename>
Examples
write list alu.lst
Saves the current data in the default List window in a file named alu.lst.
write list -win list1 group1.list
Saves the current data in window ‘list1’ in a file named group1.list.
See also
write tssi (CR-429)

write preferences CR-425
write preferences
The write preferences command saves the current GUI preference settings to a Tcl
preference file. Settings saved include current window locations and sizes; Wave, Objects,
and Locals window column widths; Wave, Objects, and Locals window value justification;
and Wave window signal name width.
Syntax
write preferences
<preference file name>
Arguments
<preference file name>
Specifies the name for the preference file. Optional. If the file is named modelsim.tcl,
ModelSim will read the file each time vsim is invoked. To use a preference file other than
modelsim.tcl you must specify the alternative file name with the MODELSIM_TCL
(UM-521) environment variable.
See also
You can modify variables by editing the preference file with the ModelSim notepad (CR-
211):
notepad <preference file name>

CR-426 write report
write report
The write report command prints a summary of the design being simulated including a list
of all design units (VHDL configurations, entities, and packages, and Verilog modules)
with the names of their source files. If you have compiled a Verilog design using -fast, the
report will also identify cells which have been optimized.
Syntax
write report
[[-file <filename>] [-recursive | <instance_name1>...<instance_nameN>]] |
[-tcl]
Arguments
<filename>
Specifies the name of the output file where the data is to be written. Optional. If the
<filename> is omitted, the report is written to the Transcript pane.
-l
Generates more detailed information about the design including a list of sparse
memories. Default.
-s
Generates a short list of design information. Optional.
-tcl
Generates a Tcl list of design unit information. Optional. This argument cannot be used
with a filename.
Examples
write report alu.rep
Saves information about the current design in a file named alu.rep.

write timing CR-427
write timing
The write timing command prints timing information about the specified instance.Syntax
write timing
[-recursive] [-file -file <filename>]
Arguments
-recursive
Generates timing information for the specified instance and all instances underneath it in
the design hierarchy. Optional.
-file <filename>
Specifies the name of the output file where the data is to be written. Optional. If the -file
argument is omitted, timing information is written to the Transcript pane.
<instance_name1>...<instance_nameN>
The name(s) of the instance(s) for which timing information will be written. Required.
Examples
write timing -r -f timing.txt /top/u1
Writes timing about /top/u1 and all instances underneath it in the hierarchy to the file
timing.txt.
write timing /top/u1 /top/u2 /top/u3 /top/u8
Writes timing information about the designated instances to the Transcript pane.

CR-428 write transcript
write transcript
The write transcript command writes the contents of the Transcript pane to the specified
file. The resulting file can be used to replay the transcribed commands as a DO file (macro).
The command cannot be used in batch mode. In batch mode use the standard "Transcript"
(GR-16) file or redirect stdout.
Syntax
write transcript
[<filename>]
Arguments
<filename>
Specifies the name of the output file where the data is to be written. Optional. If the
<filename> is omitted, the transcript is written to a file named transcript.
See also
do (CR-151)

write tssi CR-429
write tssi
The write tssi command records the contents of the default or specified List window in a
"TSSI format" file. The file contains simulation data for all HDL objects displayed in the
List window that can be converted to TSSI format (VHDL signals and Verilog nets). A
signal definition file is also generated.
The List window needs to be using symbolic radix in order for write tssi to produce useful
output.
Syntax
write tssi
[-window <wname>] <filename>
Arguments
-window <wname>
window.
<filename>
Description
“TSSI format” is documented in the Fluence TDS Software System, Chapter 2 of Volume
I, Getting Started, R11.1, dated November 15, 1999. In that document, TSSI format is
called Standard Events Format (SEF).
If the <filename> has a file extension (e.g., listfile.lst), then the definition file is given the
same file name with the extension .def (e.g., listfile.def). The values in the listfile are
produced in the same order that they appear in the List window. The directionality is
determined from the port type if the object is a port, otherwise it is assumed to be
bidirectional (mode INOUT).
Objects that can be converted to SEF are VHDL enumerations with 255 or fewer elements
and Verilog nets. The enumeration values U, X, 0, 1, Z, W, L, H and - (the enumeration
values defined in the IEEE Standard 1164 std_ulogic enumeration) are converted to SEF
values according to the table below. Other values are converted to a question mark (?) and
cause an error message. Though the write tssi command was developed for use with
std_ulogic, any signal which uses only the values defined for std_ulogic (including the
VHDL standard type bit) will be converted.
std_ulogic State SEF State Characters

Characters
Input Output Bidirectional
U N X ?
X N X ?
0 D L 0

CR-430 write tssi
std_ulogic State SEF State Characters

Characters
Input Output Bidirectional
1 U H 1
Z Z T F
W N X ?
L D L 0
H U H 1
- N X ?
Bidirectional logic values are not converted because only the resolved value is available.
The Fluence (TSSI) TDS ASCII In Converter and ASCII Out Converter can be used to
resolve the directionality of the signal and to determine the proper forcing or expected value
on the port. Lowercase values x, z, w, l, and h are converted to the same values as the
corresponding capitalized values. Any other values will cause an error message to be
generated the first time an invalid value is detected on a signal, and the value will be
converted to a question mark (?).
Note: The TDS ASCII In Converter and ASCII Out Converter are part of the TDS
software from Fluence Technology. ModelSim outputs a vector file, and Fluence’s tools
determine whether the bidirectional signals are driving or not.
See also
tssi2mti (CR-288)

write wave CR-431
write wave
The write wave command records the contents of the most currently opened or specified
Wave window in PostScript format. The output file can then be printed on a PostScript
printer.
Syntax
write wave
[-window <wname>] [-width <real_num>] [-height <real_num>]
[-margin <real_num>] [-start <time>] [-end <time>] [-perpage <time>]
[-landscape] [-portrait] <filename>
Arguments
-window <wname>
window.
-width <real_num>
Specifies the paper width in inches. Optional. Default is 8.5.
-height <real_num>
Specifies the paper height in inches. Optional. Default is 11.0.
-margin <real_num>
Specifies the margin in inches. Optional. Default is 0.5.
-start <time>
Specifies the start time (on the waveform timescale) to be written. Optional.
-end <time>
Specifies the end time (on the waveform timescale) to be written. Optional.
-perpage <time>
Specifies the time width per page of output. Optional.
-landscape
Use landscape (horizontal) orientation. Optional. This is the default orientation.
-portrait
Use portrait (vertical) orientation. Optional. The default is landscape (horizontal).
<filename>
Specifies the name of the PostScript output file. Required.
Examples
write wave alu.ps
Saves the current data in the Wave window in a file named alu.ps.
write wave -win wave2 group2.ps
Saves the current data in window ‘wave2’ in a file named group2.ps.

CR-432 write wave
write wave -start 600ns -end 800ns -perpage 100ns top.ps

Writes two separate pages to top.ps. The first page contains data from 600ns to 700ns,
and the second page contains data from 701ns to 800ns.
To make the job of creating a PostScript waveform output file easier, use the File > Print
Postscript menu selection in the Wave window. See "Saving a .eps file and printing
under UNIX" (UM-262) for more information.

CR-433
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Rev. 040401, Part Number 221417


Index
CR = Command Reference, UM = User’s Manual, GR = GUI Reference
Symbols add_submenu command CR-61

aggregates, SystemC UM-180
#, comment character UM-476 alias command CR-62
+acc option, design object visibility UM-126 analog
+typdelays CR-365 signal formatting CR-53, GR-239
-, in a coverage report UM-353 supported signal types GR-239
.so, shared object file annotating interconnect delays, v2k_int_delays CR-389
loading PLI/VPI C applications UM-568 architecture simulator state variable UM-542
loading PLI/VPI C++ applications UM-574 archives
{} CR-15 described UM-59
’hasX, hasX CR-24 archives, library CR-356
argc simulator state variable UM-542
arguments
Numerics passing to a DO file UM-487
arguments, accessing commandl-line UM-183
1076, IEEE Std UM-30 arithmetic package warnings, disabling UM-538
differences between versions UM-75 array of sc_signal<T> UM-180
1364, IEEE Std UM-30, UM-113 arrays
2001, keywords, disabling CR-366 indexes CR-12
64-bit libraries UM-66 slices CR-12, CR-15
64-bit ModelSim, using with 32-bit FLI apps UM-598 AssertFile .ini file variable UM-529
64-bit time assertion fail command CR-63
now variable UM-543 assertion pass command CR-65
Tcl time commands UM-481 assertion report command CR-67
AssertionFailEnable .ini variable UM-529
A AssertionFailLimit .ini variable UM-529
AssertionFailLog .ini variable UM-529
+acc option, design object visibility UM-126 AssertionFormat .ini file variable UM-529
abort command CR-44 AssertionFormatBreak .ini file variable UM-529
absolute time, using @ CR-18 AssertionFormatError .ini file variable UM-529
ACC routines UM-591 AssertionFormatFail .ini file variable UM-530
accelerated packages UM-65 AssertionFormatFatal .ini file variable UM-530
access AssertionFormatNote .ini file variable UM-530
hierarchical objects UM-417 AssertionFormatWarning .ini file variable UM-530
limitations in mixed designs UM-190 AssertionPassEnable .ini variable UM-530
Active Processes pane GR-108 AssertionPassLimit .ini variable UM-530
see also windows, Active Processes pane AssertionPassLog .ini variable UM-530
add button command CR-45 assertions
Add file to Project dialog GR-44 configuring from the GUI GR-86
Add Folder dialog GR-47 enabling CR-63, CR-65
add list command CR-48 failure behavior CR-63
add monitor command CR-51 file and line number UM-529
add PSL files UM-53, GR-53, GR-56 flow UM-362
add wave command CR-52 library and use clauses UM-367
add_menu command CR-56 limitations UM-362
add_menucb command CR-58 messages
add_menuitem simulator command CR-59 alternate output file UM-381
add_separator command CR-60 turning off UM-538
Index
multiclocked properties UM-369 stop simulation run GR-35

pass behavior CR-65 BreakOnAssertion .ini file variable UM-530
reporting on CR-67, UM-381 breakpoints
selecting severity that stops simulation GR-86 C code UM-403
setting format of messages UM-529 conditional CR-407
testing for with onbreak command CR-214 continuing simulation after CR-252
viewing in Wave window UM-382 deleting CR-70, GR-203, GR-264
warnings, locating UM-529 listing CR-75
Assertions pane setting CR-75, GR-203
described GR-110 setting automatically in C code UM-407
hiding/showing columns GR-112 signal breakpoints (when statements) CR-407
assume directives Source window, viewing in GR-199
disabling UM-363 time-based
SimulateAssumeDirectives .ini variable UM-533 in when statements CR-411
AtLeast counts, functional coverage UM-387 .bsm file UM-313
attributes, of signals, using in expressions CR-24 buffered/unbuffered output UM-534
auto find bp command UM-406 bus contention checking CR-84
auto step mode, C Debug UM-407 configuring CR-86
disabling CR-87
bus float checking
B configuring CR-89
disabling CR-90
bad magic number error message UM-227
enabling CR-88
balloon dialog, toggling on/off GR-256
busses
balloon popup
escape characters in CR-15
C Debug GR-99
RTL-level, reconstructing UM-234
base (radix)
user-defined CR-53, UM-264
List window UM-259
buswise format UM-279
Memory window GR-183
button
Wave window UM-255
adding to windows GR-106
batch_mode command CR-69
buttons, adding to the Main window toolbar CR-45
batch-mode simulations UM-28
halting CR-410
bd (breakpoint delete) command CR-70 C
binary radix, mapping to std_logic values CR-29
BindAtCompile .ini file variable UM-527 C applications
binding, VHDL, default UM-79 compiling and linking UM-568
bitwise format UM-279 debugging UM-399
blocking assignments UM-134 C callstack
bookmark add wave command CR-71 moving down CR-237
bookmark delete wave command CR-72 moving up CR-219
bookmark goto wave command CR-73 C Debug UM-399
bookmark list wave command CR-74 auto find bp UM-406
bookmarks auto step mode UM-407
Source window GR-204 debugging functions during elaboration UM-410
Wave window UM-250 debugging functions when exiting UM-414
bp (breakpoint) command CR-75 function entry points, finding UM-406
brackets, escaping CR-15 initialization mode UM-410
break menu reference GR-31
on assertion GR-86 registered function calls, identifying UM-407
on signal value CR-407 running from a DO file UM-402
Index
Stop on quit mode UM-414 coverage exclude command CR-129

C Debug setup dialog GR-99 coverage reload command CR-131
C debugging CR-79 coverage report command CR-132
C++ applications coverage save command CR-135
compiling and linking UM-574 Current Exclusions pane GR-121
cancelling scheduled events, performance UM-108 data types supported UM-335
case choice, must be locally static CR-314 Details pane GR-123
case sensitivity display filter toolbar GR-127
named port associations UM-207 enabling with vcom or vlog UM-337
VHDL vs. Verilog CR-15 enabling with vsim UM-337
causality, tracing in Dataflow window UM-306 excluding lines/files UM-347
cd (change directory) command CR-78 exclusion filter files UM-348
cdbg command CR-79 expression coverage UM-334, UM-356
cdbg_wait_for_starting command UM-402 important notes UM-336
cell libraries UM-144 Instance Coverage pane GR-122
cells Main window coverage data UM-340
hiding in Dataflow window GR-140, GR-141 merge utility UM-354
change command CR-81 merging report files CR-131
change directory, disabled GR-21 merging reports CR-320
Change Memory dialog GR-179 missed branches GR-120
Change Selected Variable dialog GR-167 missed coverage GR-120
change_menu_cmd command CR-83 pragma exclusions UM-347
chasing X UM-307 reports UM-350
check contention add command CR-84 Source window data UM-341
check contention config command CR-86 source window details GR-124
check contention off command CR-87 statistics in Main window UM-340
check float add command CR-88 toggle coverage UM-334
check float config command CR-89 excluding signals CR-281
check float off command CR-90 toggle details GR-123
check stable off command CR-91 vcover report command CR-322
check stable on command CR-92 Workspace pane GR-116
-check_synthesis argument CR-312 collapsing ports, and coverage reporting UM-345
warning message UM-552 collapsing time and delta steps UM-232
CheckPlusargs .ini file variable (VLOG) UM-530 colorization, in Source window GR-205
checkpoint command CR-93 columns
checkpoint/restore UM-86, UM-142 hide/showing in GUI GR-262
CheckpointCompressMode .ini file variable UM-531 moving GR-262
CheckSynthesis .ini file variable UM-527 sorting by GR-262
class member selection, syntax CR-13 Combine Selected Signals dialog GR-161
class of sc_signal<T> UM-180 combining signals, busses CR-53, UM-264
cleanup command history GR-28
SystemC state-based code UM-175 command line args, accessing
clean-up of SystemC state-based code UM-175 vsim sc_arg command CR-389
clock change, sampling signals at UM-268 CommandHistory .ini file variable UM-531
clocked comparison UM-276 command-line arguments, accessing UM-183
Code Coverage command-line mode UM-27
$coverage_save system function UM-152 commands
by instance UM-334 .main clear CR-43
columns in workspace GR-116 abort CR-44
condition coverage UM-334, UM-355 add button CR-45
coverage clear command CR-128 add list CR-48
Index
add monitor CR-51 dataset alias CR-136

add wave CR-52 dataset clear CR-137
add_menu CR-56 dataset close CR-138
add_menucb CR-58 dataset info CR-139
add_menuitem CR-59 dataset list CR-140
add_separator CR-60 dataset open CR-141
add_submenu CR-61 dataset rename CR-142, CR-143
alias CR-62 dataset snapshot CR-144
assertion fail command CR-63 delete CR-146
assertion pass CR-65 describe CR-147
assertion report CR-67 disable_menu CR-149
batch_mode CR-69 disable_menuitem CR-150
bd (breakpoint delete) CR-70 disablebp CR-148
bookmark add wave CR-71 do CR-151
bookmark delete wave CR-72 down CR-152
bookmark goto wave CR-73 drivers CR-154
bookmark list wave CR-74 dumplog64 CR-155
bp (breakpoint) CR-75 echo CR-156
cd (change directory) CR-78 edit CR-157
cdbg CR-79 enable_menu CR-159
change CR-81 enable_menuitem CR-160
change_menu_cmd CR-83 enablebp CR-158
check contention add CR-84 environment CR-161
check contention config CR-86 event watching in DO file UM-487
check contention off CR-87 examine CR-162
check float add CR-88 exit CR-166
check float config CR-89 fcover clear
check float off CR-90 functional coverage
check stable off CR-91 clearing database CR-167
check stable on CR-92 fcover comment CR-168
checkpoint CR-93 fcover configue CR-169
compare add CR-94 fcover reload CR-171
compare annotate CR-98, CR-101 fcover report CR-173
compare clock CR-99 fcover save CR-175
compare close CR-105 find CR-176
compare delete CR-104 force CR-180
compare info CR-106 gdb dir CR-183
compare list CR-107 getactivecursortime CR-184
compare open CR-119 getactivemarkertime CR-185
compare options CR-108 help CR-186
compare reload CR-112 history CR-187
compare savediffs CR-115 lecho CR-188
compare saverules CR-116 left CR-189
compare see CR-117 log CR-191
compare start CR-114 lshift CR-193
configure CR-123 lsublist CR-194
coverage clear CR-128 macro_option CR-195
coverage exclude CR-129 mem display CR-196
coverage reload CR-131 mem list CR-198
coverage report CR-132 mem load CR-199
coverage save CR-135 mem save CR-202
Index
mem search CR-204 step CR-272

modelsim CR-206 stop CR-273
next CR-207 system UM-479
noforce CR-208 tb (traceback) CR-274
nolog CR-209 tcheck_set CR-275
notation conventions CR-10 tcheck_status CR-277
notepad CR-211 toggle add CR-279
noview CR-212 toggle disable CR-281
nowhen CR-213 toggle enable CR-282
onbreak CR-214 toggle report CR-283
onElabError CR-215 toggle reset CR-284
onerror CR-216 transcribe CR-285
pause CR-217 transcript CR-286
play CR-218 transcript file CR-287
pop CR-219 TreeUpdate CR-423
power add CR-220 tssi2mti CR-288
power report CR-221 unsetenv CR-289
power reset CR-222 up CR-290
printenv CR-223, CR-224 variables referenced in CR-17
profile clear CR-225 vcd add CR-292
profile interval CR-226 vcd checkpoint CR-293
profile off CR-227 vcd comment CR-294
profile on CR-228 vcd dumpports CR-295
profile option CR-229 vcd dumpportsall CR-297
profile reload CR-230 vcd dumpportsflush CR-298
profile report CR-231 vcd dumpportslimit CR-299
property list CR-234 vcd dumpportsoff CR-300
property wave CR-235 vcd dumpportson CR-301
push CR-237 vcd file CR-302
pwd CR-238 vcd files CR-304
quietly CR-239 vcd flush CR-306
quit CR-240 vcd limit CR-307
radix CR-241 vcd off CR-308
readers CR-242 vcd on CR-309
record CR-243 vcom CR-311
report CR-244 vcover convert CR-319
restart CR-246 vcover merge CR-320
restore CR-248 vcover report CR-322
resume CR-249 vdel CR-327
right CR-250 vdir CR-328
run CR-252 verror CR-329
sccom CR-254 vgencomp CR-330
scgenmod CR-258 view CR-332
search CR-260 virtual count CR-334
searchlog CR-262 virtual define CR-335
seetime CR-264 virtual delete CR-336
setenv CR-265 virtual describe CR-337
shift CR-266 virtual expand CR-338
show CR-267 virtual function CR-339
splitio CR-270 virtual hide CR-342
status CR-271 virtual log CR-343
Index
virtual nohide CR-345 icons UM-281

virtual nolog CR-346 method UM-276
virtual region CR-348 options UM-278
virtual save CR-349 pathnames UM-279
virtual show CR-350 reference dataset UM-272
virtual signal CR-351 reference region UM-275
virtual type CR-354 tab UM-273
vlib CR-356 test dataset UM-273
vlog CR-358 timing differences UM-279
vmake CR-369 tolerance UM-276
vmap CR-370 values UM-280
vopt CR-371 wave window display UM-279
vsim CR-373 compare add command CR-94
VSIM Tcl commands UM-480 compare annotate command CR-98, CR-101
vsimDate CR-392 compare by region UM-275
vsimId CR-392 compare clock command CR-99
vsimVersion CR-392 compare close command CR-105
wave CR-394 compare delete command CR-104
wave create CR-397 compare info command CR-106
wave edit CR-400 compare list command CR-107
wave export CR-403 Compare Memory dialog GR-181
wave import CR-404 compare open command CR-119
wave modify CR-405 compare options command CR-108
WaveActivateNextPane CR-423 compare reload command CR-112
WaveRestoreCursors CR-423 compare savediffs command CR-115
WaveRestoreZoom CR-423 compare saverules command CR-116
when CR-407 compare see command CR-117
where CR-412 compare simulations UM-225
wlf2log CR-413 compare start command CR-114
wlf2vcd CR-415 compatibility, of vendor libraries CR-328
wlfman CR-416 compile
wlfrecover CR-420 gensrc errors during UM-185
write cell_report CR-421 projects
write format CR-422 add PSL files UM-53, GR-53, GR-56
write list CR-424 compile order
write preferences CR-425 auto generate UM-46
write report CR-426 changing UM-46
write timing CR-427 Compile Order dialog GR-69
write transcript CR-428 Compile Source Files dialog
write tssi CR-429 dialogs
write wave CR-431 Compile Source Files GR-59
comment character compiler directives UM-153
Tcl and DO files UM-476 IEEE Std 1364-2000 UM-153
comment characters in VSIM commands CR-10 XL compatible compiler directives UM-154
compare Compiler Options dialog GR-60
add region UM-275 compiling
add signals UM-274 changing order in the GUI UM-46
by signal UM-274 graphic interface to GR-59
clocked UM-276 grouping files UM-47
difference markers UM-279 order, changing in projects UM-46
displayed in List window UM-281 properties, in projects UM-52
Index
range checking in VHDL CR-316, UM-74 contention checking CR-84

source errors, locating GR-264 context menu
SystemC CR-254, CR-258, UM-164 List window GR-155
converting sc_main() UM-164 context menus
exporting top level module UM-165 Library tab UM-61
for source level debug UM-167 context sensitivity UM-501
invoking sccom UM-167 control function, SystemC UM-192
linking the compiled source UM-172 control_foreign_signal() function UM-183
modifying source code UM-164 conversion, radix CR-241
replacing sc_start() UM-164 convert real to time UM-99
using sccom vs. raw C++ compiler UM-170 convert time to real UM-98
Verilog CR-358, UM-114 coverage
incremental compilation UM-115 merging data UM-354
library components, including CR-361 saving raw data UM-354
optimizing performance CR-360 see also Code Coverage
XL ’uselib compiler directive UM-120 see also functional coverage
XL compatible options UM-119 coverage clear command CR-128
VHDL CR-311, UM-73 coverage exclude command CR-129
at a specified line number CR-313 coverage reload command CR-131
selected design units (-just eapbc) CR-313 coverage report command CR-132
standard package (-s) CR-316 Coverage Report dialog GR-90
VITAL packages UM-95 coverage reports UM-350
compiling the design reporting all signals UM-345
overview UM-25 sample reports UM-352
component declaration xml format UM-351
generating SystemC from Verilog or VHDL UM- coverage save command CR-135
223 $coverage_save system function UM-152
generating VHDL from Verilog UM-204 CoverAtLeast .ini file variable UM-531
vgencomp for SystemC UM-223 CoverEnable .ini file variable UM-531
vgencomp for VHDL UM-204 CoverLimit .ini file variable UM-531
component, default binding rules UM-79 CoverLog .ini file variable UM-531
Compressing files CoverWeight .ini file variable UM-531
VCD tasks UM-462 covreport.xsl UM-351
compressing files CppOptions .ini file variable (sccom) UM-528
VCD files CR-295, CR-304 CppPath .ini file variable (sccom) UM-528
concatenation Create a New Library dialog GR-38
directives CR-28 Create Project dialog GR-37
of signals CR-27, CR-351 Create Project File dialog GR-43
ConcurrentFileLimit .ini file variable UM-531 current exclusions
conditional breakpoints CR-407 pragmas UM-347
configuration simulator state variable UM-542 Current Exclusions pane GR-121
configurations cursors
instantiation in mixed designs UM-203 adding, deleting, locking, naming UM-245
Verilog UM-122 link to Dataflow window UM-302
configurations, simulating CR-373 measuring time with UM-245
configure command CR-123 trace events with UM-306
Configure cover directives dialog GR-149 Wave window UM-245
connectivity, exploring UM-303 Customize Toolbar dialog GR-106
constants customizing
in case statements CR-314 adding buttons CR-45
values of, displaying CR-147, CR-162 via preference variables GR-266
Index
D defaults
restoring UM-520
deltas +define+ CR-359
explained UM-80 Define Clock dialog GR-188
data types definition (ID) of memory GR-170
Code Coverage UM-335 delay
database, functional coverage, saving UM-395 delta delays UM-80
Dataflow Options dialog GR-140 interconnect CR-378
Dataflow Page Setup dialog GR-138 modes for Verilog models UM-144
Dataflow window UM-300, GR-128 SDF files UM-439
automatic cell hiding GR-140, GR-141 stimulus delay, specifying GR-187
menu bar GR-129 +delay_mode_distributed CR-359
options GR-140, GR-141 +delay_mode_path CR-359
pan UM-305 +delay_mode_unit CR-359
zoom UM-305 +delay_mode_zero CR-360
see also windows, Dataflow window ’delayed CR-24
dataflow.bsm file UM-313 DelayFileOpen .ini file variable UM-532
dataset alias command CR-136 delaying test signal, Waveform Comparison GR-244
Dataset Browser UM-229, GR-49 delete command CR-146
dialog GR-49 deleting library contents UM-61
dataset clear command CR-137 delta collapsing UM-232
dataset close command CR-138 delta simulator state variable UM-542
dataset info command CR-139 deltas
dataset list command CR-140 collapsing in the List window GR-163
dataset open command CR-141 collapsing in WLF files CR-382
dataset rename command CR-142, CR-143 hiding in the List window CR-124, GR-163
Dataset Snapshot UM-231 in List window UM-265
dataset snapshot command CR-144 referencing simulator iteration
datasets UM-225 as a simulator state variable UM-542
environment command, specifying with CR-161 dependencies, checking CR-328
managing UM-229 dependent design units UM-73
openingdialogs describe command CR-147
Open File GR-39 descriptions of HDL items GR-203
reference UM-272 design library
restrict dataset prefix display UM-230 creating UM-60
test UM-273 logical name, assigning UM-62
DatasetSeparator .ini file variable UM-531 mapping search rules UM-63
debuggable SystemC objects UM-176 resource type UM-58
debugging VHDL design units UM-73
C code UM-399 working type UM-58
debugging the design, overview UM-26 design object icons, described GR-12
declarations, hiding implicit with explicit CR-318 Design Optimization dialog GR-70
default binding design portability and SystemC UM-168
BindAtCompile .ini file variable UM-527 design units UM-58
disabling UM-79 report of units simulated CR-426
default binding rules UM-79 Verilog
default clock UM-368 adding to a library CR-358
Default editor, changing UM-521 details
DefaultForceKind .ini file variable UM-531 code coverage GR-123
DefaultRadix .ini file variable UM-531 dialogs GR-49
DefaultRestartOptions variable UM-531, UM-539 Add file to Project GR-44
Index
Add Folder GR-47 SystemC Link dialog GR-68

C Debug setup GR-99 directories
Change Memory GR-179 mapping libraries CR-370
Change Selected Variable GR-167 moving libraries UM-63
Combine Selected Signals GR-161 directory, changing, disabled GR-21
Compare Memory GR-181 disable_menu command CR-149
Compile Order GR-69 disable_menuitem command CR-150
Compiler Options GR-60 disablebp command CR-148
Configure cover directives GR-149 distributed delay mode UM-145
Coverage Report GR-90 dividers
Create a New Library GR-38 adding from command line CR-52
Create Project GR-37 Wave window UM-256
Create Project File GR-43 DLL files, loading UM-568, UM-574
Customize Toolbar GR-106 do command CR-151
Dataflow Options GR-140 DO files (macros) CR-151
Dataflow Page Setup GR-138 error handling UM-490
Define Clock GR-188 executing at startup UM-521, UM-534
Design Optimization GR-70 parameters, passing to UM-487
File Breakpoint GR-98 Tcl source command UM-491
Filter instance list GR-92 docking
Find in Assertions GR-113 window panes GR-258
Find in dataflow GR-139 documentation UM-35
Find in FCovers GR-148 DOPATH environment variable UM-521
Find in List GR-156 down command CR-152
Find in Locals GR-168 DPI
Find in memory GR-182 export TFs UM-551
Find in Process GR-109 DPI export TFs UM-551
Force Selected Signal GR-186 DPI use flow UM-566
Functional coverage filter GR-151 drag & drop preferences GR-103
Functional coverage reload GR-145 drivers
Functional coverage report GR-146 Dataflow Window UM-303
List Signal Properties GR-159 show in Dataflow window UM-269
List Signal Search GR-157 Wave window UM-269
Load Coverage Data GR-89 drivers command CR-154
Macro GR-102 drivers, multiple on unresolved signal GR-53, GR-62
Modify Breakpoints GR-95 dump files, viewing in ModelSim CR-310
Modify Display Properties GR-162 dumplog64 command CR-155
Optimization Configuration GR-45 dumpports tasks, VCD files UM-461
Preferences GR-104
Print GR-135
Print Postscript GR-137 E
Profile Report GR-93, GR-197
echo command CR-156
Project Compiler Settings GR-50
edges, finding CR-189, CR-250
Project Settings GR-57
edit command CR-157
Properties (memory) GR-183
Editing
Restart GR-88
in notepad windows UM-605
Runtime Options GR-85
in the Main window UM-605
Save Memory GR-177
in the Source window UM-605
Signal Breakpoints GR-97
EDITOR environment variable UM-521
Simulation Configuration GR-46
editor, default, changing UM-521
Start Simulation GR-76
Index
elab_defer_fli argument UM-84, UM-140 environment, displaying or changing pathname CR-161

elaboration file error
creating UM-83, UM-139 can’t locate C compiler UM-551
loading UM-83, UM-139 Error .ini file variable UM-536
modifying stimulus UM-83, UM-139 errors
resimulating the same design UM-82, UM-138 bad magic number UM-227
simulating with PLI or FLI models UM-84, UM- during compilation, locating GR-264
140 getting details about messages CR-329
elaboration, interrupting CR-373 getting more information UM-546
embedded wave viewer UM-304 libswift entry not found UM-555
empty port name warning UM-551 multiple definition UM-186
enable_menu command CR-159 onerror command CR-216
enable_menuitem command CR-160 out-of-line function UM-186
enablebp command CR-158 SDF, disabling CR-380
encryption SystemC loading UM-184
+protect argument CR-365 Tcl_init error UM-552
‘protect compiler directive UM-155 void function UM-186
-nodebug argument (vcom) CR-314 VSIM license lost UM-555
-nodebug argument (vlog) CR-363 errors, changing severity of UM-546
securing pre-compiled libraries UM-70 escape character CR-15
end_of_construction() function UM-183 event order
end_of_simulation() function UM-183 changing in Verilog CR-358
ENDFILE function UM-91 in optimized designs UM-128
ENDLINE function UM-91 in Verilog simulation UM-132
endpoint directives event queues UM-132
clocking and UM-371 event watching commands, placement of UM-487
restrictions on UM-371 events, tracing UM-306
endpoints, PSL directive UM-398 examine command CR-162
‘endprotect compiler directive UM-155 examine tooltip
entities toggling on/off GR-256
default binding rules UM-79 exclusion filter files UM-348
entities, specifying for simulation CR-390 excluding udp truth table rows UM-349
entity simulator state variable UM-542 exclusions
enumerated types lines and files UM-347
user defined CR-354 exit codes UM-549
environment command CR-161 exit command CR-166
environment variables UM-521 expand net UM-303
accessed during startup UM-613 Explicit .ini file variable UM-527
reading into Verilog code CR-359 export TFs, in DPI UM-551
referencing from ModelSim command line UM-523 Exporting SystemC modules
referencing with VHDL FILE variable UM-523 to Verilog UM-214
setting in Windows UM-522 exporting SystemC modules
specifying library locations in modelsim.ini file to VHDL UM-223
UM-525 exporting top SystemC module UM-165
specifying UNIX editor CR-157 Expression Builder UM-253
state of CR-224 configuring a List trigger with UM-266
TranscriptFile, specifying location of UM-534 saving expressions to Tcl variable UM-253
used in Solaris linking for FLI UM-568, UM-574 extended identifiers CR-16
using in pathnames CR-15 in mixed designs UM-203, UM-222
using with location mapping UM-67
variable substitution using Tcl UM-479
Index
F folders, in projects UM-50

font scaling
-f CR-360 for dual monitors GR-28
F8 function key UM-607 fonts
-fast CR-360 controlling in X-sessions GR-13
fcover clear command CR-167 scaling GR-13
fcover comment command CR-168 force command CR-180
fcover configue command CR-169 defaults UM-539
fcover reload command CR-171 Force Selected Signal dialog GR-186
fcover report command CR-173 foreign language interface UM-100
fcover save command CR-175 foreign model loading
features, new UM-499 SmartModels UM-618
field descriptions foreign module declaration
coverage reports UM-352 Verilog example CR-259, UM-210
FIFOs, viewing SystemC UM-181 VHDL example UM-218
File Breakpoint dialog GR-98 foreign module declaration, SystemC UM-209
File compression format file UM-261
VCD tasks UM-462 List window CR-422
file compression Wave window CR-422, UM-261
SDF files UM-439 FPGA libraries, importing UM-69
VCD files CR-295, CR-304 function calls, identifying with C Debug UM-407
file format Functional coverage
MTI memory data GR-178 merging databases offline CR-320
file I/O functional coverage
splitio command CR-270 AtLeast counts UM-387
TextIO package UM-88 comments in the database CR-168
VCD files UM-455 compiling and simulating UM-385
file-line breakpoints GR-203 configuring directives CR-169
files described UM-360
opening in GUI GR-39 merging statistics CR-171, UM-396
files, grouping for compile UM-47 reloading CR-171, UM-396
filter reporting CR-173, UM-391
processes GR-108 saving database CR-175, UM-395
Filter instance list dialog GR-92 weighting directives UM-387
filtering signals in Objects window GR-185 Functional coverage filter dialog GR-151
filters Functional coverage reload dialog GR-145
for Code Coverage UM-348 Functional coverage report dialog GR-146
find command CR-176 functions
Find in Assertions dialog GR-113 SystemC
Find in dataflow dialog GR-139 control UM-192
Find in FCovers dialog GR-148 observe UM-192
Find in List dialog GR-156 unsupported UM-182
Find in Locals dialog GR-168
Find in memory dialog GR-182
Find in Process dialog GR-109
G
Find in Transcript dialog
-g C++ compiler option UM-178
dialogs
g++, alternate installations UM-168
Find in Transcript GR-48
gate-level designs
fixed point types UM-182
optimizing UM-127
FLI UM-100
gdb
debugging UM-399
Index
setting source directory CR-183 referencing signals in UM-97, UM-422, UM-432

gdb debugger UM-400 releasing signals in UM-97, UM-427, UM-436
gdb dir command CR-183 viewing signal names without GR-255
generate statements, Veilog UM-123 highlighting, in Source window GR-205
GenerateFormat .ini file variable UM-532 history
generic support of commands
SystemC instantiating VHDL UM-218 shortcuts for reuse CR-19, UM-603
generics history command CR-187
assigning or overriding values with -g and -G CR- hm_entity UM-629
375 HOME environment variable UM-521
examining generic values CR-162 HP aCC, restrictions on compiling with UM-169
limitation on assigning composite types CR-376
VHDL UM-195
get_resolution() VHDL function UM-96 I
getactivecursortime command CR-184
I/O
getactivemarkertime command CR-185
splitio command CR-270
glitches
TextIO package UM-88
disabling generation
VCD files UM-455
from command line CR-384
icons
from GUI GR-78
shapes and meanings GR-12
global visibility
ieee .ini file variable UM-525
PLI/FLI shared objects CR-376, UM-581
IEEE libraries UM-65
GlobalSharedObjectsList .ini file variable UM-532
IEEE Std 1076 UM-30
graphic interface UM-237, UM-299, GR-9
differences between versions UM-75
UNIX support UM-29
IEEE Std 1364 UM-30, UM-113
grayed-out menu options UM-501
IgnoreError .ini file variable UM-532
grouping files for compile UM-47
IgnoreFailure .ini file variable UM-532
grouping objects, Monitor window GR-209
IgnoreNote .ini file variable UM-532
GUI preferences, saving GR-266
IgnoreVitalErrors .ini file variable UM-527
IgnoreWarning .ini file variable UM-532
GUI expression builder UM-253
implicit operator, hiding with vcom -explicit CR-318
syntax CR-23
importing EVCD files, waveform editor GR-295
importing FPGA libraries UM-69
H +incdir+ CR-361
incremental compilation
hardware model interface UM-628 automatic UM-116
’hasX CR-24 manual UM-116
Hazard .ini file variable (VLOG) UM-525 with Verilog UM-115
hazards index checking UM-74
-hazards argument to vlog CR-361 indexed arrays, escaping square brackets CR-15
-hazards argument to vsim CR-385 INF, in a coverage report UM-353
limitations on detection UM-135 $init_signal_driver UM-429
help command CR-186 init_signal_driver UM-419
hierarchical reference support, SystemC UM-183 $init_signal_spy UM-432
hierarchical references init_signal_spy UM-97, UM-422
SystemC/HDL designs UM-192 init_usertfs function UM-412, UM-561
hierarchical references, mixed-language UM-190 Initial dialog box, turning on/off UM-520
hierarchy initialization of SystemC state-based code UM-175
driving signals in UM-419, UM-429 initialization sequence UM-615
forcing signals in UM-97, UM-425, UM-434 inlining
Index
Verilog modules UM-125 importing FPGA libraries UM-69

VHDL subprograms UM-74 including precompiled modules GR-71, GR-80
instance listing contents CR-328
code coverage UM-334 mapping
instantiation in mixed-language design from the command line UM-62
Verilog from VHDL UM-203 from the GUI UM-62
VHDL from Verilog UM-207 hierarchically UM-537
instantiation in SystemC-Verilog design search rules UM-63
SystemC from Verilog UM-214 modelsim_lib UM-96
Verilog from SystemC UM-209 moving UM-63
instantiation in SystemC-VHDL design multiple libraries with common modules UM-118
VHDL from SystemC UM-217 naming UM-62
instantiation in VHDL-SystemC design precompiled modules, including CR-361
SystemC from VHDL UM-222 predefined UM-64
interconnect delays CR-378, UM-451 refreshing library images CR-316, CR-365, UM-66
annotating per Verilog 2001 CR-389 resource libraries UM-58
internal signals, adding to a VCD file CR-292 std library UM-64
IOPATH Synopsys UM-65
matching to specify path delays UM-445 vendor supplied, compatibility of CR-328
iteration_limit, infinite zero-delay loops UM-81 Verilog CR-386, UM-117, UM-194
IterationLimit .ini file variable UM-532 VHDL library clause UM-64
working libraries UM-58
working vs resource UM-24
K working with contents of UM-61
library map file, Verilog configurations UM-122
keyboard shortcuts
library mapping, overview UM-25
List window UM-608
library maps, Verilog 2001 UM-122
Main window UM-605
library simulator state variable UM-542
Source window UM-605
library, definition in ModelSim UM-24
Wave window UM-609
libsm UM-618
keywords
libswift UM-618
disabling 2001 keywords CR-366
entry not found error UM-555
enabling System Verilog keywords CR-365
License .ini file variable UM-532
licensing
L License variable in .ini file UM-532
linking SystemC source UM-172
-L work UM-118 lint-style checks CR-362
language templates GR-201 List Signal Properties dialog GR-159
language versions, VHDL UM-75 List Signal Search dialog GR-157
lecho command CR-188 List window UM-243, GR-153
left command CR-189 adding items to CR-48
libraries context menu GR-155
64-bit and 32-bit in same library UM-66 GUI changes UM-509
archives CR-356 setting triggers UM-266
creating UM-60 waveform comparison UM-281
dependencies, checking CR-328 see also windows, List window
design libraries, creating CR-356, UM-60 LM_LICENSE_FILE environment variable UM-521
design library types UM-58 Load Coverage Data dialog GR-89
design units UM-58 loading the design, overview UM-26
group use, setting up UM-63 Locals window GR-166
IEEE UM-65 see also windows, Locals window
Index
location maps, referencing source files UM-67 manuals UM-35

locations maps mapping
specifying source files with UM-67 data types UM-193
lock message UM-551 libraries
locking cursors UM-245 from the command line UM-62
log command CR-191 hierarchically UM-537
log file symbols
log command CR-191 Dataflow window UM-313
nolog command CR-209 SystemC in mixed designs UM-202
overview UM-225 SystemC to Verilog UM-199
QuickSim II format CR-413 SystemC to VHDL UM-202
redirecting with -l CR-377 Verilog states in mixed designs UM-194
virtual log command CR-343 Verilog states in SystemC designs UM-198
virtual nolog command CR-346 Verilog to SytemC, port and data types UM-198
see also WLF files Verilog to VHDL data types UM-193
Logic Modeling VHDL to SystemC UM-196
SmartModel VHDL to Verilog data types UM-195
command channel UM-622 mapping libraries, library mapping UM-62
SmartModel Windows mapping signals, waveform editor GR-295
lmcwin commands UM-623 master slave library (SystemC), including CR-256
memory arrays UM-624 math_complex package UM-65
long simulations math_real package UM-65
saving at intervals UM-231 +maxdelays CR-362
lshift command CR-193 mc_scan_plusargs()
lsublist command CR-194 using with an elaboration file UM-84, UM-140
mc_scan_plusargs, PLI routine CR-388
MDI frame UM-501, GR-17
M MDI pane
tab groups GR-18
Macro dialog GR-102
mem display command CR-196
macro_option command CR-195
mem list command CR-198
MacroNestingLevel simulator state variable UM-542
mem load command CR-199
macros (DO files) UM-487
mem save command CR-202
breakpoints, executing at CR-76
mem search command CR-204
creating from a saved transcript GR-17
memories
depth of nesting, simulator state variable UM-542
displaying the contents of GR-169
error handling UM-490
initializing GR-175
executing CR-151
loading memory patterns GR-175
forcing signals, nets, or registers CR-180
MTI memory data file GR-178
parameters
MTI’s definition of GR-170
as a simulator state variable (n) UM-542
navigating to memory locations GR-182
passing CR-151, UM-487
saving memory data to a file GR-177
total number passed UM-542
selecting memory instances GR-171
relative directories CR-151
sparse memory modeling UM-156
shifting parameter values CR-266
viewing contents GR-171
Startup macros UM-538
viewing multiple instances GR-171
.main clear command CR-43
memory
Main window GR-14
modeling in VHDL UM-101
code coverage UM-340
memory allocation profiler UM-318
GUI changes UM-500
Memory Declaration, View menu UM-513
see also windows, Main window
memory leak, cancelling scheduled events UM-108
Index
Memory window GR-169 mixed-language simulation UM-188

GUI changes UM-510 access limitations UM-190
modifying display GR-183 mnemonics, assigning to signal values CR-354
see also windows, Memory window MODEL_TECH environment variable UM-521
window MODEL_TECH_TCL environment variable UM-521
Memory window modeling memory in VHDL UM-101
see also Memory window ModelSim
memory, displaying contents CR-196 commands CR-31–CR-432
memory, listing CR-198 modes of operation UM-27
memory, loading contents CR-199 simulation task overview UM-23
memory, saving contents CR-202 tool structure UM-22
memory, searching for patterns CR-204 verification flow UM-22
menu options grayed-out UM-501 modelsim command CR-206
menus MODELSIM environment variable UM-521
Dataflow window GR-129 modelsim.ini
List window GR-154 found by ModelSim UM-615
Main window GR-20 default to VHDL93 UM-539
Profiler windows GR-195 delay file opening with UM-539
Source window GR-206 environment variables in UM-537
Wave window GR-216 force command default, setting UM-539
merging coverage data UM-354, UM-396 hierarchical library mapping UM-537
merging coverage reports CR-320 opening VHDL files UM-539
messages UM-545 restart command defaults, setting UM-539
bad magic number UM-227 startup file, specifying with UM-538
echoing CR-156 transcript file created from UM-537
empty port name warning UM-551 turning off arithmetic package warnings UM-538
exit codes UM-549 turning off assertion messages UM-538
getting more information CR-329, UM-546 modelsim.tcl file GR-266
loading, disbling with -quiet CR-316, CR-365 modelsim_lib UM-96
lock message UM-551 path to UM-525
long description UM-546 MODELSIM_TCL environment variable UM-521
message system variables UM-536 modes of operation, ModelSim UM-27
metavalue detected UM-552 Modified field, Project tab UM-45
ModelSim message system UM-546 Modify Breakpoints dialog GR-95
redirecting UM-534 Modify Display Properties dialog GR-162
sensitivity list warning UM-552 modules
suppressing warnings from arithmetic packages handling multiple, common names UM-118
UM-538 with unnamed ports UM-206
Tcl_init error UM-552 Monitor window
too few port connections UM-554 adding items to CR-51
turning off assertion messages UM-538 grouping/ungrouping objects GR-209
VSIM license lost UM-555 monitor window GR-208
warning, suppressing UM-548 add monitor command CR-51
metavalue detected warning UM-552 monitors, dual, font scaling GR-28
MGC_LOCATION_MAP env variable UM-67 mouse shortcuts
MGC_LOCATION_MAP variable UM-521 Main window UM-605
+mindelays CR-362 Source window UM-605
MinGW gcc UM-569, UM-575 Wave window UM-609
missed coverage .mpf file UM-38
branches GR-120 loading from the command line UM-55
Missed Coverage pane GR-120 order of access during startup UM-612
Index
MTI memory data file GR-178 +nolibcell CR-363

mti_cosim_trace environment variable UM-521 nolog command CR-209
mti_inhibit_inline attribute UM-74 NOMMAP environment variable UM-522
MTI_SYSTEMC macro UM-168 non-blocking assignments UM-134
MTI_TF_LIMIT environment variable UM-522 NoOthersStaticError .ini file variable UM-527
multiclocked assertions UM-369 NoRangeCheck .ini file variable UM-527
multiple document interface UM-501, GR-17 Note .ini file variable UM-536
multiple drivers on unresolved signal GR-53, GR-62 notepad command CR-211
Multiple simulations UM-225 Notepad windows, text editing UM-605
multi-source interconnect delays CR-378 -notrigger argument UM-268
noview command CR-212
NoVital .ini file variable UM-527
N NoVitalCheck .ini file variable UM-527
Now simulator state variable UM-542
n simulator state variable UM-542
now simulator state variable UM-542
name case sensitivity, VHDL vs. Verilog CR-15
+nowarn<CODE> CR-364
Name field
nowhen command CR-213
Project tab UM-45
numeric_bit package UM-65
name visibility in Verilog generates UM-123
numeric_std package UM-65
names, modules with the same UM-118
disabling warning messages UM-538
negative pulses
NumericStdNoWarnings .ini file variable UM-533
driving an error state CR-388
Negative timing
$setuphold/$recovery UM-150 O
negative timing
algorithm for calculating delays UM-136 object
check limits UM-136 defined UM-34
extending check limits CR-385 object_list_file, WLF files CR-416
nets Objects window GR-184
Dataflow window, displaying in UM-300, GR-128 see also windows, Objects window
drivers of, displaying CR-154 observe function, SystemC UM-192
readers of, displaying CR-242 observe_foreign_signal() function UM-183
stimulus CR-180 onbreak command CR-214
values of onElabError command CR-215
displaying in Objects window GR-184 onerror command CR-216
examining CR-162 Open File dialog GR-39
saving as binary log file UM-226 opening files GR-39
waveforms, viewing GR-211 operating systems supported, See Installation Guide
new features UM-499 Optimization Configuration dialog GR-45
next and previous edges, finding UM-610 Optimization Configurations UM-49
next command CR-207 optimizations
Nlview widget Symlib format UM-313 disabling for Verilog designs CR-364
no space in time literal GR-53, GR-62 disabling for VHDL designs CR-315
-no_risefall_delaynets CR-387 disabling process merging CR-311
NoCaseStaticError .ini file variable UM-527 gate-level designs UM-127
NoDebug .ini file variable (VCOM) UM-527 Verilog designs UM-124
NoDebug .ini file variable (VLOG) UM-526 VHDL subprogram inlining UM-74
-nodebug argument (vcom) CR-314 via the gui GR-70
-nodebug argument (vlog) CR-363 vopt command CR-371
noforce command CR-208 optimize for std_logic_1164 GR-53, GR-62
NoIndexCheck .ini file variable UM-527 Optimize_1164 .ini file variable UM-527
Index
optimizing Verilog designs improving for Verilog simulations UM-124

design object visibility UM-126 vopt command CR-371
event order issues UM-128 platforms supported, See Installation Guide
timing checks UM-128 play command CR-218
OptionFile entry in project files GR-56, GR-65 PLI
order of events loading shared objects with global symbol visibility
changing in Verilog CR-358 CR-376, UM-581
in optimized designs UM-128 specifying which apps to load UM-562
ordering files for compile UM-46 Veriuser entry UM-562
organizing projects with folders UM-50 PLI/VPI UM-158, UM-560
organizing windows, MDI pane GR-18 debugging UM-399
OSCI 2.1 features supported UM-183 tracing UM-599
OSCI simulator, differences from ModelSim UM-182 PLIOBJS environment variable UM-522, UM-562
OSCI simulator, differences with vsim UM-182 pop command CR-219
others .ini file variable UM-525 popup
overriding the simulator resolution UM-174 toggling waveform popup on/off UM-280, GR-256
overview, simulation tasks in ModelSim UM-23 Port driver data, capturing UM-467
ports, unnamed, in mixed designs UM-206
ports, VHDL and Verilog UM-193
P Postscript
saving a waveform in UM-262
packages
saving the Dataflow display in UM-310
standard UM-64
power add command CR-220
textio UM-64
power report command CR-221
util UM-96
power reset command CR-222
VITAL 1995 UM-93
pragmas UM-347
VITAL 2000 UM-93
precedence of variables UM-541
page setup
precision, simulator resolution UM-129, UM-191
Dataflow window UM-312
pref.tcl file GR-266
Wave window UM-262, GR-230
Preference dialog GR-104
pan, Dataflow window UM-305
preference variables
panes
.ini files, located in UM-524
docking and undocking GR-258
editing GR-266
parameter support
saving GR-266
SystemC instantiating Verilog UM-211
Tcl files, located in GR-266
Verilog instantiating SystemC UM-214
Preferences
parameters
drag and drop GR-103
making optional UM-488
preferences, saving GR-266
using with macros CR-151, UM-487
primitives, symbols in Dataflow window UM-313
path delay mode UM-145
Print dialog GR-135
path delays,matching to IOPATH statements UM-445
Print Postscript dialog GR-137
pathnames
printenv command CR-223, CR-224
comparisons UM-279
printing
hiding in Wave window UM-255
Dataflow window display UM-310
in VSIM commands CR-12
waveforms in the Wave window UM-262
spaces in CR-11
Process window GR-143
PathSeparator .ini file variable UM-533
see also windows, Process window
pause command CR-217
processes
PedanticErrors .ini file variable UM-527
optimizations, disabling merging CR-311
performance
without wait statements GR-53, GR-62
cancelling scheduled events UM-108
profile clear command CR-225
Index
profile interval command CR-226 override mapping for work directory with vcom CR-
profile off command CR-227 256, CR-317
profile on command CR-228 override mapping for work directory with vlog CR-
profile option command CR-229 366
profile reload command CR-230 overview UM-38
profile report command CR-231, UM-331 propagation, preventing X propagation CR-378
Profile Report dialog GR-93, GR-197 Properties (memory) dialog GR-183
Profiler UM-317 property list command CR-234
%parent fields UM-325 property wave command CR-235
clear profile data UM-321 Protect .ini file variable (VLOG) UM-526
enabling memory profiling UM-319 ‘protect compiler directive UM-155
enabling statistical sampling UM-321 protected types UM-101
getting started UM-319 PSL
handling large files UM-320 assume directives UM-363
Hierarchical View UM-325 endpoint directives UM-398
interpreting data UM-323 standard supported UM-30
memory allocation UM-318 PSL assertions UM-359
memory allocation profiling UM-321 see also assertions
profile report command UM-331 pulse error state CR-388
Profile Report dialog UM-332, GR-93 push command CR-237
Ranked View UM-324 pwd command CR-238
report option UM-331
reporting GR-93
results, viewing UM-324 Q
statistical sampling UM-318
quick reference
Structural View UM-326
table of ModelSim tasks UM-23
unsupported on Opteron UM-317
QuickSim II logfile format CR-413
view_profile command UM-324
Quiet .ini file variable
viewing profile details UM-327
VCOM UM-527
Programming Language Interface UM-158, UM-560
Quiet .ini file variable (VLOG) UM-526
Project Compiler Settings dialog GR-50
quietly command CR-239
Project Settings dialog GR-57
quit command CR-240
project tab
information in UM-45
sorting UM-45 R
Projects
MODELSIM environment variable UM-521 race condition, problems with event order UM-132
projects UM-37 radix
accessing from the command line UM-55 changing in Objects, Locals, Dataflow, List, and
adding files to UM-41 Wave windows CR-241
benefits UM-38 character strings, displaying CR-354
code coverage settings UM-338 default, DefaultRadix variable UM-531
compile order UM-46 List window UM-259
changing UM-46 of signals being examined CR-163
compiler properties in UM-52 of signals in Wave window CR-54
compiling files UM-43 specifying in Memory window GR-183
creating UM-40 Wave window UM-255
creating simulation configurations UM-48 radix command CR-241
folders in UM-50 range checking UM-74
grouping files in UM-47 disabling CR-315
loading a design UM-44 enabling CR-316
Index
readers and drivers UM-303 RunLength .ini file variable UM-533

readers command CR-242 Runtime Options dialog GR-85
real type, converting to time UM-99
reative testbenches, PSL endpoints UM-398
rebuilding supplied libraries UM-65 S
reconstruct RTL-level design busses UM-234
record command CR-243 Save Memory dialog GR-177
record field selection, syntax CR-13 saving
records, values of, changing GR-167 simulation options in a project UM-48
$recovery UM-150 waveforms UM-225
redirecting messages, TranscriptFile UM-534 saving simulations UM-86, UM-142
reference region UM-275 sc_argc() function UM-183
refreshing library images CR-316, CR-365, UM-66 sc_argv() function UM-183
sc_clock() functions, moving UM-164
registered function calls UM-407
sc_cycle() function UM-182
registers
sc_fifo UM-181
values of
sc_foreign_module UM-217
displaying in Objects window GR-184
and parameters UM-211
saving as binary log file UM-226
sc_initialize(), removing calls UM-182
waveforms, viewing GR-211
sc_main() function UM-182
report
sc_main() function, converting UM-164
simulator control UM-520
SC_MODULE_EXPORT macro UM-165
simulator state UM-520
sc_set_time_resolution() function UM-182
report command CR-244
sc_start() function UM-182
reporting
sc_start() function, replacing in SystemC UM-182
code coverage UM-350
sc_start(), replacing for ModelSim UM-164
variable settings CR-17
ScalarOpts .ini file variable UM-526, UM-527
RequireConfigForAllDefaultBinding variable UM-527
scaling fonts GR-13
resolution
sccom
in SystemC simulation UM-174
using sccom vs. raw C++ compiler UM-170
mixed designs UM-191
sccom command CR-254
overriding in SystemC UM-174
sccom -link command UM-172, UM-223
returning as a real UM-96
sccomLogfile .ini file variable (sccom) UM-528
specifying with -t argument CR-380
sccomVerbose .ini file variable (sccom) UM-528
verilog simulation UM-129
scgenmod command CR-258
VHDL simulation UM-78
scgenmod, using UM-209, UM-217
Resolution .ini file variable UM-533
-sclib command CR-389
resolution simulator state variable UM-542
scope, setting region environment CR-161
resource libraries UM-64
SCV library, including CR-255
restart command CR-246
SDF
defaults UM-539
controlling missing instance messages CR-380
in GUI GR-26
disabling individual checks CR-275
toolbar button GR-35, GR-127, GR-222
disabling timing checks UM-451
Restart dialog GR-88
errors and warnings UM-441
restore command CR-248
errors on loading, disabling CR-380
restoring defaults UM-520
instance specification UM-440
results, saving simulations UM-225
interconnect delays UM-451
resume command CR-249
mixed VHDL and Verilog designs UM-450
right command CR-250
specification with the GUI UM-441
RTL-level design busses
troubleshooting UM-452
reconstructing UM-234
Verilog
run command CR-252
Index
$sdf_annotate system task UM-444 show drivers

optional conditions UM-449 Dataflow window UM-303
optional edge specifications UM-448 Wave window UM-269
rounded timing values UM-449 show source lines with errors GR-52, GR-61
SDF to Verilog construct matching UM-445 Show_BadOptionWarning .ini file variable UM-526
VHDL Show_Lint .ini file variable (VLOG) UM-526, UM-527
resolving errors UM-443 Show_source .ini file variable
SDF to VHDL generic matching UM-442 VCOM UM-528
warning messages, disabling CR-380 Show_source .ini file variable (VLOG) UM-526
$sdf_done UM-152 Show_VitalChecksWarning .ini file variable UM-528
search command CR-260 Show_Warning1 .ini file variable UM-528
search libraries CR-386, GR-71, GR-80 Show_Warning2 .ini file variable UM-528
searching Show_Warning3 .ini file variable UM-528
binary signal values in the GUI CR-29 Show_Warning4 .ini file variable UM-528
Expression Builder UM-253 Show_Warning5 .ini file variable UM-528
in the source window GR-204 Show3DMem .ini file variable UM-533
List window ShowEnumMem .ini file variable UM-533
signal values, transitions, and names CR-22, ShowIntMem .ini file variable UM-533
CR-152, CR-290 Signal Breakpoints dialog GR-97
next and previous edge in Wave window CR-189, signal interaction
CR-250 Verilog and SystemC UM-196
Verilog libraries UM-117, UM-207 Signal Spy UM-97, UM-422
Wave window overview UM-418
signal values, edges and names CR-189, CR- using in PSL assertions UM-367
250, GR-233 $signal_force UM-434
searchlog command CR-262 signal_force UM-97, UM-425
seetime command CR-264 $signal_release UM-436
sensitivity list warning UM-552 signal_release UM-97, UM-427
setenv command CR-265 signals
$setuphold UM-150 alternative names in the List window (-label) CR-48
severity, changing level for errors UM-546 alternative names in the Wave window (-label) CR-
shared library 53
building in SystemC UM-172, GR-25 applying stimulus to GR-186
shared objects attributes of, using in expressions CR-24
loading FLI applications breakpoints CR-407
see ModelSim FLI Reference manual combining into a user-defined bus CR-53, UM-264
loading PLI/VPI C applications UM-568 Dataflow window, displaying in UM-300, GR-128
loading PLI/VPI C++ applications UM-574 drivers of, displaying CR-154
loading with global symbol visibility CR-376, UM- driving in the hierarchy UM-419
581 environment of, displaying CR-161
shift command CR-266 filtering in the Objects window GR-185
Shortcuts finding CR-176
text editing UM-605 force time, specifying CR-181
shortcuts hierarchy
command history CR-19, UM-603 driving in UM-419, UM-429
command line caveat CR-18, UM-603 referencing in UM-97, UM-422, UM-432
List window UM-608 releasing anywhere in UM-427
Main window UM-605 releasing in UM-97, UM-436
Source window UM-605 log file, creating CR-191
Wave window UM-609 names of, viewing without hierarchy GR-255
show command CR-267 pathnames in VSIM commands CR-12
Index
radix optimizing Verilog performance CR-360

specifying for examine CR-163 saving dataflow display as a Postscript file UM-310
specifying in List window CR-49 saving options in a project UM-48
specifying in Wave window CR-54 saving simulations CR-191, CR-382, UM-225
readers of, displaying CR-242 saving waveform as a Postscript file UM-262
sampling at a clock change UM-268 speeding-up with the Profiler UM-317
states of, displaying as mnemonics CR-354 stepping through a simulation CR-272
stimulus CR-180 stimulus, applying to signals and nets GR-186
transitions, searching for UM-249 stopping simulation in batch mode CR-410
types, selecting which to view GR-185 SystemC UM-159, UM-173
unresolved, multiple drivers on GR-53, GR-62 usage flow for SystemC only UM-163
values of time resolution GR-77
displaying in Objects window GR-184 Verilog UM-129
examining CR-162 delay modes UM-144
forcing anywhere in the hierarchy UM-97, hazard detection UM-135
UM-425, UM-434 optimizing performance UM-124
replacing with text CR-354 resolution limit UM-129
saving as binary log file UM-226 XL compatible simulator options UM-136
waveforms, viewing GR-211 VHDL UM-78
Signals (Objects) window UM-514 viewing results in List window UM-243, GR-153
SimulateAssumeDirectives .ini file variable UM-533 VITAL packages UM-95
Simulating simulating the design, overview UM-26
Comparing simulations UM-225 simulation
simulating basic steps for UM-24
batch mode UM-27 Simulation Configuration
command-line mode UM-27 creating UM-48
default run length GR-86 dialog GR-46
delays, specifying time units for CR-18 simulations
design unit, specifying CR-373 event order in UM-132
elaboration file UM-82, UM-138 saving results CR-143, CR-144, UM-225
graphic interface to GR-76 saving results at intervals UM-231
iteration limit GR-86 saving with checkpoint UM-86, UM-142
mixed language designs simulator resolution
compilers UM-190 mixed designs UM-191
libraries UM-190 returning as a real UM-96
resolution limit in UM-191 SystemC UM-174
mixed Verilog and SystemC designs Verilog UM-129
channel and port type mapping UM-196 VHDL UM-78
SystemC sc_signal data type mapping UM-197 vsim -t argument CR-380
Verilog port direction UM-198 simulator state variables UM-542
Verilog state mapping UM-198 simulator version CR-381, CR-392
mixed Verilog and VHDL designs simulator, ModelSim and OSCI differences UM-182
Verilog parameters UM-193 simultaneous events in Verilog
Verilog state mapping UM-194 changing order CR-358
VHDL and Verilog ports UM-193 sizetf callback function UM-587
VHDL generics UM-195 sm_entity UM-619
mixed VHDL and SystemC designs SmartModels
SystemC state mapping UM-202 creating foreign architectures with sm_entity UM-
VHDL port direction UM-201 619
VHDL port type mapping UM-200 invoking SmartModel specific commands UM-622
VHDL sc_signal data type mapping UM-200 linking to UM-618
Index
lmcwin commands UM-623 files accessed during UM-612

memory arrays UM-624 macro in the modelsim.ini file UM-534
Verilog interface UM-625 startup macro in command-line mode UM-27
VHDL interface UM-618 using a startup file UM-538
so, shared object file Startup .ini file variable UM-534
loading PLI/VPI C applications UM-568 state variables UM-542
loading PLI/VPI C++ applications UM-574 statistical sampling profiler UM-318
software version GR-33 status bar
source balloon Main window GR-19
C Debug GR-99 status command CR-271
source code pragmas UM-347 Status field
source code, security UM-70, UM-155 Project tab UM-45
source directory, setting from source window GR-21, std .ini file variable UM-525
GR-206 std_arith package
source errors, locating during compilation GR-264 disabling warning messages UM-538
source files, referencing with location maps UM-67 std_developerskit .ini file variable UM-525
source files, specifying with location maps UM-67 Std_logic
source highlighting, customizing GR-205 mapping to binary radix CR-29
source libraries std_logic_arith package UM-65
arguments supporting UM-119 std_logic_signed package UM-65
source lines with errors std_logic_textio UM-65
showing GR-52, GR-61 std_logic_unsigned package UM-65
Source window GR-199 StdArithNoWarnings .ini file variable UM-534
code coverage data UM-341 STDOUT environment variable UM-522
colorization GR-205 step command CR-272
tab stops in GR-205 steps for simulation, overview UM-24
see also windows, Source window stimulus
source-level debug applying to signals and nets GR-186
SystemC, enabling UM-178 modifying for elaboration file UM-83, UM-139
spaces in pathnames CR-11 stop command CR-273
sparse memories struct of sc_signal<T> UM-180
listing with write report CR-426 subprogram inlining UM-74
sparse memory modeling UM-156 subprogram write is ambiguous error, fixing UM-90
SparseMemThreshhold .ini file variable UM-526 Support UM-36
specify path delays CR-388 Suppress .ini file variable UM-536
matching to IOPATH statements UM-445 symbol mapping
speeding-up the simulation UM-317 Dataflow window UM-313
splitio command CR-270 symbolic constants, displaying CR-354
square brackets, escaping CR-15 symbolic link to design libraries (UNIX) UM-63
stability checking symbolic names, assigning to signal values CR-354
disabling CR-91 Synopsis hardware modeler UM-628
enabling CR-92 synopsys .ini file variable UM-525
Standard Developer’s Kit User Manual UM-35 Synopsys libraries UM-65
standards supported UM-30 syntax highlighting GR-205
Start Simulation dialog GR-76 synthesis
start_of_simulation() function UM-183 rule compliance checking CR-312, UM-527, GR-
Startup 52, GR-61
macros UM-538 system calls
startup VCD UM-461
alternate to startup.do (vsim -do) CR-374 Verilog UM-146
environment variables access during UM-613 system commands UM-479
Index
system tasks exporting for use in VHDL UM-223

VCD UM-461 SystemVerilog UM-30
Verilog UM-146 SystemVerilog DPI
Verilog-XL compatible UM-150 registering DPIapplications UM-565
system tasks and functions specifying the DPI file to load UM-580
ModelSim Verilog UM-152
System Verilog
enabling with -sv argument CR-365 T
SystemC
aggregates of signals/ports UM-180 tab groups GR-18
class and structure member naming syntax CR-13 tab stops
compiling for source level debug UM-167 Source window GR-205
compiling optimized code UM-167 tb command CR-274
tcheck_set command CR-275
component declaration for instantiation UM-223
tcheck_status command CR-277
control function UM-192
Tcl UM-472–UM-482
converting sc_main() UM-164
command separator UM-478
exporting sc_main, example UM-165
command substitution UM-477
exporting top level module UM-165
command syntax UM-474
foreign module declaration UM-209
evaluation order UM-478
generic support, instantiating VHDL UM-218
history shortcuts CR-19, UM-603
hierarchical reference support UM-183
Man Pages in Help menu GR-33
hierarchical references in mixed designs UM-192
preference variables GR-266
instantiation criteria in Verilog design UM-214
relational expression evaluation UM-478
instantiation criteria in VHDL design UM-222
time commands UM-481
Link dialog GR-68
variable
linking the compiled source UM-172
in when commands CR-408
maintaining design portability UM-168
substitution UM-479
mapping states in mixed designs UM-202
VSIM Tcl commands UM-480
VHDL UM-202
Tcl_init error message UM-552
master slave library, including CR-256
Technical support and updates UM-36
mixed designs with Verilog UM-188
temp files, VSOUT UM-523
mixed designs with VHDL UM-188
test signal
observe function UM-192
delaying GR-244
parameter support, Verilog instances UM-211
testbench, accessing internal objectsfrom UM-417
prim channel aggregates UM-180
testbenches
replacing sc_start() UM-164
PSL endpoint reactivity UM-398
sc_clock(), moving to SC_CTOR UM-164
text and command syntax UM-34
sc_fifo UM-181
Text editing UM-605
simulating UM-173
TEXTIO
source code, modifying for ModelSim UM-164
buffer, flushing UM-92
specifying shared library path, command CR-389
TextIO package
stack space for threads UM-184
alternative I/O files UM-92
state-based code, initializing and cleanup UM-175
containing hexadecimal numbers UM-91
troubleshooting UM-184
dangling pointers UM-91
unsupported functions UM-182
ENDFILE function UM-91
verification library, including CR-255
ENDLINE function UM-91
viewable/debuggable objects UM-176
file declaration UM-88
viewing FIFOs UM-181
implementation issues UM-90
virtual functions UM-175
providing stimulus UM-92
SystemC modules
standard input UM-89
exporting for use in Verilog UM-214
Index
standard output UM-89 toggle statistics

WRITE procedure UM-90 enabling CR-279
WRITE_STRING procedure UM-90 reporting CR-283
TF routines UM-593, UM-595 resetting CR-284
TFMPC toggling waveform popup on/off UM-280, GR-256
disabling warning CR-387 tolerance
explanation UM-554 leading edge UM-276
time trailing edge UM-276
absolute, using @ CR-18 too few port connections, explanation UM-554
measuring in Wave window UM-245 toolbar
resolution in SystemC UM-174 Dataflow window GR-132
simulation time units CR-18 Main window GR-34
time resolution as a simulator state variable UM-542 Wave window GR-220
time collapsing CR-382, UM-232 waveform editor GR-222
time literal, missing space GR-53, GR-62 tooltip, toggling waveform popup GR-256
time resolution tracing
in mixed designs UM-191 events UM-306
in Verilog UM-129 source of unknown UM-307
in VHDL UM-78 transcribe command CR-285
setting transcript
with the GUI GR-77 clearing CR-43
with vsim command CR-380 disable file creation UM-537, GR-17
time type file name, specifed in modelsim.ini UM-537
converting to real UM-98 redirecting with -l CR-377
time, time units, simulation time CR-18 reducing file size CR-287
timescale directive warning saving GR-16
disabling CR-387 using as a DO file GR-17
investigating UM-130 transcript command CR-286
timing transcript file command CR-287
$setuphold/$recovery UM-150 TranscriptFile .ini file variable UM-534
annotation UM-439 transitions, signal, finding CR-189, CR-250
differences shown by comparison UM-279 TreeUpdate command CR-423
disabling checks CR-364, UM-451 triggers, in the List window UM-266
disabling checks for entire design CR-379 triggers, in the List window, setting UM-265, GR-163
disabling individual checks CR-275 troubleshooting
in optimized designs UM-128 SystemC UM-184
negative check limits unexplained behaviors, SystemC UM-184
described UM-136 TSCALE, disabling warning CR-387
extending CR-385 TSSI CR-429
status of individual checks CR-277 in VCD files UM-467
title, Main window, changing CR-381 tssi2mti command CR-288
TMPDIR environment variable UM-522 type
to_real VHDL function UM-98 converting real to time UM-99
to_time VHDL function UM-99 converting time to real UM-98
toggle add command CR-279 Type field, Project tab UM-45
toggle coverage types, fixed point in SystemC UM-182
excluding signals CR-281
toggle disable command CR-281
toggle enable command CR-282
toggle report command CR-283
toggle reset command CR-284
Index
U simulator state variables

current settings report UM-520
-u CR-365 iteration number UM-542
unbound component GR-53, GR-62 name of entity or module as a variable UM-542
UnbufferedOutput .ini file variable UM-534 resolution UM-542
undeclared nets, reporting an error CR-362 simulation time UM-542
undefined symbol, error UM-184 value of
unexplained behavior during simulation UM-184 changing from command line CR-81
unexplained simulation behavior UM-184 changing with the GUI GR-167
ungrouping objects, Monitor window GR-209 examining CR-162
unit delay mode UM-145 values of
unknowns, tracing UM-307 displaying in Objects window GR-184
unnamed ports, in mixed designs UM-206 saving as binary log file UM-226
unresolved signals, multiple drivers on GR-53, GR-62 Variables (Locals) window UM-518
unsetenv command CR-289 variables, Tcl, user hook GR-107
unsupported functions in SystemC UM-182 vcd add command CR-292
up command CR-290 vcd checkpoint command CR-293
UpCase .ini file variable UM-526 vcd comment command CR-294
use 1076-1993 language standard GR-51, GR-60 vcd dumpports command CR-295
use clause, specifying a library UM-64 vcd dumpportsall command CR-297
use explicit declarations only GR-52, GR-61 vcd dumpportsflush command CR-298
use flow vcd dumpportslimit command CR-299
Code Coverage UM-334 vcd dumpportsoff command CR-300
SystemC-only designs UM-163 vcd dumpportson command CR-301
UseCsupV2 .ini file variable UM-534 vcd file command CR-302
user hook Tcl variable GR-107 VCD files UM-455
user-defined bus CR-53, UM-233, UM-264 adding items to the file CR-292
UserTimeUnit .ini file variable UM-534 capturing port driver data CR-295, UM-467
UseScv .ini file variable (sccom) UM-528 case sensitivity UM-456
util package UM-96 converting to WLF files CR-310
creating CR-292, UM-456
dumping variable values CR-293
V dumpports tasks UM-461
flushing the buffer contents CR-306
-v CR-366 from VHDL source to VCD output UM-463
v2k_int_delays CR-389 generating from WLF files CR-415
values inserting comments CR-294
describe HDL items CR-147 internal signals, adding CR-292
examine HDL item values CR-162 specifying maximum file size CR-307
of HDL items GR-203 specifying name of CR-304
replacing signal values with strings CR-354 specifying the file name CR-302
variable settings report CR-17 state mapping CR-302, CR-304
variables stimulus, using as UM-458
describing CR-147 supported TSSI states UM-467
environment variables UM-521 turn off VCD dumping CR-308
LM_LICENSE_FILE UM-521 turn on VCD dumping CR-309
personal preferences UM-520 VCD system tasks UM-461
precedence between .ini and .tcl UM-541 viewing files from another tool CR-310
reading from the .ini file UM-536 vcd files command CR-304
referencing in commands CR-17 vcd flush command CR-306
setting environment variables UM-521 vcd limit command CR-307
Index
vcd off command CR-308 simulation resolution limit UM-129

vcd on command CR-309 SmartModel interface UM-625
vcd2wlf command CR-310 source code viewing GR-199
vcom standards UM-30
enabling code coverage UM-337 system tasks UM-146
vcom command CR-311 TF routines UM-593, UM-595
vcover command UM-354 to SystemC, channel and port type mapping UM-
vcover convert command CR-319 196
vcover merge command CR-320 XL compatible compiler options UM-119
vcover report command CR-322 XL compatible routines UM-597
vdel command CR-327 XL compatible system tasks UM-150
vdir command CR-328 verilog .ini file variable UM-525
vector elements, initializing CR-81 Verilog 2001
vendor libraries, compatibility of CR-328 disabling support CR-366, UM-526
Vera, see Vera documentation Verilog PLI/VPI
Verilog 64-bit support in the PLI UM-598
ACC routines UM-591 compiling and linking PLI/VPI C applications UM-
capturing port driver data with -dumpports CR-302, 568
UM-467 compiling and linking PLI/VPI C++ applications
cell libraries UM-144 UM-574
compiler directives UM-153 debugging PLI/VPI code UM-599
compiling and linking PLI C applications UM-568 PLI callback reason argument UM-585
compiling and linking PLI C++ applications UM- PLI support for VHDL objects UM-590
574 registering PLI applications UM-561
compiling design units UM-114 registering VPI applications UM-563
compiling with XL ’uselib compiler directive UM- specifying the PLI/VPI file to load UM-580
120 Verilog-XL
component declaration UM-204 compatibility with UM-111, UM-559
configurations UM-122 Veriuser .ini file variable UM-534, UM-562
event order in simulation UM-132 Veriuser, specifying PLI applications UM-562
generate statements UM-123 veriuser.c file UM-589
instantiation criteria in mixed-language design UM- verror command CR-329
203 version
instantiation criteria in SystemC design UM-209 obtaining via Help menu GR-33
instantiation of VHDL design units UM-207 obtaining with vsim command CR-381
language templates GR-201 obtaining with vsim<info> commands CR-392
library usage UM-117 vgencomp command CR-330
mapping states in mixed designs UM-194 VHDL
mapping states in SystemC designs UM-198 compiling design units UM-73
mixed designs with SystemC UM-188 creating a design library UM-73
mixed designs with VHDL UM-188 delay file opening UM-539
parameter support, instantiating SystemC UM-214 dependency checking UM-73
parameters UM-193 field naming syntax CR-13
port direction UM-198 file opening delay UM-539
sc_signal data type mapping UM-197 foreign language interface UM-100
SDF annotation UM-444 hardware model interface UM-628
sdf_annotate system task UM-444 instantiation criteria in SystemC design UM-217
simulating UM-129 instantiation from Verilog UM-207
delay modes UM-144 instantiation of Verilog UM-193
XL compatible options UM-136 language templates GR-201
simulation hazard detection UM-135 language versions UM-75
Index
library clause UM-64 virtual signal command CR-351, UM-233

mixed designs with SystemC UM-188 virtual signals
mixed designs with Verilog UM-188 reconstruct RTL-level design busses UM-234
object support in PLI UM-590 reconstruct the original RTL hierarchy UM-234
optimizations virtual hide command UM-234
inlining UM-74 virtual type command CR-354
port direction UM-201 visibility
port type mapping UM-200 column in structure tab UM-228
sc_signal data type mapping UM-200 VITAL
simulating UM-78 compiling and simulating with accelerated VITAL
SmartModel interface UM-618 packages UM-95
source code viewing GR-199 compliance warnings UM-94
standards UM-30 disabling optimizations for debugging UM-95
timing check disabling UM-78 specification and source code UM-93
VITAL package UM-65 VITAL packages UM-93
VHDL utilities UM-96, UM-97, UM-422, UM-432 vital95 .ini file variable UM-525
get_resolution() UM-96 vlib command CR-356
to_real() UM-98 vlog
to_time() UM-99 enabling code coverage UM-337
VHDL-1987, compilation problems UM-75 vlog command CR-358
VHDL-1993, enabling support for CR-311, UM-528 vlog.opt file GR-56, GR-65
VHDL-2002, enabling support for CR-311, UM-528 vlog95compat .ini file variable UM-526
VHDL93 .ini file variable UM-528 vmake command CR-369
view command CR-332 vmap command CR-370
view_profile command UM-324 vopt
viewing gui access GR-70
library contents UM-61 vopt command CR-371, UM-124
waveforms CR-382, UM-225 VoptFlow .ini file variable UM-534
viewing FIFOs UM-181 VPI, registering applications UM-563
virtual count commands CR-334 VPI/PLI UM-158, UM-560
virtual define command CR-335 compiling and linking C applications UM-568
virtual delete command CR-336 compiling and linking C++ applications UM-574
virtual describe command CR-337 vsim build date and version CR-392
virtual expand commands CR-338 vsim command CR-373
virtual function command CR-339 VSIM license lost UM-555
virtual functions in SystemC UM-175 vsim, differences with OSCI simulator UM-182
virtual hide command CR-342, UM-234 VSOUT temp file UM-523
virtual log command CR-343
virtual nohide command CR-345
virtual nolog command CR-346 W
virtual objects UM-233
Warning .ini file variable UM-536
virtual functions UM-234
WARNING[8], -lint argument to vlog CR-362
virtual regions UM-235
warnings
virtual signals UM-233
changing severity of UM-546
virtual types UM-235
disabling at time 0 UM-538
virtual region command CR-348, UM-235
empty port name UM-551
virtual regions
exit codes UM-549
reconstruct the RTL hierarchy in gate-level design
getting more information UM-546
UM-235
messages, long description UM-546
virtual save command CR-349, UM-234
metavalue detected UM-552
virtual show command CR-350
Index
SDF, disabling CR-380 icons UM-281

suppressing VCOM warning messages CR-315, introduction UM-270
UM-548 leading edge tolerance UM-276
suppressing VLOG warning messages CR-364, List window display UM-281
UM-548 pathnames UM-279
suppressing VSIM warning messages CR-387, UM- reference dataset UM-272
548 reference region UM-275
Tcl initialization error 2 UM-552 test dataset UM-273
too few port connections UM-554 timing differences UM-279
turning off warnings from arithmetic packages UM- trailing edge tolerance UM-276
538 values column UM-280
waiting for lock UM-551 Wave window display UM-279
watching a signal value GR-208 Waveform Editor
watching signal values CR-51 Waveform Compare, using with GR-296
wave commands CR-394 waveform editor
wave create command CR-397 creating waveforms GR-289
wave edit command CR-400 creating waves CR-397
wave export command CR-403 editing commands CR-400
wave import command CR-404 editing waveforms GR-290
Wave Log Format (WLF) file UM-225 importing vcd stimulus file CR-404
wave log format (WLF) file CR-382 mapping signals GR-295
of binary signal values CR-191 modifying existing waves CR-405
see also WLF files saving stimulus files GR-294
wave modify command CR-405 saving waves CR-403
wave viewer, Dataflow window UM-304 simulating GR-293
Wave window UM-240, GR-211 toolbar buttons GR-222
adding items to CR-52 waveform logfile
compare waveforms UM-279 log command CR-191
docking and undocking UM-241, GR-212 overview UM-225
in the Dataflow window UM-304 see also WLF files
saving layout UM-261 waveform popup UM-280, GR-256
toggling waveform popup on/off UM-280, GR-256 waveforms UM-225
values column UM-280 optimize viewing of UM-535
see also windows, Wave window optimizing viewing of CR-382
WaveActivateNextPane command CR-423 saving and viewing CR-191, UM-226
Waveform Compare viewing GR-211
created waveforms, using with GR-296 WaveRestoreCursors command CR-423
Waveform Comparison CR-94 WaveRestoreZoom command CR-423
add region UM-275 WaveSignalNameWidth .ini file variable UM-534
adding signals UM-274 weighting, coverage directives UM-387
clocked comparison UM-276 Welcome dialog, turning on/off UM-520
compare by region UM-275 when command CR-407
compare by signal UM-274 when statement
compare options UM-278 time-based breakpoints CR-411
compare tab UM-273 where command CR-412
comparison method UM-276 wildcard characters
comparison method tab UM-276 for pattern matching in simulator commands CR-17
delaying the test signal GR-244 Windows
difference markers UM-279 Main window
flattened designs UM-283 text editing UM-605
hierarchical designs UM-283 Source window
Index
text editing UM-605 converting to VCD CR-415

windows creating from VCD CR-310
Active Processes pane GR-108 filtering, combining CR-416
buttons, adding to GR-106 limiting size CR-382
code coverage statistics UM-340 log command CR-191
Dataflow window UM-300, GR-128 optimizing waveform viewing CR-382, UM-535
toolbar GR-132 overview UM-226
zooming UM-305 repairing CR-420
Functional coverage browser GR-143 saving CR-143, CR-144, UM-227
List window UM-243, GR-153 saving at intervals UM-231
display properties of UM-259 specifying name CR-382
formatting HDL items UM-259 wlf2log command CR-413
output file CR-424 wlf2vcd command CR-415
saving data to a file UM-263 WLFCollapseMode .ini file variable UM-534
saving the format of CR-422 WLFFilename UM-535
setting triggers UM-265, UM-266, GR-163 wlfman command CR-416
Locals window GR-166 wlfrecover command CR-420
Main window GR-14 work library UM-58
adding user-defined buttons CR-45 creating UM-60
status bar GR-19 workspace GR-15
time and delta display GR-19 code coverage GR-116
toolbar GR-34 Files tab GR-116
Memory window GR-169 write cell_report command CR-421
monitor GR-208 write format command CR-422
Objects window GR-184 write list command CR-424
opening write preferences command CR-425
from command line CR-332 WRITE procedure, problems with UM-90
with the GUI GR-23 write report command CR-426
Process window GR-143 write timing command CR-427
specifying next process to be executed GR-143 write transcript command CR-428
viewing processing in the region GR-143 write tssi command CR-429
Signals window write wave command CR-431
VHDL and Verilog items viewed in GR-184
Source window GR-199
viewing HDL source code GR-199 X
Variables window
X
VHDL and Verilog items viewed in GR-166
tracing unknowns UM-307
Wave window UM-240, GR-211
.Xdefaults file, controlling fonts GR-13
adding HDL items to UM-244
X propagation
cursor measurements UM-245
disabling for entire design CR-378
display properties UM-255
disabling X generation on specific instances CR-
display range (zoom), changing UM-249
275
format file, saving UM-261
xml format
path elements, changing CR-125, UM-534
coverage reports UM-351
time cursors UM-245
X-session
zooming UM-249
controlling fonts GR-13
WLF file
collapsing deltas CR-382
collapsing time steps CR-382
WLF files
collapsing events UM-232
Index
Y
-y CR-366
Z
zero delay elements UM-80
zero delay mode UM-145
zero-delay loop, infinite UM-81
zero-delay oscillation UM-81
zero-delay race condition UM-132
zoom
Dataflow window UM-305
from Wave toolbar buttons UM-249
saving range with bookmarks UM-250
with the mouse UM-249
zooming window panes GR-260

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ModelSim ®

Advanced Verification and Debugging

ModelSim SE Command Reference

Technical support and updates

Latest version email

ModelSim SE Command Reference

Where to find our documentation

Document Format How to get it

ModelSim Installation & paper shipped with ModelSim

ModelSim Quick Guide paper shipped with ModelSim

ModelSim User’s Manual PDF, HTML select Help > Documentation

ModelSim Command PDF, HTML select Help > Documentation

ModelSim GUI Reference PDF, HTML select Help > Documentation

Foreign Language PDF, HTML select Help > Documentation

Technotes HTML select Technotes dropdown on www.model.com/support

ModelSim SE Command Reference

ModelSim SE Command Reference

configure CR-123 fcover save CR-175

ModelSim SE Command Reference

profile interval CR-226 toggle add CR-279

ModelSim SE Command Reference

virtual define CR-335 wave create CR-397

ModelSim SE Command Reference

Syntax and conventions

Design object names . . . . . . . . . . . . . . CR-12

Wildcard characters . . . . . . . . . . . . . . CR-17

ModelSim variables . . . . . . . . . . . . . . CR-17

Comments in argument files . . . . . . . . . . . . CR-18

Command shortcuts . . . . . . . . . . . . . . CR-18

Numbering conventions . . . . . . . . . . . . . CR-20

ModelSim SE Command Reference

Syntax notation Description

< > angled brackets surrounding a syntax item indicate a user-

{ } braces indicate that the enclosed expression contains one or

| the vertical bar indicates a choice between items on either side

# comments included with commands are preceded by the number

add wave {vector1[4:0]}

ModelSim SE Command Reference

File and directory pathnames

ModelSim SE Command Reference

Design object names

Object name syntax

ModelSim SE Command Reference

SystemC class/structure/union member specification

class beagle : public dog

You have an sc_signal<> of type beagle somewhere in your code:

Legal names for viewing this signal are:

To examine the member value of member d, you would type:

To examine the member value, you would type:

ModelSim SE Command Reference

clk specifies the object clk in the current context

/top/clk specifies the object clk in the top-level design unit.

array_sig[4] specifies an index of an array object

{array_sig(1 to 10)} specifies a slice of an array object in VHDL or

{mysignal[31:0]} specifies a slice of an array object in Verilog or

record_sig.field specifies a field of a record, a C++ class or structure

ModelSim SE Command Reference

Escaping brackets and spaces in array slices

Environment variables and pathnames

Name case sensitivity

ModelSim SE Command Reference

\\ext\ ident\!\\ # All non-alpha characters escaped

ModelSim SE Command Reference

* matches any sequence of characters