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Abstract
20
This paper studies the suitability of CMOS device technology
for mixed-signal applications. The currently proposed scaling
scenario's for CMOS technologies lead to strong degradation
of analog transistor performance. As a result, the combined
optimization of digital and analog devices for system-on-a- AAn=3 mVum 5 0
-20
404 , I
-120 40 0 60 120
Vt-Vtref (rnv)
Figore 3. Calculated response of SNM (p4do) to changing the NMOS
threshold voltage in the 0.1 pm SRAM cell. Increasing Vt above the
nominal voltage (Vtref) increases cell stability by shifting m,and allows
for less stringent requirementson matching parameter &v,. Figure 6. NMOS transistor with -3.5 nm pure gate oxide and TiN/AI metal
gate, fabricated in a 0.15 pn replacement gate process. The channel doping
was defined by well and pocket implants (no Vt-adjust), yielding a
nmt iot threshold voltage of -0.4 V.
pocket energy
nitrided oxides of 2 nm. The circles in Fig. 5 represent
RTOfor pory oxidation predictions [5] of AAvt for future “conventional” CMOS
fiwniwpoc
devices architectures, under the bestcase assumption of
statistical dopant fluctuations being the only mismatch
mod9 poly thickress
source. Since additional fluctuation effects usually further
optimized process degrade mismatch, it will become virtually impossible to
push AAV~ below -2 mVpn in future technology generations
0 2 4 6 a io
if they are to be based on conventional transistor
Matching coefficient b,,~(rnVum)
architectures.
This limit calls for alternative device architectures such
Figure 4. Evolution of NMOS and PMOS matching coefficients in as retrograde channels (ground plane devices) [5,11,12] or
response to various sequential process improvements (0.18 pm CMOS).
& y ~ 3mVpm is reached in the final development phase for both N- and
undoped thin-filmSO1 to minimize the impact of channel
PMOS,well belowthe SRAM requirements(Fig. 2). dopant fluctuations, or metal gates to avoid mismatch
associated with poly grain effects [4]. As an illustration,
During process development, dedicated experiments are NMOS transistors with an oxideRiN1Al gate stack (Fig. 6)
usually required to bring AAvtto an acceptable level. This is and lowly doped channels exhibit good matching behavior at
illustrated by the example for a 0.18 pm technology in Fig. 4 T,,,-3.5 nm (Fig. 7). This is demonstrated by the fairly low
(see also Ref. 10). By employing process refinements intrinsic AAvtof 3.6 mVpm, which is a very promising result
specifically aimed at reducing microscopic transistor property in view of the immature processing technology employed to
fluctuations, the mismatch performance can sipficantly be fabricate the metal gate transistors. In addition, the strong
improved Figure 5 Summarizes the scaling of AAvt with sensitivity of AAvtto counterdoping As implants confirms
technology. In line with older generations [2], AAvt drops that the matching is dominated by channel dopant variations
with decreasing oxide thickness, reaching -2.7 m V w for rather than gate electrode effects.
2 16-IEDM 0 1 10.2.2
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8.00
6.00
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0.00 Gate Length [urn]
0.00 0.50 1.oo 1.so 2.00 Figure 9. NMOS threshold voltage as a function of channel length in 0.15
pm technology. Short channel effects were controlled by conventional B
1/sq rt(W L) [I/U m] counterdoping implants (solid symbols) and lateral workfunction
Figure 7. Matching behavior of NMOS transistors with -3.5 nm pure gate engineering (open symbols; see Fig. 12).
oxide and TiN!A1 metal gate. The good matching for lowly doped channels
(Vt-0.4 V, % ~ = 3 . 6 mVpm) is significantly worsened when As .- I
Low-frequency (or l/f noise) is very important for analog and 3 1.E-
RF applications in advanced CMOS technologies. In Fig. 8, I
some trends of l/f noise with gate oxide thickness are shown.
The transition from pure to nitrided furnace oxides for 0.18
pn CMOS and beyond, results in a sigruficant increase in the
Ilf noise level due to nitrogen-induced oxide traps. The 0 60 100 1#) 200 260 300
PMOS noise level is af€ected by the specific nitridation gm(gdsat L=l m
process, suggesting that the exact nitrogen distribution and
concentration wittun the oxide is controlling the noise Fignre 10. Trade-off between digital (IJLfr) and analog (gdrdgd.) in 0.15 pm
NMOS devices for different variants in pocket dose and lateral
behavior. Alternative processing schemes to localize the w o r k h a i o n engineering. Strong short-channel control (i.e., high is
nitrogen at the gate/gatemide interface [I31 (e.g., plasma detrimental for the voltage gain (i.e., low &riar), whereas weak short-
nitridation) may prove beneficial for noise performance. channel control yields the opposite effect.
1 OE-07 Gain
N
A key analog transistor performance indicator that needs to
I,
iOE-08
be maximized, is the so-called voltage gain, defined as the
ratio of the transconductance and outputconductance (U&)
$
=
,>
[l]. It has been shown [14,15] that the pocket implants,
commonly used to control short channel effects (Fig. 9), are
( 1 OE43 detrimental for t h i s voltage gain. This is illustrated for a 0.15
d pm CMOS implementation in Fig. 10 by the trade-off
between digital (IO&*) and analog device performance
1 OE-10
(gdgdg). The degradation of voltage gain arises from the
0 10 20 30 40 50
dram-bias-induced modulation of the barrier created by the
Tox'(nR26 .
pocket on the drain side [14]. Device simulations (Fig. 11)
Figure 8. Input voltage I/f noise spectral ens* at 1Hz as normalized to show that the trade-off between digital and analog degrades
the transistor area. This has been measured at V,=V,=V, on PMOS and for each technology generation, due to the fact that both LE
NMOS devices in IMEC's 0.35 to 0.13 pm process generations (0.35&0.25
pm -pure oxides, 0.18M.13 - nitrided furnace oxides). Predicted noise and g& increase with device down scaling. l l u s puts ever
stronger limits on the maximum voltage gain that can be
~
levels for NMOS devices with pure oxides [ZO] are shown as a reference.
For the post-nitrided oxides used in 0.18 and 0.13 p (circles), a strong reached in digital technologies, exemp-ng the need for
increase in lif noise is observed compared to pure oxides, mainly for independent extasiodpocket optimization for analog
PMOS. devices.
As a possible alternative to pockets, lateral workfunction
engineering of the gate has been proposed for controlling
218-IEDM 01 10.2.4