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MAHENDRA ENGINEERING COLLEGE
(AUTONOMOUS)
Question Bank for Unit - II & III
Third Semester
ELECTRICAL AND ELECTRONICS ENGINEERING
EE13301 - DIGITAL LOGIC CIRCUITS
(Regulation - 2015)
PART – A (One Mark Questions)
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15. CO3 R In Moore model input changes does not affect the output.
PART – B ( Two Mark Questions)
16. CO2 R What is parity generator and parity checker?
17. CO2 R Define look ahead carry addition
18. CO2 R Write the limitation of using K-map and what is alternate of using K-map
19. CO2 U Write about Decoder and Encoder
20. CO2 R Write the applications of decoder and Multiplexers
21. CO2 R Write the truth table for E-OR gate.
22. CO2 R Write about parallel adder and subtractor.
23. CO2 U Distinguish between De-multiplexer and decoder
24. CO2 R What is Logic Gates?
25. CO2 R What are universal gates? Why it is called so?
26. CO3 R What are combinational circuits?
27. CO3 R What are the classifications of sequential circuits?
28. CO3 R What is a master-slave flip-flop?
29. CO3 U Give the comparison between combinational circuits and sequential circuits
30. CO3 R Define filpflop. What are the different types of flip-flop?
PART – C (12 Marks)
31. i)Explain the operations of adders and subtractors along with truth table
U and logic diagram
CO2 & 12
Analyze ii) Explain about MUX and DEMUX
Principal
(Approved)
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