ELECTRONIC CIRCUIT DESIGN AND ANALYSIS [EEEN 321]

LAB REPORTS COMPILATION

Presentation

The field-impact transistor was known as a "unipolar" transistor. The term alludes
to the way that current is transported via bearers of one extremity (lion's share),
while in the traditional bipolar transistor transporters of the two polarities (larger
part and minority) are included. The family tree of FET gadgets (Figure 1) might
be partitioned into two fundamental branches, Junction FETs (JFETs) and
Insulated Gate FETs (or MOSFETs, metal-oxide-semiconductor field-impact
transistors). Intersection FETs are intrinsically consumption mode gadgets, and are
accessible in both n-and p-channel designs. MOSFETs are accessible in both
upgrade and exhaustion modes, and furthermore exist as both n-and p-channel
gadgets. The two fundamental FET bunches rely upon various marvels for their
operation, and will be talked about independently. [1]

Fig 1

Given that it is over a couple of volts (fig 1), changing the deplete source voltage
does not modify the channel current in particular. By taking a gander at these
bends we can see that the JFET has two ranges of operation:

at low (couple of volts) deplete source voltage and it acts like a variable resistance
whose esteem is controlled by the connected door source voltage
At higher deplete source voltages it passes a present whose esteem relies upon the
connected entryway source voltage [2]

Destinations

Ro look at the qualities (the exchange and yield attributes) of a field impact
transistor

MATERIALS

1 FET transistor 2N3821

One PSU 20V variable DC metered yield

One PSU 0-5V DC metered yield

One voltmeter 0-50V DC

One voltmeter 0-20V DC

One plant ammeter 0-10mA DC

Hypothesis
The field impact transistor (FET) is a three – terminal semiconductor gadget
having qualities like that of a pentode vacuum tube. Not at all like the bipolar
transistors, the FET is a voltage worked gadget i.e. rather than being one-sided by
current; the FET is one-sided by a voltage.

There are two sorts of field – impact gadgets: The intersection FET (JFET) and the
metal – oxide semiconductor FET (MOSFET).

The FET has a to a great degree high info resistance and has no balanced voltage
when utilized as a switch (or chopp). The esteem s of the diode current (If) and
voltage (Vf) were recorded as the supply voltage is expanded from zero to +25V.

Methodology

For the exchange qualities, the circuit was associated as appeared in fig 20.0 and it
was guaranteed the power supply unit (psu) control was set to least. The VDS was
set to +15V and kept consistent, with VGS at 0V and ID was measured. VGS was
expanded (adversely) in steps and the estimations of ID were measured. This was
done until the point that ID achieves zero and this occurred at a VGS around -
3.5V. The acquired estimations of ID were recorded in Table 20.0. The diagram of
ID (vertically) against VGS was plotted and a suitable scale was picked. The
estimation of shared conductance (gm) at VGS was evaluated to - 1V.

Utilizing a similar circuit to discover the yield attributes, the power supply unit
(psu) control was set to least and VGS to 0V and kept steady. VDS was changed
from 0V to +20V in steps and ID was measured. This was rehashed with the VGS
estimations of - 1.0 V, - 2.0V and - 3.0V and the comparing estimations of ID were
recorded in table 20.1. The chart of ID (vertically) against VDS were plotted
picking a fitting scale.

CIRCUIT DIAGRAM

RESULTS AND ANALYSIS

At the point when VDS = 15V

VGS(V) ID(mA)

0 -1.405

- 0.25 -1.407

- 0.5 -1.412

- 0.75 -1.415

- 1.0 -1.419

- 1.25 -1.425
- 1.5 -1.43

- 1.75 -1.432

- 2.0 -1.438

- 2.25 -1.44

- 2.5 -1.446

- 2.75 -1.452

- 3.0 -1.461

- 3.25 -1.463

- 3.5 -1.469

At the point when VGS= 0V

VDS (V) ID (mA)

0 0
1 6.449

2 10.367

3 11.716

4 11.742

5 11.768

6 11.794

7 11.82

8 11.846

9 11.872

10 11.898

12 11.95
14 12.002

16 12.054

18 12.106

20 12.158

At the point when VGS= - 1V

VDS (V) ID (mA)

0 0

1 3.888

2 5.207

3 5.218

4 5.23

5 5.241
6 5.253

7 5.265

8 5.276

9 5.288

10 5.3

12 5.323

14 5.346

16 5.369

18 5.392

20 5.416

Gauge the estimation of shared conductance (gm) at VGS = - 1V

g_m= I_D/V_GS = ((0-3.888)mA )/(0-1)V=3.888mA/V

Evaluating the estimation of deplete incline resistance (rds) on the bend for Vds = -
1

r_ds= V_DS/I_D = 2V/5.201mA= 384 V⁄mA

r_ds= V_DS/I_D = 15V/5.357mA= 2.8 KV⁄mA

At the point when VGS= - 2V

VDS (V) ID (mA)

0 0

1 1.3

2 1.303

3 1.306

4 1.309
5 1.312

6 1.315

7 1.318

8 1.321

9 1.324

10 1.326

12 1.332

14 1.338

16 1.334

18 1.35

20 1.356

Whenever VGS=3V
VDS (V) ID (ρA)

0 0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0
10 0

12 0

14 0

16 0

18 0

20 0

Discourse

CONCLUSION

REFERENCES

Investigation 21

FIELD-EFFECT TRANSISTOR (FET) AMPLIFIER

Targets
To research the activity of a typical source field impact transistor intensifier.

MATERIALS

1 FET transistor 2N3819 or proportional

One DC supply (+15V)

Two capacitors (0.1µF)

One capacitor (100µF, 25V)

One resistor each (4.7kω, 33kω, 1MΩ)

One flag generator

One oscilloscope

One DC voltmeter

Hypothesis
The field impact transistor (FET) is a three – terminal semiconductor gadget
having qualities like that of a pentode vacuum tube. Dissimilar to the bipolar o that
of a pentode vacuum tube. Not at all like the bipolar transistors, the FET is a
voltage worked gadget i.e. rather than being one-sided by current; the FET is one-
sided by a voltage.

There are two sorts of field – impact gadgets: The intersection FET (JFET) and the
metal – oxide semiconductor FET (MOSFET).

The FET has a to a great degree high info resistance and has no counterbalanced
voltage when utilized as a switch (or chopp).

Similarly as with BJTs, JFET has three methods of operation, to be specific: basic
source, regular door and normal deplete, which are methods of intensification. In
the regular source speaker, the info flag voltage is provided to the door source
circuit through a coupling capacitor. The yield flag voltage is created over the
deplete stack resistor (RL) as the consequence of the current through it and coupled
through another coupling capacitor to the outside world. By and by, the different
DC supply for the door source voltage is given via programmed biasing. There is
likewise a bypassing capacitor which goes about as a sidestep for the AC flag,
typically associated source (for basic source arrangement) to the ground.

System

Circuit in fig.21.0 above was set up and the power supply unit or just psu was set
to least. DC operation condition was checked by measuring the voltage as for the
0V line: that is; 1) over the RS (VRS) which is roughly around 1V and in
conclusion 2) at the deplete (VD) which was around 8V. The deplete source
voltage (VDS) was figured as VDS = VD – VRS which was around one-portion of
the provided voltage. Alignment of the flag generator began, recurrence was set to
1 kHz and the yield level to 100mV top to-crest. The yield was measured and
subsequently the voltage pick up was figured along. Finally utilizing the
estimations of the past Experiment 20 that is, the gm and rds, a hypothetical
estimation of the voltage pick up was figured.

RESULTS

DC OPERATING CONDITION

Crosswise over RS (VRS) 0.644 V

At Drain (VD) 8.26 V

Figuring OF THE DRAIN-SOURCE VOLTAGE

VDS = VD – VRS

VDS = 8.26 V – 0.644V = 7.616 V

Yield VOLTAGE = 7.8 V

Voltage pick up = Av = (Id/Vgs) x (R2)

Av = gm x RD

Where gm = (δId/δVgs)

Av = ((36.2µω)/(568.768mV+(36.2µΩ)(4.7kΩ))) x (33kω)

Av = 1.62

Utilizing estimations of gm and rds from the past trial 20, the hypothetical
estimation of voltage pick up is;

Av = gm x rds

Av = (3.888mA) x (384 V/mA)

AV = 1.49

Talk

The figured deplete source voltage VDS is 7.616V, this was because of the
distinction amongst VD and VRS. The deliberate yield voltage is 7.8V, after the
flag generator was set to 1 kHz and yield level to 100mV (p-p). The ascertained
voltage pick up is 1.62. Utilizing the hypothetical esteems from analyze 20, the
voltage pick up is 1.49.
CONCLUSION

The activity of a typical source field impact transistor enhancer was examined

Trial 22

BIPOLAR JUNCTION TRANSISTORS (BJT) CHARACTERISTICS

Goals

To get the put, yield and exchange attributes of a typical producer transistor.

Materials

NPN Transistor(BC109)

DC supply (variable from 0V to +12V)

DC supply (variable from 0V to +1V)

Microammeter
DC ammeter

DC voltmeter(digital)

Hypothesis

The BJT is a three-terminal gadget and it comes in two distinct sorts. The npn BJT
and the pnp BJT. The BJT images and their relating square outlines are appeared
on Figure 1. The BJT is manufactured with three independently doped locales. The
npn gadget has one p locale between two n districts and the pnp gadget has one n
area between two p areas.

The BJT has two intersections (limits between the n and the p areas).

These intersections are like the intersections we found in the diodes and in this way
they might be forward one-sided or turn around one-sided. For the most part, BJT
has three terminals, and the three terminals of the BJT are known as the Base (B),
the Collector (C) and the Emitter (E).Three diverse sorts of voltages are associated
with the depiction of transistors and transistor circuits. They are:

Transistor supply voltages: VCC, VBB.

Transistor terminal voltages: VC, VB, VE.

Voltages crosswise over transistor intersections: VBE, VCE, VCB.

The three terminals of the transistors and the two intersections, give us various
administrations. Keeping in mind the end goal to recognize these administrations
we observe I-V attributes of the gadget. The most vital normal for the BJT is the
plot of the authority current, IC, versus the gatherer producer voltage, VCE, for
different estimations of the base current,