Microcoputer Structure and Operation

Microcomputer Structure and
Operation – Chapter 5
• A Microprocessor (P)
contains the controller,
ALU and internal
registers
• A Microcomputer (C)
contains a
microprocessor, memory
(RAM, ROM, etc), input
and output units
• A P and C can deliver
an inexpensive (cost and
hours) solution to a
design problem
• Custom circuits are
generally preferred in
areas where very high
speed is necessary, but
they are very costly
© 2003-2013 Roberto Muscedere Images and Text Portions © 2003 Prentice Hall 1
Typical Applications
• A C receives input information or
data and executes a sequence of
instructions which processes this
information and then provides an
output
• A C may control the engine of an
automobile and provides feedback
via the display panel
• Many parameters such as
temperature, oxygen, fuel, etc
provide the information to the
algorithms which control the
performance of the engine
• A C may also control an electric
oven where information is entered
via a keyboard to indicate cooking
temperature and time
• It responds by controlling the
burner through an output
• A temperature sensor provides
feedback on the current
temperature of the oven so that it
can be better controlled
68HC11 in Expanded Mode
Microcomputer Architecture
• The 68HC11 is set in expanded mode by “pulling”
MODA and MODB high
• This mode allows “external” memory and I/O
devices to be connected directly to the MPU
busses
• Not all the information is shown; still a simple diagram
• Three busses carry all the information necessary
• Address (A15-A0)
• Data (D7-D0)
• Control (R/W, etc)
• The MPU is constantly transferring information to
and from memory
Ports
• A port is a set of pins
on the chip through
which digital
information is
transmitted to and
from the MPU
• 68HC11 has 5 ports:
A, B, C, D, and E
• We are only interested
in ports B and C for
expanded mode
Ports B and C
• In expanded mode, port B is an
output and C is bi-directional
• Port B is used to provide the upper
order address information for
memory access
• Port C is a multifunction port
depending on the state of E-clock
and address strobe (AS)
1. Provides the lower order address
information for memory access
2. Provides the data for writing to
memory and reads the data from
memory while reading
• Port C is time-multiplexed since it
delivers different signals at
different times
• A latch is used to capture the low
order address to be used at a later
time
• Additional decoders can be used
to allow for different memory types
Control Bus
• The control bus synchronizes
the operation of the MPU with
other elements
• R/W is set to indicate the
direction of data on the data
bus
• AS is high when the information
on Port C is the low order
address of a memory access
• /RESET is used to reset the
MPU; it can also be initiated by
the 68HC11
• /XIRQ and /IRQ are “interrupt”
signals that tell the MPU that
something important has
happened and it must be
investigated
• E is the 68HC11’s E-clock
(more on this later)
Clock Signals
• 68HC11 uses a single
clock signal known as the
E-clock both internally and
externally
• The frequency is
determined by the
external clock
components connected to
EXTAL and XTAL
• E-clock is always ¼ this
frequency
• Maximum external clock is
8MHz; maximum internal
is 2MHz
Clock Signals
• 68HC11 also uses an
internal clock PH2
• The PC is incremented
on the rising edge of
PH2
• Data is latched into the
accumulator on the
falling edge of E-clock
• When E-clock is low, AS
goes high and address
information is placed on
ports B and C
• PH2 has the same
frequency as E-clock but
it leads by 90 degrees;
they do not overlap
• Falling edge of E-clock
signifies the beginning
of a clock cycle
I/O Interfacing and Ports
• There can be several I/O
devices connected to the
bus
• Cannot be directly
connected to the bus;
must use interfacing
circuitry
• Interfacing may be
required when voltage
levels and timing are
different
• Most Cs have many
ports which can be used
to interface with other
devices
Read and Write Timing
• The MPU is constantly performing READ and
WRITE operations as it executes a program
• READ:
• Fetches the op-code from memory
• Fetches the operand from memory
• Fetches the data from memory (LDAA, ADDA, SUBA)
• WRITE:
• Transfers data from internal register to memory (STAA)
• Transfers data from internal register to output device
• Read operations are more common since they are
necessary to read the program instructions
Read Operations
• Everything is in
reference to
PH2, E-clock
and AS
1. Rising edge of
AS
• R/W = 1
• Address is set
2. Rising edge of
PH2
• PC is
incremented
Read Operations
3. Falling edge of
AS
• Low order address
is fully latched
• Remove low order
address from port
C
4. Rising edge of E-
clock
• Enable selected
devices (RAM,
ROM, I/O)
• Port C becomes
an input
Read Operations
5. Falling edge of E-
clock
• Data on port C are
latched to an
internal register
• Memory must
deliver a value
within this time
• When E-clock
goes low, external
memory is
disabled and bus
goes to high-Z
Write Operations
1. Rising edge of
AS
• R/W = 0
• Address is set
2. Rising edge of
PH2
• Nothing
happens
Write Operations
3. Falling edge of
AS
• Low order address
is fully latched
• Remove low order
address from port
C
4. Rising edge of E-
clock
• Enable selected
devices (RAM,
ROM, I/O)
• Port C becomes
an output
• Data is placed on
port C
Write Operations
5. Falling edge of
E-clock
• Data on port C
is latched into
selected
memory device
• Memory must
commit this
value within
this time
Sample Program for Bus Activity
Memory Contents Mnemonic Description
• Execute 2 Address
instructions $C300 $BB ADDA ADD contents
$C301 $D7 of $D75C to
• ADDA and STAA $C302 $5C Accumulator A
• Requires 8 cycles $C303 $B7 STAA STORE

$C304 $D2 contents of
$C305 $50 Accumulator A
to $D250
$C306 ?? ???? Next op-code
Bus Activity During Program
Execution
Execution
• Read operation:
a. Rising edge of AS
• MPU places PC/DAR on address bus
• R/W=1
b. Rising edge of PH2
• Increment PC
c. Falling edge of AS
• Low order address is latched
d. Rising edge of E-clock
• Memory device is enabled
e. Falling edge of E-clock
• Latch data word from memory device
Execution
• Write operation:
a. Rising edge of AS
• MPU places DAR on address bus
• R/W=0
b. Rising edge of PH2
• Nothing takes place
c. Falling edge of AS
• Low order address is latched
d. Rising edge of E-clock
• Memory device is enabled
• Output is placed on data bus
e. Falling edge of E-clock
• Latch data word to memory device
MPU Address Space Allocation
• When a Read or Write is
performed the MPU places an
address on the bus
• The 68HC11 has 65536 (64K)
of available addresses
• This can be allocated into
different types of memory
(RAM, I/O, ROM)
• Figure on right is an example
of what you might find in one
of the 68HC11s
• This could be the memory
available in expanded mode
On-Chip Memory and I/O
• Various
68HC11s
• All contain the
same number of
internal
registers, etc
• Different
memory
configurations
• RAM and ROM
are generally
fixed while I/O
can be moved
(more on this
later)
On-Chip Memory and I/O
• Some have a
different number
of Timers, Serial
interfaces, A-to-
D converters as
well as Pulse
Width
Modulators
• Some also
operate at
different voltages
and speeds
Memory Pages
• The 64K of memory can be
divided into 256 blocks of 256
addresses
• Each is called a page
• The upper 8-bits of an address
can be referred to as the page
number
• The lower 8-bits of an address
can be referred to as the word
number
• Upon startup, we can specify
the location of the I/O in the
68HC11 by writing the desired
page number to a fixed
memory register
Memory Modules and Address
Decoding
• The amount of
memory in a C
depends on the
intended application
• Once the memory
arrangement is
decided, an address
decoding system
must be put in place
to enable the
particular memories
at the right time
• Generally higher-
order memory
addresses are used
to dictate which
memory is in use
Microcomputer Decoding Example
• Create an external circuit
to connect to a 68HC11 in
expanded mode
• RAM is usually placed
starting at address 0 to
take advantage of “zero
page” operations
• ROM is placed at the
highest point since the
startup information for the
68HC11 is located
between $FFFC and
$FFFF
• I/O is placed at $8000 to
simplify decoding circuitry
RAM Decoding Logic
• 4K x 8 RAM memory
required
• Use 1K x 8 components
• Need to use a decoder
(74HC138) to determine
which $0400 part of
$0000-$0FFF is being
addressed
• Use of an inverting input
NAND gate for higher
order address lines
provides FULL address
decoding
RAM Decoding Logic
• Can use partial address
decoding
• Address lines A14-A12
are not considered for
decoding
• $0000-$0FFF is
mirrored to $1000,
$2000, $3000, $4000,
etc…
• This is acceptable as
long as the programmer
is aware that these
memory addresses are
shared
ROM Decoding Logic
• 16K x 8 ROM memory
required
• Use 4K x 8 components
• Need to use a decoder
(74HC138) to determine
if $C000-$FFFF is
addressed
• Use of an inverter on
A15 as well as A14-A12
to determine which 4K
page is being used
• /8000 is used later for
I/O
I/O Decoding Logic
• A large amount of I/O is
usually not necessary
• In this example, we will only
have 8 input and 8 output bits
• A2 decides on which to
enable
• Writing to $8000 puts data on
the output I/O
• Reading from $8004 reads
data from the input I/O
• $8000 is mirrored to $8001,
$8002, $8003, $8008, $8009,
etc…
• $8004 is mirrored to $8005,
$8006, $8007, $800C,
$800D, etc…

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• Requires 8 cycles $C303 $B7 STAA STORE

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