Operating System Updates For CPU 315-2DP

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January 2018
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Entry type: Download, Entry ID: 16750732, Entry date: 11/30/2009
Operating System Updates for CPU 315-2DP
DESCRIPTION:
When updating the operating system, you should always update to the latest version available for the product with the relevant order no. The previous versions of
the operating system are just meant to be a backup to enable you to downgrade to the original version. Until now this is not known to have been necessary in any
case.
The latest version of a CPU operating system is always valid for all the versions of that order no..
The update can be performed either with a Micro Memory Card or online:
1. Micro Memory Card:
Requirements for creating an operating system update card:
Micro Memory Card with at least 4 MB storage capacity
Order no. 6ES7 953-8LM20-0AA0
STEP 7 V5.1 SP2 or higher
PC with external PROM programmer (6ES7 792-0AA00-0XA0) or
PG720 / 740 with adapter (6ES7 798-0BA00-0XA0) or
FieldPG / PowerPG for programming the Memory Card
Creating an operating system update card with STEP7:
1. Download the desired CPU file.
2. Unpack the file by double-clicking the file name
3. Delete the Micro Memory Card by executing: "File/S7 Memory Card/Delete" in Simatic Manager.
4. Program the operating system by selecting "Update target system/operating system" in SIMATIC Manager, then select the target directory and "Open" the
CPU_HD.UPD file to start the programming process.
5. Programming of the operating system update card is completed when the message "The firmware update for the module with the order number 6ES7 315-
2AG10-0AB0 was transferred successfully to the S7 memory card" appears on the screen.
To update the operating system:
1. Switch OFF the power supply (PS) of the rack in which the CPU is located
2. Isolate the PLC from the communication network
3. Insert the prepared operating system update card in the CPU
4. Switch ON the power supply (PS) for the rack in which the CPU is located
5. The operating system is transferred from the Micro Memory Card to the internal CPU flash EPROM. During this time all the CPU's LEDs will be on (FRCE, RUN,
STOP, SF, BF).
6. The operating system update is completed after about 2 minutes and is indicated by slow flashing of the STOP LED on the CPU => prompt for overall reset by
the system
7. Switch the power OFF at the power supply and insert the Micro Memory Card required for operation.
8. Switch ON the power supply. The CPU automatically does an overall reset and is then immediately ready for operation.
9. Before connecting the PLC to the communication network again the clock must be synchronized.
2. Online:
Requirements:
Online updating of the firmware is possible with STEP 7 V5.3 and higher.
The module in the station whose firmware is to be updated must have firmware version V2.6.1 or higher and be accessible online.
The module status of the CPU can be checked with STEP7 in the online mode. Version A0.21.0 or higher must be displayed to be able to perform the
firmware update.
Select: SIMATIC Manager -> <Name of station> -> Strg+D

Fig 1: Module status
The module must be listed with firmware version V2.6 in the Hardware Configuration in SIMATIC-Manager.
IA MMC (Micro Memory Card) must be inserted in the module as buffer memory.
The unpacked files with the latest firmware version must be available in the file system of your PG or PC:
BG_ABL.UPD
CPU_HD.UPD
KOMP_1.UPD
Any one folder may only contain the files for one firmware version.
To update the firmware:
1. Start STEP 7 and switch to HW-Config.
2. Open the station with the CPU to be updated.
3. Earmark the CPU.
4. Select the command "Target system > Update firmware". The command can only be activated, if the marked CPU supports the function "Firmware update".
5. In the opened dialog "Update firmware" now use the "Search" button to find the path to the firmware update files (*.UPD).
6. When you have selected a file, information will come up in the lower part of the "Firmware update" dialog, for which module and as from which firmware version
the file is valid.
7. Click the "Execute" button. STEP 7 will check whether the selected file can be interpreted by the module and then load the file to the CPU if the answer is
positive. If the operating mode of the CPU must be changed for this purpose, you will be prompted via dialogs. The CPU will then execute the firmware update by
itself.
8. Check with STEP 7 (read diagnostic buffer of the CPU), whether the CPU successfully starts up with the new firmware.
Overview of order no.’s and latest versions of the CPU 315-2DP:

Order No. FW Upgrade with ...
version
6ES7315-2AG10-0AB0
V2.6.11 Recommended for upgrading:
Update V2.6.11 description
3152AG10_V2611.EXE ( 902 KB )
V2.6.9 For backup only:
3152AG10_V269.EXE ( 902 KB )
3152AG10_V266.EXE ( 900 KB )
3152AG10_V264.EXE ( 899 KB )
3152AG10_V2012.EXE ( 817 KB )
3152AG10_V2011.EXE ( 812 KB )
3152AG10_V2010.EXE ( 812 KB )
3152AG10_V208.EXE ( 808 KB )
. V2.0.5 For backup only:
3152AG10_V205.EXE ( 779 KB )
. V2.0.0 For backup only:
3152AG10_V200.EXE ( 767 KB )
Update V2.6.11 (6ES7 315-2AG10-0AB0)
The above CPU version does not contain any new functions.
Note on STEP7:
To operate this CPU you require STEP7 V5.4 + SP3 or STEP7 V5.2 + SP1 with HSP 0125 or higher.
Firmware update V2.6.11 provides the following corrections:
After power ON there will be no more sporadical loss of actual values after overall reset with Event ID 16#6522 or 16#4580 ( backup buffer inconsistent ).
No more sporadical Defect Z1=97EA when monitoring blocks or variables with simultaneously connected HMI devices.
If a DB is available, the SFC 24 "TEST_DB" will now always supply the correct length of the DB, irrespective of the latter's memory attribute or SFC83 called
in parallel.
When putting the clock forward, the weekday ( variable "OB10_DATE_TIME" ) will now be adjusted immediately in the local data of the OB10.
Update V2.6.9 (6ES7 315-2AG10-0AB0)
Note on STEP7:
To operate this CPU you require STEP7 V5.2 + SP1 + HSP 0125 or STEP7 V5.4 + SP3 or higher.
Loss of actual value during operation with event code 16#6523 and Z2=8020 / Z3=1410 now prevented.
Forcing will no longer result in a loss of timed interrupts.
Fast scrolling when monitoring blocks or variables tables no longer causes Defect Z1=6A6F.
Incorrect length specifications of ANY Pointers for SFCs 20 and 21 will now result in BLF (Length-of-Area Error: 8x22 or 8x23); this prevents follow-up errors
such as cycle time exceeded and watchdog.
In the case of communication problems with external HMI systems e.g. ProSCADA, or when using a CP343-1EX11, Defect Z1=98C6 will no longer occur.
Update V2.6.6 (6ES7 315-2AG10-0AB0)
Note on STEP7:
To operate this CPU you require STEP7 V5.2 + SP1 with HSP 0125 or higher.
If the connection is aborted during cyclic HMI reading, the CPU will no longer enter defect mode Z1=7173.
Routing problems with the CP5613 A2 have been corrected.
Soft keys assigned to bit variables in an OP3 will now set the assigned bit in the PLC if the key is pressed.
Forcing of inputs (PAI) is now always effective also in alarm OBs.
Communication with HMI devices has been speeded up.
If the connection is aborted during monitoring of blocks or variables, defect Z1=7393 will no longer occur.
If the error message "The memory space on the module is insufficient. Should the loading memory be compressed?" comes up when uploading software
blocks, the acknowledgement with "Yes" no longer remains ineffective.
If blocks FB48 and FB49 ("Signal system errors") are loaded, DEFECT Z1=FFFF will no longer occur after program loading and voltage off/on.
Update V2.6.4 (6ES7 315-2AG10-0AB0)
Note on STEP7:
To operate this CPU you require STEP7 V5.2 + SP1 with HSP 0125 or higher.
The callup parameters of SFBs 52, 53, 75, 81 and SFCs 11, 51, 55-59 will only be checked if the REQ bit has been set. If the REQ bit has not been set,
RET_VAL will not signal an error anymore.
An address offset of > 4096 bytes on the ANY Pointer of parameters SRCBLK or DSTBLK of the SFCs 82/83/84 will no longer lead to the checkback signal
8x22 on RET_VAL.
Loading the SDBs from the STEP7 block container will no longer lead to STOP because of a configuration inconsistency.
The CPU correctly enters STOP mode because of a missing slave, if the configuration bit "Start-up if desired configuration equals actual configuration" is not
set. If the bit "Startup if desired configuration equals actual configuration" is subsequently set and the configuration post-loaded to the CPU, the latter will now
start-up.
In the case of a block comparison in the online view of the block list, all blocks will now be shown and not only the first 50 blocks of each type.
SFBs 52, 53 and 81 will no longer deliver Retval 8x3a if data type BLOCK_DB has been entered in the Parameter Record.
Connection establishment to operator panels has been improved.
Update V2.6.3 (6ES7 315-2AG10-0AB0)
Note on STEP7:
To operate this CPU you require STEP7 V5.4 + SP3 or STEP7 V5.2 + SP1 with HSP 0125 or higherer.
Firmware update V2.6.3 results in the following corrections:
RLO corruption with “O“ operation (OR before AND function) in programmer operation with block status has been corrected.
Due to a problem with firmware V2.6.1 and V2.6.2, a corruption of the RLO could occur during operation with a programming device and online
monitoring of block status, with the following program sequence:
A a b.c
A d e.f
.
.
A x y.z
O // the RLO thus formed could be corrupted (only during block status monitoring of this sequence)
A y z.x
.
.
A s t.u
If an addressed bit is set at input SD of SFCs 17, 18, 107 and 108, the complete byte will not be set to zero.
The data types Word and DWord are now also permitted with the RECORD parameter of SFBs 52 and 53.
Update V2.6.1 (6ES7 315-2AG10-0AB0)
The above CPU version includes the following new functions:
Identification and maintenance data of the CPU (e.g. plant and location code)
Reset of the CPU to its delivery status
Online firmware update via network
Measuring initiator for Diagnostic Repeater (SFC 103 "DP_TOPOL") *
Extension of the block-related messages (SFC 105-108) *
Change of protection stage with SFC 109 "PROTECT“ *
SFC 64 "TIME_TCK" with 1 ms separation *
New software blocks SFC 70 "GEO_LOG", SFC 71 "LOG_GEO" and SFB 81 "RD_DPAR" *
Clock synchronization via PROFIBUS DP
Changed response of the CPU as clock master on MPI and DP interfaces - see Product Information / entry ID  25323411
* You will find detailled information on the additions to the various SFCs in the Operations List and the System Software Reference Manual for S7-300/400, System
and Standard Functions.
Note on STEP7:
To operate this CPU you require STEP7 V5.4 SP3 or STEP7 V5.2 + SP1 with HSP 0125 or higher.
The following changes will become effective with firmware update V2.6.1:
If cyclic HMI reading is aborted, defect Z1:72C1 will now be prevented.
Copy functions (in particular with SCL programming) with parameters of the typ ANY STRING will now copy the exact no. of data contained in the length
specification.
Copy functions with parameters of the type ANY will now also permit area code #85 and the RETVAL of the SFC83 will no longer display #8525 "Area error
with writing".
When monitoring with callup path it is now possible to specify up to 7 blocks for the callup environment.
Loading of projects with CP or FM modules in which the MPI address of the CPU has been changed, no longer causes the error message "Station cannot
be reached".
Update V2.0.12 (6ES7 315-2AG10-0AB0)
Note on STEP7:
To operate this CPU you require STEP7 V5.1 + SP4 or higher.
Firmware update V2.0.12 results in the following corrections:
Defect Z1:E802 in the case of OB request error and simultaneous high alarm load
An OB request error (caused by long alarm processing time) will no longer lead to Defect when the load by other alarms is high at the same time.
Defect Z1:72F1, or non-operable MPI, if several variables tables are monitored simultaneously
If more than four variables tables are activated at the same time, the message "(8304): No further simultaneous upload process possible. There is a
resource bottleneck" will be generated, and not a Defect.
Communication problems with the CP340: CP gets stuck during sending
Communication with the CP has been improved.
Module remains up with a fault in HW Config
After a corrected encoder short circuit on a DPV1 slave, the “faulty“ symbol in the configuration will now be removed.
Update V2.0.11 (6ES7 315-2AG10-0AB0)
The above CPU version does not contain any functional changes.
Note on STEP7:
To operate this CPU, you require STEP7 V5.1+SP4 or higher.

Firmware update V2.0.11 will result in the following changes:
Problems when calling the SFC58/59 with BUSY
In the case of RET_VAL=7000h the BUSY bit will now be deleted correctly.
Alarm_SQ messages will not be displayed in the case of a Runtime Start
After a cold restart of WinCC-Runtime all the Alarm_SQ messages previously generated by a controller will be displayed in the WinCC AlarmControl.
OB Request error after a clock interrupt
A clock interrupt will now be earmarked for the next interrupt point in the future, if that interrupt time coincides with the current time.
Defect Z1:F102 after power ON
The response in the case of power ON has been stabilized.
STOP event 16#6522 after power ON
The response in the case of power ON has been stabilized.
Update V2.0.10 (6ES7 315-2AG10-0AB0)
Note on STEP7:

With the firmware update V2.0.10, the changes described below become effective:
Defect Z1:64D2 following a connection termination
If a connection is terminated while the communication function "Status Block" or "Status/Control Tag" is running, the connection will now be cancelled
correctly and the defect no longer occurs.
Defects Z1:7015 and Z1:7010 following a connection termination
If a connection is terminated while the communication function "Block Details" is running (if the CPU contains more than 51 blocks of one type (DB, FB,
FC)), the connection will now be cancelled correctly and the defect no longer occurs.
Messages of the ALARM_SQ for down/up of WinCC can not be acknowledged
When an ALARM_SQ message comes up while the HMI is not available, and the HMI is later activated again, the acknowledged message will now be
deleted from the update memory.
No difference in the OB100_STRT_INFO between RUN switch and power-on
The start info of the OB 100 will now indicate the correct type of startup.
Defect Z1:7350, if an OP cyclically accesses a DB which is not present or too small
OP area pointers pointing to a DB that is not present or too small no longer result in a CPU defect.
After writing of DS1 to BUS1*-ASIC modules, the PZF will be set
If a DS1 is written to certain non-parameterizable modules with the SFC55 (modules with BUS13 or BUS1*-ASIC), the PZF will no longer be set for these
modules and the modules remain addressable following the SFC call.
No BF LED after a master failure / outputs will possibly not be deactivated
When used as passive I slave behind a repeater without a further active station in this bus segment, and occurrence of a fault or removal of a cable, a
master failure will now be signalled and the I slave will deactivate its outputs.
Diagnostics buffer entry "Faulty Module" for DPV1 slaves does not disappear
Two subsequent channel diagnostics from different slots of a DPV1 slave - that are both correctly entered in the diagnostics buffer - are no longer shown as
faulty following the subsequent correction of both channel diagnostics.

Update V2.0.8 (6ES7 315-2AG10-0AB0)
The above CPU version does not contain any significant new functions.
Note on STEP7:
Error 6523 "Master reset request upon accessing the MMC" following RAM-to-ROM
The reloading of data blocks following the function RAM-to-ROM no longer results in the master reset request with the event entry 6523.
"Identical source and target blocks" cause a coordination error (80C0) with the SFCs 83 and 84
When calling the SFCs 83 and 84, the selected source and target blocks can now be identical.
Sporadic RETVAL 80C4 with SFC59
Resource administration of the SFC59 "RD_REC" has been improved.
Defect FFFF in the case of repeated registration for process error diagnostics
Even repeated registration for process error diagnostics will no longer cause defect FFFF.
Defect following MCRA command when accessing flag > 255 or I/O > 127
MCR-dependent allocations/transfer operations to flag > 255 or I/O > 127 no longer result in a CPU defect message.
Incorrect status display before a loop
The display of status data before loops now functions correctly.
Loading of the application program --> CPU goes into master reset mode
Loading an application program no longer results in the error message "(8404) S7 Protocol: The function can not be executed" and thus the master reset
request by the CPU.
CPU defect 3324 upon STOP/RUN if SFB52/53 is running
STOP/RUN of the CPU if the SFB52/53 is running no longer results in the defect 3324.
DEFECT 9862 after repeatedly plugging/unplugging the Profibus connector
If the Profibus connector is pulled repeatedly (e.g. in the case of a loose connection), the CPU no longer goes into DEFECT mode.
DEFECT e800 when loading SDBs
When reloading an edited configuration, the CPU no longer goes into DEFECT mode.
If the IM151-1 HF is configured as DPV1 slave, the periphery access error remains set for the diagnostics addresses
If an IM151-1 HF (6ES7 151-1BA00-0AB0) is configured as DPV1 slave, the power module and the packed modules receive a diagnostics address. For
these diagnostics addresses, the periphery access error will no longer be set.
Defect F102 after activating an I slave that starts up very quickly
In the case of configuration-dependent quickly starting I slaves, the CPU will no longer go into defect mode following their activation.
RET_VAL 8010 with FC10 and FC11, if CPU is DP slave
The FCs 10 and 11 from the PROFInet system library now return the correct RET_VAL=0 after the Master has been switched to RUN.
Update V2.0.5 (6ES7 315-2AG10-0AB0)
The above CPU version does not contain any significant new functions.
Note on STEP7:
Sporadic defects F402 AND F204 after COMPRESSION
Defects no longer occur after compression.
Defect 8113 following power-on with alarm times > 12.31.2064
Alarm times > 12.31.2064 no longer cause this defect.
When periodically processing the system function SFC 39 "DIS_IRT", alarm events that have been locked are briefly unlocked again
The periodic locking of alarm events is now possible without problems.
PA-enabling transfers the last process image completely to the periphery
If the function PA-enabling is used now, the outputs of the centralized periphery will no longer take up their last value, i.e. they will now be deleted or take up a
substitute value.
When deactivating PA-enabling, the modules configured as "Keep last Value" are reset
When deactivating the function PA-enabling, the modules that are configured as "Keep last Value" and have not been controlled previously will resume their
last value.
Sporadic defect 98C1 when using an Applicom driver card
Applicom driver cards can now be used without problems.
Cycle time fluctuations when using the LOOP command
When using the LOOP command, cycle time fluctuations no longer occur.
With a status block, the flag > 511 is no longer displayed correctly (CPU315 only)
The status of the flag Bits > 511 is now displayed correctly.
If a standard slave fails, the uninvolved input module will return a periphery access error
When employing standard slaves (CPU is the DP Master), whose available user data slots start with slot 1 and slot 2 is configured for the output, a failure of
these slaves no longer causes the uninvolved input module (or address) to report a periphery access error, if it possesses the same input address as the
output slot in slot 2.
Defect 7089 during the online selection from HW-Config (or HW Diagnostics)
When employing slaves with a large number of slots (configured slots)
Even when employing slaves with a large number of slots (configured slots from 120 to 244), selections can now be made without problems using the HW-
Config online mode or the HW Diagnostics.
Sporadic defect when overloading the CPU315-2DP Modular from HW-Config
The overloading via the MPI interface with low Baud rates (9.6 kbit, 19.2kbit) is now possible without problems in the case of a DP master system with
Profibus settings.
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