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POWER SUPPLY
• No min or max Voltage (VDD, VSS)
• ISUPPLY = 0 Amps
• Power Supply Rejection Ratio (PSRR) = ∞
INPUT
• Input Current (IB) = 0
VDD
OUTPUT
• Input Impedance (ZIN) = ∞ VIN-
• VOUT = VSS to VDD
• Input Voltage Range (VIN) → no limits VOUT • IOUT =
OP AMP
• Zero Input Voltage and Current Noise
VIN+
• Slew Rate (SR) =∞
• Zero DC offset error (VOS)
• Common-Mode Rejection = ∞ • ZOUT = 0Ω
VSS
SIGNAL TRANSFER
• Open Loop Gain (AOL)= ∞
• Bandwidth = 0 → ∞
• Zero Harmonic Distortion (THD)
FIGURE 1: The ideal op amp description can be separated into four basic categories: input, power supply, output, and
signal transfer.
IB- VDD
VIN- ← ↓ IDD VIN-
VOUT
ZOL VOUT +
VERRAOL VIN+
+ IB+
VOS
VIN+ ←
VERR OFFSET VOLTAGE
VSS PRODUCTION DISTRIBUTION
-2000
-1600
-1200
-800
-400
0
400
800
1200
1600
2000
Input Offset Voltage (VOS)
Specification Discussion - The input offset voltage Offset Voltage (uV)
specification of an amplifier defines the maximum volt-
age difference that will occur between the two input ter- OFFSET VOLTAGE DRIFT MAGNITUDE
minals in a closed loop circuit while the amplifier is PRODUCTION DISTRIBUTION
operating in its linear region. The input offset voltage is 25
always specified at room temperature in terms of µV or Typical production
Percent of Amplifiers (%)
0.75
1.25
1.75
2.25
2.75
3.25
3.75
the temperature, power supply voltage, common-mode
voltage or output voltage changes, as shown in Offset Voltage Drift (uV / deg C)
Figure 3 as part of VERR. The affects of these changes
are discussed later. FIGURE 4: The input offset voltage of an amplifier
varies from part to part but always falls within the
stated specification voltage range.
Application Challenge - The offset voltage error of a
particular amplifier may or may not be a problem,
dependent on the application circuit. For instance, if a
device is configured as a buffer (also known as a volt-
age follower), amplifiers with larger offset voltage
errors, in the range of 2mV to 10mV, are usually not sig-
nificantly different in performance than high precision
amplifiers with extremely low offset voltage specifica-
tions, in the range of 100µV to 500µV. On the other
hand, an amplifier with a high offset voltage that is in a
high closed loop gain configuration can dramatically
compromise the dynamic range of the circuit.
For example, the circuit in the Figure 5 is designed so
that the analog input voltage (VIN) is gained by:
VOUT = (1 + RF / RIN) (VIN + VOS)
↓
IB IB
1
← →
VIN+ Q1 Q2 VIN-
3
VIN+ VIN-
Q1 Q2
→ ←
IB IB
↓ -VSUPPLY
-VSUPPLY
(a) PMOS differential input stage (b) NMOS differential input stage
+VSUPPLY
↓
VBIAS
VIN+ VIN-
Q3 Q1 Q2 Q4
→ →
← ←
IB IB
↓
(c) Composite PMOS and NMOS differential input stage
-VSUPPLY
FIGURE 7: The input voltage range of an op amp is dependant on the topology of the input stage of the amplifier. The
input stage can be constructed of PMOS (a) devices allowing for the input to swing below the negative supply or a
NMOS differential pair (b) where the inputs can swing above the positive supply. A composite input stage (c) uses
PMOS and NMOS differential pairs so the input voltage range can extend from above the positive rail to below the
negative rail.
Percent Charge
of the closed loop system will generate a small change 100
Battery Voltage,
4-cell, NiMH (V)
80
in offset voltage. The offset voltage error is then gained 5
(%)
60
by the closed loop system, generating a gain error.
4 40
(Refer to Figure 3, where ∆VOS = open loop gain error.)
20
A load will degrade the open loop gain performance. 3 0
Some manufacturers recognize this and specify more 0 50 100
Minutes
than one test condition.
Power Supply Rejection (PSRR)
PSR (V/V) = ∆VOS/∆VSUPPLY
Specification Discussion - The power supply rejection
ratio specification quantifies the amplifier’s sensitivity to VOUT = (1 + RF/RIN) (VIN + VOS)
power supply changes. Ideally, the power supply rejec-
tion ratio should be infinite. Typical specifications for a
power supply rejection ratio of an amplifier range from FIGURE 9: A battery powered application can see a
60dB to 100dB. change in power supply voltage of several hundreds of
millivolts over the life of the product. If an op amp is
As is with the open loop gain (AOL) characteristics of an configured with a high closed loop gain in these types
amplifier, DC and lower frequency power supply noise of applications, it must have good DC power supply
is rejected more than at higher frequencies. In a closed rejection.
loop system, a less than ideal power supply rejection
capability of an amplifier manifests itself as an offset Common Mode Rejection Ratio (CMRR)
voltage error as shown in Figure 3 (PSRRERROR = ∆VOS). Specification Discussion - The Common Mode Rejec-
This error is best described with the formula: tion Ratio of an amplifier describes the amplifier’s input
PSRR(dB) = 20 log (∆VSUPPLY / ∆VOS) sensitivity to equivalent voltage changes of both inputs.
This error manifests itself as an offset error
The formula that describes power supply rejection is:
(CMRR ERROR), as shown in Figure 3.
PSR(V/V) = ∆VOS / ∆VSUPPLY
CMRR(dB) = 20 log (∆VCM / ∆VOS)
Where:
Where:
VSUPPLY = VDD - VSS
∆VOS = CMRRERROR
Application Challenge - An application where power
Application Challenge - The specification range for
supply rejection is critical is shown in Figure 9. In this
CMRR in single supply amplifiers is from 45dB up to
circuit, a battery is used to power an amplifier which is
90dB. Typically, this error becomes an issue when an
configured in a high, closed loop gain of 101V/V. During
amplifier is in a circuit where the input common mode
the life of the battery, the output voltage ranges from
voltage changes with input signal. A good example
5.75V down to 4.75V. If the power supply rejection of
where this is the case, is when the amplifier is in a
the amplifier is 500µV/V (or 66dB), the error at the out-
non-inverting configuration. A common circuit that has
put of the amplifier over time would be 50.5mV. In a
this configuration is shown in the Figure 10.
12-bit system with a full-scale range of 4.096V, this
would equate to a 50.5 counts worth of offset change
over the life of the battery.
Measured Measured
Output Voltage Swing Test Conditions Output Swing Output Swing
from VSS (mV) from VDD (mV)
TABLE 1: This data was taken with one sample of the MCP601 op amp and demonstrates the effects of the output
conditions on the output swing performance of that amplifier. This data was taken with no regard to the open loop gain
of the amplifier.
10
0
Offset Voltage (mV)
VIN RCL
AOL VOUT
-10
-20
VREF
-30
FIGURE 12: The closed loop output resistance of an
-40 amplifier is lessened by the magnitude of the open
0 1 2 3 4 5 loop gain of the amplifier.
Output Voltage (V)
Power Supply Requirements (VSS, VDD, IDD, IQ)
FIGURE 11: This graph shows the relationship Specification Discussion - Power supply voltage
between the output swing of an amplifier and input defines the acceptable difference between VDD and
offset voltage with a 25kΩ load and VDD = 5V. The VSS which allows linear operation of the amplifier. If this
open loop gain of the amplifier can be calculated by voltage difference is less than specification, the ampli-
selecting two points on the graph and calculating the fier may not operate reliably. If the power supply voltage
slope. As the output swing of the amplifier goes is greater than specified, the amplifier most likely will
towards the rail, the amplifier function eventually operate as expected, but it is possible that damage may
breaks down. This is first manifested with changes in occur due to overvoltage stress on the internal transis-
input offset voltage. tors in the amplifier.
Output Impedance (ROUT, RCL, ROL, ZCL, ZOL) The power supply range is usually listed as a separate
Specification Discussion - The fact that the output line item in the specification table in the product data
impedance of an op amp is low, makes the device use- sheet. Occasionally, the specification is called out as a
ful in terms of “isolating” the impedance of two portions condition under the PSRR specification.
of a circuit. For this reason, low output impedance of an Power supply current (IDD or IQ) is specified with no
op amp is an important characteristic, but the precise load. Typically, if a load is applied to the amplifier, a
output impedance is usually is not specified. source current will primarily be pulled from VDD,
When the output impedance is specified, it is given in through the op amp output stage, and then through the
terms of a resistance or impedance of a closed loop load. A sink current will primarily result in an increase
configuration (RCL or ZCL) or an open loop configura- of VSS.
tion (ROL or ZOL). Output impedance is most often spec-
ified as resistance.
Closed loop output resistance is the easiest to measure
and is equal to:
RCL = ∆VOUT / ∆IL
where
∆VOUT = the change in output voltage and
∆IL = the change in output current with a change in
output voltage
CONCLUSION
When searching for the right amplifier for an applica-
tion, various performance specifications need to be
taken into consideration. The first set of specifications
to consider are the affects of the DC limitations of the
amplifier. In single supply applications, amplifier errors
such as input voltage swing, input offset voltage and
input bias current could reduce the dynamic range of
the amplifier. Conversely, in high gain circuits, the out-
put voltage swing could cause signal clipping problems.
The second set of specifications to consider are the AC
specifications. These issues are discussed in detail in
the application note from Microchip entitled “Opera-
tional Amplifier AC Specifications and Applications”,
AN723 (available December, 1999.)
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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