Code:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:31:23 11/09/2017
-- Design Name:
-- Module Name: RangkaianSederhana - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RangkaianSederhana is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end RangkaianSederhana;

architecture Behavioral of RangkaianSederhana is

begin
C <= A and B;

end Behavioral;
Percbaan 2

Code:

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 16:32:25 11/09/2017

-- Design Name:

-- Module Name: bcd7SEgment - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity bcd7SEgment is

Port ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

HEX1 : OUT STD_LOGIC_VECTOR (1 TO 7));

end bcd7SEgment;

architecture Behavioral of bcd7SEgment is

CONSTANT NOL : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";

CONSTANT SATU : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";

CONSTANT DUA : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";

CONSTANT TIGA : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";

CONSTANT EMPAT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";

CONSTANT LIMA : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";

CONSTANT ENAM : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";

CONSTANT TUJUH : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";

CONSTANT DELAPAN : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";

CONSTANT SEMBILAN: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";

BEGIN

PROCESS(SW)

BEGIN

CASE SW IS

WHEN NOL => HEX1 <= "1111110";

WHEN SATU => HEX1 <= "0110000";

WHEN DUA => HEX1 <= "1101101";

WHEN TIGA => HEX1 <= "1111001";

WHEN EMPAT => HEX1 <= "0110011";

WHEN LIMA => HEX1 <= "1011011";

WHEN ENAM => HEX1 <= "1011111";

WHEN TUJUH => HEX1 <= "1110000";

WHEN DELAPAN => HEX1 <= "1111111";

WHEN SEMBILAN => HEX1 <= "1110011";

WHEN OTHERS => HEX1 <= "0000000";

END CASE;

END PROCESS;

end Behavioral;