The Digital

Pathfinder Velox Investment Services

8/3/04

Volume 1, Issue 2

Eric Jhonsa
ejhonsa@veloxinvest.com
203-545-5072

FPGAs, ASICs, and the Xilinx-Altera Duopoly

Company Ticker Price Market Cap. 52-Week Range

Altera ALTR $21.39 $8.01 Billion $17.43-$26.82
Xilinx XLNX $29.89 $10.38 Billion $24.59-$45.40

The effects of Moore’s Law, along with support for a growing number of embedded IP cores, have put FPGAs on a trajectory to
take considerable market share from ASICs over the next few years in the field of custom chip designs. This FastNote takes a
look at the trends driving the FPGA market’s growth, and how the market’s two dominant and comparably-valued vendors,
Xilinx and Altera, stack up in the battle to capitalize on them.

FPGA Growth Drivers

Historically, the demarcation lines separating the use of application-specific integrated circuits (ASICs) and programmable logic
devices (PLDs) for OEM chip designs have been pretty straight-forward. PLDs, owing to their fast design times, minimal design
costs, and ability to be reprogrammed indefinitely, were chosen for those applications where time-to-market was of the essence
and/or unit volumes couldn’t justify the design costs of an ASIC. For basic, low-end applications such as interface and “glue
logic” chips, complex programmable logic devices (CPLDs) were used; for everything more demanding (80% of PLD
applications in 2003 on a revenue basis), field-programmable gate arrays (FPGAs) were deployed. Meanwhile, ASICs, on
account of their lower power consumption and far superior gate densities, were used for all applications where the
aforementioned constraints were not an issue. Until recently, a rule of thumb was that, save for prototypes, where an FPGA’s fast
design time makes it preferable, an ASIC would be used for any device requiring more than 500,000 gates or more than 100,000
units.

However, as with so many other battles within the semiconductor industry, the push of Moore’s Law is quickly rewriting the
rules of the ASIC-FPGA debate, and in doing so allowing the latter architecture to become a viable solution for many custom
chip applications previously withheld for the former. The primary changes being wrought by Moore’s Law that are improving
the viability of FPGAs are as follows:

Soaring ASIC Design Times – The EDA software tools used to develop ASICs, such as those made by Cadence and Synopsys,
have failed to keep pace with the growth in transistor counts caused by the transition to cutting-edge process geometries. As a
result of this shortcoming, design times for 130-nm and 90-nm ASICs have often been several months longer than design times
for predecessors using less advanced geometries. The growing use of third-party intellectual property (IP) cores by ASIC
developers can be seen as an attempt to curb this trend, but one that has only been partially successful.

Soaring Photomask Costs – At the 180-nm node, the average cost for a set of photomasks used to etch the circuits for a complex
chip design onto a semiconductor wafer is about $250,000. For the 130-nm node, that figure triples to $750,000; and it doubles
again at 90-nm to $1.5 million. Already, it’s being estimated that the average mask cost for a complex 65-nm chip will reach $3
million, and the possibility of $10 million mask sets becoming routine by the end of the decade isn’t out of the question. Costs
for cutting-edge mask sets can be noticeably higher than averages, and many ASICs require multiple mask sets to be developed.
Since a single FPGA design is generally used by hundreds or even thousands of different OEM customers, the customer’s
photomask costs, paid indirectly through the cost of the chip, are invariably much lower with an FPGA than with an ASIC.

1
This report is based on information available to the public; no representation is made with regard to its accuracy or completeness. This document is neither an offer nor
solicitation to buy or sell securities. All expressions of opinion reflect judgment at this date and are subject to change. Velox Investment Services and others associated
with it may have positions in securities of companies mentioned. Reproduction of this report is strictly prohibited.
The Digital
Pathfinder Velox Investment Services

8/3/04

Volume 1, Issue 2

FPGAs, ASICs, and the Xilinx-Altera Duopoly

Growing Manufacturing Complexity – The days when the only important variable in determining the length of a chip design
project was the time required to design a chip’s circuitry are long gone. Today, due to the complexities involved with
manufacturing a chip at a cutting-edge process node, it’s estimated that efforts following a chip design’s physical verification (i.e.
tape-out) take up 30% of all design time. Growing demand among chip developers for design-for-manufacturing (DFM) tools,
and growing collaboration between chip developers and wafer foundries during the chip design process, are signs of this trend.
Meanwhile, just as it’s taking longer for chip designs to be prepared for manufacturing, it’s also taking much longer for a chip to
move from design tape-out to photomask tape-out, the point where a photomask supplier has all of the necessary data to produce
a chip’s mask set: Whereas the mask tape-out process typically took only 2-3 days at the 180-nm node, it often takes as long as a
month at the 90-nm node. Using an FPGA instead of an ASIC allows a chip designer to sidestep these issues.

A Narrowing Performance Gap – The complexities involved with designing and manufacturing high-performance chips at
cutting-edge process geometries, along with growing problems related to power consumption and heat dissipation, have resulted
in many new chip designs failing to keep pace with Moore’s Law in terms of performance. Intel’s recent difficulties in scaling its
Netburst (Pentium 4 and Xeon) architecture to higher clock speeds, along with its announcement to transition its desktop CPU
lineup to a dual-core platform based on its Banias (Pentium M) architecture, signifies a broader dilemma faced by many
semiconductor developers, including ASIC designers. FPGAs, on the other hand, have had little trouble keeping pace with
Moore’s Law on a performance basis; in fact, the development of new product architectures has often allowed FPGA vendors to
improve the price/performance of their solutions at a rate faster than Moore’s Law.

In addition to the toll of Moore’s Law, the FPGA market has received a major boost in recent years through the efforts of device
vendors and various third-parties to develop an extensive array of IP cores for leading FPGA platforms. By delivering off-the-
shelf support for features such as memory interfaces, high-speed communications links and protocols, analog-digital conversions,
and embedded microprocessors and DSPs, FPGA vendors have been able to neutralize the historical advantage of ASICs in
supporting off-the-shelf IP, while adding to the design time advantage of their products. Meanwhile, the rapid pace of
standards/protocol changes in the consumer electronics, mobile communications, and optical networking markets have also given
FPGAs a boost, as such an environment increases the value of an FPGA’s fast design times and reprogrammability, while making
an ASIC’s design and mask costs more prohibitive. This last issue has helped make FPGAs not only a competitive alternative to
ASICs, but at times, also to application-specific standard products (ASSPs) offered by third-party semiconductor developers.

Due to these factors, OEMs have found themselves using FPGAs in many applications that go well beyond the platform’s
traditional gate and unit boundaries. High-performance FPGAs containing millions of gates - in some cases, more than five
million - have been used with growing frequency in a variety of demanding enterprise and telecommunications applications,
including multi-gigabit transceivers, network search co-processors, protocol framers and mappers, and network management
CPUs. At the same time, low-cost FPGAs are now routinely being used within high-volume consumer electronics products, such
as set-top boxes, DVD recorders, telematics systems, flat-panel TVs and HDTVs, and even some handheld devices. These trends
were pivotal in allowing the PLD market, which includes the slower-growing CPLD segment, to grow 14% during 2003, to $2.6
billion; this compares with 3% growth for the $17 billion ASIC market. Gartner Dataquest estimated that ASIC design starts,
which numbered over 11,000 in 1997, numbered less than 3,800 in 2003. From 2004 to 2008, Gartner expects the PLD market to
register a CAGR of 20%, as compared with an 8% CAGR for the ASIC market. Considering the market opportunity availability
to FPGAs, the ongoing trend of declining ASIC design starts, and the extent to which OEMs have adopted FPGAs for new
applications over the last two years, upside potential for the FPGA forecast clearly exists.

2
This report is based on information available to the public; no representation is made with regard to its accuracy or completeness. This document is neither an offer nor
solicitation to buy or sell securities. All expressions of opinion reflect judgment at this date and are subject to change. Velox Investment Services and others associated
with it may have positions in securities of companies mentioned. Reproduction of this report is strictly prohibited.
The Digital
Pathfinder Velox Investment Services

8/3/04

Volume 1, Issue 2

FPGAs, ASICs, and the Xilinx-Altera Duopoly

Xilinx and Altera: Comparing the Titans

The similarities between Xilinx and Altera, two companies that were estimated to have 83% of the PLD market (and an even
larger percentage of the FPGA market) between them in 2003, are easy to spot. Each company is a near pure-play in the PLD
space, with almost all of its revenues coming from sales of FPGAs, CPLDs, and related products and services. Each company’s
product line includes high-performance FPGA families, low-cost FPGA families, and CPLD families, as well as a comprehensive
FPGA design software suite that can work with third-party tools from the likes of Synplicity and Mentor Graphics. Each
company can claim thousands of customers scattered over numerous end-markets, with manufacturers of networking and telecom
equipment being the largest consumers of their devices on a revenue basis. Each company is a fabless semiconductor developer,
outsourcing all of its manufacturing work to foundries. And the two companies are comparably valued, although Altera presently
has a slight premium: Xilinx trades at 6.9x sales and 21x its estimated earnings for the March 2006 fiscal year, while Altera
trades at 8.5x sales and 24x its estimated earnings for the December 2005 fiscal year.

In the battle for capitalizing on the FPGA market’s emerging growth opportunities, none of the market’s other prominent vendors
– Actel (NASDAQ: ACTL), Lattice Semiconductor (NASDAQ: LSCC), and QuickLogic (NASDAQ: QUIK) - have the ability to
effectively compete with Xilinx and Altera. None of these firms have the R&D resources to develop competitive truly hardware
architectures, software suites, and IP libraries for mainstream, high-performance and low-cost applications. A close look at the
product lines of these companies demonstrates that they’re aware of this fact as well, with each company’s FPGA business
depending primarily on the sale of chips using nonvolatile memory cells rather than the SRAM-based cells that Xilinx and Altera
use in their products. FPGAs based on nonvolatile cells are popular for certain low-end applications due to the fact that they
don’t need a separate memory chip to house their configuration data; and in the cases of the antifuse FPGA architectures of Actel
and Quicklogic, they also possess attractive radiation-tolerance and power consumption features. However, the fact that
nonvolatile memory cells invariably possess much lower logic densities and clock speeds prohibits them from delivering the type
of price/performance needed to compete with SRAM-based FPGAs in either high-performance or high-volume mainstream
applications.

But in spite of the similarities, and the extent to which the two firms stand apart from their competition, Xilinx and Altera do
possess notable differences, with each company able to claim several important competitive strengths relative to its rival. These
strengths are as follows:

Altera’s Strengths

130-nm High-Performance FPGA Leadership – Altera shipped the first engineering samples for its Stratix family of 130-nm,
high-performance FPGAs in April 2002, and began volume production of the devices in early 2003. Xilinx delivered the first
samples of its competing Virtex-II Pro family in March 2002, but due to manufacturing problems, was unable to ramp production
until much later in 2003. This time-to-market advantage provided Altera with an important competitive advantage in terms of
scoring design wins for Stratix during 2002 and 2003. Adding to this momentum was the fact that Stratix represented a major
architectural improvement over Altera’s older, 180-nm, Apex II family of high-performance FPGAs. Advances such as new
routing and high-density memory architectures, and improved signal communications performance, were instrumental in allowing
Stratix to demonstrate 60% sequential revenue in the last quarter, emerge as Altera’s largest product family in terms of revenue,
and allow Altera to solidly outpace Xilinx in terms of overall sequential revenue growth (11% compared with 5%). With large
numbers of design wins having yet to ramp, Stratix should allow Altera to continue gaining market share in the high-performance
FPGA space during 2004.

130-nm Low-Cost FPGA Dominance – Altera began shipping engineering samples of its Cyclone family of 130-nm, low-cost
FPGAs in December 2002, and began volume production in March 2003. Xilinx never released a competing 130-nm solution,
choosing to rely instead on its Spartan-IIE family of 150-nm FPGAs in the low-cost segment until 90-nm products were

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This report is based on information available to the public; no representation is made with regard to its accuracy or completeness. This document is neither an offer nor
solicitation to buy or sell securities. All expressions of opinion reflect judgment at this date and are subject to change. Velox Investment Services and others associated
with it may have positions in securities of companies mentioned. Reproduction of this report is strictly prohibited.
The Digital
Pathfinder Velox Investment Services

8/3/04

Volume 1, Issue 2

FPGAs, ASICs, and the Xilinx-Altera Duopoly

developed. Like Stratix, Cyclone represented a new product architecture for Altera, and it stacked up quite well against the
Spartan-IIE in terms of features such as logic densities and memory and I/O functionality. Whereas the Spartan-IIE only scaled
to 300,000 gates, Cyclone could offer over 1.2 million. Released at a time when consumer electronics manufacturers and
residential/SOHO networking equipment firms were beginning to use low-end FPGAs to an unprecedented extent, Altera has
already obtained over 3,000 customers for Cyclone, with revenues up 35% sequentially during the last quarter.

Soft CPU Core Leadership – Altera’s Nios family of soft (i.e. configurable) CPU cores, used for integration with its FPGA
products, have traditionally been acclaimed for their ease-of-use and flexibility. With the release of its Nios-II family in May
2004, Altera also develops a clear price/performance advantage over Xilinx’s competing MicroBlaze and PicoBlaze families.
Altera claims that the most powerful version of the Nios-II can deliver 4x the performance of the fastest Nios solution while
consuming only 1/3 as many logic elements. At 90-nm, Altera claims that the performance of the Nios-II is comparable to that of
a 180-nm ARM9 “hard” CPU core, an impressive accomplishment. Owing to their configurability, soft CPU cores are
considered preferable to hard cores for many FPGA applications, and the release of the Nios-II will likely add to the current
momentum of Stratix and Cyclone.

Max II CPLDs – With the development of Max II, Altera moved away from the traditional CPLD architecture used by the
market’s leading vendors, and in effect opted for an architecture based on a no-frills FPGA. By making this move while still
allowing to treat the device as a CPLD, Altera is able to bring to the CPLD space the enormous advances FPGAs have made over
the years in terms of logic densities and price/performance, while reducing power consumption by eliminating the need for
power-hungry sense amplifier technology. The Max II, which should see samples delivered this summer and mass-production
begin in Q1 2005, offers Altera the ability not only to gain market share in the traditional CPLD space, but to also encroach on
the turf of low-end, non-volatile FPGA solutions.

HardCopy Structured ASICs – In response to the growing threat posed by FPGAs, a number of ASIC vendors, including LSI
Logic, NEC, and Fujitsu, have developed solutions known as structured ASICs. Offering pre-built functionality for certain ASIC
elements while allowing others to be customized, structured ASIC vendors are trying to create a middle ground between the
superior performance and lower unit costs of a standard-cell ASIC, and the lower design costs and faster time-to-market of an
FPGA. Given the advances that FPGAs have made in recent years, and the fact that structured ASICs can’t be reprogrammed, we
believe that the devices will do more to take share away from standard-cell ASICs than they will to compete against FPGAs.
Nonetheless, the structured ASIC market does have growth potential, and Altera offers an innovative solution for it called
HardCopy. HardCopy allows a company needing an ASIC design to develop the product using an Altera FPGA, after which
Altera converts the design into ASIC form. Such a solution both exploits an FPGA’s fast design capabilities and guarantees that
the developed ASIC won’t suffer from yield or reliability problems. Altera’s HardCopy revenues doubled during the most recent
quarter, with ten designs taping out. The company expects HardCopy to eventually account for 15-20% of its revenues.

Xilinx’s Strengths

90-nm Low-Cost FPGA Time-to-Market – Xilinx began shipping samples of its 90-nm, Spartan-3 FPGA family in March
2003, and began volume production in early 2004. Altera, by contrast, doesn’t begin sampling its Cyclone II family of 90-nm
FPGAs until February 2005. Although Altera shouldn’t take as long as Xilinx to move from sampling to volume production, it’s
clear that Spartan-3 possesses an enormous time-to-market advantage. The Spartan-3, in addition to eliminating the Cyclone’s
memory and I/O functionality advantages, features advanced DSP capabilities and an I/O pad architecture that cuts down on a
chip’s die size. Perhaps most importantly, it delivers enormous price/performance improvements over the Spartan-IIE, and can
scale to five million gates. Xilinx claims that it currently has five times as many design registrations for the Spartan-3 than it
does with any other product family, with these registrations already accounting for over 40% of all Spartan-related registrations in
the company’s history. A number of these registrations involve high-volume consumer electronics applications. Xilinx expects
to release a version of the Spartan-3 that lowers power consumption by 2/3 during Q4 2004.

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This report is based on information available to the public; no representation is made with regard to its accuracy or completeness. This document is neither an offer nor
solicitation to buy or sell securities. All expressions of opinion reflect judgment at this date and are subject to change. Velox Investment Services and others associated
with it may have positions in securities of companies mentioned. Reproduction of this report is strictly prohibited.
The Digital
Pathfinder Velox Investment Services

8/3/04

Volume 1, Issue 2

FPGAs, ASICs, and the Xilinx-Altera Duopoly

90-nm High-Performance FPGA Technology Leadership – Altera’s Stratix II 90-nm FPGA platform should be a competitive
solution in the high-performance segment, making use of low-k dielectric materials to enhance performance and improving on
Stratix’s architecture through the use of adaptive logic module (ALM) technology that allows logic elements to work with 25%
greater efficiency. However, we believe Xilinx’s Virtex-4 family has a technology edge in this space, due largely to what Xilinx
calls an application-specific modular block architecture (ASMBL). Unlike traditional high-performance FPGA families, which
offer a common architecture for all applications, the Virtex-4 family is broken up into three product lines to address different
customer requirements. This customized approach not only results in more effective targeting of a customer’s needs, but also
leads to higher logic densities. The Virtex-4 also benefits from the use of triple-oxide manufacturing technology, which,
according to Xilinx, will result in 50% lower power consumption for the Virtex-4 relative to the Virtex-II Pro. By contrast,
Altera, like many chip developers, expects its 90-nm products to have higher power consumption than their 130-nm predecessors.
Both the Virtex-4 and the Stratix II began sampling this summer, and each should move to volume production in early 2005.

Hard CPU Core Leadership – Both the Virtex-II Pro and the Virtex-4 offer support for embedded IBM PowerPC CPU cores.
The superior performance of hard CPU cores has led to their adoption for many demanding FPGA applications, particularly those
involving networking and telecommunications equipment. Xilinx currently has over 1,400 PowerPC licenses. By contrast,
Altera currently doesn’t offer hard CPU cores for the Stratix or Stratix II, and has opted to end development work on its Excalibur
FPGA line, which supported embedded ARM9 cores.

Serial Transceiver Leadership – Both Xilinx and Altera’s high-performance FPGAs support the integration of 3.125-Gbps
serial transceiver cells for networking/telecom applications. However, only Xilinx, through its Virtex-II Pro X line, currently
supports serial transceivers operating at speeds of 10-Gbps and higher. In addition, Xilinx’s 10-Gbps solutions already support
the AdvancedTCA (ATCA) serial backplane standard, which is expected to be widely adopted among telecom equipment
manufacturers.

Embedded FPGA Solutions – In June 2002, Xilinx and IBM signed an agreement to develop ASICs with embedded FPGA
cells, with the solution to be made available in 2004 to IBM’s ASIC customers. Previously, such a platform would have been
impractical on account of the enormous amount of die size that the FPGA cells would take up. However, at the 90-nm node, the
value proposition of such devices becomes far more compelling, offering the potential to create ASIC platforms that can be
reused over multiple product generations, with the FPGA portion being used to handle new standards. And in March 2004,
Xilinx announced its acquisition of Triscend, a developer of microcontroller products with embedded FPGA cells. The Triscend
acquisition gives Xilinx a novel platform for addressing the 8-bit and 32-bit segments of the $11 billion microcontroller market.

Conclusion
Given the market opportunities in front of them within the FPGA market, the extent to which each company has positioned itself
to take advantage of them, and the barriers to entry for any would-be competitor, we expect both Xilinx and Altera to outgrow the
broader semiconductor industry during the next few years. For the upcoming 6-9 months, we believe that Altera’s shares will
outperform Xilinx’s, owing to continued market share gains for Stratix; the ramping of Cyclone design wins; and to a lesser
extent, growth in HardCopy volumes. But we also believe that as 2005 progresses, Xilinx is likely to become the superior market
performer, as Spartan-3 revenues take off and the impact of Virtex-4, boosted by Xilinx’s PowerPC and serial transceiver
capabilities, begins to be felt. Over the near-term, the relatively high (though not exorbitant) valuations of the firms and ongoing
inventory concerns will weigh on Xilinx and Altera’s shares, but they should also present good buying opportunities for those
investors looking beyond the third quarter of 2004.

5
This report is based on information available to the public; no representation is made with regard to its accuracy or completeness. This document is neither an offer nor
solicitation to buy or sell securities. All expressions of opinion reflect judgment at this date and are subject to change. Velox Investment Services and others associated
with it may have positions in securities of companies mentioned. Reproduction of this report is strictly prohibited.