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– Signal declarations:
Examples:
signal clock:BIT;
signal data_bus:BIT_VECTOR(0 to7);
signal gate_delay:TIME :=10ns;
signal init_P: STD_LOGIC_VECTOR(7 downto 0):=
(0 => ‘1’, others => ‘U’);
© Ali Elkateeb, 2000 Programmable Logic Course Basic Language Elements 8
Data Objects
– File declarations:
file file-names: file-type-name [[open mode] is string-expression];
– string expression: interpreted by the host environment
as the physical name of a file
– mode specifies whether the files is to be used as
read-only or write-only, or in the append mode
Examples:
file STIMULUS:TEXT open READ_MODE
is “/usr/home/jb/add.sti”;
file VECTOR: BIT_FILE is “/usr/home/james/add.vec”;
--default is READ_MODE
type DIGIT is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, ‘9’);
subtype MIDDLE is DIGIT range ‘3’ to ‘7’;
-- DIGIT is a user-defined enumeration type. MIDDLE is subtype
© Ali Elkateeb, 2000 Programmable Logic Course Basic Language Elements 11
Data Types
– Subtype could not impose a constraint
Example:
subtype NUMBER is DIGIT --NUMBER is a subtype with no constraint
-- the subtype simply gives another name to an already existing type
Examples:
type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);
type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL);
subtype ARITH_OP is MICR_OP range ADD to MUL;
Examples: of objects defined for these types
signal CONTROL_A: MVL;
signal CLOCK: MVL range ‘0’ to ‘1’; --CLOCK restricted to ‘0’ or ‘1’
--range constraint can be specified in an object declaration