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The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin
CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations
to achieve high performance levels.
231455 – 2
40 Lead
Figure 2. 8086 Pin
Configuration
231455 – 1
Figure 1. 8086 CPU Block Diagram
The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘Local
Bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to
additional bus buffers).
Symbol Pin No. Type Name and Function
AD15 –AD0 2–16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address (T1), and data (T2, T3, TW, T4) bus. A0 is
analogous to BHE for the lower byte of the data bus, pins D7 –D0. It is
LOW during T1 when a byte is to be transferred on the lower portion
of the bus in memory or I/O operations. Eight-bit oriented devices tied
to the lower half would normally use A0 to condition chip select
functions. (See BHE.) These lines are active HIGH and float to 3-state
OFF during interrupt acknowledge and local bus ‘‘hold acknowledge’’.
A19/S6, 35–38 O ADDRESS/STATUS: During T1 these are the four most significant
A18/S5, address lines for memory operations. During I/O operations these
A17/S4, lines are LOW. During memory and I/O operations, status information
A16/S3 is available on these lines during T2, T3, TW, T4. The status of the
interrupt enable FLAG bit (S5) is updated at the beginning of each
CLK cycle. A17/S4 and A16/S3 are encoded as shown.
This information indicates which relocation register is presently being
used for data accessing.
These lines float to 3-state OFF during local bus ‘‘hold acknowledge.’’
A17/S4 A16/S3 Characteristics
0 (LOW) 0 Alternate Data
0 1 Stack
1 (HIGH) 0 Code or None
1 1 Data
S6 is 0
(LOW)
BHE/S7 34 O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal
(BHE) should be used to enable data onto the most significant half of
the data bus, pins D15 –D8. Eight-bit oriented devices tied to the upper
half of the bus would normally use BHE to condition chip select
functions. BHE is LOW during T1 for read, write, and interrupt
acknowledge cycles when a byte is to be transferred on the high
portion of the bus. The S7 status information is available during T2,
T3, and T4. The signal is active LOW, and floats to 3-state OFF in
‘‘hold’’. It is LOW during T1 for the first interrupt acknowledge cycle.
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None
RD 32 O READ: Read strobe indicates that the processor is performing a
memory or I/O read cycle, depending on the state of the S2 pin. This
signal is used to read devices which reside on the 8086 local bus. RD
is active LOW during T2, T3 and TW of any read cycle, and is
guaranteed to remain HIGH in T2 until the 8086 local bus has floated.
This signal floats to 3-state OFF in ‘‘hold acknowledge’’.
2
8086
The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MX e VSS).
Only the pin functions which are unique to maximum mode are described; all other pin functions are as
described above.
S2, S1, S0 26–28 O STATUS: active during T4, T1, and T2 and is returned to the passive state
(1, 1, 1) during T3 or during TW when READY is HIGH. This status is used
by the 8288 Bus Controller to generate all memory and I/O access control
signals. Any change by S2, S1, or S0 during T4 is used to indicate the
beginning of a bus cycle, and the return to the passive state in T3 or TW is
used to indicate the end of a bus cycle.
3
8086
4
8086
The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX e VCC). Only the pin
functions which are unique to minimum mode are described; all other pin functions are as described above.
M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to
distinguish a memory access from an I/O access. M/IO becomes valid in
the T4 preceding a bus cycle and remains valid until the final T4 of the cycle
(M e HIGH, IO e LOW). M/IO floats to 3-state OFF in local bus ‘‘hold
acknowledge’’.
WR 29 O WRITE: indicates that the processor is performing a write memory or write
I/O cycle, depending on the state of the M/IO signal. WR is active for T2, T3
and TW of any write cycle. It is active LOW, and floats to 3-state OFF in
local bus ‘‘hold acknowledge’’.
INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active
LOW during T2, T3 and TW of each interrupt acknowledge cycle.
ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch the
address into the 8282/8283 address latch. It is a HIGH pulse active during
T1 of any bus cycle. Note that ALE is never floated.
DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that desires to
use an 8286/8287 data bus transceiver. It is used to control the direction of
data flow through the transceiver. Logically DT/R is equivalent to S1 in the
maximum mode, and its timing is the same as for M/IO. (T e HIGH, R e
LOW.) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’.
DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in a
minimum system which uses the transceiver. DEN is active LOW during
each memory and I/O access and for INTA cycles. For a read or INTA cycle
it is active from the middle of T2 until the middle of T4, while for a write cycle
it is active from the beginning of T2 until the middle of T4. DEN floats to 3-
state OFF in local bus ‘‘hold acknowledge’’.
HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus ‘‘hold.’’ To be
HLDA acknowledged, HOLD must be active HIGH. The processor receiving the
‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the
middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines. After HOLD is
detected as being LOW, the processor will LOWer the HLDA, and when the
processor needs to run another cycle, it will again drive the local bus and
control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up
resistors.
The same rules as for RQ/GT apply regarding when the local bus will be
released.
HOLD is not an asynchronous input. External synchronization should be
provided if the system cannot otherwise guarantee the setup time.
5
8086
6
8086
7
8086
231455 – 5
231455 – 6
8
8086
231455 – 8
9
8086
Status bits S3 through S7 are multiplexed with high- NMI asserted prior to the 2nd clock after the end of
order address bits and the BHE signal, and are RESET will not be honored. If NMI is asserted after
therefore valid during T2 through T4. S3 and S4 indi- that point and during the internal reset sequence,
cate which segment register (see Instruction Set de- the processor may execute one instruction before
scription) was used for this bus cycle in forming the responding to the interrupt. A hold request active
address, according to the following table: immediately after RESET will be honored before the
first instruction fetch.
S4 S3 Characteristics
0 (LOW) 0 Alternate Data (extra segment) All 3-state outputs float to 3-state OFF during
RESET. Status is active in the idle state for the first
0 1 Stack
clock after RESET becomes active and then floats
1 (HIGH) 0 Code or None to 3-state OFF. ALE and HLDA are driven low.
1 1 Data
INTERRUPT OPERATIONS
S5 is a reflection of the PSW interrupt enable bit.
S6 e 0 and S7 is a spare status bit. Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts
and software aspects of hardware interrupts are
I/O ADDRESSING specified in the Instruction Set description. Hard-
ware interrupts can be classified as non-maskable or
In the 8086, I/O operations can address up to a maskable.
maximum of 64K I/O byte registers or 32K I/O word
registers. The I/O address appears in the same for- Interrupts result in a transfer of control to a new pro-
mat as the memory address on bus lines A15 –A0. gram location. A 256-element table containing ad-
The address lines A19 –A16 are zero in I/O opera- dress pointers to the interrupt service program loca-
tions. The variable I/O instructions which use regis- tions resides in absolute locations 0 through 3FFH
ter DX as a pointer have full address capability while (see Figure 3b), which are reserved for this purpose.
the direct I/O instructions directly address one or Each element in the table is 4 bytes in size and
two of the 256 I/O byte locations in page 0 of the corresponds to an interrupt ‘‘type’’. An interrupting
I/O address space. device supplies an 8-bit type number, during the in-
terrupt acknowledge sequence, which is used to
I/O ports are addressed in the same manner as ‘‘vector’’ through the appropriate element to the new
memory locations. Even addressed bytes are trans- interrupt service program location.
ferred on the D7 –D0 bus lines and odd addressed
bytes on D15 –D8. Care must be taken to assure that
each register within an 8-bit peripheral located on NON-MASKABLE INTERRUPT (NMI)
the lower portion of the bus be addressed as even.
The processor provides a single non-maskable inter-
rupt pin (NMI) which has higher priority than the
maskable interrupt request pin (INTR). A typical use
External Interface would be to activate a power failure routine. The
NMI is edge-triggered on a LOW-to-HIGH transition.
PROCESSOR RESET AND INITIALIZATION The activation of this pin causes a type 2 interrupt.
(See Instruction Set description.)
Processor initialization or start up is accomplished
with activation (HIGH) of the RESET pin. The 8086 NMI is required to have a duration in the HIGH state
RESET is required to be HIGH for greater than 4 of greater than two CLK cycles, but is not required to
CLK cycles. The 8086 will terminate operations on be synchronized to the clock. Any high-going tran-
the high-going edge of RESET and will remain dor- sition of NMI is latched on-chip and will be serviced
mant as long as RESET is HIGH. The low-going at the end of the current instruction or between
transition of RESET triggers an internal reset se- whole moves of a block-type instruction. Worst case
quence for approximately 10 CLK cycles. After this response to NMI would be for multiply, divide, and
interval the 8086 operates normally beginning with variable shift instructions. There is no specification
the instruction in absolute location FFFF0H (see Fig- on the occurrence of the low-going edge; it may oc-
ure 3b). The details of this operation are specified in cur before, during, or after the servicing of NMI. An-
the Instruction Set description of the MCS-86 Family other high-going edge triggers another response if it
User’s Manual. The RESET input is internally syn- occurs after the start of the NMI procedure. The sig-
chronized to the processor clock. At initialization the nal must be free of logical spikes in general and be
HIGH-to-LOW transition of RESET must occur no free of bounces on the low-going edge to avoid trig-
sooner than 50 ms after power-up, to allow complete gering extraneous responses.
initialization of the 8086.
10
8086
231455 – 9
11
8086
Basic System Timing A write cycle also begins with the assertion of ALE
and the emission of the address. The M/IO signal is
Typical system configurations for the processor op- again asserted to indicate a memory or I/O write
erating in minimum mode and in maximum mode are operation. In the T2 immediately following the ad-
shown in Figures 4a and 4b, respectively. In mini- dress emission the processor emits the data to be
mum mode, the MN/MX pin is strapped to VCC and written into the addressed location. This data re-
the processor emits bus control signals in a manner mains valid until the middle of T4. During T2, T3, and
similar to the 8085. In maximum mode, the MN/MX TW the processor asserts the write control signal.
pin is strapped to VSS and the processor emits cod- The write (WR) signal becomes active at the begin-
ed status information which the 8288 bus controller ning of T2 as opposed to the read which is delayed
uses to generate MULTIBUS compatible bus control somewhat into T2 to provide time for the bus to float.
signals. Figure 5 illustrates the signal timing relation-
ships. The BHE and A0 signals are used to select the prop-
er byte(s) of the memory/IO word to be read or writ-
ten according to the following table:
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to
odd address
1 0 Lower byte from/to
even address
1 1 None
12
8086
lines D7 –D0 as supplied by the inerrupt system logic acknowledge, or software halt. The 8288 thus issues
(i.e., 8259A Priority Interrupt Controller). This byte control signals specifying memory read or write, I/O
identifies the source (type) of the interrupt. It is multi- read or write, or interrupt acknowledge. The 8288
plied by four and used as a pointer into an interrupt provides two types of write strobes, normal and ad-
vector lookup table, as described earlier. vanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write.
The advanced write strobes have the same timing
BUS TIMING–MEDIUM SIZE SYSTEMS as read strobes, and hence data isn’t valid at the
For medium size systems the MN/MX pin is con- leading edge of write. The transceiver receives the
nected to VSS and the 8288 Bus Controller is added usual DIR and G inputs from the 8288’s DT/R and
DEN.
to the system as well as a latch for latching the sys-
tem address, and a transceiver to allow for bus load-
The pointer into the interrupt vector table, which is
ing greater than the 8086 is capable of handling.
passed during the second INTA cycle, can derive
Signals ALE, DEN, and DT/R are generated by the
from an 8259A located on either the local bus or the
8288 instead of the processor in this configuration
system bus. If the master 8259A Priority Interrupt
although their timing remains relatively the same.
Controller is positioned on the local bus, a TTL gate
The 8086 status outputs (S2, S1, and S0) provide
is required to disable the transceiver when reading
type-of-cycle information and become 8288 inputs.
from the master 8259A during the interrupt acknowl-
This bus cycle information specifies read (code,
edge sequence and software ‘‘poll’’.
data, or I/O), write (data or I/O), interrupt
13
8086
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature Under Bias ¿¿¿¿¿¿0ß C to 70ß C
*WARNING: Stressing the device beyond the ‘‘Absolute
Storage Temperature ¿¿¿¿¿¿¿¿¿¿ b 65ß C to a 150ß C Maximum Ratings’’ may cause permanent damage.
Voltage on Any Pin with These are stress ratings only. Operation beyond the
Respect to Ground¿¿¿¿¿¿¿¿¿¿¿¿¿¿ b 1.0V to a 7V ‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
Power Dissipation¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿¿2.5W may affect device reliability.
NOTES:
1. VIL tested with MN/MX Pin e 0V. VIH tested with MN/MX Pin e 5V. MN/MX Pin is a Strap Pin.
2. Not applicable to RQ/GT0 and RQ/GT1 (Pins 30 and 31).
3. HOLD and HLDA ILI min e 30 mA, max e 500 mA.
14
8086
15
8086
TIMING RESPONSES
8086 8086-1 8086-2 Test
Symbol Parameter Units
Min Max Min Max Min Max Conditions
NOTES:
1. Signal at 8284A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state. (8 ns into T3).
16
8086
231455-11
A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V 231455 – 12
for a Logic ‘‘0’’. Timing measurements are made at 1.5V for both
a Logic ‘‘1’’ and ‘‘0’’. CL Includes Jig Capacitance
WAVEFORMS
MINIMUM MODE
231455 – 13
17
8086
WAVEFORMS (Continued)
231455 – 14
SOFTWARE HALT–
RD, WR, INTA e VOH
DT/R e INDETERMINATE
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control
signals shown for second INTA cycle.
4. Signals at 8284A are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
18
8086
A.C. CHARACTERISTICS
19
8086
TIMING RESPONSES
8086 8086-1 8086-2 Test
Symbol Parameter Units
Min Max Min Max Min Max Conditions
20
8086
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T3).
21
8086
WAVEFORMS
MAXIMUM MODE
231455 – 15
22
8086
WAVEFORMS (Continued)
231455 – 16
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for
pointer address is shown for second INTA cycle.
5. Signals at 8284A or 8288 are shown for reference only.
6. The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN)
lags the active high 8288 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T4.
23
8086
WAVEFORMS (Continued)
231455 – 17
NOTE:
1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
231455 – 18
231455 – 19
231455 – 20
NOTE:
The coprocessor may not drive the buses outside the region shown without risking contention.
24
8086
WAVEFORMS (Continued)
231455 – 21
25
8086
PUSH e Push:
Register 0 1 0 1 0 reg
POP e Pop:
Register 0 1 0 1 1 reg
XCHG e Exchange:
IN e Input from:
Fixed Port 1110010w port
Variable Port 1110110w
26
8086
INC e Increment:
Register/Memory 1111111w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA e ASCII Adjust for Add 00110111
BAA e Decimal Adjust for Add 00100111
SUB e Subtract:
Reg./Memory and Register to Either 001010dw mod reg r/m
Immediate from Register/Memory 100000sw mod 1 0 1 r/m data data if s w e 01
Immediate from Accumulator 0010110w data data if w e 1
DEC e Decrement:
Register/memory 1111111w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG e Change sign 1111011w mod 0 1 1 r/m
CMP e Compare:
Register/Memory and Register 001110dw mod reg r/m
27
8086
AND e And:
Reg./Memory and Register to Either 001000dw mod reg r/m
Immediate to Register/Memory 1000000w mod 1 0 0 r/m data data if w e 1
Immediate to Accumulator 0010010w data data if w e 1
TEST e And Function to Flags, No Result:
Register/Memory and Register 1000010w mod reg r/m
OR e Or:
Reg./Memory and Register to Either 000010dw mod reg r/m
Immediate to Register/Memory 1000000w mod 0 0 1 r/m data data if w e 1
Immediate to Accumulator 0000110w data data if w e 1
STRING MANIPULATION
CONTROL TRANSFER
CALL e Call:
seg-low seg-high
28
8086
seg-low seg-high
Intersegment 11001011
INT e Interrupt
Type 3 11001100
29
8086
30
SISTEMAS NUMÉRICOS
Los sistemas numéricos son un conjunto de símbolos y reglas que se usan para
representar cantidades numéricas. La base de los diferentes sistemas numéricos nos
indica la cantidad de diferentes símbolos y dígitos que el sistema utiliza y también es la
que determina cual es el valor de cada símbolo dependiendo de la posición que ocupa.
Ejemplos:
Hexadecimal Binario Hexadecimal Binario
0 0000 8 1000
1 0001 9 1001
2 0010 A 1010
3 0011 B 1011
4 0100 C 1100
5 0101 D 1101
6 0110 E 1110
7 0111 F 1111
0x E 8 = NUMERO HEXADECIMAL
1 1 1 0 1 0 0 0 VALOR EN BINARIO
0x 7 F =
0 1 1 1 1 1 1 1
0x 9 C =
1 0 0 1 1 1 0 0
Ejemplos:
163 = 1 0 1 0 0 0 1 1
División
163/2 = 81 residuo = 1
81/2 = 40 residuo = 1
40/2 = 20 residuo = 0
20/2 = 10 residuo = 0
Los residuos se ordenan
10/2 = 5 residuo = 0 dese el ultimo hasta el
primero para formar el
valor en binario
5/2 = 2 residuo = 1
2/2 = 1 residuo = 0
1/2 = 0 residuo = 1
93 = 0 1 0 1 1 1 0 1
93/2 = 46 residuo = 1
46/2 = 23 residuo = 0
23/2 = 11 residuo = 1
11/2 = 5 residuo =1
5/2 = 2 residuo = 1
2/2 = 1 residuo = 0
1/2 = 0 residuo = 1
89 = 0 1 0 1 1 0 0 1
89/2 = 44 residuo = 1
44/2 = 22 residuo = 0
22/2 = 11 residuo = 0
11/2 = 5 residuo = 1
5/2 = 2 residuo = 1
2/2 = 1 residuo = 0
1/2 = 0 residuo = 1
Conversión
Para convertir de sistema numérico a maya primero tenemos que visualizar bien cuánto
vale cada uno de los símbolos por ejemplo una raya vale 5 y un punto vale 1 entonces si
hay una raya con 3 puntos sobre la raya entonces ese símbolo vale 8 una vez que se
saben los valores de los símbolos se ponen en forma vertical y se les asigna un numero
de posición empezando de cero hasta un numero cualquiera dependiendo de si base que
en este caso es 20 y estos valores se asignar empezando de abajo hacia arriba ya
identificada la posición de cada símbolo se hace una multiplicación que es el valor del
símbolo multiplicado por la base 20 elevada a la posición de símbolo uno vez realizada la
operación para cada uno de los símbolos se suman los resultados y el resultado de la
suma es el valor en sistema decimal.
Ejemplos:
ARITMÉTICOS
Se les conoce como operadores binarios ya que requieren de dos operandos se utilizan
para realizar cálculos y operaciones con números reales para obtener un resultado. Los
operadores aritméticos son la suma, resta, multiplicación, y división. En c se dispone de
un operador adicional que se denomina operador modulo (%) que permite obtener el resto
de una división entre enteros. los operadores aritméticos también cuentan con operadores
de incremento y de decremento en ellos se tienen acciones diferentes dependiendo de su
ubicación con respecto a la variable, si el operador precede a la variable se le conoce
como pre-incremento o pre-decremento y se dice que el operador está en su forma prefija
y si el operador es posterior a la variable este se encuentra en su forma posfija y se le
llama pos-incremento o pos-decremento según sea el caso. En el caso de que un
operador se preceda a su variable se realiza una operación de incremento o decremento
antes de utilizar el valor del operando y en el caso de que el operador este posterior a la
variable pasara lo contrario. Los operadores aritméticos son:
operador significado
= Asignación
- Resta
+ Suma
/ División
* Multiplicación
% Modulo (resto de la división)
-- Decremento
++ Incremento
Operador Significado
< Menor que
> Mayor que
== Igual a
!= Distinto de o no igual que
<= Menor o igual que
>= Mayor o igual que
Todos ellos son operadores binarios ya que utilizan dos operandos y dos de ellos son de
igualdad == y != que sirven para verificar la igualdad o desigualdad entre valores
aritméticos o punteros los dos operadores pueden comparar cierto tipos de punteros en
cambio el resto de los operadores relacionales no se pueden utilizar con ellos.
En las operaciones relacionales los operandos deben cumplir alguna de las reglas
siguientes: deben ser tipos aritméticos, son valores a versiones cualificadas o no
calificadas de tipos compatibles, uno de ellos es un puntero a un objeto, mientras que el
otro es un puntero a una versión cualificada o no cualificada de void y uno de los dos es
un valor, mientras que el otro es un valor nulo constante.
Los operadores lógicos producen un resultado booleano, y sus operandos son también
valores lógicos son asimilados a cierto o falso según su valor sea cero o distinto de cero
por el contrario las operaciones entre bits producen valores arbitrarios. Los operadores
lógicos en c son:
Operador Significado
&& Lógico AND
ll Lógico OR
! Negación Lógica
Los operadores lógicos son tres donde dos de ellos son binarios y uno de ellos (!) es
unario porque solo tiene un operando.
El operador “&&” equivale al “AND” este devuelve true (verdadero) sólo si los dos
operandos true o lo que es equivalente, distintas de cero. En cualquier otro caso el
resultado es false (falso).
El operador “||” equivale al “OR” este devuelve true si cualquiera de las expresiones
evaluadas es true, o distinta de cero, en caso contrario devuelve false.
Este operador se denomina también no lógico, el operador “!” es equivalente al “NOT”, o
“NO”, y este devuelve true cuando la operación evaluada es false o cero, en caso
contrario devuelve false.
La prioridad de estos operadores especifica el orden en que se realizan las operaciones
en las expresiones que contienen más de un operador. La asociatividad de los operadores
especifica si, en una expresión que contiene varios operadores con la misma prioridad, un
operando se agrupa con el de su izquierda o con el de su derecha.
Los operadores que tienen el mismo número de prioridad tienen la misma prioridad al
menos que se expresen mediante paréntesis.
Ejemplos:
Chr Binario Hex Decimal Chr Binario Hex Decimal Chr Binario Hex Decimal Chr Binario Hex Decimal
NUL 0000 0000 0x00 000 F 0100 0110 0x46 070 î 1000 1100 0x8C 140 ╠ 1100 1100 0xCC 204
SOH 0000 0001 0x01 001 G 0100 0111 0x47 071 ì 1000 1101 0x8D 141 ═ 1100 1101 0xCD 205
STX 0000 0010 0x02 002 H 0100 1000 0x48 072 Ä 1000 1110 0x8E 142 ╬ 1100 1110 0xCE 206
ETX 0000 0011 0x03 003 I 0100 1001 0x49 073 Å 1000 1111 0x8F 143 ¤ 1100 1111 0xCF 207
EOT 0000 0100 0x04 004 J 0100 1010 0x4A 074 É 1001 0000 0x90 144 ð 1101 0000 0xD0 208
ENQ 0000 0101 0x05 005 K 0100 1011 0x4B 075 æ 1001 0001 0x91 145 Ð 1101 0001 0xD1 209
ACK 0000 0110 0x06 006 L 0100 1100 0x4C 076 Æ 1001 0010 0x92 146 Ê 1101 0010 0xD2 210
BEL 0000 0111 0x07 007 M 0100 1101 0x4D 077 ô 1001 0011 0x93 147 Ë 1101 0011 0xD3 211
BS 0000 1000 0x08 008 N 0100 1110 0x4E 078 ö 1001 0100 0x94 148 È 1101 0100 0xD4 212
HT 0000 1001 0x09 009 O 0100 1111 0x4F 079 ò 1001 0101 0x95 149 I 1101 0101 0xD5 213
LF 0000 1010 0x0A 010 P 0101 0000 0x50 080 û 1001 0110 0x96 150 Í 1101 0110 0xD6 214
VT 0000 1011 0x0B 011 Q 0101 0001 0x51 081 ù 1001 0111 0x97 151 Î 1101 0111 0xD7 215
FF 0000 1100 0x0C 012 R 0101 0010 0x52 082 ÿ 1001 1000 0x98 152 Ï 1101 1000 0xD8 216
CR 0000 1101 0x0D 013 S 0101 0011 0x53 083 Ö 1001 1001 0x99 153 ┘ 1101 1001 0xD9 217
SO 0000 1110 0x0E 014 T 0101 0100 0x54 084 Ü 1001 1010 0x9A 154 ┌ 1101 1010 0xDA 218
SI 0000 1111 0x0F 015 U 0101 0101 0x55 085 ø 1001 1011 0x9B 155 █ 1101 1011 0xDB 219
DEL 0001 0000 0x10 016 V 0101 0110 0x56 086 £ 1001 1100 0x9C 156 ▄ 1101 1100 0xDC 220
DC1 0001 0001 0x11 017 W 0101 0111 0x57 087 Ø 1001 1101 0x9D 157 ¦ 1101 1101 0xDD 221
DC2 0001 0010 0x12 018 X 0101 1000 0x58 088 × 1001 1110 0x9E 158 Ì 1101 1110 0xDE 222
DC3 0001 0011 0x13 019 Y 0101 1001 0x59 089 ƒ 1001 1111 0x9F 159 ▀ 1101 1111 0xDF 223
DC4 0001 0100 0x14 020 Z 0101 1010 0x5A 090 á 1010 0000 0xA0 160 Ó 1110 0000 0xE0 224
NAK 0001 0101 0x15 021 [ 0101 1011 0x5B 091 í 1010 0001 0xA1 161 ß 1110 0001 0xE1 225
SYN 0001 0110 0x16 022 \ 0101 1100 0x5C 092 ó 1010 0010 0xA2 162 Ô 1110 0010 0xE2 226
ETB 0001 0111 0x17 023 ] 0101 1101 0x5D 093 ú 1010 0011 0xA3 163 Ò 1110 0011 0xE3 227
CAN 0001 1000 0x18 024 ^ 0101 1110 0x5E 094 ñ 1010 0100 0xA4 164 õ 1110 0100 0xE4 228
EM 0001 1001 0x19 025 _ 0101 1111 0x5F 095 Ñ 1010 0101 0xA5 165 Õ 1110 0101 0xE5 229
SUB 0001 1010 0x1A 026 ` 0110 0000 0x60 096 ª 1010 0110 0xA6 166 µ 1110 0110 0xE6 230
ESC 0001 1011 0x1B 027 a 0110 0001 0x61 097 º 1010 0111 0xA7 167 Þ 1110 0111 0xE7 231
FS 0001 1100 0x1C 028 b 0110 0010 0x62 090 ¿ 1010 1000 0xA8 168 Þ 1110 1000 0xE8 232
GS 0001 1101 0x1D 029 c 0110 0011 0x63 099 ® 1010 1001 0xA9 169 Ú 1110 1001 0xE9 233
RS 0001 1110 0x1E 030 d 0110 0100 0x64 100 ¬ 1010 1010 0xAA 170 Û 1110 1010 0xEA 234
US 0001 1111 0x1F 031 e 0110 0101 0x65 101 ½ 1010 1011 0xAB 171 Ù 1110 1011 0xEB 235
Space 0010 0000 0x20 032 f 0110 0110 0x66 102 ¼ 1010 1100 0xAC 172 ý 1110 1100 0xEC 236
! 0010 0001 0x21 033 g 0110 0111 0x67 103 ¡ 1010 1101 0xAD 173 Ý 1110 1101 0xED 237
" 0010 0010 0x22 034 h 0110 1000 0x68 104 « 1010 1110 0xAE 174 ¯ 1110 1110 0xEE 238
# 0010 0011 0x23 035 i 0110 1001 0x69 105 » 1010 1111 0xAF 175 ´ 1110 1111 0xEF 239
$ 0010 0100 0x24 036 j 0110 1010 0x6A 106 ░ 1011 0000 0xB0 176 - 1111 0000 0xF0 240
% 0010 0101 0x25 037 k 0110 1011 0x6B 107 ▒ 1011 0001 0xB1 177 ± 1111 0001 0xF1 241
& 0010 0110 0x26 038 l 0110 1100 0x6C 108 ▓ 1011 0010 0xB2 178 ‗ 1111 0010 0xF2 242
' 0010 0111 0x27 039 m 0110 1101 0x6D 109 │ 1011 0011 0xB3 179 ¾ 1111 0011 0xF3 243
( 0010 1000 0x28 040 n 0110 1110 0x6E 110 ┤ 1011 0100 0xB4 180 ¶ 1111 0100 0xF4 244
) 0010 1001 0x29 041 o 0110 1111 0x6F 111 § 1111 0101 0xF5 245
Á 1011 0101 0xB5 181
* 0010 1010 0x2A 042 p 0111 0000 0x70 112 ÷ 1111 0110 0xF6 246
 1011 0110 0xB6 182
+ 0010 1011 0x2B 043 q 0111 0001 0x71 113 ¸ 1111 0111 0xF7 247
À 1011 0111 0xB7 183
, 0010 1100 0x2C 044 r 0111 0010 0x72 114 ° 1111 1000 0xF8 248
© 1011 1000 0xB8 184
- 0010 1101 0x2D 045 s 0111 0011 0x73 115 ¨ 1111 1001 0xF9 249
. 0010 1110 0x2E 046 t 0111 0100 0x74 116 ╣ 1011 1001 0xB9 185
· 1111 1010 0xFA 250
/ 0010 1111 0x2F 047 u 0111 0101 0x75 117 ║ 1011 1010 0xBA 186
¹ 1111 1011 0xFB 251
0 0011 0000 0x30 048 v 0111 0110 0x76 118 ╗ 1011 1011 0xBB 187
³ 1111 1100 0xFC 252
1 0011 0001 0x31 049 w 0111 0111 0x77 119 ╝ 1011 1100 0xBC 188
² 1111 1101 0xFD 253
2 0011 0010 0x32 050 x 0111 1000 0x78 120 ¢ 1011 1101 0xBD 189 1111 1110 0xFE 254
■
3 0011 0011 0x33 051 y 0111 1001 0x79 121 ¥ 1011 1110 0xBE 190
nbsp 1111 1111 0xFF 255
4 0011 0100 0x34 052 z 0111 1010 0x7A 122 ┐ 1011 1111 0xBF 191
5 0011 0101 0x35 053 { 0111 1011 0x7B 123 └ 1100 0000 0xC0 192
6 0011 0110 0x36 054 | 0111 1100 0x7C 124 ┴ 1100 0001 0xC1 193
7 0011 0111 0x37 055 } 0111 1101 0x7D 125
┬ 1100 0010 0xC2 194
8 0011 1000 0x38 056 ~ 0111 1110 0x7E 126
9 0011 1001 0x39 057 DEL 0111 1111 0x7F 127 ├ 1100 0011 0xC3 195
: 0011 1010 0x3A 058 Ç 1000 0000 0x80 128 ─ 1100 0100 0xC4 196
; 0011 1011 0x3B 059 ü 1000 0001 0x81 129 ┼ 1100 0101 0xC5 197
< 0011 1100 0x3C 060 é 1000 0010 0x82 130
ã 1100 0110 0xC6 198
= 0011 1101 0x3D 061 â 1000 0011 0x83 131
à 1100 0111 0xC7 199
> 0011 1110 0x3E 062 ä 1000 0100 0x84 132
╚ 1100 1000 0xC8 200
? 0011 1111 0x3F 063 à 1000 0101 0x85 133
╔ 1100 1001 0xC9 201
@ 0100 0000 0x40 064 å 1000 0110 0x86 134
A 0100 0001 0x41 065 ç 1000 0111 0x87 135 ╩ 1100 1010 0xCA 202
B 0100 0010 0x42 066 ê 1000 1000 0x88 136 ╦ 1100 1011 0xCB 203
C 0100 0011 0x43 067 ë 1000 1001 0x89 137
D 0100 0100 0x44 068 è 1000 1010 0x8A 138
E 0100 0101 0x45 069 ï 1000 1011 0x8B 139
Teoría
Una integral es una acción de la suma de infinitos sumandos, infinitamente
pequeños. La integral definida de una función representa el área limitada por la
gráfica de la función, en un sistema de coordenadas cartesianas con signo positivo
cuando la función toma valores positivos y signo negativo cuando toma valores
negativos. Dada una función f(x) de una variable real x y un intervalo [a, b] de
la recta real, la integral es igual al área de la región del plano x, y limitada entre
la gráfica de f, el eje x, y las líneas verticales x=a y x=b, donde son negativas las
áreas por debajo del eje x.
Sea una función f: [a, b]=R, es decir, definida en un intervalo. Supongamos que es
positiva, es decir, que f(x) ≥ 0 (su gráfica está por encima del eje de abscisas).
Entonces, la integral definida representa el área encerrada entre la gráfica de f y el
eje de abscisas entre las rectas x=a y x=b.
Teoría
Una integral es una acción de la suma de infinitos sumandos, infinitamente pequeños. La
integral definida de una función representa el área limitada por la gráfica de la función, en un
sistema de coordenadas cartesianas con signo positivo cuando la función toma valores positivos
y signo negativo cuando toma valores negativos. Dada una función f(x) de una variable real x y
un intervalo [a, b] de la recta real, la integral es igual al área de la región del plano x, y limitada
entre la gráfica de f, el eje x, y las líneas verticales x=a y x=b, donde son negativas las áreas por
debajo del eje x.
Sea una función f: [a, b]=R, es decir, definida en un intervalo. Supongamos que es positiva, es
decir, que f(x) ≥ 0 (su gráfica está por encima del eje de abscisas). Entonces, la integral definida
representa el área encerrada entre la gráfica de f y el eje de abscisas entre las rectas x=a y x=b.
Si una función tiene una integral, se dice que es integrable. De la función de la cual se calcula la
integral se dice que es el integrando. Se denomina dominio de integración a la región sobre la
cual se integra la función. Si la integral no tiene un dominio de integración, se considera indefinida
(la que tiene dominio se considera definida). En general, el integrando puede ser una función de
más de una variable, y el dominio de integración puede ser un área, un volumen, una región de
dimensión superior, o incluso un espacio abstracto que no tiene estructura geométrica en ningún
sentido usual. El caso más sencillo, la integral de una función real f de una variable real x sobre
el intervalo [a, b]
𝑏
∫ 𝑓(𝑥)𝑑𝑥
𝑎
Código C+
Diagrama de flujo
Resultados de wolfram alpha