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Aim- Designing of 4 Bit Adder cum Subtractor using Gate Level Modelling Style.
Theory-
Full Adder:
A full adder adds binary numbers and accounts for values carried in as well
as out. A one-bit full-adder adds three one-bit numbers, often written as A, B,
and Cin , A and B are the operands, and Cin is a bit carried in from the previous
less-significant stage.
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full Subtractor:
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
D= X⊕Y⊕Bin
BOUT = X'Bin+X'Y+YBin
Circuit Diagram of Full Subtractor :
XOR gate:
Below the figure shows the symbol of xor gate with A and B as inputs and Q
as output. And Truth table is for the same is also given below.
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
So we can see from the truth table dat if we hold the one input of XOR gate
to be 1 then it can act as not gate if the second input is 0. And if the hold the
first input to 0 then it acts as a buffer passing on the second input as it is. So
this logic can be used to build a adder subtractor circuit.
Ripple Carry Adder:
Now that we have learnt how about all the basic things that are required for
an adder subtractor circuit. We will design a adder subtractor circuit using
these only.
Ci
Cout
Verilog Code:
//—————————test bench—————————
module addsubtb();
reg [3:0]a,b;
reg cin,sel;
wire [3:0]sum;
wire cout;
addsub_4 a5 (cout,sum,a,b,cin,sel);
initial
begin
a=4'b0000;b=4'b0000;cin=1;sel=0;
#5 a=4'b0001;b=4'b1101;cin=1;sel=0;
#5 a=4'b1110;b=4'b1111;cin=0;sel=0;
#5 a=4'b1110;b=4'b0110;cin=1;sel=0;
#5 a=4'b1010;b=4'b1111;cin=0;sel=1;
#5 a=4'b1100;b=4'b0011;cin=0;sel=1;
#5 a=4'b1001;b=4'b0011;cin=1;sel=1;
#10 $stop;
end
endmodule
Results: