Teaching Plan

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

UNIVERSITI MALAYSIA PERLIS

DIGITAL ELECTRONICS 1

EKT 124 SEMESTER 2 SESSION 2017/2018

This course is intended to cover the introduction and discussion

of the fundamental of digital circuit design and analysis. The
lecturer covers the following topics: Boolean Algebra,
SYNOPSIS
Numbering System, Basic Logic Gates, Combinational Circuit
Design, Timing Diagram, Bi-Stable Memory Device and
Sequential Circuit Design.
CO1: Ability to apply the knowledge of different NUMBERING
SYSTEMS and to understand basic THEORY of BINARY
SYSTEM.
COURSE CO2: Ability to apply method of MINIMIZING BOOLEAN
OUTCOME (CO) FUNCTIONS for digital logic circuit.
CO3: Ability to solve and design COMBINATIONAL LOGIC
circuit in terms of Boolean Function.
CO4: Ability to solve and design SEQUENTIAL LOGIC circuit
in terms of Boolean Function.

TEXT BOOK/ 1. Floyd. TL, “Digital Fundamentals”, 11th edition,

REFERENCE Prentice Hall
BOOK 2. Tocci.

TEACHING STAFF RK20 – Pn Aznor Hanah Abdul Halim (aznor@unimap.edu.my)

RK53 – Dr Nur Hafizah Ghazali (hafizahghazali@unimap.edu.my)
RK93 – Dr Yasmin Yacob (yasmin.yacob@unimap.edu.my)

ASSESSMENT

(i) Examination: 70%

Mid Term Exam : 10%
Final Examination : 60%

(ii) Course work: 30%

Centralized Quiz : 10%
Quizzes : 10%
Assignments : 10% (Technical Report of Combinational and Sequential Design)

School of Computer and Communication Engineering (SCCE)

Universiti Malaysia Perlis 1 /4
 TEACHING PLAN GUIDE
Week Topic and Sub Topic Assessment Remarks

INTRODUCTION TO DIGITAL LOGIC

Numbering System
1  Numbering system and base conversion. 16&17 Feb -
(12-16 Feb  1’s and 2’s complement of binary number. CNY
2018)
 Signed number.
 Arithmetic operation with signed numbers
 Codes (BCD, ASCII, and Gray).

Arithmetic
2  Binary arithmetic. Lab1: Intro to Quartus
(19-23 Feb  2’s complement representation and arithmetic. II
2018)  Hexadecimal arithmetic.
 BCD arithmetic.

Algebra Switching
 Boolean operations and expressions.
 Law and rules of Boolean algebra.
 Basic logic gates.
3  Boolean algebra:
(26 Feb – 2
March 2018) o De Morgan’s Theorem.
o Boolean analysis of logic circuit.
o Simplification using Boolean algebra.
o Standard forms of Boolean expression (Sum of
Product and Product of Sum).
o Boolean expressions and truth table.

Boolean Function
4  The Karnaugh map (K-map).
(5-9 March
 K-map SOP and POS minimization.
2018)
 5-variable K-map.

COMBINATIONAL LOGIC DESIGN

5 Arithmetic Mid Term Exam

(12-16 March  Arithmetic circuits. ** to be confirmed
2018)
 Adder.
 Subtractor.
 System design and application.

School of Computer and Communication Engineering (SCCE)

Universiti Malaysia Perlis 2 /4
 Week Topic and Sub Topic Activities Remarks

COMBINATIONAL LOGIC DESIGN

6 Converter
(19-23 March  Comparator.
2018)
 Encoder.
 Decoder.
 Code converter.

7 COMBINATIONAL LOGIC DESIGN

(26-30 March Lab 2: Combinational
2018) Multiplexer and demultiplexer Logic Design
 Selectors

(2 – 8 April
MID SEMESTER BREAK
2018)

8 COMBINATIONAL LOGIC DESIGN

(9-13 Apr
2018)
Party generator and checker

SEQUENTIAL LOGIC DESIGN Israk Mikraj

9 14 Apr 2018
(16-20 Apr Latches and flip-flop (Saturday)
2018)
 Latches.
 Edge triggered flip-flop.

SEQUENTIAL LOGIC DESIGN

10 Latches and flip-flop (cont.)

(23-27 Apr  Latches. Lab 3: Sequential
2018) Logic Design
 Edge triggered flip-flop.
 Master slave flip-flop.
 Flip-flop operating characteristic and operations.

SEQUENTIAL LOGIC DESIGN Labour Day

1/5/2018
11 Shift register (Tuesday)
(30 Apr – 4  Basic shift register function.
May 2018)
 Serial in/ serial out shift register.
 Serial in/ parallel out shift register.

SEQUENTIAL LOGIC DESIGN

12 Shift register (cont.)

CENTRALIZED QUIZ
(7-11 May  Parallel in/ serial out shift register.
2018)
 Parallel in/ parallel out shift register. **to be confirmed
 Bidirectional shift register.
 Shift register application.

School of Computer and Communication Engineering (SCCE)

Universiti Malaysia Perlis 3 /4
 Week Topic and Sub Topic Activities Remarks

SEQUENTIAL LOGIC DESIGN **Awal

13 Ramadhan
(14-18 May Counter 17/5/2018
2018)  Asynchronous counter operation. (Thursday)
 Synchronous counter operation.
 Up/ down synchronous counter.

SEQUENTIAL LOGIC DESIGN

Counter (cont.)
14
(21-25 May  Design of synchronous counter.
2018)  Cascaded counter.
 Counter decoding.
 Counter application.

15
(28 May – 1 STUDY WEEK
June 2018)

16-18
(4 – 22 June FINAL EXAMINATION
2018)

School of Computer and Communication Engineering (SCCE)

Universiti Malaysia Perlis 4 /4