2/5/2018 Lab

Lab 4 - ECE 421L 

Authored by Michael Kajkowski,
9/23/2014
kajkowsk@unlv.nevada.edu 
 
 Introduction:
For this lab we will be creating NMOS and PMOS transistors using Cadence. We will first make four schematics: nmos3, nmos4,
pmos3, & pmos4.
For the nmos3 we will simulate the ID vs VDS curves (ID vs VSD for the pmos3) and for the nmos4 we will simulate the ID vs VGS
curve (ID vs VSG for the pmos4). Finally, we will then create a layout (with corresponding schematic views) for an nmos4 and a
pmos4, ensuring that both pass DRC and LVS.
 
PART I:
  
Three Terminal NMOS Transistor & Simulation:
We start  with a new library called mk_lab4. We create a new cell/schematic called sim_nmos_ID_VDS. We then want to place a 3
terminal nmos transistor. Here is the component to use:

 
 Notice that the width is 6 microns and the length is .6 microns.
  
 You then need to place two voltage sources on to the schematic. Here is what your finished schematic should like:

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 We set the VGS variable to zero and V1 to zero (Be sure to save and check).
  
Now that we have the schematic completed, we can now start by simulating the ID vs VDS curves.
 Launch the ADE L and goto Setup => Model Libraries.  To ensure we use the correct model for the nmos simulations, make sure to
match the window as seen below (pay attention to the file path):

 Note that we will do the same for pmos except we use ami06P
  
Next we need click Variables => Edit, we then add the variable VGS and make it equal to zero. Then click Analyses => Choose.
Here are the two windows for editing the VGS variable and choosing analyses:

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Notice that we are using dc analysis, the component name is V1 (VDS), and we will sweep VDS from 0 to 5 volts with 1mV steps.
Also, we need to select the Drain terminal of the NMOS as our input. 
   
Here is what your ADE window should look like:

  
Finally, goto Tools => Parametric Analysis. This will allow us to sweep VGS from 0 to 5 volts. The following window will appear:

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 Hit the green play button and wait for the simulation window to load.
 
Here is the simulation that you should see:

  
 Four Terminal NMOS Transistor & Simulation:
The process for this section is the same as the previous section except we will be using a four terminal NMOS (nmos4) and we will
 be simulating the ID vs VGS curve.
  
 Here is the completed schematic that you should get:

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 Notice that we set V1 with the variable VDS (which will be set to 100mV), V0 (VGS) is set to zero, and the bulk is connected to
ground.
The procedure for setting up the simulation is similar to the first one except we will only be sweeping VGS (0 to 2 volts with 1mV
steps), VDS will be constant. So after we select the dc analysis, we simplyhit the play button in the ADE window. (Note that the
output remains the same).
  
Here is the simulation:

  
 Three Terminal PMOS Transistor & Simulation:
   
Here is the schematic that you should construct:

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Note that we are using a pmos part with W=12 microns and L=.6 microns. Also, V1 is assigned the variable VSG (which is set to zero),
V0 is VDS (which is set to zero), and V2 is VDD. Recall, that the NMOS required connecting the source to ground. In the PMOS
flavor we typically set the source to VDD. 
  
In order to properly simulate this schematic we need to make sure to use the ami06P model (as seen earlier in this lab).
  
 We will follow the same procedure as the three terminal NMOS, except we will simulate ID vs VSD. Our variable will be VSG with a
value of zero. We will sweep VSD from 0 to 5 volts with 1mV steps. VSG will sweep from 0 to 5 volts. And the output will be the
source.
Here is the simulation:

 
  
Four Terminal PMOS Transistor & Simulation:
  
 Here is the schematic that you should construct:

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 Notice that we are using a four terminal PMOS. The Bulk is connected to the source (VDD). Also, V0 is assigned the variable VSD
with a value of 100mV. And V1 (VSG) is set to zero. 
 
 To simulate this schematic we sweep VSG from 0 to 2 volts with 1mV steps. The output is the source.
  
 Here is the simulation:

  PART II:

 Four Terminal NMOS Layout:

 We first need to create a new cell that will have a layout and schematic views. 
 Open the layout view and create instance (I). Select the NCSU_TechLib_ami06 library, and then select the nmos4 part. The
widthwill be 6 microns and the length will be .6 microns. 
 
 Here is what the completed layout should look like:

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  In this layout we added a ptap contact below the source terminal and assigned a pin called gnd!. We also added an M1_poly contact
at the top. 
We place metal 1 rectangles across the source and drain and then we assign the appropriate pin names to them. Finally, we add a poly
rectangle, connecting the gate with the M1_poly contact, again assigning the proper pin name. 
Notice that the layout passes DRC.
    
 In order to perform a LVS check, we create a simple NMOS schematic/symbol:
   

  

Make sure to use the same pin names as the layout and to connect bulk to gnd!.
  
We then extract the layout and perform a LVS check:

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Notice that LVS was successful.

 
 Four Terminal PMOS Layout:

 We create a new cell with a layout and schematic view.  

Open the layout view and place a pmos4 part with width=12 microns & length=.6 microns.

Here is the completed layout:

  
In this layout we added a ntap contact above the drain terminal and assigned a pin called B (the bulk). We also added an M1_poly
contact at the bottom. We place metal 1 rectangles across the source and drain and then we assign the appropriate pin names to
them. Finally, we add a poly rectangle, connecting the gate with the M1_poly contact, again assigning the proper pin name. 
Notice that the layout passes DRC.
 
 Here is the schematic view with matching pin names:

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 Finally, we extract the layout and perform a LVS check:

 LVS Passes!
  
  
  
 Now let's connect the layouts to Probe Pads.
 The probe pad is a square of metal 3 with over glass. This is what we will use for both the NMOS and PMOS layouts. We will also
incorporate a probe pad connections in the schematics. This will allow us to perform LVS verification. 
  
Here is the schematic and layout for the NMOS:

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 Here is the schematic and layout of for the PMOS:

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THIS CONCLUDES LAB 4.

WE NOW KNOW HOW TO PROPERLY SIMULATE THE ID VS VDS/VSD & ID VS VGS/VSG CURVES  FOR BOTH NMOS &
PMOS TRANSISTORS. WE ALSO NOW KNOW HOW TO PROPERLY CREATE NMOS/PMOS LAYOUTS & to properly connect
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them to a probe pad.

  
Here is my lab 4 directory: mk_lab4.zip
          
MAKE SURE TO BACK UP ALL OF YOUR LAB 4 CONTENTS 
(zip and email your work to yourself).

     
Return to EE421L Labs
    

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