Sun Square Technologies

IEEE PROJECTS FOR VERY-LARGE-SCALE INTEGRATION AND

COMMUNICATION

S.NO PROJECT NAME YEAR DOMAIN NAME

1 A 520k (18 900, 17 010) Array Dispersion 2017-18 VLSI
LDPC
Decoder Architectures for NAND Flash
Memory
2 A Fixed-Point Squaring Algorithm Using an 2017-18 VLSI
Implicit Arbitrary Radix Number System
3 A Hybrid Frequency/Phase-Locked Loop for 2017-18 VLSI
Versatile Clock Generation with
Wide Reference Frequency Range
4 A Method to Design Single Error Correction 2017-18 VLSI
CodesWith Fast Decoding for a Subset of
Critical Bits
5 A Mixed-Decimation MDF Architecture 2017-18 VLSI
for Radix-2k Parallel FFT
6 A Modified Partial Product Generator for 2017-18 VLSI
Redundant Binary Multipliers
7 A Test-per-Cycle BIST Architecture with Low 2017-18 VLSI
Area Overhead andNo Storage Requirement
8 An Efficient Hardware Implementation of 2017-18 VLSI
CannyEdge Detection Algorithm
9 An Efficient Single and Double-Adjacent Error 2017-18 VLSI
Correcting Parallel Decoderfor the (24,12)
Extended Golay Code
10 An Improved Signed Digit Representation 2017-18 VLSI
Approach for Constant Vector Multiplication
11 Area-Delay Efficient Digit-Serial Multiplier 2017-18 VLSI
Based
on k-Partitioning Scheme Combined With
TMVP Block Recombination Approach
12 Code Compression for Embedded Systems 2017-18 VLSI
Using Separated Dictionaries
13 Concept, Design, and Implementation of 2017-18 VLSI
Reconfigurable CORDIC
14 Design Methodology for Voltage-Scaled 2017-18 VLSI
Clock Distribution Networks
15 Efficient Implementation of Scan Register 2017-18 VLSI
Insertionon Integer Arithmetic Cores for
FPGAs
16-3-245, 3rd floor, Trendset Towers, Opp: HDFC Bank, Anoos Upstairs, Ramalingapuram
Main Road, Nellore-524 001. Cell: 8179898924, 7075909312,
E-Mail: sunsquareliveprojects@gmail.com
 Sun Square Technologies
16 Enhanced Built-In Self-Repair Techniques for 2017-18 VLSI
Improving Fabrication Yield and Reliability
of Embedded Memories
17 Floating-Point Butterfly Architecture Based on 2017-18 VLSI
Binary Signed-Digit Representation
18 High-Performance Pipelined Architecture of 2017-18 VLSI
Elliptic
Curve Scalar Multiplication Over GF(2m)
19 Improving the Realization of Multiple-Control 2017-18 VLSI
Toffoli
Gates Using the NCVW Quantum Gate Library
20 Logic Synthesis in Reversible PLA 2017-18 VLSI
21 Low-Power FPGA Design Using 2017-18 VLSI
Memoization-Based Approximate Computing
22 Low-Power Split-Radix FFT Processors Using 2017-18 VLSI
Radix-2 Butterfly Units
23 LUT Optimization for Distributed Arithmetic- 2017-18 VLSI
Based
Block Least Mean Square Adaptive Filter
24 On Efficient Retiming of Fixed-Point Circuits 2017-18 VLSI
25 Path Constraint Solving based Test Generation 2017-18 VLSI
forObservability-enhanced Branch Coverage
26 Scalable Approach for Power Droop Reduction 2017-18 VLSI
During Scan-Based Logic BIST
27 Self-Repairing Digital System Based on State 2017-18 VLSI
Attractor Convergence Inspired by the
Recovery Process of a Living Cell
28 Source Code Error Detection in High-Level 2017-18 VLSI
Synthesis Functional Verification
29 Squaring in Reversible Logic using Zero 2017-18 VLSI
Garbage and Reduced Ancillary inputs
30 Using Tweaks To Design Fault Resistant 2017-18 VLSI
Ciphers
2017-18
31 A High Throughput List Decoder Architecture 2017-18 VLSI
for Polar Codes
32 Design and Analysis of Inexact 2017-18 VLSI
Floating-Point Adders
33 Floating-Point Butterfly Architecture Based on 2017-18 VLSI
Binary Signed-Digit Representation
34 Hardware and Energy-Efficient Stochastic 2017-18 VLSI
LU Decomposition Scheme for MIMO
Receivers

16-3-245, 3rd floor, Trendset Towers, Opp: HDFC Bank, Anoos Upstairs, Ramalingapuram
Main Road, Nellore-524 001. Cell: 8179898924, 7075909312,
E-Mail: sunsquareliveprojects@gmail.com
 Sun Square Technologies
35 Hybrid LUT/Multiplexer FPGA Logic 2017-18 VLSI
Architectures
36 Low-Power Parallel Chien Search Architecture 2017-18 VLSI
Using a Two-Step Approach
37 Memory-Reduced Turbo Decoding 2017-18 VLSI
Architecture Using NII Metric Compression
38 Multiple Constant Multiplication Algorithm 2017-18 VLSI
for High-Speed and Low-Power Design
39 Pre-Encoded Multipliers Based on 2017-18 VLSI
Non-Redundant Radix-4 Signed-Digit
Encoding
40 VLSI Design for Convolutive Blind 2017-18 VLSI
Source Separation
1 A 5.8-GHz Wideband TSPC Divide-by-16/17 2017-18 VLSI
Dual Modulus Prescaler
2 A Generalization of Addition Chains and Fast 2017-18 VLSI
Inversions in Binary Fields
3 A Generalized Algorithm and Reconfigurable 2017-18 VLSI
Architecture for Efficient and Scalable
Orthogonal
Approximation of DCT
4 A High-Performance FIR Filter Architecture 2017-18 VLSI
forFixed and Reconfigurable Applications
5 A Low-Power Hybrid RO PUF With Improved 2017-18 VLSI
Thermal Stability for Lightweight Applications
6 A parallel radix-sort-based VLSI architecture 2017-18 VLSI
forfinding the first W maximum/minimum
values
7 Aging-Aware Reliable Multiplier Design With 2017-18 VLSI
Adaptive Hold Logic
8 An Accuracy-Adjustment Fixed-Width Booth 2017-18 VLSI
Multiplier Based on Multilevel Conditional
Probability
9 Area–Delay–Power Efficient Carry-Select 2017-18 VLSI
Adder
10 Design and Analysis of Approximate 2017-18 VLSI
Compressors for Multiplication

16-3-245, 3rd floor, Trendset Towers, Opp: HDFC Bank, Anoos Upstairs, Ramalingapuram
Main Road, Nellore-524 001. Cell: 8179898924, 7075909312,
E-Mail: sunsquareliveprojects@gmail.com