Analog Integr Circ Sig Process (2015) 82:217–227
DOI 10.1007/s10470-014-0464-0
High performance folded cascode OTA using positive feedback
and recycling structure
Meysam Akbari • Sadegh Biabanifard •
Shahrouz Asadi • Mustapha C. E. Yagoub
Received: 8 February 2014 / Revised: 16 September 2014 / Accepted: 28 November 2014 / Published online: 10 December 2014
Ó Springer Science+Business Media New York 2014
Abstract In this paper, a new technique for enhancing
the transconductance and low frequency output impedance
of recycling folded cascode amplifiers is presented. These
improvements were achieved by using a positive feedback
and upgrading the recycling structure. The new structure
benifits from better transconductance, slew rate, and DC
gain in comparison to conventional folded cascode (FC)
amplifier. Moreover, the input referred noise and input
offset are reduced and the phase-margin is improved. The
improved amplifier is simulated in 0.18 lm CMOS tech-
nology, demonstrates a DC gain enhancement of 16.4 dB
as well as 117.5 MHz increase in gain bandwidth com-
pared with conventional FC configuration. The amplifier
consumes 360 lW @ 1.2 V which makes it appropriate for
low-voltage applications.
Keywords Recycling structure  Folded cascode 
Positive feedback  Transconductance
M. Akbari  S. Biabanifard (&)
Microelectronic Lab, Shahid Beheshti University, G. C., Tehran,
Iran
e-mail: s.biabanifard@mail.sbu.ac.ir
M. Akbari
e-mail: Mey.akbari@yahoo.com
S. Asadi
Department of Communication Engineering, Shahid Beheshti
University, G. C., Tehran, Iran
e-mail: sh_asadi@sbu.ac.ir
M. C. E. Yagoub
School of Electrical Engineering and Computer Science,
University of Ottawa, Ottawa, ON, Canada
e-mail: myagoub@eecs.uottawa.ca
1 Introduction
The advancement of CMOS technologies has improved the
growing market of mobile and portable electronic devices.
This is achieved by the continual integration of complex
analog and digital building blocks on a single chip. As a
result, silicon area and power consumption have emerged
as key parameters to consider for successful design [1, 2].
Because of their high gain and speed, folded cascode
(FC) operational transconductance amplifiers (OTAs) play
a key role in many analog systems. However, their large
die area and high power consumption limit their use in
mobile and portable systems [3]. With its higher gain and
bandwidth over conventional FC amplifier, the recycling
folded cascode (RFC) configuration was introduced to
address these issues. However, the RFC amplifier has an
extra pole-zero pair which leads to degeneration in the
phase-margin [4–6]. Recent works on RFC include phase-
margin network [7, 8], positive feedback [9, 10], or extra
current sources [11] to enhance performance of RFC
amplifiers. In the two last approaches, the transconductance
is increased without consuming extra power. However, the
improvement in transconductance is counterbalanced by a
serious degradation in the phase-margin, leading to sta-
bility problems in the amplifier. The double recycling
technique uses extra shunt current sources added to the
input stage to recycle the bias current once again [11, 12].
In addition, the positive feedback can be used for
increasing the output impedance, leading to boosted
transconductance and low frequency output impedance
[10–13].
In this paper, an enhanced low-voltage RFC amplifier
with a high-speed current mirror is presented. It presents an
improved transconductance, DC gain, slew rate and phase-
margin over existing RFC circuits. Also, the input referred
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218 Analog Integr Circ Sig Process (2015) 82:217–227

noise is reduced through a transconductance boosting. The

paper is organized as follows. In Sect. 2, a brief description
M9 M10
of recycling FC amplifiers is presented. Then in Sect. 3, a CMFB M0
V3

theoretical analysis is given for transconductance, DC gain, 2I

(k-1)I/2

phase-margin, slew rate, noise, offset and common mode

rejection ratio (CMRR). Simulation results and conclusion Vin+ Vin- M7
V2
M8

are presented in the last section. Ma1 Mb1 Mb2 Ma2

Vout- Vout+

CL CL

2 Conventional recycling structure

M11 M12 M5 M6
V1 V1

Conventional configurations of FC and RFC amplifiers are

shown in Figs. 1 and 2, respectively. Compared with FC,
RFC amplifier exploits M3 and M4 as driving transistors Ma3 Mb3 Mb4 Ma4
[2, 5]. In addition, input drivers (M1, M2) are separated
K : 1 1 : K
into Ma1, Ma2 and Mb1, Mb2, with equal current flow of I/
2 (Fig. 2). Also, the cross-over connections of current
mirrors Ma3:Mb3 and Ma4:Mb4 ensure that the small Fig. 2 Schematic of recycling folded cascode amplifier
signal current is intensified by a ratio factor k. Therefore,
the operative transconductance (Gm) of the RFC can be 3 Architecture of the proposed RFC amplifier
expressed as (1)
GmRFC ¼ gma1 ð1 þ kÞ ð1Þ The proposed recycling folded cascode (PRFC) amplifier is
shown in Fig. 3. Note that transistors M9 and M10 conduct
Despite the fact that the gain bandwidth (GBW) product
a large current value; thus, can demonstrate large trans-
is boosted due to transconductance improvement, the
conductance. Therefore, Besides the Ma3 and Ma4 in RFC,
phase-margin is degenerated by the large value of k ratio.
M9 and M10 in PRFC are involved in input drive. In order
In other words, enhancement in transconductance is con-
to exploit M9 and M10 as driving transistors, the cross-
fined by phase-margin degradation. Usually, a value k = 3
over connections of current mirrors Mb3:M9 and
allows maintaining the power budget unchanged. Thus, the
Mb4:M10 ensure that the small signal current is intensified
transconductance of the RFC is twice that of the FC, and
by a ratio factor (k - 1) (the signal being injected into the
consequently twice the GBW [4, 6].
gate of M9 and M10 through these current mirrors).
Finally, M11 and M12 maintain equal drain potentials
across Ma3:Mb3 and Ma4:Mb4 for improved matching.
These modifications provide the PRFC with improved
features over that of FC and RFC.
In order to quantitatively present these enhancements,
M9 M10
CMFB M0 V3 all devices are assumed to operate in the strong inversion
I
region following the simplified square-law drain current
2I
model expressed by
M7 M8 1 W
V2 Id ¼ lCox ðVGS  Vth Þ2 ð2Þ
Vin+ Vin- 2 L
M1 M2
Vout- Vout+
Here all symbols have their usual meanings [1, 2].
CL CL

3.1 Small signal transconductance

M5 M6
V1
The amplifier’s transconductance (Gm) is obtained by
calculating the short-circuit current at the output with
regards to the input. Because M1 is twice the size of Ma1,
M3 M4
V4 it conducts twice current, thus gm1 = 2gma1. Also, the
current gain k shown in Fig. 3 is selected equal to 3 to keep
same power consumption and area. Therefore, the PRFC
Fig. 1 Schematic of conventional folded cascode amplifier has 150 and 50 % improvement in transconductance

123
Analog Integr Circ Sig Process (2015) 82:217–227 219

1 : (K-1)
M9
1 : (K-1)
CMFB M0 M10
(k-1)I/2
2I C

M7 M8
Vin+ Vin-
Ma1 Mb1 Mb2 Ma2 Vout- Vout+

CL CL
A
M11 M12 M5 M6
V1 V1
B

R R
Ma3 Mb3 Mb4 Ma4
K : 1 1 : K

Fig. 3 Schematic of proposed recycling folded cascode amplifier

Fig. 4 The proposed amplifier AC model

compared with the FC and RFC, respectively. Also, for the
same amount of power, the PRFC gain-bandwidth (GBW)
product is increased by a factor of 3 compared with that of
the FC. However, this will affect the amplifier power
supply rejection ratio (PSRR). Small signal transconduc-
tance for FC and PRFC are expressed in (3) and (4).
GmFC ¼ gm1
GmPRFC ¼ gma1 ð2kÞ
3.2 DC gain
The DC gain of transconductance amplifiers is usually
described as the product of the small signal transconduc-
tance, Gm, with the low frequency output impedance, Rout
[2]. Thus, enhancing transconductance and increasing the
output impedance should boost the DC gain. The AC
model of the proposed amplifier is shown in Fig. 4. Where
Cb1, Cb2 and Cb3 are respectively the parasitic capaci-
tances in drain node of transistor Mb1/Mb2, source node of
M6/M5 and source node of M7/M8. Also, gm and go are
obtained from the DC biasing conditions.
As shown in Fig. 3, the positive feedback structure in
the PRFC amplifier is created by connecting the gate ter-
minal of cascode transistors M7 and M8 to the folded
nodes. In fact, in order to make positive feedback (i.e.,
ð3Þ phase difference of 180°), the gates of M7 and M8 need to
be connected to folded nodes, almost double the output
ð4Þ impedance. However, this will affect the amplifier linearity
and output voltage swing. It should be noted that the
positive feedback used in this paper is different from the
ones in [9, 13]. Indeed, in those feedback structures, the
stability criteria should be checked out while in the pro-
posed structure, the output impedance is always positive
(because the currents of M5–M8 are all the same), thus
leading to a stable circuit.
The low frequency output impedance of the PRFC was
demonstrated to be twice that of the FC for almost the same
power consumption. It was assumed that transistors M6

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220 Analog Integr Circ Sig Process (2015) 82:217–227

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
and M8 have similar small signal features including output
gmb4 CL
impedance and transconductance along with goa4 & go10 kPRFC  ð9Þ
12gma1 Cgsb4
and goa4  goa2. Therefore, the low frequency output
impedance of PRFC amplifier can be expressed as (5) However, as the ratio k of the current mirror becomes
 2 larger, the first non-dominant pole will move toward lower
gm8 þ gmb8 þ go10 þ go8
go8 go10
frequency. It leads to phase-margin degradation in the
RoutPRFC ¼   ð5Þ PRFC and thus, unstable behavior in the closed-loop.
gm8 þ gmb8 þ 2go10 þ 2go8
go8 go10 Though, when compared with the FC amplifier, the phase-
margin of the PRFC still degrade by 14°–16°, which is a
By assuming ðgm8 þ gmb8 Þ  ðgo8 þ go10 Þ, (5) can be
disadvantage regarding stability. To overcome this prob-
simplified to
lem, a compensator resistor R was added between the gates
gm8 þ gmb8 þ go8 þ go10 of the current mirror as reported in [7, 8]. Note that, at the
RoutPRFC  ð6Þ
go8 go10 difference with [7], M9 and M10 are used as drivers to
Also GmPRFC = 3GmFC results in a 10 dB gain increase the transconductance.
enhancement for the same output impedance. Therefore, an According to Fig. 5, the transfer function of the high-
overall low frequency gain enhancement of 15–17 dB can speed current mirror is described as
 
be expected for the PRFC compared with the FC config- ðgma4 þ gm10 Þ S þ RCgs1
Ia4 ðSÞ þ I10 ðSÞ b4
uration. The open loop DC gain can be obtained directly HðsÞ ¼ ¼ gmb4
from the circuit of Fig. 4 by eliminating the parasitic Ib4 ðSÞ ð2k  1ÞCgsb4 S2 þ 2k
R S þ RCgsb4
capacitances. It is given by: ð10Þ

gma1 þ gm b1
ðgma4 þ gm10 Þ This equation has one additional zero, given by
Ad   gmb4  ¼ 2kgma1 ðRoutÞ ð7Þ 1
go8 go10
gm8 þ gmb8 þ go8 þ go10 xz2 ¼  ð11Þ
RCgsb4
3.3 Phase-margin Also, the new first non-dominant pole of the PRFC is
transposed as,
The transient response of an amplifier can be evaluated by the gmb4
phase margin. For clarity, let us assume that ln ¼ 3lp , Ln ¼ x0p2 ¼  ð12Þ
pffiffiffi pffiffiffi kCgsb4
3Lp and Wp ¼ 3Wn and that Cgsn = Cgsp where lP, ln,
The addition of a zero makes the system faster but more
LP, Ln, Wp and Wn are carrier mobility, channel length and
susceptible to oscillate as the zero moves in the negative
width of transistors M9 and Mb3 in equal bias conditions,
axis toward the origin. The value of R can be chosen in a
respectively. By applying the Laplace transform, consider-
way such that the described zero and pole cancel each other
ing pole separation and ignoring the parasitic capacitances at
x0p2 ¼ xz2
the other nodes, the circuit of Fig. 4 shows that the PRFC
amplifier has three non-dominant poles and two zeros. k
R¼ ð13Þ
According to Figs. 3 and 4, the input signal passes from four gmb4
nodes named as A, B, C and output. By associating one pole
The new first non-dominant pole is determined by the
to each of these nodes, the poles of nodes B and C (xB and
parasitic capacitor at nodes B and C. Thus, the phase-
xC) are usually smaller than xP2 and xP1 associated with
nodes A and output. The dominant pole xP1 is determined by
the output impedance and capacitive load. Also a pole-zero
pair, xP2 and xZ1 = (2 k)xP2 is associated with the current
mirrors Mb3:Ma3:M9 and Mb4:Ma4:M10; it can be Ib 4 I a4
described by
gmb4 Ma4
xp2;PRFC   ; ð8Þ R
2kCgsb4 : (K-1)
Mb4 M10
where gmb4 is the transconductance and Cgsb4 the gate– 1 : k
source capacitance of transistor Mb4. For good phase-
I 10
margin and stability, k can be chosen such that xP2 C 3xu,
where xu is the unity-gain frequency of the amplifier [1, 2].
Fig. 5 The high speed current mirror with new driver P-channel
It places an upper boundary on k such as transistor

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Analog Integr Circ Sig Process (2015) 82:217–227 221

margin of the PRFC is enhanced without limiting the KFp

Vif2 ;PRFC ¼ 2 2
GBW. 2kCox f lp ðWLÞa1
"  
1 þ ð2k  1Þ2 k þ ð2k  1Þ2 KFn La1 2
3.4 Slew-rate þ
2k 2k KFP La3
 2 #
The slew rate for the FC and PRFC can be expressed by ðk  1Þ La1
þ :Df ð21Þ
(14) and (15), respectively. The slew rate has been care- 2k L9
fully analyzed in [2, 4], so just a brief feedback is presented
here. By applying a large signal to Vin? , Ma1 and Mb1 The improvements made to the amplifiers did not alter
will be turned off. Ma2 will operate in deep triode in the the channel lengths of the devices, only the widths.
strong inversion region. The tail current 2I flows into Mb2 Therefore, by substituting Wa1 in terms of W1, (21) can be
and is mirrored by a factor of k and (k - 1) into CL. By transformed to (22).
substituting value of k in (15), the slew rate of the PRFC is KFp
enhanced 5 times over the FC amplifier. Vif2 ;PRFC ¼ 2 2 ðWLÞ f
lp Cox 1
"  2   #
2I 13 14 KFn L1 1 L1 2
S:RFC ¼ ð14Þ þ þ :Dff ð22Þ
CL 9 9 KFP L3 9 L9
2I ð2k  1Þ The above equation may be inconclusive as which
S:RPRFC ¼ ð15Þ
CL configuration exhibits the smallest noise. However, since
3.5 Noise two terms in (19) and (22) are smaller than their counter-
parts in (17) and (20), it is likely the PRFC has a lesser or
The maximum noise current power seen at the output of a equivalent noise to that of FC. This will be confirmed in the
MOSFET is given by [2, 14]. simulation results.
 
KF Id
i2o ¼ 4KB Tcgm þ :Df ð16Þ 3.6 Input offset
Cox L2 f
For comparison purposes, flicker and thermal noise Fabrication process variations across the chip lead to
components were tested singularly to decrease clutter [2]. considerable mismatch in devices, which are otherwise
The input referred thermal noise of FC and PRFC can be identical by design [2]. A mismatch model [15] based on
expressed as the study of equal area rectangular devices, states that the
  variance of a parameter DP can be expressed as [2]
4KB Tc gm3 gm9
2
ViT;FC ¼2 1þ þ :Df ð17Þ A2P
gm1 gm1 gm1 r2 ðDPÞ ¼ ; ð23Þ
" WL þ S2P DX
2 4KB Tc 1 þ ð2k  1Þ2 where AP is the area proportionality constant for parameter
ViT;PRFC ¼ 2
2kgma1 2k P, SP is the variation of P with spacing, and DX is the
#
k þ ð2k  1Þ2 gma3 gm9 distance between two devices along X. Since critical
þ þ :Df ð18Þ devices, such as the input pair or current mirrors, are
ð2kÞkgma1 2kgma1
interdigitated or cross-coupled, DX approaches zero, and
By substituting gma1 in terms of gm1 and gma3 in terms the second term of (23) can be neglected. Using (2), the
of gm3, the Eq. (18) can be reformulated as drain–current variance due to process variation can be
expressed as [2, 15].
 
4KB Tc 13 7 gm3 1 gm9
2
ViT;PRFC ¼2 þ þ :Df ð19Þ r2 ðVT Þ r2 ðbÞ
gm1 9 9 gm1 9 gm1 r2 ðID Þ ¼ 4ID2 þ ID2 ð24Þ
ðVGS  VT Þ b2
The expressions of the flicker noise for the two ampli-
assuming r2 ðVT Þ and r2 ðbÞ are uncorrelated. Hereb rep-
fiers can be expressed as
resents lCox W=L. Equation (24) is very useful, because
"    2 # from a circuit analysis stand point, the drain-current vari-
KFp KFn L1 2 L1
Vif2 ;FC ¼2 2
1þ2 þ :Df ance can be treated as a small signal that can be referred to
lp Cox ðWLÞ1 f KFP L3 L9
the gate of the MOS device through its transconductance,
ð20Þ gm [2]. The result is

123
222 Analog Integr Circ Sig Process (2015) 82:217–227

ID2 r2 ðbÞ
r2 ðVGS Þ ¼ r2 ðVT Þ þ ð25Þ
gm2 b2 CMFB 1 : (K-1)
M0 M10
and since in analog design Gm/ID is generally maximized,
I
the effect of the second term of (25) is diminished.
Therefore M8
Vin cm Mb1
A2VT Ma2 Vout
r2 ðVGS Þ ffi r2 ðVT Þ ¼ ð26Þ
WL CL

Here AVT is the area proportionality constant for the V1 V1

M12 M6
threshold voltage, VT, which is provided by process char-
acterization. Using (26), the input offset variance can be
expressed as the sum of all device drain-current variances
seen at the output, and then referred to the input using the R
Mb4 Ma4
amplifier’s Gm [2]. The results for PRFC and FC are given 1 : K
in (27) and (28).
"  2  2 #
2 2
A VTp l A L1 L1 Fig. 6 Half circuit topology of the PRFC in the common mode
r2 ðVOS ÞFC ¼ 2 1 þ 2 n VTn þ conditions
ðWLÞ1 lp A2VTp L3 L9
ð27Þ
the common mode conditions. Therefore, decreasing
2
A2VTp CMRR due to the new derivers M9/M10 and Ma3/Ma4 can
r ðVOS ÞPRFC ¼ 2
2kðWLÞa1 be compensated by positive feedback structure and higher
"   DC gain in the differential mode. These mentions can be
1 þ ð2k  1Þ 2
k þ ð2k  1Þ2 ln A2VTn La1 2
þ described in Fig. 6. This figure shows the half circuit
2k 2k lp A2VTp La3 topology of the PRFC in the common mode conditions.
  #
k  1 La1 2 It was assumed that transistors M6 and M8 have similar
þ ð28Þ small signal features including output impedance and
2k L9
transconductance along with goa4 & go10. Therefore, the
By substituting for Wa1 in terms of W1 and for the value of CMG of the FC and PRFC amplifiers can be expressed
k, we transform (28) to (29). Again, by examining (27) and approximately by (30) and (31), respectively.
(29), it is inconclusive as to which has lesser input offset.  
goo gm1 gm8 þ go8 þ go10
AcmFC  ð30Þ
"     # 2ðgoo þ 2gm1 Þ go10 go8
2
A2VTp 13 14 ln A2VTn L1 2 1 L1 2  
r ðVOS ÞPRFC ¼ 2 þ þ goo gmb1 gm8 þ go8 þ go10
ðWLÞ1 9 9 lp A2VTp L3 9 L9 AcmPRFC  ð2k  2Þ :
3ðgoo þ 4gmb1 Þ go10 go8
ð29Þ
ð31Þ
3.7 CMRR
By substituting value of k in (31), it can be seen that the
CMG of the PRFC is increased over the FC that leads to the
CMRR is defines the ability of an amplifier to reject
lower CMRR ¼ 20 logjAd =Acm j than the FC. But an overall
common mode disturbances. Ideally CMRR for a differ-
differential gain (Ad) enhancement of 15–17 dB can be
ential amplifier should be infinite. However, in practical
expected for the PRFC compared with the FC configuration
situations, non-idealities such as mismatch, finite output
that leads to the compensation of such CMRR reduction.
impedance of current sources cause CMRR to have finite
Therefore, the CMRR of the FC and PRFC amplifiers can
value. The new feed-forward paths using high speed cur-
be expressed by (32) and (33), respectively.
rent mirrors to improve transconductance of the PRFC lead
to increasing common mode gain (CMG), consequently 2ðgoo þ 2gm1 Þ
CMRRFC ¼ 20 log
ð32Þ
lower CMRR for the proposed structure [3, 5]. As men- goo
tioned, the positive feedback structure in Sect. 3.2
3kðgoo þ 4gmb1 Þ
increased output impedance of the PRFC in the differential CMRRPRFC ¼ 20 log : ð33Þ
ðk  1Þgoo
mode, but that leads to the decreasing output impedance in

123
Analog Integr Circ Sig Process (2015) 82:217–227 223

By substituting for gma1 in terms of gm1 and for the 2 PRFC

10
RFC
value of k in (33), it can be seen that the CMRR of the
FC
PRFC is increased over the FC. This will be confirmed in

Spectral density, pV2/Hz)

the next section. 10
0

4 Simulation results -2
10

We designed three amplifiers (one per configuration, i.e.,

PRFC, RFC and FC) in standard 0.18 lm CMOS process -4
10
and biased them with a 1.2 V power supply (assuming
same power consumption). The open-loop AC response of
0 5
the amplifiers, loaded with a 2 9 5 pF capacitor, is shown 10 10

in Fig. 7. The simulated GBW of the FC, RFC and PRFC Frequency, Hz
amplifiers is 31.4, 66.2 and 148.9 MHz, respectively. It Fig. 8 Spectral density of the input referred noise for amplifiers
indeed demonstrates the enhanced transconductance of the
PRFC. As for the phase margin, it is of 86.9°, 78.9° and
80.3° relatively to the GBW of the FC, RFC and PRFC,
C2
respectively. Compared with RFC, PRFC shows 1.4o C1
Vin- C1
increment. On the other hand, the phase margin of the FC _ Vout+
drops to 74.8° at 148.9° MHZ, and hence the PRFC shows +
_
5.5° of increment. Moreover, the DC gain of the FC, RFC +
Vin+ C1 Vout-
and PRFC is respectively of 49.3, 57 and 65.7 dB, thus
highlighting a significant enhancement of the PRFC over C1 C2
the two other amplifiers.
The noise was also investigated and the spectral density Fig. 9 Unity gain capacitive buffer [4]
of the input referred noise given in Fig. 8. The input
referred noise of the FC, RFC and PRFC is 183.1, 54.08
Three amplifiers were used as a unity gain capacitive
and 35.33 pV2/Hz, respectively. Hence, the PRFC
buffer, as seen in Fig. 9, driving a total capacitive load of
improves noise performance while the FC exhibits, as
10 pF (C1 = 5 pF, C2 = 5 pF) [4]. As for the slew rate, a
expected, the worse noise performance.
large step of 0.5VPP at 2.5 MHz was applied to the
amplifiers and the results are given in Fig. 10. The PRFC
shows a clear improved slew rate over the FC and RFC
60
despite the same power consumption. The average slew
rate of the FC, RFC and PRFC is 12, 18.3, and 31.8 V/ls
Gain, dB

40
respectively, i.e. the slew rate of the PRFC is enhanced by
20 2.65 times over the FC for the same power consumption.
Figure 11 shows the CMRR curves of the amplifiers.
0
The PRFC shows a clear improved CMRR over the FC and
-20
RFC. At the low frequency, the CMRR of the FC, RFC and
Phase, deg

PRFC is 31.6, 38.3 and 42.9 dB, respectively. The CMRR

-40 of the PRFC is enhanced 11.3 dB over the FC with the
same power consumption.
-60 Capacitive load and Power supply variations are repor-
ted to considering the 0.1 % settling time changes. Step
-80
response of the proposed OTA with 10 % power supply
PRFC
-100 variations and the 3.8 pF capacitive load variations (from
RFC
FC
1.2 to 5 pF) are shown in Figs. 12 and 13, respectively.
-120 Also, temperature dependent simulation and corner
0 5
10 10
analysis are reported to demonstrate the mismatch and
Frequency, Hz
temperature effects on main specifications of the proposed
Fig. 7 Frequency response of the three designed amplifiers OTA. Open loop AC response of the proposed OTA with

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224 Analog Integr Circ Sig Process (2015) 82:217–227

Fig. 10 Step responses of FC, 0.8 0.5

PRFC
RFC and PRFC
0.6 RFC

Vout, mV
X 0.4
FC X
0.4 0.3 PRFC
RFC
FC
0.2 0.2

Vout, mV
40 60 80 100 120 140
0 Time, nS

-0.2 PRFC
Y RFC

Vout, mV
-0.4 -0.3 FC

-0.4
Y
-0.6

-0.8 -0.5
0 100 200 300 400 500 240 260 280 300 320 340
Time, nS Time, nS

45

40

35
CMRR, dB

30

25
PRFC
RFC
FC
20
0 2 4 6 8
10 10 10 10 10
Frequency, Hz

Fig. 11 Simulated CMRR of the PRFC, RFC and FC amplifiers Fig. 13 Power supply variations of step response

80
Gain, dB

60

40

20

-20
Phase, deg

-40
TT process
-60
SF process
-80 FF process
SS process
-100 FS process
0 5
10 10
Frequency, Hz

Fig. 12 Capacitive load variations of step response Fig. 14 Corner cases of frequency response

123
Analog Integr Circ Sig Process (2015) 82:217–227 225

Table 2 Specifications of PRFC compared with FC and RFC and to

recent designs
Parameter FC RFC [4] [6] [10] PRFC

Supply voltage 1.2 1.2 1.2 1.8 1 1.2

(V)
Technology (nm) 180 180 180 180 65 180
Power 360 360 661 1080 800 360
consumption
(lW)
Capacitive load 295 295 2 9 0.5 8 10 295
(pF)
GBW (MHz) 31.4 66.2 489.8 170.4 203.2 148.9
Phase-margin (°) 86.9 78.9 77.2 80.1 66.2 80.3
DC gain (dB) 49.3 57 50.9 68.1 54.5 65.7
CMRR (dB) 31.6 38.3 – – – 42.9
Fig. 15 Temperature variations of frequency response 0.1 % settling 151.2 91.6 5.1 142 10.7 60.9
time (nS)
five process corners (TT, SS, FF, SF and FS) and 100 °C Input voltage 13.5 7.35 – – – 5.94
noise @ 1 Hz
temperature variations (from -10 to ?90 °C) are shown in (lV/sq Hz)
Figs. 14 and 15, respectively. Table 1 summarizes the Input referred 76.8 62.1 – – 25.8 56.7
important specifications of the PRFC amplifier in the pro- noise (1 Hz–
cess corners, temperature variations and power supply 100 MHz)
variations. (lVrms)
The amplifiers were configured such that the output is Average slew- 12 18.3 200 – 84.1 31.8
rate (V/ls)
set at Vdd/2 to maximize swing, 0.8 V in this work.
Linear signal 900 900 – – – 800
Table 2 compares the specifications of the PRFC amplifier swing (mVp–p)
over the FC and the RFC, as well as over exiting designs. It
Estimated area 700 700 – 875 480 800
clearly demonstrates the efficiency of the proposed design. (lm2)
FOM1 43 105 37 86 138 271
(MHz dB pF/
5 Conclusion lW)

In this paper, an improved recycled FC configuration was

presented. Compared with the conventional FC amplifier,
the designed circuit shows better DC gain, bandwidth, slew
rate and CMRR without adversely affecting noise, input
offset and phase-margin performance, thus resulting in
better FOM while keeping almost same power
consumption. Simulated in the 0.18 lm CMOS process, it
exhibits an enhanced DC gain, bandwidth and slew rate of
16.4 dB, 117.5 MHz and 19.8 V/ls, respectively, therefore
demonstrating the proposed approach.

Table 1 Important Parameter Power supply variations Corner analysis Temperature dependent
specifications of PRFC in the
power supply variation, process Vdd ? 10 % Vdd - 10 % SS FF -10 °C ?90 °C
corners and temperature
variation Unit gain-bandwidth (MHz) 198 104 132.5 160.8 123 185.8
Phase margin (o) 89 55 83.9 76.9 82.4 64.1
DC gain (dB) 74 58.5 76 67 69.5 55.6
Average slew-rate (V/ls) 38.6 22.6 27.9 31.6 30.1 29.5
0.1 % settling time (nS) 60.3 85.4 75.2 59.4 58.3 73.3

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226 Analog Integr Circ Sig Process (2015) 82:217–227

References Meysam Akbari was born in

Kermanshah, Iran in 1988. He
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2. Assaad, R. S., & Silva-Martinez, J. (2009). The recycling folded Shahid Beheshti University in
cascode: a general enhancement of the folded cascode amplifier. 2013, respectively. His research
IEEE Journal of Solid-State Circuits, 44, 2535–2542. interests include low power and
3. Largani, H., Mehdi, S., Shahsavari, S., Biabanifard, S., & Jalali, high speed data converter, low
A. (2014). A new frequency compensation technique for three voltage analogue circuits and
stages OTA by differential feedback path. International Journal RF integrated circuits design.
of Numerical Modelling: Electronic Networks, Devices and He is currently with Department
Fields. doi:10.1002/jnm.2013. of Electrical and Computer
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performance of folded cascode amplifier by recycling current. tronic Laboratory in Shahid Beheshti University, G. C., Tehran, Iran.
Electronics Letters, 43, 1243–1244.
5. Thandri, B. K., & Silva-Martinez, J. (2006). An overview of feed- Sadegh Biabanifard was born
forward design techniques for high-gain wideband operational in Tehran, Iran in 1989. He
transconductance amplifiers. Microelectronics Journal, 37, received the B.S. degree in
1018–1029. Electronic Engineering from
6. Akbari, M., & Hashemipour, O. (2014). Enhancing transcon- Imam Reza International Uni-
ductance of ultralow-power two-stage folded cascode OTA. versity, Mashhad, Iran in 2011
Electronics Letters, 50, 1514–1516. and M.S. degree in Analog
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technique for recycling folded cascode amplifier. Analog Inte- shti University, G.C., Tehran,
grated Circuits and Signal Processing, 74, 479–483. Iran, in 2014. His research
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(2014). Design and analysis of DC gain and transconductance log and mixed mode integrated
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Journal of Electronics and Communications, 68, 1047–1052. Power Ultra-Low-Voltage
9. Zhao, X., Fang, H., & Xu, J. (2011). DC gain enhancement applications, OTA, current con-
method for recycling folded cascode amplifier in deep submicron veyer and data converter.
CMOS technology. IEICE Electronics Express, 8, 1450–1454.
10. Ramazani, A., Biabani, S., & Hadidi, G. (2014). CMOS ring Shahrouz Asadi received the
oscillator with combined delay stages. AEU-International Jour- B.Sc. degree in Electrical Engi-
nal of Electronics and Communications, 68(6), 515–519. neering and the M.Sc. degree in
11. Yan, Z., Mak, P.-I., & Martins, R. P. (2012). Double recycling Electronics both from Amirka-
technique for folded-cascode OTA. Analog Integrated Circuits bir University, Tehran, Iran, in
and Signal Processing, 71, 137–141. 2003 and 2007, respectively and
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enhanced recycling structure for folded cascode amplifier. Analog in the School of Information
Integrated Circuits and Signal Processing, 72, 259–263. Technology and Engineering
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enhanced folded cascode Op-Amp using positive feedback and Ottawa, ON, Canada. He joined
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Analog Integr Circ Sig Process (2015) 82:217–227
Mustapha C. E. Yagoub
received the Dipl.-Ing. degree in
Electronics and the Magister
degree in Telecommunications,
both from the EcoleNationalePo-
lytechnique, Algiers, Algeria, in
1979 and 1987 respectively, and
the Ph.D. degree in Electronics
from the Institute National Poly-
technique, Toulouse, France, in
1994. After few years working in
industry as a design engineer, he
joined the Institute of Electronics,
Université des Sciences et de la
TechnologieHouariBoumédiene,
Algiers, Algeria, first as a Lecturer during 1983–1991 and then as an
227
Assistant Professor during 1994–1999. From 1996 to 1999, he has been
head of the communication department. From 1999 to 2001, he was a
visiting scholar with the Department of Electronics, Carleton University,
Ottawa, ON, Canada, working on neural networks applications in
microwave areas. In 2001, he joined the School of Information Tech-
nology and Engineering (SITE), University of Ottawa, Ottawa, ON,
Canada, where he is currently a Professor. His research interests in-
cludeRF/microwave device/system CAD, neural networks for high fre-
quency applications, planar antennas, and applied electromagnetics. He
has authored or coauthored more than 200 publications in these topics in
international journals and referred conferences. He is the first author of
Conception de circuits linéaireset non linéaires micro-ondes (Cépadues,
Toulouse, France, 2000), and the co-author of Computer Manipulation
and Stock Price Trend Analysis (Heilongjiang Education Press, Harbin,
China, 2005). Dr. Yagoub is a senior member of the IEEE and a member
of the Professional Engineers of Ontario, Canada.
123