2 - 1 Verilog HDL PDF

Verilog HDL
Teaching Assistant: Lien-Fei Chen (陳聯霏)

Instructor: Prof. Yeong-Kang Lai
Multimedia & Communication IC Design Lab

Electrical Engineering, National Chung Hsing University
Fall, 2005
2005 VLSI Training Course -1-
Outline
¾ Introduction to Verilog HDL

¾ Verilog data types and models
¾ Verilog test bench
¾ Introduction to Verilog-XL simulator
¾ Annotating SDF Timing
1
What is a Hardware Description
Language ?
¾ High-level programming language with special

constructs used to model the function of hardware
logic circuits
¾ The special language constructs provides the ability
to
• Describe the connectivity of the circuit
• Describe the functionality of a circuit
• Describe a circuit at various levels of abstraction
• Describe the timing of a circuit
• Express concurrency
Why Use an HDL ?

¾ There are several benefits in using an HDL to
describe your design
• Top-down methodology using synthesis
Design at an implementation-independent, higher level
Explore design alternatives easily
Find problems eariler in the design cycle
Automate mapping of high-level descriptions to technology-
specific implementations
• An HDL provides greater flexibility
Re-use
Choice of tools, vendors
• An HDL provides the advantages of decades of software
practices
Faster design capture
Easier to manage
2
What is Verilog HDL ?
¾ A hardware description language

• Verilog models digital electronic system
• Verilog lets you model at different levels of abstraction
• Verilog lets you develop tests to verify the functionality of the
devices you model
A Brief History of Verilog
¾ 1981 – Gateway Design Automation released

GenRad’s Hardware Description Language (GHDL)
¾ 1983 – Gateway released Verilog HDL
¾ 1985 – Enhanced simulator Verilog-XL released
¾ 1989 – Cadence bought Gateway
¾ 1990 – Cadence released Verilog to public domain
¾ 1993 – EE Times reported 85% designs submitted to
ASIC foundries were designed and submitted using
Verilog
¾ 1995 – Reviewed and adopted as IEEE standard 1364
3
Levels of Abstraction for Verilog
HDL & VHDL
VHDL
System
Behavioral
Behavioral
Level
Level Verilog
Algorithm
RTL
RTL RTL Synthesizable RTL Code
Level
Level
Logic
Gate
Gate
Level
Level vital
Gate
Levels of Abstraction for Verilog

¾ Models can be written with different levels of details
¾ Three main levels of abstraction in Verilog
• Behavioral
Describes a system by the flow of data between its functional
blocks
Schedules assignments at functional boundaries only when
necessary
• Register Transfer Level (RTL)
Describes a system by the flow of data and controls
signals within and between functional blocks
Defines the model in terms of cycles, based on a defined
clock
• Structural (Gate-level)
Models components by connecting primitives or low-level

components (gates) for greater accuracy, especially in timing
Uses technology-specific, low-level components when mapping
from an RTL description to a gate-level netlist, such as during
synthesis
4
Behavioral and RTL (1/2)
module mux2to1 (a, b, sel, out);

input [7:0] a, b;
input sel;
output [7:0] out;
reg [7:0] out; a
always @ (a or b or sel)
begin out
if (sel == 1’b1) b
out = a;
else
out = b; sel
end
endmodule
¾ The behavioral/RTL description does not handle unknown and

tristate inputs exactly as the structural implementation would,
and has no propagation delays
Behavioral and RTL (2/2)
¾ Behavioral model
• The function of the logic is modeled using high level
language constructs, such as @, while, wait, if/else
and case
¾ RTL model
• Based on clock
• RTL model must be accurate at the boundary of every
clocked elements
• RTL level is appropriate for synthesis, so designers use RTL
to mean the synthesizable subset of behavioral Verilog
¾ Testbenchs, or test fixtures, are typically modeled at
the behavioral level.
¾ All behavior constructs are legal for testbenchs.
2005 VLSI Training Course - 10 -
5
Overall Structure
Top module
No glue logic within top module
Outline

• Verilog operations
• Verilog data types
• Verilog models
6
Module Definition
module MyCPU (clk, rst, data, address, result);

input clk, rst; I/O port
input [31:0] data, address; declarations
output [31:0] result;
.
. Resource/variable declarations
.
.
. RTL modeling
.
endmodule
Value Set and Numbers
¾ Value set
• 0 – logic zero or false condition
• 1 – logic one or true condition
• x – unknown or don’t care logic value
• z – high-impedance state
¾ Number representation
• <number>
• ‘<base><number>
• <width>’<base><number>
• base – b, d, o ,h
7
Data Types (1/2)
¾ Signal nets
• wire, tri
¾ Wired nets
• wand, wor, triand, trior
• trireg
• tri0, tri1
¾ Supply nets
• supply0, supply1
Data Types (2/2)
¾ Registers
• reg
¾ Memories
• array of register variables
¾ Integers (32-bit)
• integer
¾ Time (64-bit)
• time
¾ Real numbers
• real
¾ Parameters
• parameter
8
Operators (1/2)
¾ Arithmetic operators
• +, 1, *, /, %
¾ Relational operators (0, 1, x)
• <, >, <=, >=
¾ Equality operators (0, 1)
• ==, !=, ===, !==
¾ Logical operators (0, 1)
• &&, ||, !
¾ Bit-wise operators
• ~, &, |, ^, ~^, ^~
Operators (2/2)
¾ Reduction operators (unary)

• &, |, ^, ~&, ~|, ~^, ^~
¾ Shift operators (fill with zeros)
• <<, >>
¾ Conditional operator
• ?...:
¾ Concatenations
• {, }
9
Module Connectivity
¾ Order list module top (…);
…
wire [7:0] data, result;
inv INV0 (data, result);
endmodule
module inv (in, out);

input [7:0] in, out;
out = ~in;
endmodule
module top (…);
¾ Name …
wire [7:0] data, result;
inv INV0 (.in(data),
.out(result));
endmodule
Better !!!
module inv (in, out);
input [7:0] in, out;
out = ~in;
endmodule
Parameters
¾ Use parameters to declare run-time constants

¾ You can use a parameter anywhere that you can use
a literal
¾ Parameters are local, known only to the module in
which they are defined
module mod (in1, in2, out);
parameter cycle = 20, prop_del = 3,

setup = cycle/2 – prop_del,
p1 = 8,
x_word = 16’bx,
file = “/usr1/jdough/design/mem_file.dat”;
...
wire [p1:0] w1; // a wire declaration using parameter
...
endmodule
10
Overriding the Values of
Parameters (1/2)
Defparam
Defparam Statement
Statement
<<example>>
parameter p1 = 8,
real_constant = 2.039,
x_word = 16’bx,
...
endmodule
module test;
...
mod I1 (.in1(in1), .in2(in2), .out(out));
defparam
I1.p1 = 6;
I1.file = “../my_mem.dat”;
endmodule
Overriding the Values of

Parameters (2/2)
Module
Module Instance
Instance Parameter
Parameter Override
Override
<<example>>
parameter p1 = 8,
real_constant = 2.039,
x_word = 16’bx,
endmodule
module top;
...
mod #(5, 3.0, 16’bx, “../my_mem.dat”)
I1 (.in1(in1), .in2(in2), .out(out));
...
endmodule
11
Register Arrays
¾ You can declare an array of registers in Verilog

integer nums [7:0]; // array of 8 integer variables
time t_vals [3:0]; // array of 4 time variables
¾ An array of the datatype reg is often called a memory

reg [15:0] MEM [0:1023]; // 1K x 16-bit memory array
reg [7:0] PREP [`hFFFE:`hFFFF]; // 2 x 8-bit memory array
¾ You can use parameters to model memory size

parameter WORDSIZE = 16;
parameter MEMSIZE = 1024;
reg [WORDSIZE-1:0] mem3 [MEMSIZE-1:0];
Memory Addressing
<<example>>
module mems;
reg [7:0] mema [0:255]; // declare memory called mema

reg [7:0] mem_word; // temp register called mem_word
...
initial
begin
// Display contents of the 6th memory address
$display(mema[5]);
// Display the MSB of the 6th memory word
mem_word = mema[5];
$displayb(mem_word[7]); // Display the MSB
end
endmodule
12
Behavioral Modeling
¾ Event-driven procedures
• always, initial
¾ Sequential blocks
• Begin...end
¾ Parallel blocks
• Fork...join
Procedure blocks
initial always
¾ All procedure blocks are activated at time 0

¾ All procedural blocks execute concurrently
13
Procedure Timing Control
¾ Simple delays, or pound delays

• #
¾ Event control (edge-sensitive)
• @
¾ Level-sensitive timing control
• wait
Edge-Sensitive Timing
module reg_adder(clk, a, b, out);
input clk;
input [2:0] a, b;
output [3:0] out;
reg [3:0] out, sum;
always @ (a or b) // when any change occurs on a or b
#5 sum = a + b;
always @ (negedge clk) // at every negative edge of clk
out = sum;
endmodule
Example
Example
14
Conditional Statements
<<example>>
if (<expression>) if (index>0)
<statement_or_null> if (rega > regb)
result = rega;
else
result = regb;
if (<expression>) if (index > 0)

<statement_or_null> begin
else if (rega > regb)
<statement_or_null> result = rega;
end
else
result = regb;
Multi-way Decision Statements
<<example>>
if (<expression>) reg [15:0] rega;

<statement> reg [7:0] result;
...
else if (<expression>)
<statement> case (rega)
else if (<expression>) 16’d0: result = 8’hff;
<statement> 16’d1: result = 8’hbf;
else 16’d2: result = 8’hdf;
<statement> ...
default result = 8’hxx;
endcase
case/casez/casex (<epression>)
<case_item>
endcase
15
Nonblocking Procedural
Assignment
<<example>> Non-blocking
Non-blocking Assignment
Assignment
module swap_vals (clk, rst, a, b);
parameter BIT_SIZE = 4
input clk, rst;

output [BIT_SIZE-1:0] a, b;
// Non-blocking procedural assignment

always @ (posedge clk)
begin
if (rst == 1’b1)
begin
a <= 4’h0;
b <= 4’h0;
end
else
begin
b <= a;
a <= b;
end
end
endmodule
Continuous Assignments
¾ Drive values onto nets, both vector and scalar

¾ The assignment is always active
¾ Provide a way to model combinational logic
without specifying an interconnection of gates
¾ Can make continuous assignments explicit or implicit
/* Better !!! */
wire out;
assign out = a & b; //explicit
/* not the best choice */

wire out = a & b //implicit
16
Functions and Tasks (1/2)
¾ Tasks and functions provides the ability to execute

common procedures from several different places in
a description
Functions and Tasks (2/2)
¾ Task
• Is typically used to perform debugging operations, or to
behaviorally describe hardware
• Can contain timing controls (#, @, wait)
• Can have input, output, and inout arguments
• Can enable other tasks or functions
¾ Function
• Is typically used to perform a computation, or to represent
combinational logic
• Cannot contain any delays; functional happen in zero
simulation time
• Has only input arguments and returns a single value through
the function name
• Can enable other functions, but not tasks
17
Verilog Tasks
<<example>>
module mult (clk, a, b, out, en_mult);

input clk, en_mult;
input [3:0] a, b;
output [7:0] out;
reg [7:0] out;

multme (a, b, out); // task invocations
task multme; // task definition

input [3:0] xme, tome;
output [3:0] result;
wait (en_mult)
result = xme * tome;
endtask
endmodule
Verilog Functions
<<example>>
module foo (loo, goo);

input [7:0] loo;
output [7:0] goo;
// you can call a function from a continuous assignment

wire [7:0] goo = zero_count (loo);
function [3:0] zero_count // task definition

input [3:0] in_bus;
integer i;
begin
zero_count = 0;
for (i = 0; i < 8; i = i + 1)
if (!in_bus[i])
zero_count = zero_count + 1;
end
endfunction
endmodule
18
Special Language Token
¾ System Tasks and Functions: $<identifier>

¾ The “$” sign denotes Verilog system tasks and
functions
¾ A number of system tasks and functions are available
to perform different operations, such as
• $time – finding the current simulation time
• $display, $monitor – Displaying/monitoring the values
of the signals
• $stop – stopping the simulation
• $finish – finishing the simulation
《Example》
$monitor($time, “a = %b, b = %h”, a, b);
Text Substitution
¾ The `define compiler directive provides a simple

text-substitution facility.
¾ `define <macro_name> <macro_text>
《Example》
`define D_NOT #1
`define D_AND #2
`define D_OR #1

input a, b, sel;
output out;
not `D_NOT not1(sel_, sel);
and `D_AND and1(a1, a, sel_);
and `D_AND and2(b1, b, sel);
or `D_OR or1(out, a1, b1);
endmodule
19
Text Inclusion
¾ Use the ìnclude compiler directive to insert the

contents of an entire file
ìnclude “global.v”
ìnclude “parts/count.v”
ìnclude “../../library/mux.v”
¾ You can use ìnclude to

• Include global or commonly used definitions, such as text
macros
• Include tasks without encapsulating repeated code within
module boundaries
Timescale
¾ `timescale compiler directive declares the time
unit and precision
• `timescale <time_unit>/<time_precision>
`timescale 1ns/100ps
¾ The `timescale compiler directive must appear

before a module boundary
¾ Keep precision as close in scale to the time units as
is practical
`timescale 1ns/10ps
// All time units are in multiples of 1 nanosecond
input a, b, sel;
output out;
not #1 not1(sel_, sel);
and #2 and1(a1, a, sel_);
and #2 and2(b1, b, sel);
or #1 or1(out, a1, b1);
endmodule
20
Outline

Test Bench Organization
Testbench
Design to verify
Simple
Simple test
test bench
bench
Testbench
Design to verify
Sophisticated
Sophisticated test
test bench
bench
21
Test Fixture
module testfixture;
// data type declaration

reg [7:0] a, b;
reg sel;
wire [7:0] out;
// instantiate modules
mux2to1 test_mux (.a(a),
.b(b),
.sel(sel),
.out(out));
// apply stimulus
// display results
endmodule
Test Fixture ― Response Generation
¾ Verilog provides a number of system tasks and

system functions, including:
• $time is a system function that returns the current
simulation time.
• $monitor is a system task that displays the values of the
argument list at the end of any time unit in which any of the
arguments change.
• $monitor ([“format_specifiers”,]<arguments>);
《example》
$monitor($time, o, in1, in2);

$monitor($time,, out,, a,, b,, sel);
$monitor($time, “%b %h %d %o”, sig1, sig2, sig3, sig4);
22
Test Fixture ― Describing Stimulus
module testfixture;
// data type declaration
reg a, b, sel;
wire out;
// instantiate modules
mux2to1 test_mux (.a(a),
.b(b),
.sel(sel),
.out(out));
// apply stimulus
initial
begin
a = 0; b = 1; sel = 0;
#5 b = 0;
#5 b = 1; sel = 0;
#5 a = 1;
$finish;
end
// display results
Initial
$monitor($time,,”out = %b a = %b b = %b sel = %b”, out, a, b, sel);
endmodule
The VCD Database
Verilog provides a set of system tasks to record signal value changes in

the standard VCD (Value Change Dump) format. Most wave display tools
read this formant, among others.
S ystem task Action

$dumpfile(“file.dump”); O pen a V C D database for recording
$dumpvars(); Select signals for recording
$dumpflush; Flush all V C D data to disk
$dumpoff; Stop recording
$dumpon; Start recording again
$dumplimit(<file_size>); Lim it the s ize (in b ytes) of the VC D data base created
$dumpall; D um p the values of all specified signal values
23
Dumping Signals
¾ Supply levels and scope arguments to $dumpvars

$dumpvars; // Dump all signals in the hierarchy
$dumpvars (1, top); // Dump all signals in module “top”
//Dump signals in instance top.u1 and its subscope

$dumpvars (2, top.u1);
//Dump signals in top.u2 and below, and signal top.u1.u13.q

$dumpvars (0, top.u2, top.u1.u13.q);
//Dump signals in top.u1 and top.u2, and in all their subscopes of them, two level down
$dumpvars (3, top.u2, top.u1)
¾ $dumpvars could replace the $monitor command

《Example》
initial
begin
$dumpfile(“verilog_dump.vcd”);
$dumpvars(0, testfixture);
end
File Input (1/2)
¾ $readmemb
$readmemb(“file_name”,<memory_name>);
$readmemb(“file_name”,<memory_name>,<start_addr>);
$readmemb(“file_name”,<memory_name>,<start_addr>,<finish_addr>);
¾ $readmemh
$readmemh(“file_name”,<memory_name>);
$readmemh(“file_name”,<memory_name>,<start_addr>);
$readmemh(“file_name”,<memory_name>,<start_addr>,<finish_addr>);
24
File Input (2/2)
Declared Memory Array

reg[0:7] mem[0:1023]
00000000 0
Text File 01100001
mem_file.txt
00110010
...
0000_0000
0110_0001 0011_0010
// addresses 3-255 are not defined
@100 //hex
1111_1100
/* addresses 257-1022 are not defined */ 11111100 256
@3FF
1110_0010
...
11100010 1023
0 7
File Output (1/2)

¾ $fopen opens a file and returns a multi-channel
descriptor (MCD)
• The MCD is a 32-bit unsigned integer uniquely associated
with the file
• If the file cannot be opened for writing, MCD will equal 0
• If the file is successfully opened, one bit in the MCD will be
set.
¾ Display system tasks that begin with $f direct their
output to whichever file or files are associated with
the MCD MCD1 = $fopen(“<name_of_file>”);
$fdisplay(MCD1, P1, P2, …, Pn);

$fwrite(MCD1, P1, P2, …, Pn);
$fstrobe(MCD1, P1, P2, …, Pn);
$fmonitor(MCD1, P1, P2, …, Pn);
$fclose(MCD1);
Example
Example
25
File Output (2/2)
<<example>>
...
integer message, broadcast, cpu_chann, alu_chann;
initial
begin
cpu_chann = $fopen(“cpu.dat”); if (!cpu_chann) $finish;
alu_chann = $fopen(“alu.dat”); if (!alu_chann) $finish;
// channel to both cpu.dat and alu.dat
message = cpu_chann | alu_chann;
// channel to both files, standard out, verilog.log
broadcast = 1 | message;
end

$fdisplay(alu_chann, “acc = %h f = %h a = %h b = %h”, acc, f, a, b);
/* at every rst print a message to alu.dat, cpu.dat, standard output

and the verilog.log file */
always @ (posedge rst)

$fdisplay(broadcast, “system reset at time %d”, $time);
...
In Line Stimulus
¾ Variable can be listed only when their values change
¾ Complex timing relationship are easy to define
¾ A test bench can become very large for complex
tests module inline_tb;
reg [7:0] data_bus, addr;

wire [7:0] results;
DUT u1 (data_bus, addr, results);
initial
fork
data_bus = 8’h00;
addr = 8’h3f;
#10 data_bus = 8’h45;
#15 addr = 8’hf0;
#40 data_bus = 8’h0f;
#60 $finish;
join
endmodule
Example
Example
26
Stimulus From Loops
¾ The same set of stimulus variables are modified in
every iteration
¾ Timing relationships are regular in nature
¾ Code is compact
module loop_tb;
reg clk;
reg [7:0] stimulus;
wire [7:0] results;
integer i;
DUT u1 (clk, stimulus, results);

always begin // clk generator
#5 clk = ~clk;
end
initial
begin
clk = 1’b1;
for (i = 0; i < 256; i = i + 1)
@ (negedge clk) stimulus = i;
#20 finish;
end
endmodule
2005 VLSI Training Course - 53 - Example
Example
Stimulus From Arrays

¾ The same set of stimulus variables are modified in
every iteration
¾ Stimulus can be read into an array directly from a file
module array_tb;
reg [7:0] data_bus, stim_array[0:15];

integer i ;
DUT u1 (data_bus, addr, results);
initial
begin
// load array with values
#20 stimulus = stim_array[0];
#30 stimulus = stim_array[15]; // in line
#20 stimulus = stim_array[1];
for (i = 14; i > 1; i = i - 1) // from loop
#50 stimulus = stim_array[i];
#30 finish;
end
endmodule
Example
Example
27
Stimulus From Vector
module read_file_tb;
parameter num_vecs = 256;

reg [7:0] data_bus, stim[0:num_vecs-1:0];
wire [7:0] results
integer i ;
DUT u1 (data_bus, results);
initial
begin // Vectors are loaded
$readmemb(“vec.txt”, stim);
for (i = 0; i < num_vecs; i = i + 1)
#50 data_bus = stim[i];
end
endmodule
Example
Example
Outline

¾ Introduction to Verilog-
Verilog-XL simulator
28
Simulation Algorithms
¾ There are three broad categories of simulation

algorithm
• Time-based (used by SPICE simulators)
• Event-based (used by Verilog-XL and NC-Verilog simulators)
• Cycle-based
Simulation of a Verilog Model
¾ Verilog simulation takes the following steps

• Compilation
• Initialization
During initialization, parameters are initialized, undriven nets
default to z, and other nodes get the value x. These values
propagate through the design hierarchy as they do during a real
simulation
• Simulation
Simulation commences at time zero.
Initial and always block are not preceded by timing controls.
These assignments can trigger events at time zero and at later
times
29
Invoking Verilog-XL
¾ Syntax
• verilog [verilog-xl_operations] design_files
¾ No command line options
• verilog mux.v test.v
¾ Using the -c command-line option to check the
syntax and connectivity of your design without
actually simulating
• verilog –c mux.v test.v
¾ Using the -f command-line option to specify a file
that contains command-line arguments
• verilog –f run.f run.f
mux.v
test.v
-c
Outline

30
Delay Calculators
¾ Two categories of delay calculators

• Delay calculators embedded in the tools
• Custom delay calculators
User-defined
Vendor-supplied
Standard Delay Format
¾ Standard Delay Format (SDF) provides a tool-

independent, uniform way to represent timing
information
¾ SDF represent
• Module path delays – conditional and unconditional
• Device delays
• Interconnect delays
• Port delays
• Timing checks
• Path and net timing constraints
31
SDF Annotator
¾ Use the $sdf_annotate system task to annotate

SDF timing information
¾ You can invoke this task interactively or from within
the source code
$sdf_annotate(“sdf_file”,[module_instance,
“config_file”, “log_file”, “mtm_spec”,
“scale_factors”, “scale_type”]);
Example
Example
Running the SDF Annotator
module top;
...
cpu u1 (...);
fpu u2 (...);
dma u3 (...);
...
initial
begin
$sdf_annotate(“sdffiles/cpu.sdf”,m1,,”logfiles/cpu_sdf.log”);
$sdf_annotate(“sdffiles/fpu.sdf”,m1,,”logfiles/fpu_sdf.log”);
$sdf_annotate(“sdffiles/dma.sdf”,m1,,”logfiles/dma_sdf.log”);
end
...
endmodule
Example
Example
32
Reference
1. 國家晶片系統設計中心, “CIC訓練課程: Verilog Training Manual,” July. 2004
33

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Verilog HDL

Teaching Assistant: Lien-Fei Chen (陳聯霏)

Multimedia & Communication IC Design Lab

2005 VLSI Training Course -1-

¾ Introduction to Verilog HDL

2005 VLSI Training Course -2-

¾ High-level programming language with special

2005 VLSI Training Course -3-

Why Use an HDL ?

¾ A hardware description language

2005 VLSI Training Course -5-

A Brief History of Verilog

¾ 1981 – Gateway Design Automation released

2005 VLSI Training Course -6-

2005 VLSI Training Course -7-

Levels of Abstraction for Verilog

module mux2to1 (a, b, sel, out);

¾ The behavioral/RTL description does not handle unknown and

2005 VLSI Training Course -9-

Behavioral and RTL (2/2)

2005 VLSI Training Course - 10 -

No glue logic within top module

2005 VLSI Training Course - 11 -

¾ Introduction to Verilog HDL

2005 VLSI Training Course - 12 -

module MyCPU (clk, rst, data, address, result);

2005 VLSI Training Course - 13 -

Value Set and Numbers

2005 VLSI Training Course - 14 -

2005 VLSI Training Course - 15 -

Data Types (2/2)

2005 VLSI Training Course - 16 -

2005 VLSI Training Course - 17 -

¾ Reduction operators (unary)

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module inv (in, out);

¾ Use parameters to declare run-time constants

parameter cycle = 20, prop_del = 3,

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module mod (in1, in2, out);

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Overriding the Values of

module mod (in1, in2, out);

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¾ You can declare an array of registers in Verilog

¾ An array of the datatype reg is often called a memory

¾ You can use parameters to model memory size

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reg [7:0] mema [0:255]; // declare memory called mema

2005 VLSI Training Course - 24 -

2005 VLSI Training Course - 25 -

¾ All procedure blocks are activated at time 0

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¾ Simple delays, or pound delays

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module reg_adder(clk, a, b, out);

2005 VLSI Training Course - 28 -

if (<expression>) if (index > 0)

2005 VLSI Training Course - 29 -

Multi-way Decision Statements

if (<expression>) reg [15:0] rega;

2005 VLSI Training Course - 30 -

module swap_vals (clk, rst, a, b);