IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.

4, APRIL 2011 1197

Effects of Device Structure and Back Biasing on HCI

and NBTI in Silicon-on-Thin-BOX (SOTB)
CMOSFET
Takashi Ishigaki, Member, IEEE, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii, Member, IEEE, and
Shin’ichiro Kimura, Senior Member, IEEE

Abstract—The silicon-on-thin-buried-oxide (SOTB) CMOSFET

is one of the strong candidates for further scaling because of its
smallest Vth variation and back-bias controllability. This study
focuses on its reliability, i.e., the hot-carrier-injection (HCI) degra-
dation for the n-channel MOS and the negative-bias temperature
instability (NBTI) for p-channel MOS. A comparison of the SOTB
CMOSFET with a conventional bulk CMOSFET showed that the
SOTB structure, which has a low-dose channel without a halo
implant, produces higher reliability. The impact of the wide-range
back biasing in SOTB devices on reliability was determined, i.e.,
the back biasing changes the mechanism of the HCI degradation
but does not affect the NBTI degradation. Fig. 1. Schematic cross section of the SOTB MOSFET with the integrated
bulk MOSFET and a TEM image of the SOTB MOSFET.
Index Terms—Back bias, back gate, fully depleted silicon on in-
sulator (FD-SOI), hot-carrier injection (HCI), negative-bias tem-
perature instability (NBTI), reliability, thin buried oxide (BOX).
dopant fluctuation [3]–[5]. A value of the Pelgrom coefficient,
which is often used as an index of the Vth variation, is about half
I. I NTRODUCTION of that of the conventional bulk device of the same technology
generation [3]. The thin BOX and the impurity doping in the

T HE SCALING of conventional bulk CMOSFETs, which

has continued for a long time, is approaching its end.
In particular, increasing the channel dopant concentration to
counter the short-channel effect (SCE) increases the variation in
the threshold voltage Vth . This is one of the main reasons why
the supply voltage Vdd could not be decreased as the scaling
law assumes. Unless Vdd is reduced, the power consumption
of large-scale integrations will significantly increase in both
operational and standby-leakage states [1].
Recently, fully depleted silicon-on-insulator (FD-SOI) tran-
sistors or fin-shaped FETs have attracted much attention as a
promising technology to prolong the scaling of CMOSFETs.
These device structures have high immunity from the SCE even
with an intrinsic or low-dose channel. An FD-SOI CMOSFET
with an ultrathin buried oxide (BOX), called a “silicon-on-
thin-BOX” (SOTB) [2], as illustrated in Fig. 1, was previously
developed. Its ultrathin SOI and BOX layers make the transistor
highly immune from the SCE, and its low-dose channel without
a halo implant suppresses the Vth variation due to the random
Manuscript received October 31, 2010; revised December 1, 2010,
December 19, 2010 and January 13, 2011; accepted January 13, 2011. Date
of current version March 23, 2011. The review of this paper was arranged by
Editor J. S. Suehle.
The authors are with Central Research Laboratory, Hitachi Ltd.,
Kokubunji-shi 185-8601, Japan (e-mail: takashi.ishigaki.ug@hitachi.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2107520
0018-9383/$26.00 © 2011 IEEE
substrate just beneath the thin BOX enable a multiple Vth
design [3]. This thin BOX and this doped region also enable
wide-range back-gate controllability, which optimizes both the
performance and the power after the device fabrication [6], [7].
Results for CMOS devices with the same structure as the SOTB
were reported by several groups [8]–[12]. Another advantage
of the SOTB structure is that bulk transistors for input–output
and analog circuits, operating at a voltage higher than the
maximum operating voltage of an FD-SOI device, can be easily
integrated by simply removing both the thin SOI and BOX
layers [13].
While some intrinsic problems concerning an FD-SOI struc-
ture (such as low breakdown voltage) are well known [14],
the reliability of this structure is not fully understood. In
particular, in the SOTB structure, the electric-field strength in
the device is different from that in conventional thick-BOX
SOI devices because of the thin BOX and the efficacy of back
biasing. In this paper, the hot-carrier injection (HCI) and the
negative-bias temperature instability (NBTI) were investigated
as representative reliability issues for n- and p-channel MOSs
(NMOS and PMOS), respectively. Their characteristics were
compared with the ones of conventional bulk CMOSFETs. The
electric fields in the CMOS devices were simulated by using
a 2-D device simulator. Moreover, the wide-range back biasing
through the thin BOX is one special feature of the SOTB device.
The influences on both the HCI degradation and the NBTI
degradation on the device performance were examined for the
first time.
1198
Fig. 2. Comparison of Id –Vd characteristics between the SOTB and bulk
NMOSFETs.
II. D EVICE FABRICATION AND
E LECTRICAL C HARACTERIZATION
The SOTB CMOSFETs were fabricated by using a standard
65-nm low-standby-power CMOS technology combined with
additional raised source/drain (S/D) and fully silicided (FUSI)
metal-gate processes. The details of the fabrication process
are described elsewhere [3], [13]. The thicknesses of the thin
SOI layer tSOI and the thin BOX layer tBOX were about
12 and 10 nm, respectively. Similar to the conventional bulk
CMOS process, impurity implantations for both a well and a
channel were done in the SOTB CMOS process. The channel
implant was however done for a substrate beneath the BOX
with a deeper projection range, not for the SOI channel layer.
Hence, the SOI layer was very lightly doped (i.e., density lower
than 1017 cm−3 ) without using a halo implant. In contrast,
the substrate just beneath the BOX layer was doped to about
1018 cm−3 to adjust Vth (in case where Vth was about 0.4 V).
Conventional bulk CMOSFETs, which have a polycrystalline-
silicon (poly-Si) gate and a doped channel with a halo implant,
were also fabricated for comparison. The gate dielectrics in all
devices were SiON with a 1.9-nm equivalent oxide thickness.
Since the universal mobility was obtained [15], the Si/SiO2
interface could be considered the same quality.
As for the stress-effect measurements, the HCI was eval-
uated at room temperature, and the NBTI was evaluated at
125 ◦ C. The drain-current–gate-voltage (Id –Vg ) characteristics
were measured at intervals of a certain stress time without a
recovery operation. Vth values were determined by saturation
extrapolation. The drain voltage Vd for the saturation condition
was 1.2 V. The criteria for the lifetime of the SOTB CMOSFETs
was set to 10% degradation from the initial states of the ON-
current Ion or Vth at Vd = 1.2 V.
III. R ESULTS AND D ISCUSSION
A. Current–Voltage Characteristics of the SOTB CMOSFET
First, the current–voltage characteristic of the SOTB
NMOSFET was compared with that of a conventional bulk
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
NMOSFET, as shown in Fig. 2. The gate length Lg and width
Wg used in this paper were 55 nm and 8 μm, respectively.
The device characteristics such as Vth , ON-current Ion , and
OFF-current Ioff at Vdd = 1.2 V of the NMOSFETs were
nearly identical. The SOTB NMOSFET achieved a driving
performance comparable with the bulk NMOSFET because the
raised S/D structure sufficiently lowered the S/D resistance
Rsd , namely, to less than 200 Ω · μm [6]. No self-heating
effect was observed because the BOX layer was very thin (i.e.,
10 nm) in contrast to that of conventional SOI devices (over
100 nm). No kink effect was observed either. This indicates a
fully depleted operation without the floating-body effect. The
drain breakdown voltage of the SOTB NMOSFET is about
1 V lower than that of the bulk NMOSFET. In FD-SOI de-
vices, holes, which are generated by impact ionization at the
drain edge, flow to the source. This hole current biases the
source–body junction forward and amplifies the drain current
Id due to a parasitic bipolar effect [16]. When the drain voltage
Vd is over 2 V, the Id value of the SOTB NMOSFET starts to
rapidly increase, which is independent of the gate voltage Vg .
It is thought that the impact ionization occurred because of the
potential difference between the source and the drain in short-
channel devices, unlike longer channel devices, in which the
breakdown voltage depends on the gate voltage. Note that the
drop of the drain–source voltage Vds due to the large current
(e.g., Id = 1000 μA/μm) through Rsd (200 Ω · μm) is small
enough (0.2 V) to be ignored.
B. HCI in the SOTB NMOSFET
In conventional bulk MOSFETs, the largest degradation due
to the HCI was used to occur at Vg = Vd /2, which corresponds
to the maximum substrate current Isub . For recent short-channel
devices, however, the worst case of the HCI has been reported
to change to the channel-hot-electron (CHE) condition at Vg =
Vd . On the other hand, since the hole current due to the impact
ionization flows to the source in SOI MOSFETs, it cannot be
evaluated by monitoring Isub . We confirmed that the worst case
degradation of the HCI is at Vg = Vd in both the SOTB and
bulk NMOSFETs, as shown in Fig. 3. The time dependence of
the threshold voltage shift ΔVth is represented by the power
law as
ΔVth = Atn . (1)
Here, n is the gradient of the straight line in Fig. 3. The
value of around 0.5 at the CHE condition (Vg = Vd ) indicate
that the degradation is caused by the interface-trap generation
[17]. It was reported that the hot-electron injection by the CHE
generates the interface trap and causes less electron trapping in
the case of a thin gate oxide [18]. As for the results plotted in
Fig. 3, the power-law slopes are all around 0.5 and independent
of Vg . Hence, the mechanism of the interface-trap generation
is the same within the Vg range in the figure, and the dominant
factor is presumed to be the potential gradient between the drain
and the source in both the SOTB and bulk devices. The amount
of the degradation depends on the total drain current modulated
by Vg .
ISHIGAKI et al.: EFFECTS OF DEVICE STRUCTURE AND BACK BIASING ON HCI AND NBTI
Fig. 3. Threshold-voltage shift ΔVth with dependence on the gate bias Vg under the HCI stress in the (a) SOTB and (b) bulk NMOSFETs.
Fig. 4. Stress bias Vstress dependence of the HCI degradation in the SOTB
device.
Fig. 4 shows the dependence of the stress bias Vstress of the
HCI degradation at Vg = Vd . The power-law slopes are also
around 0.5 and independent of Vstress . Hence, the interface-
trap-generation mechanism is thought to be the same even in
the case of Vstress over 2 V, in which the parasitic bipolar effect
occurs. The HCI lifetimes, defined as the 10% degradation of
Ion , under the CHE condition are shown in Fig. 5. The SOTB
lifetime dependence on Vstress produces a longer lifetime at
the operating voltage of 1.2 V than that of the bulk device.
To clarify the reason for this longer lifetime, the electric-field
strengths in the devices with and without a halo implant were
simulated by using a 2-D device simulator. The lateral electric-
field strength Ex of the silicon surface along the channel
(x-direction) at Vstress = 1.2 and 2.4 V are shown in Fig. 6(a).
The profiles of net doping in the SOTB structure with and
without a halo implant are also shown in Fig. 6(b). Ex at the
drain edge of the devices with and without a halo implant are
almost the same at Vstress = 2.4 V due to the high drain voltage.
Meanwhile, that of the device without a halo implant becomes
about 10% lower than that of the devices with a halo implant
at 1.2 V, which is due to the abrupt p-n junction between the
1199
Fig. 5. Comparison of the HCI lifetime between the SOTB and bulk
NMOSFETs for Vd = Vg .
channel and the drain. This is supposed to be the reason why
the dependence on Vstress is different between the SOTB and
bulk devices. The advantage of having no halo implant was also
experimentally confirmed in the SOTB device [19].
C. Effect of Back Biasing in the Case of the HCI
A technique for applying the substrate bias Vb adaptively
according to the state of operation has been applied in late
years [20]. However, with regard to the present scaled bulk
CMOSFETs, it is becoming difficult to apply Vb because of
the increase in the p-n junction leakage current between the
S/D and the substrate. In SOTB devices, the wide-range back
biasing including a forward bias higher than 0.6 V, which can
never be applied in a bulk device, is possible without any
leakage due to the BOX layer. It significantly changes not only
the drive currents but also the strength of the vertical electric-
field strength Ey .
Fig. 7 shows the dependences of the HCI characteristics on
Vb at Vstress = 2.4 V. The slope of the power law changes
from 0.4 at forward Vb to over 1.0 at reverse Vb . A slope of
1200
Fig. 6. (a) Simulated lateral electric-field strengths Ex along the channel surface in SOTB structures with or without a halo implant at (dashed) Vstress = 2.4
and (solid) 1.2 V. (b) Net doping profiles along the channel surface in the SOTB structures with and without a halo implant.
Fig. 7. Dependence of HCI characteristics on the back bias Vb at
Vstress = 2.4 V.
1.0 at Vg = Vd was reported in [18]. In that study, electron
trapping sites were produced by a highly energetic hot-electron
injection into the oxide. This phenomenon is different from
the electron trapping before stressing (where a power-law slope
of 0.2 is typical). When the reverse back biasing is applied in
an SOTB device, the highly energetic hot electrons due to the
high drain bias would be injected into the gate oxide by the
enhanced Ey and would generate trapping sites, particularly at
the drain edge. As a result, the electron trapping is thought
to be the dominant mechanism in the reverse back biasing.
The simulated Ey at the silicon surface along the channel is
shown in Fig. 8. Although the electrostatic potential φ of the
silicon surface becomes higher toward the drain, the drain side
of the channel (beyond the pinchoff point) is depleted by a high
drain bias. In the depleted region, φ rapidly changes into the
vertical y-direction, depending on the φ value of the substrate
beneath the BOX layer. Hence, Ey = −dφ/dy increases only
at the drain edge in the reverse back biasing. It is noted that the
lateral electric field Ex does not depend on Vb (not shown). On
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
the other hand, the worst condition is the forward back biasing
because a large number of hot electrons was generated by the
large drain current (37% larger than that at Vb = 0 V), although
Ey decreases under the forward back biasing. In Fig. 7, the
large drain current is a main factor for the amount of the
HCI degradation. Meanwhile, Ey is considered to influence a
mechanism of the degradation. To evaluate the lifetime of this
forward-bias state, condition Vb = Vstress was used. Even under
this forward back-biasing condition, the lifetime is sufficiently
longer than ten years, as shown in Fig. 9.
D. NBTI in the SOTB PMOSFET
The NBTI has not been extensively investigated in
FD-SOI devices, although it is recognized as a major reliability
issue in recent bulk PMOSFETs. We first compared the gate-
leakage currents of the SOTB PMOSFET with that of the bulk
PMOSFET, as shown in Fig. 10. In the FUSI-gate SOTB
PMOSFET (a low-dose channel without a halo implant) and
the poly-Si-gate bulk PMOSFET (a high-dose channel with
a halo implant), the Ig –Vg characteristics are almost the
same. The Ig –Vg characteristic of the poly-Si-gate SOTB
PMOSFET (a low-dose channel with a halo implant) is also
the same, although Vth is different. Hence, the gate di-
electrics of all devices are considered to be a like quality.
Then, the NBTI characteristics of the poly-Si-gate SOTB
PMOSFET and the bulk PMOSFET were compared, as shown
in Fig. 11. The characteristic of the SOTB PMOSFET with
a halo implant was also plotted. The gate bias Vg is set to
be the same stress for each device as Vg − Vth = −2.0 V at
125 ◦ C. The same power-law slopes suggest the same degrada-
tion mechanism in the SOTB device as that in the bulk device.
The n value of around 0.3 presumably indicates the well-known
reaction/diffusion model, which is the interaction of holes with
hydrogen that breaks Si–H bonds at the Si/oxide interface and
the hydrogen diffusion away from the interface into the gate
oxide, generating interface traps [21]. Although the typical n
value was 0.25 in this theory, a value over 0.3 was reported
ISHIGAKI et al.: EFFECTS OF DEVICE STRUCTURE AND BACK BIASING ON HCI AND NBTI
Fig. 8. Simulated vertical electric-field strength Ey along the channel surface at forward, reverse, and no back biasing under the HCI stress.
Fig. 9. HCI lifetime of the SOTB NMOSFET under the forward back biasing
(i.e., worst case degradation).
Fig. 10. Id , Ig –Vg characteristics of the poly-Si-gate bulk (a high-dose
channel with halo), poly-Si-gate SOTB (a low-dose channel with halo), and
FUSI-gate SOTB (a low-dose channel without halo) PMOSFETs.
in the case of nitrided gate oxide, in which the introduction of
nitrogen creates a number of oxide traps [22], [23]. The NBTI
degradation of the SOTB device with a halo implant (at 15 keV)
1201
Fig. 11. Comparison between NBTI characteristics of the SOTB and bulk
PMOSFETs.
is severer than that without a halo implant. The degradation
in the bulk device with a halo implant at 30 keV is further
enhanced. These results indicate that the NBTI degradation is
enhanced due to additional exposed Si–H bonds caused by the
halo and/or a high-energy implant [24]. The NBTI lifetime for
the SOTB PMOSFET is estimated to greatly exceed the ten-
year specification, as shown in Fig. 12.
E. Effect of Back Biasing in the Case of NBTI
The effect of the back biasing Vb on the NBTI degradation in
the FUSI-gate SOTB PMOSFET, as shown in Fig. 13, was also
investigated. In all three cases, there is a little influence of Vb on
the NBTI degradation in both forward and reverse back biasing.
This result is presumably due to the fact that the influence of
back biasing on the electric fields at the channel surface and/or
in the gate oxide is mostly screened by an inversion layer.
The simulated vertical electric field Ey and hole concentration
under the gate electrode as a function of the back-bias voltage
Vb are shown in Fig. 14. Ey in the gate oxide is determined by
1202
Fig. 12. NBTI lifetime of the SOTB PMOSFET.
Fig. 13. Dependence of NBTI characteristics on the back bias Vb .
the gate bias (not by the back biasing). It is clear that the hole
concentration at the silicon surface is slightly influenced by the
back biasing. In addition, the substrate hot-hole injection under
the reverse back biasing, which enhances the NBTI degradation
in the conventional bulk PMOS [25], does not occur in the
SOTB structure because of the BOX layer. It is also noted that
vertical electric field Ey at the Si surface must be lower in
SOTB devices with a midgap gate metal and a low-dose channel
than that in bulk devices with a poly-Si gate and a high-dose
channel.
IV. C ONCLUSION
The effects of the device structure and wide-range back
biasing on the HCI and the NBTI in SOTB CMOSFETs have
been studied. It has been shown that the HCI degradation in a
NMOSFET is mainly caused by the CHE injection generating
interface traps, which is the same mechanism as that in a
conventional bulk device. However, the lifetime of a SOTB
device is longer than that of a bulk one because of a suppressed
lateral electric field at the drain edge (due to having no halo
implant). It has been found that the mechanism of the interface-
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
Fig. 14. Simulated vertical electric-field strength Ey and hole concentration
under the gate as a function of the back-bias Vb under the NBTI stress.
trap generation changes to electron trapping under the reverse
back biasing because of the enhanced vertical electric field
at the drain edge, but the worst case HCI degradation occurs
in the forward back biasing because of the increased drive
current. The NBTI degradation in the SOTB PMOSFET can
be explained by the conventional reaction/diffusion model. The
long NBTI lifetime has been confirmed because of the low
surface Ey and of having no halo implant. In addition, it has
been demonstrated that the back biasing has a small impact on
the NBTI degradation because of the SOTB structure. These
results indicate the superior features of the SOTB technology
in terms of reliability, even under a high level of performance
boosting (i.e., back biasing).
ACKNOWLEDGMENT
The authors would like to thank the staff at Renesas Elec-
tronics Corporation (Renesas) and Hitachi Central Research
Laboratory (HCRL) for fabricating the devices. The authors
would also like to thank T. Iwamatsu, H. Oda, and Y. Inoue
of Renesas for their assistance with the device fabrication, and
K. Torii of HCRL and M. Odaka and K. Kasai of the Hitachi
Research and Development Group for their encouragement.
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[11] F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J.-P. Noel, degrees in electrical and electronic engineering from
Kobe University, Kobe, Japan, in 1999 and 2001,
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M.-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, Division, Nippon Electric Company Corporation,
Otsu, Japan, where he was involved in the research
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he has been with the Central Research Labora-
(UT2B) SOI technology for 20nm low power CMOS and beyond,” in
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isolated back gates and 30nm LG high-k/metal gate,” in VLSI Symp. Tech.
Mr. Ishigaki is a member of the IEEE Electron Devices Society.
Dig., Jun. 2010, pp. 43–44.
[13] T. Ishigaki, R. Tsuchiya, Y. Morita, N. Sugii, S. Kimura, T. Iwamatsu,
T. Ipposhi, Y. Inoue, and T. Hiramoto, “Wide-range threshold volt-
age controllable silicon on thin buried oxide integrated with bulk com-
plementary metal oxide semiconductor featuring fully silicided NiSi
gate electrode,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2585–2588,
Apr. 2008.
[14] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi,
M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mech-
anism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, Ryuta Tsuchiya received the B.S., M.S., and Ph.D.
vol. 37, no. 9, pp. 2015–2021, Sep. 1990. degrees in material science from the Tokyo Institute
[15] H. Yoshimoto, N. Sugii, D. Hisamoto, S. Saito, R. Tsuchiya, and of Technology, Tokyo, Japan, in 1993, 1995, and
S. Kimura, “Extension of universal mobility curve to multi-gate 1998, respectively.
MOSFETs,” in IEDM Tech. Dig., Dec. 2007, pp. 703–706. Since 1998, he has been with the Central Re-
[16] J. Chen, F. Assaderaghi, H.-J. Wann, P. Ko, C. Hu, P. Cheng, and search Laboratory, Hitachi Ltd., Tokyo, where he
T.-Y. Chan, “An accurate model of thin film SOI MOSFET breakdown has been engaged in research on the fabrication and
voltage,” in IEDM Tech. Dig., Dec. 1991, pp. 671–674. characterization of high-performance and low-power
[17] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consis- metal–oxide–semiconductor field-effect transistors,
tent model for the hot-carrier degradation in n-channel and p-channel including thin-film silicon-on-insulator and buried
MOSFETs,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2194– oxide transistors.
2209, Dec. 1988. Dr. Tsuchiya is a member of the Japan Society of Applied Physics.
[18] N. Koike and K. Tatsuuma, “A drain avalanche hot carrier lifetime model
for n- and p-channel MOSFETs,” IEEE Trans. Device Mater. Rel., vol. 4,
no. 3, pp. 457–466, Sep. 2004.
[19] T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, and
S. Kimura, “HCI and NBTI including the effect of back-biasing in thin-
BOX FD-SOI CMOSFETs,” in Proc. Int. Rel. Phys. Symp., May 2010,
pp. 1049–1052.
[20] M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo,
A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic Yusuke Morita received the B.S. and M.S. degrees
voltage and frequency management for a low-power embedded micro- in material engineering from Shonan Institute of
processor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28–35, Technology, Fujisawa, Japan, in 1999 and 2001,
Jan. 2005. respectively, and the Ph.D. degree from Tokyo Insti-
[21] S. Mahapatra, P. B. Kumar, and M. A. Alam, “Investigation and modeling tute of Technology, Tokyo, Japan, in 2004.
of interface and bulk trap generation during negative bias temperature Since 2005, he has been with the Central Research
instability of p-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 9, Laboratory, Hitachi Ltd., Tokyo, where he has been
pp. 1371–1379, Sep. 2004. working on the research and development of comple-
[22] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, mentary metal–oxide–semiconductor devices includ-
and T. Horiuchi, “NBTI enhancement by nitrogen incorporation into ul- ing silicon-on-insulator metal-oxide-semiconductor
trathin gate oxide for 0.10-μm gate CMOS generation,” in VLSI Symp. field-effect transistors.
Tech. Dig., Jun. 2000, pp. 92–93. Dr. Morita is a member of the Japan Society of Applied Physics.
1204
Nobuyuki Sugii (M’08) received the B.S., M.S., and
Ph.D. degrees in applied chemistry from the Uni-
versity of Tokyo, Tokyo, Japan, in 1986, 1988, and
1995, respectively.
In 1988, he joined the Central Research Labo-
ratory, Hitachi Ltd., Tokyo, where he was engaged
in the research and development of oxide super-
conducting materials and devices until 1996 and
has been working on the research and develop-
ment of SiGe materials and complementary metal–
oxide–semiconductor devices, including silicon-on-
insulator and strained-silicon metal–oxide–semiconductor field-effect transis-
tors, since 1996. From 1991 to 1994, he was a Research Scientist with
the Superconductivity Research Laboratory, International Superconductivity
Technology Center. Since 2004, he has been also a Visiting Professor with the
Tokyo Institute of Technology, Tokyo.
Dr. Sugii is a member of the Japan Society of Applied Physics and the IEEE
Electron Devices Society. He was a member of the program subcommittees of
the Solid State Devices and Materials Conference from 2002 to 2004.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
Shin’ichiro Kimura (M’87–SM’07) was born in
Miyagi, Japan, in 1955. He received the B.S. and
M.S. degrees in materials science from Tohoku Uni-
versity, Sendai, Japan, in 1978 and 1980, respec-
tively, and the Ph.D. degree from the University of
Tokyo, Tokyo, Japan, in 1989. The subject of his
Ph.D. dissertation was low-temperature oxidation of
silicon by microwave oxygen plasma.
Since 1980, he has been with the Central Research
Laboratory, Hitachi Ltd., Tokyo, where he was first
involved in the research of high-dielectric-constant
insulators. He then worked on the plasma oxidation of silicon. From 1986
to 1988, he worked on the process design and device characterization for
metal–oxide–semiconductor (MOS) dynamic memory for 16 Mb. From 1988
to 1989, he was a Visiting Research Associate with the University of Warwick,
Coventry, U.K. He is currently a Chief Senior Researcher with Central Research
Laboratory. His current research interests include new submicrometer MOS
field-effect transistor devices and processes.
Dr. Kimura is a member of the Japan Society of Applied Physics and the
IEEE Electron Devices Society (EDS). He has served as a member of the
Solid State Devices and Materials Conference from 1995 to 1998. He was as a
member of the steering committee in 2003, the Program Chair in 2005, and the
Conference Chair in 2007 of the Symposium on Very Large Scale Integration
Technology Symposia. From March 2002 to 2007, he was one of the Editors
of IEEE TRANSACTIONS ON ELECTRON DEVICES. He has also served as the
Vice Chair of the IEEE EDS Japan Chapter. Since 2010, he has been the Chair
of IEEE EDS Tokyo Chapter.