VN/VP13 Series

Application Note
AN–D8

High Voltage Pulser Circuits

Introduction Circuit Description/Design Considerations

The high voltage pulser circuit shown in Figure 1 utilizes Supertex
complementary N- and P-channel DMOS transistors to achieve
excellent performance and efficiency with minimal components.
The output voltage swings are -100V to +100V. Rise and fall
times are less than 10 nsec while sourcing and sinking over 0.75
and 1.0 amps respectively. The output is conveniently controlled
by TTL or CMOS input signals. The VDD supply voltage, however,
needs to be at the same value as the input logic high value.
High voltage, high speed, and high current pulses at low duty
cycles are required in several applications. Ultrasound cleaning
equipment, flaw detection, medical imaging, and test instruments
are but a few examples. Complementary N- and P-channel
DMOS transistors, VN1306N3, VP1306N3, TN0104N3,
TP0102N3, TP0620N3, and TN0620N3 are used for their low
threshold voltages, low input capacitances and high output
current capabilities. These are essential features to generate
high voltage pulses with high speeds and currents. Another
aspect considered was their cost-effective TO-92 package,
which saves board space.
The high voltage pulser in Figure 1 consists of 3 basic stages: (A)
input signal interface, (B) high current buffer and level translation,
and (C) high voltage and current output drivers. Each stage has
its own specific requirements for device parameters, which will
be discussed in the following section.
Stage 1:
Stage 1, consisting of VN1306N3 and VP1306N3, is an input
stage to interface directly with TTL or CMOS logic signals.
Low input capacitance and fast switching speed are the most
important considerations in this stage. The VN1306N3 and
VP1306N3 are chosen for their low in-put capacitance, 35pF
maximum, and their 2ns typical/5ns maximum td(on), tr,
td(off) and tf switching speed. This will minimize loading and
distortion on the input drive signals. Often the input signals
are from fairly resistive sources, which may be in the order
of 100’s of ohms, creating large RC constants. Low CISS and
CRSS will allow the gate voltage to charge past the transistors’
threshold voltage rapidly, to accomplish high speed switching.

VPP = +100V The low threshold ratings will accommodate TTL and CMOS
VDD = 10V
compatibility. Max threshold ratings, VGS(th), for VN1306N3
R and VP1306N3 are 2.4V and -3.5V respectively. For the
1K +
15V ‘worst case’ design consideration, VN1306N3 will turn on
VP1306N3 TP0102N3
- when the input signal voltage reaches 2.4V. For a given input
signal voltage rise and fall time of 50ns for 0 to 10V, the time
A TP0620N3 required for the input to reach 2.4V is 12ns. For VP1306N3,
C 0.01µF GP time required to turn on is about 35ns. Once the devices are
VN1306N3 TN0104N3 turned on, the output voltage rising and falling edges will
have a waveform similar to that of an RC circuit where R is
the on-resistance of the transistor and C is the total equivalent
Inputs
VDD = 10V
VOUT capacitance the transistor is driving.
RL In addition to performing the interface to TTL and CMOS
100Ω signals and improving rise and fall times, Stage 1 is also a
VP1306N3 TP0102N3
high current low impedance buffer. Output currents of more
GN than 250mA source and 500mA sink (based on ID(ON)
B TN0620N3 specifications of these devices) are available to adequately
C 0.01µF
+
drive the inputs of the 2nd stage.
VN1306N3 TN0104N3
R 15V
1K -

VNN = -100V

Figure 1. High Voltage Pulser

05/16/01

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indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products,
1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
 VN/VP13 Series Applications

Stage 2: During power up and power down conditions, it is possible for

Stage 2 provides high output peak currents, improves rise
and fall times, and performs high voltage level translation.
This stage consists of device types TN0104N3 & TP0102N3.
The Supertex low threshold DMOS transistors TN0104N3
and TP0102N3 provide typical output peak currents of 2.8
amps sink and 1.7A source. Such high currents are required
to adequately drive the input capacitances, including Miller
effect of the output transistors, to accomplish fast switching
speeds. The low threshold guaranteed maximum limits of
1.6V and -2.4V for TN0104N3 and TP0102N3 respectively
will further improve rise and fall time transitions. Resistor R
and Capacitor C provide the DC level shifting. Value of C
should be much larger than CIN of the output stage where CIN
is equal to CISS plus Miller effect: CIN = CISS + CRSS (GFS* RL).
Resistor value R is selected such that time constant RC is
much greater than the output high voltage pulse width
required.
With the source at +100V, gate voltage driving the P-channel of
the output stage are +100V and +90V to provide gate-to-source
drives of 0V and -10V. Similarly for the N-channel, with the
source at -100V, gate voltages are -100V and -90V to provide
0V and +10V gate-to-source drives.
Stage 3:
transient voltages greater than 20V to appear across the gate-
to-source on the output transistors. Maximum gate-to-source
voltage, VGS, is rated at ±20V. 15V zener diodes are connected
across the gate and source of the output transistors to protect
against such transient voltages. These diodes will not be zenering
during normal operation.
The zener protection diodes can be omitted if VPP and VNN can
be ramped slowly to their rail voltages during power up.
Input signals and corresponding voltages are shown in Figure 2.
Actual output waveforms with a 100Ω load for a 60 nsec and a
100 nsec positive and negative pulse are shown on Figures 3A
to 3D. VPP and VNN voltages can be varied without additional
changes within the circuitry. For example, VNN can be -10V and
VPP +190V for -10V to +190V pulses. Higher voltages and
currents can be accomplished with minimal changes.
10V
A
0V
10V
B
0V

Stage 3 is the output stage and consists of Supertex low 100V

GP
threshold DMOS discrete transistors TP0620N3 and
90V
TN0620N3. These devices have a breakdown voltage rating
of 200V minimum. Output voltage swings can switch from -
-90V
100V to +100V. Input capacitance is increased due to Miller
GN
effect, CIN = CISS + CRSS (GFS* RL). Low CRSS & CISS -100V
capacitance, high output current, low on-resistance and
200V breakdown voltage are required parameters for the 100V
output transistors. The Supertex TP0620N3 and TN0620N3 VOUT 0V
are ideally suited. Their guaranteed parameters are listed in -100V
Table 1:

Table 1
BVDSS (V) RDS(ON)(Ω) ID(ON) (A) CISS (pF) CRSS (pF)

DEVICE min typ max min typ max typ max

TN0620N3 200 4.0 6.0 1.0 110 150 10 35
TP0620N3 -200 9.0 12.0 -0.75 85 150 10 35

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Figure 3A. 60 nsec Output Pulse
Figure 3C. Positive Going Pulse
Optional Variations
The high voltage pulser in Figure 1 can be easily modified to suit
various high voltage pulser needs. Figures 4A to 4D show some
examples.
Figure 4A is a positive high voltage pulser with one end pulling
to ground. Basically, components R and C are not needed to
drive the N-Channel.
Figures 4B and 4C are high and low side open drain pulsers.
Supertex VP2450N3 and VN2450N3 are used to satisfy
applications with 500V pulse requirements.
Figure 4D utilizes Supertex VN0550N3 and VP0550N3 for high
voltage +250V push-pull 100mA requirements. Max input
capacitances of VN0550N3 and VP0550N3 are only 55pF and
60pF respectively. These can be driven directly from Stage 1
with minimal loss in switching speed.
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VN/VP13 Series Applications
Figure 3B. 100 nsec Output Pulse
Figure 3D. Negative Going Pulse
Conclusion
Supertex DMOS transistors are ideal for high speed, high
voltage, high current pulsing applications. Bipolar transistors
require base currents and time to recover from the saturation
region. MOSFETs do not require any DC gate current thus
enabling them to be easily driven with a simple AC coupling
scheme. Because of Miller effect on the high voltage outputs,
large peak currents are essential for the second stage to drive
the outputs hard for fast switching speeds. The Supertex line of
DMOS transistors has low input capacitance ratings making
them ideal candidates for high speed, high voltage pulsing
applications.
 VN/VP13 Series Applications







VPP = +500V
  VDD = 10V

+

   1K 15V
R
 µ VP1306N3 TP0102N3
-
  0.01µF
 Input VP2450N3
C

 
VN1306N3 TN0104N3






 VOUT
Ω

 
Figure 4B. High Side Open Drain High Voltage Pulser
 

 







 
Figure 4A. Push-Pull Positive High Voltage Pulser 


 

µ

















 
 µ


 µ
 



  


  

 

 








Figure 4C. Low Side Open Drain High Voltage Pulser Figure 4D. Push-Pull ±250V High Voltage Pulser

11/12/01

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