SIGPRO TECHNOLOGIES

2017 2018

VLSI
PROJECT PROJECT TITLE YEAR
CODE

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy 2017

SPVL01 Configurable Multipliers

SPVL02 Design of Power and Area Efficient Approximate Multipliers

SPVL03 Multipliers-Driven Perturbation of Coefficients for Low-Power Operation 2017

in Reconfigurable FIR Filters

SPVL04 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High- 2017

Speed yet Energy-Efficient Digital Signal Processing

SPVL05 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field 2017
Multiplier Using Factoring Technique

SPVL06 Design of an Area-Effcient Million-Bit Integer Multiplier Using Double 2017

Modulus NTT

SPVL07 Low Complexity and Critical Path based VLSI Architecture for LMS 2017
Adaptive Filter using Distributed Arithmetic Algorithm and Architecture
Design of Adaptive Filters With Error Nonlinearities

SPVL08 Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for 2017

Spin Hall Effect MRAM Device

SPVL09 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in 2017
the Presence of Process Variations

SPVL10 Approximate Error Detection With Stochastic Checkers 2017

SPVL11 A Fault Tolerance Technique for Combinational Circuits Based on 2017

Selective-Transistor Redundancy

SPVL12 Energy-Efficient VLSI Realization of Binary 64 Division With Redundant 2017

Number Systems

SPVL13 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression 2017

SPVL14 Power-Gated 9T SRAM Cell for Low-Energy Operation 2017

SPVL15 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder 2017

Families Using Adiabatic Quantum-Flux-Parametron Logic

SPVL16 Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET 2017
Technology for Low-Voltage Operation
SPVL17 A1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130- 2017
nm CMOS
SPVL18 Hybrid LUT/Multiplexer FPGA Logic Architectures 2017

SPVL19 A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational 2017

and Sequential Circuits
SPVL20 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design 2017

SPVL21 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM 2017

SPVL22 Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators 2017

SPVL23 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for 2017
DLL Based Clock Generator
SPVL24 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data 2017
Streams for MIMO
SPVL25 A High Throughput List Decoder Architecture for Polar Codes 2017

SPVL26 Unequal-Error-Protection Error Correction Codes for the Embedded 2017

Memories in Digital Signal Processors
SPVL27 Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC 2017
Decoding for MLC NAND Flash-Based Storage in Mobile Device
SPVL28 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval 2017
Checks
SPVL29 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable 2017
Applications
SPVL30 A Cellular Network Architecture With Polynomial Weight Functions 2017

SPVL31 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic 2017

SPVL32 Graph-Based Transistor Network Generation Method for Super gate Design 2017

SPVL33 Low-Cost High-Performance VLSI Architecture for Montgomery Modular 2017

Multiplication
SPVL34 LUT Optimization for Distributed Arithmetic-Based Block Least Mean 2017
Square Adaptive Filter
SPVL35 High-Performance NB-LDPC Decoder With Reduction of Message 2017
Exchange
SPVL36 High-Performance Pipelined Architecture of Elliptic Curve Scalar 2017
Multiplication Over GF(2m)
SPVL37 Implementing Minimum-Energy-Point Systems with Adaptive Logic 2017

SPVL38 A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for 2017
NAND-Flash Memory
SPVL39 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for 2017
MIMO Receivers
SPVL40 One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked 2017
Elements
SPVL41 Algorithm and Architecture of Configurable Joint Detection and Decoding 2017
for MIMO Wireless Communications with Convolution Codes
SPVL42 A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT 2017

SPVL43 Design and Implementation of High-Speed All-Pass Transformation-Based 2017

Variable Digital Filters by Breaking the Dependence of Operating
Frequency on Filter Order
SPVL44 A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard 2017
and Multimode Turbo Decoding
SPVL45 Code Compression for Embedded Systems Using Separated Dictionaries 2017

SPVL46 A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and 2017
Frequency Scaling
SPVL47 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a 2017
Wide Range of Supply Voltage Levels
SPVL48 A High-Speed FPGA Implementation of an RSD-Based ECC Processor 2017

SPVL49 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units 2017

SPVL50 Low-Power FPGA Design Using Memoization-Based Approximate 2017

Computing
SPVL51 A New Parallel VLSI Architecture for Real-time Electrical Capacitance 2017
Tomography
SPVL52 Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia 2017
RF Power Gating: A Low-Power Technique for Adaptive Radios
SPVL53 A Fully Digital Front-End Architecture for ECG Acquisition System with 2017
0.5 V Supply
SPVL54 Design and FPGA Implementation of a Reconfigurable 1024-Channel 2017
Channelization Architecture for SDR Application
SPVL55 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for 2017
Video Encoding
SPVL56 A Configurable Parallel Hardware Architecture for Efficient Integral 2017
Histogram Image Computing
SPVL57 A New Binary-Halved Clustering Method and ERT Processor for ASSR 2017
System
SPVL58 The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC 2017
Systems
SPVL59 Low-Power System for Detection of Symptomatic Patterns in Audio 2017
Biological Signals
SPVL60 Source Code Error Detection in High-Level Synthesis Functional 2017
Verification
SPVL61 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers 2017

SPVL62 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its 2017
Application
SPVL63 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM 2017
Cell
LOW POWER 2017

SPVL64 A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter 2017
Based on Delay Wrapping and Averaging
SPVL65 Coordinate Rotation-Based Low Complexity K-Means Clustering 2017
Architecture
SPVL66 Low-Power Scan-Based Built-In Self-Test Based on Weighted 2017
Pseudorandom Test Pattern Generation and Reseeding.
SPVL67 A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture 2017
for Low-Energy Consumption.

SPVL68 Resource-Efficient SRAM-based Ternary Content Addressable Memory 2017

SPVL69 Write-Amount-Aware Management Policies for STT-RAM Caches 2017

SPVL70 Fault Diagnosis Schemes for Low-Energy Block Cipher Midori 2017
Benchmarked on FPGA
SPVL71 High-Throughput and Energy-Efficient Belief Propagation Polar Code 2017
Decoder
SPVL72 High-Speed Parallel LFSR Architectures Based on Improved State-Space 2017
Transformations
SPVL73 Scalable Approach for Power Droop Reduction During Scan-Based Logic 2017
BIST
SPVL74 Stochastic Implementation and Analysis of Dynamical Systems Similar to 2017
the Logistic Map
SPVL75 Efficient Designs of Multi-ported Memory on FPGA 2017

SPVL76 High-Speed and Low-Latency ECC Processor Implementation Over 2017

GF(2m) on FPGA
SPVL77 An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s 2017
Chipto-Chip Interfaces With Source-Synchronous Clock
SPVL78 A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with 2017
Adaptive Injection Timing Alignment Technique
SPVL79 Hardware-Efficient Built-In Redundancy Analysis for Memory With 2017
Various Spares
SPVL80 Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search 2017
Algorithm
SPVL81 A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time 2017
Delay Control for Wireless Power Transmission
SPVL82 Scalable Device Array for Statistical Characterization of BTI-Related 2017
Parameters

AREA EFFICIENT/ TIMING & DELAY REDUCTION 2017

SPVL83 VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant 2017
Binary Encoding

SPVL84 ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware 2017

SPVL85 Hybrid Hardware/Software Floating-Point Implementations for Optimized 2017

Area and Throughput Tradeoffs
SPVL86 Efficient Soft Cancelation Decoder Architectures for Polar Codes 2017
SPVL87 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient 2017
Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
SPVL88 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal 2017
Multiplication
SPVL89 FPGA Realization of Low Register Systolic All-One-Polynomial 2017
Multipliers over GF (2m) and Their Applications in Trinomial Multipliers
SPVL90 Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic 2017
Nonbinary LDPC Codes Over Subfields.
SPVL91 Antiwear Leveling Design for SSDs With Hybrid ECC Capability. 2017

SPVL92 Energy-Efficient VLSI Realization of Binary64 Division with Redundant 2017

Number Systems
Audio, Image and Video Processing 2017

SPVL93 A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation 2017
for 8k Ultra-HD TV Encoding
SPVL94 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High- 2017
Speed yet Energy-Efficient Digital Signal Processing
SPVL95 Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations 2017

SPVL96 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy 2017

Configurable Multipliers

SPVL97 An FPGA-Based Hardware Accelerator for Traffic Sign Detection 2017

SPVL98 Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in 2017
the Presence of Process Variations
SPVL99 Time-Encoded Values for Highly Efficient Stochastic Circuits 2017

SPVL100 Design of Power and Area Efficient Approximate Multipliers 2017

VERIFICATION 2017

SPVL101 COMEDI: Combinatorial Election of Diagnostic Vectors From Detection 2017

Test Sets for Logic Circuits
SPVL102 Reordering Tests for Efficient Fail Data Collection and Tester Time 2017
Reduction
NETWORKING 2017

SPVL103 Multicast-Aware High-Performance Wireless Network-on-Chip 2017

Architectures
VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / 2017
DSCH3 - MICROWIND(um)
SPVL104 Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold 2017
Parallel Architectures
SPVL105 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field 2017
Multiplier Using Factoring Technique
SPVL106 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically 2017
Powered Read Port for Low Switching Power and Ultralow RBL Leakage
SPVL107 Delay Analysis for Current Mode Threshold Logic Gate Designs 2017

SPVL108 Area and Energy-Efficient Complementary Dual-Modular Redundancy 2017

Dynamic Memory for Space Applications
SPVL109 Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating 2017

SPVL110 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply 2017
Applications
SPVL111 A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock 2017
Generation Circuits in 130-nm CMOS
SPVL112 Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application 2017

SPVL113 An All-MOSFET Sub-1-V Voltage Reference With a-51-dB PSR up to 60 2017

MHz
SPVL114 A 65-nm CMOS Constant Current Source with Reduced PVT Variation 2017

SPVL115 A Fault Tolerance Technique for Combinational Circuits Based on Selective 2017
Transistor Redundancy
SPVL116 Preweighted Linearized VCO Analog-to-Digital Converter 2017

SPVL117 A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled 2017

LDO with Active Ripple Suppression
SPVL118 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance 2017
Asynchronous Logic QDI Cell Template
SPVL119 On Micro-architectural Mechanisms for Cache Wear out Reduction 2017

SPVL120 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in 2017

Memory Technology
SPVL121 A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using 2017
Dynamically Biased Op Amp Sharing
SPVL122 A 0.45 V 147–375 nW ECG Compression Processor With Wavelet 2017
Shrinkage and Adaptive Temporal Decimation Architectures