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VISVESVARYA NATIONAL INSTITUTE 

OF TECHNOLOGY 

NAGPUR 

   

ECE BTECH 15-19 

DEVICE MODELLING LAB 

ASSIGNMENT 4 

Submitted By: 

SAURABH DAGADGAVE 

BT15ECE019 

 
Q1. Plot transfer and output IV characteristics of NPN and PNP transistors. Use 
multiple DC sweep analysis for plotting characteristic in Ngspice.   

NPN:

*charecteristics*

.model bjt npn

r1 1 2 1meg

r2 4 3 1k

q1 3 2 0 bjt

vcc 5 0 dc 5

Vdum 5 4 dc 0

vbb 1 0 dc 0

.control

dc vbb 0 5 0.05

run

plot i(Vdum)

.endc

.end
*charecteristics*

.model bjt npn

r1 1 2 1meg

r2 4 3 1k

q1 3 2 0 bjt

vcc 5 0 dc 5

Vdum 5 4 dc 0

vbb 1 0 dc 0

.control

dc vcc 0 5 0.05 vbb 1 5 1

set xbrushwidth=3

run

plot i(Vdum)

.endc

.end
B)PNP:

*charecteristics*

.model bjt pnp

r1 2 1 1meg

r2 4 3 1k

q1 3 2 0 bjt

vcc 0 5 dc 12

Vdum 4 5 dc 0

vbb 0 1 dc 0

.control

dc vbb 0 10 0.05

run

plot i(Vdum)

.endc

.end
*charecteristics*

.model bjt pnp

r1 2 1 1meg

r2 4 3 1k

q1 3 2 0 bjt

vcc 0 5 dc 12

Vdum 4 5 dc 0

vbb 0 1 dc 0

.control

dc vcc 0 10 0.05 vbb 1 5 1

run

plot i(Vdum)

.endc

.end
Q2. Plot transfer and the output IV 
characteristics of n-channel and p-channel 
MOSFET. Use multiple DC sweep analysis 
for plotting in Ngspice. 

*nmos*

.model MOSN nmos

m1 2 1 0 0 MOSN

vg 1 0 dc 5

vd 3 0 dc 5

vdum 3 2 dc 0

.control

dc vg 0 5 0.01

run

plot i(vdum)

.endc

.end
*nmos*

.model MOSN nmos

m1 2 1 0 0 MOSN

vg 1 0 dc 5

vd 3 0 dc 5

vdum 3 2 dc 0

.control

dc vd 5 0 0.05 vg 5 0 1

run

plot i(vdum)

.endc

.end
B)PMOS:

*pmos*

.model MOSN pmos

m1 2 1 0 3 MOSN

vg 1 0 dc 5v

vd 3 0 dc 5v

vdum 3 2 dc 0

.control

dc vg -5 5 0.01

run

plot i(vdum)

.endc

.end
*Pmos*

.model MOSN pmos

m1 2 1 0 3 MOSN

vg 1 0 dc 5v

vd 3 0 dc 5v

vdum 3 2 dc 0

.control

dc vd -5 0 0.05 vg -5 0 1

run

plot i(vdum)

.endc

.end
Q4. ​Q4)Design a 3 input NAND and NOR Gate using CMOS technology.

A)NAND:

*nand using cmos*

.model MOSP pmos

.model MOSN nmos

va 1 0 pulse(0 5 0.1m 0.1m 0.1m 50m 100m)

vb 2 0 pulse(0 5 0.1m 0.1m 0.1m 25m 50m)

vc 3 0 pulse(0 5 0.1m 0.1m 0.1m 12.25m 25m)

vdd 4 0 dc 5v

m1 4 1 5 4 mosp

m2 4 2 5 4 mosp

m3 4 3 5 4 mosp

m4 5 1 6 0 mosn

m5 6 2 7 0 mosn

m6 7 3 0 0 mosn

.control

set xbrushwidth=3

tran 0.05m 100m

run

plot v(1)

plot v(2)

plot v(3)

plot v(5)

.endc

.end
INPUT A

INPUT B
INPUT C

OUTPUT OF NAND USING CMOS


TIME(ms) A B C Y
0-12.5 1 1 1 0
12.5-25 1 1 0 1
25-37.5 1 0 1 1
37.5-50 1 0 0 1
50-62.5 0 1 1 1
62.5-75 0 1 0 1
75-87.5 0 0 1 1
87.5-100 0 0 0 1
B)NOR

*nor using cmos*

.model MOSP pmos

.model MOSN nmos

va 1 0 pulse(0 5 0.1m 0.1m 0.1m 50m 100m)

vb 2 0 pulse(0 5 0.1m 0.1m 0.1m 25m 50m)

vc 3 0 pulse(0 5 0.1m 0.1m 0.1m 12.25m 25m)

vdd 4 0 dc 5v

m1 4 1 5 4 mosp

m2 5 2 6 4 mosp

m3 6 3 7 4 mosp

m4 7 1 0 0 mosn

m5 7 2 0 0 mosn

m6 7 3 0 0 mosn

.control

set xbrushwidth=3

tran 0.05m 100m

run

plot v(1)

plot v(2)

plot v(3)

plot v(7)

.endc

.end
INPUT A

INPUT B
INPUT C

OUTPUT OF NOR USING CMOS


TIME(ms) A B C Y
0-12.5 1 1 1 0
12.5-25 1 1 0 0
25-37.5 1 0 1 0
37.5-50 1 0 0 0
50-62.5 0 1 1 0
62.5-75 0 1 0 0
75-87.5 0 0 1 0
87.5-100 0 0 0 1
Q3.a) Design an Inverter/NOT gate using CMOS technology and plot its voltage 
transfer Curve (VTC) and Define 
and measure the VOH, VIH, VOL, 
VIL from VTC. 

*not gate using cmos*

.model MOSP pmos

.model MOSN nmos

vin 1 0 dc 5v

m1 4 1 2 2 mosp

m2 4 1 0 0 mosn

vdd 2 0 dc 5v

.control

dc vin 0 10 0.005

run

plot v(4)

.endc

.end
b) Perform Q3a) for Kr = 0.5, 1, 5 where kr = Kn/Kp of MOSFET. Justify the answer?

kr=0.5
Kr=1

kr=5

VOH is the ​minimum​ output high voltage of the inverter. 


VOL is the ​maximum​ output low voltage of the inverter. 

VIH is the minimum Input High voltage  

VIL is the maximum input low voltage.  

VOL: Nominal voltage corresponding to a low logic state at the output of a logic gate for vI =
VOH. Generally V- ≤ VOL.

VOH: Nominal voltage corresponding to a high logic state at the output of a logic gate for vI
= VOL. Generally VOH ≤ V+.
VIL: Maximum input voltage that will be recognised as a low input logic level.

VIH: Minimum input voltage that will be recognised as a high input logic level

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