 Introduction to I2C Protocol

 I2C Start Sequence

 I2C Stop Sequence
 Device Addressing
 Data Transfer
 Acknowledgement
 Data Write Sequence
 Data Read Sequence
 Difference between I2C and SPI
 Introduction to Port Expander IC PCF8574 ( I2C based )
 Interfacing PCF8574 to MSP430

I2C Protocol
I2C is a multi-master, two wire synchronous protocol. The two signal lines are called serial data line
and serial clock line. This protocol is generally used to connect low-speed devices like
microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in
embedded systems. Only two wires with pull-up resistors are needed to connect almost unlimited
number of I2C devices.

The devices on the I2C bus are either masters or slaves. The master is always the device that drives
the SCL clock line. The slaves are the devices that respond to the master. A slave cannot initiate a
transfer over the I2C bus, only a master can do that.

Start Sequence
To initiate the address frame, the master device leaves SCL high and pulls SDA low. This puts all
slave devices on notice that a transmission is about to start. If two master devices wish to take
ownership of the bus at one time, whichever device pulls SDA low first wins the race and gains
control of the bus.
Stop Sequence
Once all the data frames have been sent, the master will generate a stop condition. Stop conditions
are defined by a low to high transition on SDA after a low to high transition on SCL, with SCL
remaining high. During normal data writing operation, the value on SDA should not change when
SCL is high, to avoid false stop conditions.

Device Addressing
Each I2C slave device has a 7-bit address that needs to be unique on the bus. This means that you can
have up to 128 devices on the I2C bus, since a 7bit number can be from 0 to 127. Some devices have
fixed I2C address while others have few address lines which determine lower bits of the I2C address.

A6 A5 A4 A3 A2 A1 A0 R/W ACK

R/W bit indicate whether this is a read (1) or write (0) operation. The 9th bit of the frame is the
NACK/ACK bit. Once the first 8 bits of the frame are sent, the receiving device is given control over
SDA. If the receiving device does not pull the SDA line low before the 9th clock pulse, it can be
inferred that the receiving device either did not receive the data or did not know how to parse the
message. In that case, the exchange halts, and it’s up to the master of the system to decide how to
proceed.

Data Transfer
All data blocks are composed of 8 bits. The initial block has 7 address bits followed by a direction bit
(Read or Write). Following blocks have 8 data bits. Acknowledge bits are squeezed in between each
block.

D7 D6 D5 D4 D3 D2 D1 D0 ACK

Each data byte is transmitted MSB first including the address byte.

Acknowledge
The acknowledge bit (generated by the receiving device) indicates to the transmitter that the data
transfer was ok. Note that the clock pulse for the acknowledge bit is always created by the bus
master.ACK is high voltage and NACK is low voltage(0).
The acknowledge data bit is generated by either the master or slave depending on the data direction.
 For the master writing to a slave (W) the acknowledgment is generated by the slave. When a NACK
is received by the bus master the transfer has failed and the master must generate a STOP or repeated
START to abort the sequence.
For the master receiving (R) data from a slave the master generates the acknowledge bit. Normally
the master will generate an acknowledge after it has received data but to indicate to the slave that no
more data is required on the last byte transfer the master must generate a 'not-acknowledge'. This
indicates to the slave that it should stop sending data. The master can then generate the STOP bit.

Data Write Sequence (slave response in Red)

Start Address Write ACK DATA ACK DATA ACK Stop
 Send the start sequence.
 Send the slave address with R/W bit low.
 Send the register where data is to be written.
 Send the data byte.
 Send the stop sequence.

Data Read Sequence(slave response in Red)

Start Address Read ACK DATA ACK DATA NACK Stop
 Send the start sequence.
 Send the slave address with R/W bit low.
 Send the register whose data is to be read.
 Send the start sequence again.
 Send the slave address with R/W bit high.
 Read the data byte.
 Send the stop sequence.

Difference between SPI and I2C

S.Number SPI I2C

1 4 wire communication. 2 wire communication.
2 Full duplex Half duplex
3 High speed Low speed
4 Single master multiple slaves. Multi master and multiple slaves
5 Draws less power Draws more power
MSP430 connection to PCF8574

PCF8574 is 8bit I/O expander. It communicates on I2C protocol.

Pin description

 A0-A2 Address lines

 P0-P7  Input/Output lines
 GND  Ground
 INT  Interrupt line
 SCL Serial Clock
 SDA  Serial Data

SCL & SDA must be connected through a pullup resistor of 10K Ohm to the SDA & SCL pins of the
controller.
PCF8574 Connection to MSP430

PCF8574 MSP430
Pin 1 GND
Pin 2 GND
Pin 3 GND
Pin 4 (Output)
Pin 8 GND
Pin 14 (SCL) P1.6
Pin 15 (SDA) P1.7
Pin 16 Vcc
Pin 13 Not Connected