CAD Exercise 2:

Design and simulation of a

Miller-compensated operational amplifier
Aalto University School of Electrical Engineering
Department of Electronics and Nanoengineering (ECDL)

31.01.2017
1 Introduction
In this exercise, you will design the Miller compensated operational amplifier (op amp) of Fig. 1
based on given specifications. The transistors of the op amp are first sized by hand calculations.
The preliminary design is then evaluated by simulations and revised accordingly. Finally, the
revised design is layouted and re-evaluated. The transistor models to be used are based on a
generic (imaginary but on-the-level) 45 nm CMOS process.
This exercise is done in pairs. Each pair of students will be given an individual set of
specifications to fulfill. The specifications are listed in MyCourses.

VDD

M3 M4
M6
CC vout
M8
VDD vin- vin+
M1 M2 CL
IBIAS

M5B M5 M7

VSS

Figure 1: Miller-compensated operational amplifier

The Miller-compensated amplifier topology of this exercise was discussed in Lecture 4 and
analyzed in Exercise 4. Being a very common piece of circuitry, this amplifier is thoroughly
discussed and analyzed also in virtually all IC design basics textbooks.
This exercise is graded based on a report document that each group submits in MyCourses.
The report can be thought as a designer’s way to demonstrate the design process and outcome
to a supervisor. Check section 5 for further information about the desired content of the final
report.

2 Miller-compensated op amp

2.1 Specifications
The basic specification set for the op amp is listed in Table 1. Certain specifications are com-
monly fixed (supply voltages VDD and VSS , input DC-voltage level (VICM ) and phase margin
PM) while the others (DC-gain, gain-bandwidth GBW, slew rate SR and load capacitance CL )

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will be given separately to each pair of students. The necessary process parameter values for
hand calculations are listed and described in Table 2.

Table 1: Specifications for the op amp to be designed

Parameter Description Value

VDD Pos supply 1.2 V
VSS Neg supply 0V
VICM Input DC-level 0.75 V
PM Phase margin  80 o
ADC Min. DC-gain
GBW Gain bandwidth
SR Slew rate
CL Load capacitance

Table 2: Transistor parameters for the calculations

Parameter NMOS PMOS Description

VT H VT HN = 470 mV VT HP = -420 mV Threshold voltage
A A
2k 2 kN = 75 V 2 2 kP = 60 V 2
1 1 1
Transconductance
parameter
(ID = 12 k WL (VGS VT H )2(1 + VDS )
in saturation region)
 N = 0.50 1
V P = -0.50 1
V Channel length
modulation coefficient
L LN = 0.2 m LP = 0.2 m Channel length

2.2 Advice for hand calculations

The channel length of the transistors can be fixed to 0.2 m (about four times the minimum).
It is a good practice in analog designs to use a larger channel length than just the minimum, in
order to obtain better transistor matching. With the given information and by following the op
amp design principles presented in the lectures and exercises, one should be able to calculate
the required gm , drain current ID and WL -ratios for transistors M1 M6 . Sizing of the current
sources M5 and M7 can be done during simulations but their target currents should be deter-
mined already at this phase. The calculation result should be collected to table 3 and included
in the final report.

Hints:

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 Table 3: Calculated values for the designed op amp

Transistor M1 ; M2 M3 ; M4 M6 M5 M7
gm x x
ID
W x x
L

 Assume a two-pole transfer function for the op amp (neglect possible zeros at this phase)

 Compensation capacitor CC can be sized to be equal to the load capacitance CL

 Assume that the output capacitance of the first stage (CO1 ), i.e the capacitance at gate node
of M6 , is much smaller than the compensation and load capacitances (CO1  CC ; CL )

By and large, making CC equal to CL should lead to a PM of at least 60o . Unfortunately, the
compensation capacitor CC creates a right half plane (RHP) zero, which can substantially de-
grade the PM. In many cases, effect of the RHP zero on the PM is not negligible, and therefore
must be compensated. In order to improve the PM, a series resistor (implemented with a PMOS
transistor M8 ) is added to the feedback path. There are two approaches to improve the compen-
sation. One can set the RHP zero to infinity, or shift it to a left half plane (LHP) and cancel the
lowest non-dominant pole by setting magnitude of the zero equal to the pole. The resistance
value should be sized in accordance with the selected approach.

Hints:

 First, calculate the required series resistance (

) for transistor M8 .

 Once the resistance is calculated, use the triode (linear) region current equation for M8 to
determine the respective WL ratio.

3 Pre-layout simulation of the amplifier

Build the schematic of the amplifier based on your hand calculations and simulate it as in-
structed in exercise CAD 1. An example amplifier is shown in Figure 2. As previously, define
the supply voltage sources, the load capacitor and the bias current source in the test bench side.
Perform an AC simulation on your amplifier. Report the initial simulation result. Then,
tweek your design to match the specifications better. Make sure all your transistor operate in
saturation (excluding M8 , naturally). If the design target is met, see if you could save some
power or area. Also avoid over-design. Report the tweeks you make to the original sizing and
what reasoning they are based on. Note that not all specifications can necessarily be met.

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 Run and report the following set of analyses to your revised amplifier. Do your simulation
results make sense? Collect the results, discuss them shortly and move to layouting your design.

 Operating points (inc. corners and temperatures)

 AC analysis (inc. corners and temperatures)

 Noise density

 PSRR

 Step response in closed-loop configuration

 Harmonic distortion at the output in two input signal level cases

Figure 2: Example schematic of a Miller op amp

Instructions of how to run these analyses are given in exercise CAD 1d.

4 Post-layout simulation of the Miller-compensated op amp

Previously, we simulated the op amp in a pre-layout state. In other words, resistance of the metal
connections and parasitic capacitances of the wiring were not taken into account. In real analog
designs, verification of the circuit performance with included parasitics is required. Taking
parasitics into account is crucial especially at high operation frequencies and for circuits that
are sensitive to parasitic effects, such as charge amplifiers. Next, we learn to extract the parasitic
resistances and capacitances from layout, and to simulate the resulting netlist that includes the
parasitics.

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 The first step is to draw the layout of the Miller-compensated op amp. Once the design rule
check (DRC) and the layout versus schematic (LVS) check are clean, the layout is ready for
parasitic extraction. With the parasitics extracted, the op amp can be simulated in a post-layout
configuration.
First, go though the layouting tutorial in Appendix A and then proceed to drawing the layout
for your Miller op amp. When your layout is ready, continue to the next section for parasitic
extraction.

4.1 Extracting the parasitic components

We use Cadence’s PVS tool with Quantus QRC flow for the extraction.

1. After a clean DRC and LVS, in the layout drawing window, select QRC->Run PVS -
Quantus QRC from the menu.

2. In the Quantus QRC (PVS) Interface window, fulfill your design’s cell name and ensure
that the PVS data directory points to ./mylvs/svdb . The technology library path should
point to file /prog/cadence/gpdk/g045/gpdk045_v_4_0/pvtech.lib. The correct technol-
ogy is gpdk045_pvs.

3. In the Quantus QRC (PVS) Parasitic Extraction Run Form, check that the Setup, Extrac-
tion and Netlisting tabs are corresponding to figures 3, 4 and 5 (except that the library and
cell names are replaced by your naming convention, e.g ’miller_opamp’!).

4. The other tabs should be ok. Click ’Apply’ to start the extraction. Extraction process will
take a moment.

5. Once the extraction is completed, one should be able to open a new layout view ’av_extracted’
of the ’miller_opamp’ cell. Zoom in the see the parasitic components added to the layout.

6. In the new layout view, select ’Launch->ADE L’ to generate the netlist (including the
parasitics).

Repeat the previous simulations with the new netlist. Report the results. Are they different? If
yes, can you find explanations for the difference?

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Figure 3: Setup tab of Quantus QRC flow

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Figure 4: Extraction tab of Quantus QRC flow

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Figure 5: Netlisting tab of Quantus QRC flow

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5 Submission
Submission:

 The submission deadline is Feb 26th.

 Each pair of students should compose a report based on their design process and results
and upload it to MyCourses in pdf form. The report should describe:

– Hand calculations and their short justification.

– Initial simulation results for the hand-calculated design.
– Modifications made to the initial design and their justification.
– Simulation results for the revised design.
– Figure / figures of the layout of the design.
– Post-layout simulation results.
– Discussion about the final results and how they compare to the pre-layout results.

 In addition to the final report, upload the summary files (.sum) of clean DRC and LVS
runs and the ELDO netlist of the revised (pre-layout) amplifier. The DRC and LVS run
summaries can be found in their respective run folders.

Grading:

0 - 20 points

4 points will be given based on hand calculations

6 points will be given based on pre-layout simulations and design revision

4 points will be given based on layout

6 points will be given based on post-layout simulations and their interpretation

2 extra points can be gained by completing exercise CAD 1d successfully

Clean DRC and LVS check are required for passing the exercise

Hints:

 A good format for justifying the hand calculations is, for instance:
Equation N was used to size transistor M. Ideally, this should ensure that E (based on e.g.
Allen-Holmberg page P).

 In order to easily interpret agreement of the calculated and simulated values, making of a
comparison table is recommended. A comparison table for essential pre- and post-layout
simulations results would also be beneficial.

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 A screen shot program can be utilized in order to take snapshots, for instance a program
called Spectacle (this program is availble at least in KDE desktop environment, do not
work in GNOME). The program can be started by simply pressing the Print Screen button.

 Run DRC frequently during the layouting process.

 When making a large integrated capacitor, construct it from an array of small unit ca-
pacitors as shown in Fig. 6. A suitable spacing between the unit capacitors is 0.6 m.
Multiple unit capacitors can be connected in parallel in schematic by using the multiplier
parameter of a unit capacitor component.

Figure 6: Large capacitor connected between the input and the output of an inverter.

 In Eldo, internal nodes of an imported netlist are visible to the test bench. That is, you
can plot or extract the voltage of an internal node of your amplifier with a simple plotting
command in the test bench file.

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A Layout drawing tutorial
This section is a tutorial of how to use Cadence Virtuoso Layout Editor to construct a mask level
layout of a circuitry. Now it is a good time to look back at the theory in Lecture 1 about how
a typical CMOS process functions. Having a good grip on the process basics helps with avoid-
ing layout errors and, in general, following this tutorial. We will use the push-pull amplifier
(inverter) of CAD exercise 1a as a template.
First, we create a new layout cellview for the inverter. We will place instances of transistors
pmos1v and nmos1v in the Layout Editing window. Then, we will draw guard rings around
transistors (to suppress substrate noise), create wiring and add pins. When the layout is com-
pleted, a DRC (Design Rule Check) and a LVS check (Layout Versus Schematic check) will
be run. DRC uses a pre-defined set of layouting rules in attempt to make sure that the drawn
design is manufacturable (what you draw is also what you get). LVS checks that the drawn
layout matches with the schematic that it represents.

A.1 Create a layout cellview

First, you have to create a new layout cellview for the inverter in Cadence Virtuoso:

1. Open the Library Manager and open the schematic view of the inverter cell of you train-
ing library.

2. Select Launch-> Layout XL to in the Schematic Editor window.

3. Select Create new and Automatic buttons in the Startup Option window. Click OK.

4. In the New File window, verify that the Cell is set to inverter and the View is set to
layout. Click OK.

5. A pop-up window will appear asking if you are willing to check for a Layout Suite XL
license instead of Layout-L. Click Yes.

6. A blank Virtuoso Layout Suite XL window appears (Figure 7). If a “What’s new...”
window appears, you can close it.

A.2 Placing instances

Let’s start by placing a pmos1v (PMOS) instance from the gpdk045 library:

1. Open the Create Instance window with the Create->Instance pull-down menu item or
typing [i].

2. In the Create Instance window, click the Browse button. A Library Browser window
appears.

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 Figure 7: Layers and Virtuoso Layout Editing windows

3. Select a pmos1v transistor from the gpdk045 library.

4. Select layout in the View column.

5. Close the Library Browser and place the pmos1v instance in the Layout Editing window.

6. Repeat steps 1-5 to add a nmos1v (NMOS) instance below the PMOS transistor.

Notes:

 In this exercise, you do not have to optimize the design area! Leave at least 1:2um
distance between instances so that there is enough space to draw guard rings.

 You can measure distances by using Ruler.

 A ruler can be created with the Tools->Create Ruler pull-down menu item, by typing [k]
or with the Ruler shortcut icon on the left side of the Layout Editing window.

 Rulers can be removed with the Tools->Clear All Rulers pull-down menu item or by
typing [Shift+k].

Next, edit properties of the transistors so that their parameters match with the schematic.
The correct parameters are shown in Table 4.

Table 4: Properties of the transistors

Transistor Width Length Fingers
pmos1v 500n 80n 1
nmos1v 200n 60n 1

Use these steps to edit properties:

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 1. Select a transistor with a left-click on it.

2. Open Edit Instance Properties window (Figure 8) by typing [q] or selecting Edit->Basic-
>Properties.

3. Click the Parameter radio button to open the Parameter tab.

4. Change parameters.

5. If the instance is sidewards or backwards, you can rotate it in the Attribute tab of the Edit
Properties window or by selecting the instance, pressing [Shift + o] and clicking on the
instance.

Figure 8: Edit Instance Properties window

When you pick up instances from a library, only a generic box is shown in the design
window. Perform the following steps to set layers of the transistors visible.

1. Press [e].

2. Select Display Levels Start to 0 and Stop To 30, and click OK.

The shortcut for making transistors and other embedded objects visible and invisible is [Shift
+ f] and [Ctrl + f], respectively. Click the Save icon or select Design->Save (or File->Save
depending on the software version) to save the design.
At this point, your design should look as in Figure 9. Do not worry about exact placement
of the transistors, you will arrange them later.

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 Figure 9: Inverter layout view: step 1

A.3 Zoom and pan

Try to move around your design with zoom and pan commands:

1. Use your mouse’s scroll to zoom in and out. Alternatively, to scale the current window
by 0.5 type [Shift+z] or select View->Zoom Out. To scale the current window by 2, type
[Ctrl+z] or select View->Zoom In.

2. To pan the design, you can use the arrow keys, or press the [Tab] key followed a left-click
on a center point of the desired display.

3. By selecting View->Fit All or typing [f], you can fit the design to the window.

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 4. To zoom area you want to display, select View->Zoom To Area or type [z] followed
left-clicks on the corner points of the area you want to display.

A.4 Basic drawing

Signal lines are most conveniently drawn as so called paths:

1. Select the metal 1 layer with a left-click on the Metal1 drw list item of the Layers win-
dow.

2. Select Create->Shape->Path or type [p] to activate the path tool.

3. Draw a test path somewhere in the layout.

 Left click on the layout to start drawing the path. Left click again to make a turn.
 End the path by pressing [Enter].

4. Select the path and change its width to 0:26m (object properties can be edited by typing
[q]).

Sometimes larger layers have to be drawn, in which cases rectangles become useful.

1. Select the metal 2 layer with a left-click on the Metal2 drw list item of the Layers win-
dow.

2. Select Create->Shape->Rectangle or type [r] to activate the rectangle tool.

3. Draw a test rectangle somewhere in the layout.

 Left click on the layout to start drawing a rectangle. Left click again or press [Enter]
to finish the rectangle.

Try the stretching tool to modify your design:

1. Type [s] to activate the stretching tool. Bringing the cursor on an object will highlight the
part of the object that the stretch tool is about to modify.

 With left clicks, try changing the position of a part of your path.
 Try stretching the end of a path.
 Try stretching a rectangle.

Undo recent changes by pressing [u]. Redo by pressing [Shift+u].

Some embedded objects, such as a transistor, cannot be stretched. Instead, the stretching
tool will have the same effect as the move tool [m]. See what sort of effect the move tool has
on paths, rectangles and other objects.

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 Rotate an object by first selecting it and then pressing the rotation tool icon on the layout
drawing window. Alternatively, choose the tool by pressing [Shift+o].
The effect of a tool can be extended to multiple objects at a time by first selecting a group
of objects with a long left click and then selecting the tool.
Finally, remove your trial drawings by pressing [Delete] and clicking on the objects you
want deleted.

A.5 Contacts
Contacts and vias are needed to connect objects on different levels to each other. Follow these
steps to draw vias:

1. Choose Create->Via command or press [o] to create a via. Choose the via type in the
via definition drop-down menu and alter the via size by changing the number of rows or
columns.

2. The alternative, though more seldomly used, way is to draw a via as a rectangle by using
the respective layer. For instance, Via1 drw layer is used to create a via between metal 1
and metal 2.

(a) With a square using the Cont (b) With the M1_PIMP contact
drw layer item

Figure 10: Two different ways to create a contact between a metal 1 and a p-diffusion object

A.6 Creating guard rings

In this section, we will add guard rings around the transistors to prevent latch-up, cross coupling
and noise. The guard rings can be made manually but the more convenient way that is sufficient
in most cases is to use the dedicated tool.

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 Perform the following steps to create a P+ guard ring around the NMOS transistor.

1. Select the NMOS transistor and press [Shift+g].

2. The correct guard ring type is P-tap (an NMOS transistor stands on p+ type bulk). A
suitable enclosure is 0.3.

3. Click apply.

Use the stretching tool to tune the guard ring size.

Perform the following steps to create a N+ guard ring around the PMOS transistor.

1. Select the PMOS transistor and press [Shift+g].

2. The correct guard ring type is N-tap (a PMOS transistor stands on an N-type well). A
suitable enclosure is 0.3.

3. Click apply.

4. Notice that there is now a gap between the transistor’s and the ring’s N-type implant.
This is easy to observe by choosing the Nwell drawing layers and then pressing the none
visible (NV) button on the Layers menu window. Press the all visible (AV) button to make
all layers visible again.

5. Draw a Nwell rectangle over the whole guard ring in order to make the well continuous.

An example of a manually drawn N+ guard ring is shown in Figure 11.

A.7 Gate connection

In this section, we will connect the gates of the transistors together.
Follow these steps to make the gate connection:

1. Open the Create Via window (Figure 12) with the Create -> Via pull-down menu item or
by typing [o].

2. In the Create Via window, select M1_PO in the Via Definition list box.

3. Click Hide and place the contact object at the edge of the PMOS gate as shown in Figure
13.

4. Next, place another M1_PO contact at the edge of the NMOS gate as shown in Figure
14.

5. Gates will be connected using Metal 2 layer. Therefore, you need to create a via between
Metal 1 and Metal 2 (M2_M1 via).

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Figure 11: PMOS and the N+ guard ring

Figure 12: Create Via window

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Figure 13: PMOS and the M1_PO contact

Figure 14: NMOS and the M1_PO contact

(a) PMOS (b) NMOS

Figure 15:

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 Figure 16: Gate connection

A.8 Other connections

Follow these steps to complete the connections:

1. Use the Metal 2 layer to connect drains of the transistors together as shown in Figure 17.

2. Use the Metal 2 layer to create paths for input and output pins as shown in Figure 18.

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 3. Use the Metal 1 layer to connect the source of the PMOS to the guard ring as shown in
Figure 19.

4. Then, use the Metal 1 layer to draw a power rail for the vdd operating voltage.

5. Connect the source of the NMOS to the guard ring and draw a power rail for the vss
operating voltage with the Metal 1 layer as shown in Figure 20.

A.9 Bigger diffusion areas

In order to follow design rules, you sometimes have to draw a bigger N+ area on the NMOS
transistor and a bigger P+ area and N-well around the PMOS transistor.
In case such errors should occur, follow these steps to draw the areas:

1. Select the P+ layer (Pimp drw) in the Layers window.

2. Use the Pimp layer to draw a rectangle with the Create->Shape->Rectangle pull-down
menu item or by pressing [r] on the PMOS transistor as shown in Figure 21.

3. Select the N+ layer (Nimp drw) in the Layers window.

4. Use the Nimp layer to draw a rectangle on the NMOS as shown in Figure 22.

A.10 Pins
There are pins for the input (IN) and output (OUT) on the schematic you drew in the beginning
of this exercise. In this section, you will learn how to define pins in a layout cellview.
Perform the following steps to place pins on the inverter layout:

1. First, create the IN pin:

 Select the Metal 1 drw layer in the Layers window.

 Open the Create Pin window with the Create -> Pin pull-down menu item.
 In the Create Pin window, type “IN” in the Terminal names field.
 Then, check I/O type as ’input’.
 Check Create Label and click Options. Type ’0.1’ in the Height field and OK.
 Finally, place the pin by defining the corners of the pin with the left button. After
that, place the text (inside the rectangle).

2. Use the above steps to add the OUT pin. The I/O Type should be selected as output. Also
create pins for vdd! and vss! of type inputOutput.

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 Figure 17: Drain connection

3. Verify that your inverter with pins looks like in Figure 23 (The supply pins are missing
from the figure but should be included).

4. Save the design.

Now your inverter layout is ready for a Design Rules Check.

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 Figure 18: Input and output paths

Figure 19: Source of the PMOS

A.11 Design Rules Check (DRC)

Real processes have a certain resolution, variations, inaccuracies and defects. In order to ensure
correct functionality of the design, the layout must be drawn according to strict design rules. A
Design Rules Check is used to check that the design rules have been followed.
In this section, you will learn how to run a Design Rules Check (DRC). Perform the follow-
ing steps:

1. In the Layout Editing window of the inverter, select File -> Save to ensure that the design
is saved.

2. Select Launch -> Plugins -> PVS in order to take Cadence’s Physical Verification system

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 Figure 20: Source of the NMOS

Figure 21: The bigger N-well and P+ areas

in use.

3. Then, select PVS -> Run DRC.... DRC Run Submission Form window opens.

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 Figure 22: The bigger N+ area

4. In the Run Data menu, set the run directory as ./drc. Your DRC data will processed and
saved there.

5. In the Rules menu, verify that the technology file path field is filled as
/prog/cadence/gpdk/g045/gpdk045_v_4_0/pvtech.lib. Choose gpdk045_pvs as the tech-
nology and use the default rule set.

6. The other menu items do not need any modifications. Click Apply to run the DRC. A
DRC run log window and a DRC Debug Environment window will open. Use the DRC
Debug Environment to clean all generated errors. Clicking an item on the generated error
list will create a highlight on the layout that helps locating the error, like in Figure 24. In
addition, a description of the chosen error is shown in the bottom of the window.

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 Figure 23: The complete inverter layout

A.12 Layout Versus Schematic (LVS)

The fact that your layout follows the design rules does not ensure that it matches the schematic.
To make sure that a schematic and its intended layout match, run a layout versus schematic
check.
Follow these steps to run a LVS check:

1. In the Layout Editing window of the inverter, select File -> Save to ensure that the design
is saved.

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Figure 24: Highlighted error. The purple quadrangle shows a points where two metal lines
(blue) of different nets are too close to each other.

2. Select PVS -> Run LVS.... The LVS Run Submission Form window appears.

3. Ensure that the Rules menu is configured as previously.

4. In the Output menu, make sure that the Create Quantus QRC Input Data tab is selected.

5. In the LVS Options menu’s Extract Options tab, write your power and ground net names
in their respective fields in the Net Names section (vdd! and vss!).

6. Click Apply to run LVS. An LVS run log window and an LVS Debug Environment win-
dow will open. Use the LVS Debug Environment to clean all generated errors. Clicking
an item on the generated error list will show a description of that error in the bottom of
the window.

7. Choose Tools -> Probing form to open a probe tool. By clicking on the Add Probe
menu item and then a net on the layout, the tool will highligh all drawing layers that the
probed net is connected to. This helps locating an open or a short. Click on the Clear
Probe menu item to remove old probes.

8. Choose Tools -> Graphical LVS Debugger to see a colour-coded comparison figure of
your layout and schematic.

9. A separate "clean" window will pop up after an LVS run once all LVS errors are cleared.
Remember to rerun DRC after making any changes to the layout.

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