Adder Description

cla-1 Carry Lookahead Adder Notes cla-1
Carry Lookahead Adder (CLA)
A fast but costly adder.
Speed due to computing carry bit i without waiting for carry bit i − 1.
These Notes
Intended to supplement other sources.
For a basic introduction see Brown & Vranesic 3rd Edition Section 3.4.
Describe an ordinary (also called flat) and hierarchical CLA.
Provide simple delay and cost estimates.
The cost analysis for the hierarchical CLAs has been omitted for now.
cla-1 LSU EE 3755 Lecture Transparency. Formatted 8:33, 23 April 2014 from cla. cla-1
cla-2 cla-2
Carry Lookahead Cell (CLC)
ai bi CLCi
Operates on single bits. a b CLC
g gi
Ports for CLC i
Operands and Carry In

a, b, c
p pi
Sum
s = a ⊕ b ⊕ c.
ci c
Propagate Signal s
p=a+b si
Generate Signal
g = ab
cla-3 cla-3
ai bi CLCi
CLC Important Features a b CLC
There is no carry out. g gi
Signal p and g do not depend on c.
p pi
ci c
s
si
cla-4 Overview of CLA cla-4
Structure of n-bit Carry Lookahead Adder

A
B
a0 b0 a1 b1 a2 b2 an-1 bn-1
CLC0 CLC g0 CLC1 CLC g1 CLC2 CLC g2 CLCn-1 CLC gn-1
carry out
carry in
c0 p0 c1 p1 c2 p2 cn-1 pn-1 cn
s0 s1 s2 sn-1
g-1
S
Carry Generation Logic
Types of carry generation logic (CGL): lookahead and ripple.
With lookahead CGL adder above is a CLA.
With ripple CGL adder above is equivalent to a ripple adder.
Note: g−1 is used as a synonym for c0 .
cla-5 Carry Generation Logic cla-5
Lookahead CGL for first three cells.

A
B
a0 b0 a1 b1 a2 b2 a3 b3
CLC0 CLC g0 CLC1 CLC g1 CLC2 CLC g2 CLC3 CLC g3
carry in
c0 p0 c1 p1 c2 p2 c3 p3
s0 s1 s2 s3
S
g-1
cla-6 cla-6
A
B
a0 b0 a1 b1 a2 b2 a3 b3
CLC0 CLC g0 CLC1 CLC g1 CLC2 CLC g2 CLC3 CLC g3
carry in
c0 p0 c1 p1 c2 p2 c3 p3
s0 s1 s2 s3
S
g-1
Boolean expressions for carry signals c0 to c3 :
c0 = g−1 .
c1 = g−1 p0 + g0 .
c2 = g−1 p0 p1 + g0 p1 + g1 .
c3 = g−1 p0 p1 p2 + g0 p1 p2 + g1 p2 + g2 .
cla-7 cla-7
Generalization of Lookahead Carry Generation
c0 = g−1 .
c1 = g−1 p0 + g0 .
c2 = g−1 p0 p1 + g0 p1 + g1 .
c3 = g−1 p0 p1 p2 + g0 p1 p2 + g1 p2 + g2 .
Generalizing we get
ci = g−1 p0 p1 · · · pi−1 + g0 p1 p2 · · · pi−1 + g1 p2 p3 · · · pi−1 + · · · + gi−2 pi−1 + gi−1

i−1
X i−1
Y
= gj pk
j=−1 k=j+1
cla-8 CLA Delay Analysis cla-8
Delay Models
About These Models
Intended for hand analysis.
These models for making rough comparisons of different kinds of adders.
For example, ripple adder v. carry lookahead adder.
These models too crude for choosing between adders with delays within 40% of each other. . .
. . . in such cases write HDL descriptions . . .
. . . and use synthesis program to determine delays.
cla-9 cla-9
Unrealistic Delay Model
Easiest to use, but exaggerates performance of CLA.
n-input XOR Gate: tg = 2 delay units.
n-input AND, OR, NAND, NOR Gates: tg = 1 delay unit.
Conservative Delay Model
More tedious, understates performance of CLA.
n-input XOR Gate: tg = 2 lg n delay units.
n-input AND, OR, NAND, NOR Gates: tg = lg n delay units.
cla-10 cla-10
How To Analyze Delay of Combinational Circuit—A Review
Steps
(0) Mark all inputs to the circuit with time t = 0.
(1) If all gate outputs are marked with a time then go to step (2).
Otherwise, consider gates that do not have a time marked at their outputs . . .
. . . and find one in which all inputs are marked with a time.
Mark the output of the gate with time max{t1 , t2 , . . . , tn } + tg . . .

. . . where t1 , . . . , tn are the times marked on the gate’s inputs . . .
. . . and tg is the delay of the gate based on the model in use.
Go to step (1).
(2) The circuit delay is the largest time assigned to a wire.
cla-11 CLA Delay Analysis cla-11
Critical (longest) Path
Starts at inputs, flows through p0 (or any other pi ), cn−1 , ending at sn−1 .
You can follow along by following the red path!
t=0 Unrealistic Delay

A
t=0 Conservative Delay
B Red Wires on Critical Path
a0 b0 a1 b1 an-1 bn-1
CLC0 g0 CLC1 CLC g1 gn-2 CLC gn-1 Delays (longest
n-1
carry out
p0 pn-1 path to output). c
carry in
c1 p1 pn-2 n
c0 0+1 cn-1
3+2 5
0+1 s1 sn-1 1+2lgn+ 2
s0 3+2lg n S
g-1
gn-4
gn-3
pn-3
Unrealistic
Delay 1+1
1+lg n
Conservative 2+1
Delay 1+lg n+ lg n
cla-12 cla-12
Critical (longest) Path:

A
t=0 Conservative Delay
B Red Wires on Critical Path
Generation of p and g: a0 b0 a1 b1 an-1 bn-1
CLC0 g0 CLC1 CLC g1 gn-2 CLC gn-1 Delays (longest
Delay 1, Total 1 p0
n-1
pn-1 path to output).

carry out
c
carry in
c1 p1 pn-2 n
c0 0+1 cn-1
3+2 5
0+1 s1 sn-1 1+2lgn+ 2 3+2lg n S
Generation of c: g
s0
-1
Unrealistic: Delay 2, Total 3 gn-4

gn-3
Conservative: Delay 2⌈lg n⌉, Total 1 + 2⌈lg n⌉ pn-3
Unrealistic
Computation of s: Delay 1+1
1+lg n
Unrealistic: Delay 2, Total 5 Conservative
Delay
2+1
1+lg n+ lg n
Conservative: Delay 2, Total 3 + 2⌈lg n⌉
Total Delay:
Unrealistic Model Delay: 5 gate delays.
Conservative Model Delay: 3 + 2⌈lg n⌉ gate delays.
cla-13 cla-13
Comparison
n-bit ripple: Delay 2n.
n-bit CLA: Delay 5 or 3 + 2⌈lg n⌉.
8-bit ripple: Delay 16.
8-bit CLA: Delay 5 or 8.
CLA looks much better. . .

. . . until we compute the cost!
cla-14 CLA Cost Analysis cla-14
Cost Model
Cost of a-input AND Gate: a − 1.
Cost of 3-input XOR Gate: 5
cla-15 cla-15
n-bit CLA Cost Analysis
Sum Gen. Prop.

z}|{ z}|{ z}|{
Cost of each CLA Cell: 5 + 1 + 1 = 7
Cost of logic to compute ci given p and g signals:
AND Gates
z }| {
OR Gate i+1
z}|{ X i(i + 1) i(i + 3)
i + j−1 =i+ =
j=2
2 2
Cost of logic to compute c1 to cn :

n
X i(i + 3) 1
= n(n + 1)(n + 5)
i=1
2 6
Cost of entire n-bit CLA
Carry Gen Logic

CLA Cells z }| {
z}|{ 1 n3
7n + n(n + 1)(n + 5) ≈
6 6
cla-16 CLA v. Ripple Cost Comparison cla-16
Cost of Selected Sizes
n-bit ripple: 10n
n-bit CLA: 7n + 16 n(n + 1)(n + 5)
8-bit ripple: 80
8-bit CLA: 212 or 2.65× cost of ripple adder.
32-bit ripple: 320
32-bit CLA: 6736 or 21× cost of ripple adder.
64-bit ripple: 640
64-bit CLA: 48288 or 75× cost of ripple adder.
cla-17 Hierarchical CLA cla-17
Instead of using n 1-bit carry lookahead cells . . .

. . . use m l-bit Carry Lookahead Blocks. (Note that n = l × m.)
Structure:
A
lm bits l bits
B
l bits
a0 b0 a1 b1 a2 b2 a b

CLB-x0 CLB-x G0 CLB-x1 CLB-x G1 CLB-x2 CLB-x G2 CLB-x CLB-x G
carry out

carry in
c0 P0 c1 P1 c2 P2 c P c

s0 s1 s2 s
lm bits

G l bits
S

The CLB-x blocks can contain any kind of l-bit adder, including ripple and CLA.
Carry generation logic (CGL) can be ripple or lookahead.
cla-18 cla-18
Benefit of Hierarchical CLA
Since CGL and the logic to generate P and G operate on fewer bits . . .
. . . cost is lower.
cla-19 cla-19
We will consider two kinds of CLB-x modules:
CLB-c, in which the l-bit adder is a CLA.
CLB-r, in which the l-bit adder is a ripple adder.
cla-20 Carry Lookhead Block (CLB-x) cla-20
CLB-x contains an l-bit adder of type x (e.g., ripple or CLA). . .

. . . and logic to compute P and G.
A[(i+1)l-1:il] B[(i+1)l-1:il] CLB-x

a b l bits of B from bit # il to bit # (i+1)l-1. CLB-x
a0
b0
l bits a1
b1
a b
G G
c l-bit al-3

cin

type-x
bl-3
adder
s al-2
s
bl-2
l bits al-1 P P

bl-1
S[(i+1)l-1:il]
cla-21 cla-21
A[(i+1)l-1:il] B[(i+1)l-1:il] CLB-x

a b l bits of B from bit # il to bit # (i+1)l-1. CLB-x
a0
CLB Propagate and Generate Outputs b0
l bits a1
Let gi = ai bi and pi = ai + bi . b1
a b
G G
c l-bit al-3

l−1 cin

Y type-x
bl-3
adder
P = pj s al-2
s
j=0 bl-2
l bits al-1 P P
= p0 p1 · · · pl−1

bl-1
l−1 l−1 S[(i+1)l-1:il]

X Y
G= gj pk
j=0 k=j+1
= g0 p1 p2 · · · pl−1 + g1 p2 p3 · · · pl−1 + · · · + gl−2 pl−1 + gl−1
Notice that logic for G is almost the same as the logic for ci . . .
. . . an important difference is that the carry in is ignored.
cla-22 cla-22
Design Options for Hierarchical CLA
Value of l. (Since n is given, if we choose l that fixes m = n/l.)
Type of CLB: CLB-c (block uses l-bit CLA) or CLB-r (block uses l-bit ripple adder).
Type of CGL: lookahead or ripple.
Design Options Example
Given: We want a 32-bit adder, money is no object.
Choose l = 8, this fixes m = 4.
For CLB use a CLA.
For CGL use lookahead logic.
Are these good choices? To find answer need to analyze cost and performance.
cla-23 Hierarchical CLA Delay Analysis cla-23
Delay Analysis for Hierarchical CLA with CLB-r and lookahead CGL
Critical Path and delay under unrealistic and conservative models:

A Red Wires on Critical Path
t=0 Conservative Delay lm bits
am-1 l bits 5+2(l-1)
B 1+2lglm+2(l-1)
lb bm-1
a0 b0 0+3
carry out
a b
CLB-rm-1 l-bit ripple adder
CLB-r0 a0
a1
b0 0+1+2lg l a0
a1
b0
al-3
b1
G0 al-3
b1
G
Gm-1
carry in
c0 bl-3 bl-3
al-2
al-1
bl-2 P0 cm-1 al-2
al-1
bl-2
P
Pm-1 cm
bl-1 bl-1
s0 l bits sm-1 S
l-bit ripple adder lm bits

G-1 Delay of Entire Circuit
Gm-2
Pm-3
Unrealistic
Delay
3+2 = 5
Conservative Delay 1+2lg l + 2lgm = 1+2lglm
cla-24 Hierarchical CLA Delay Analysis cla-24
Delays for m × l-bit Hierarchical CLA. (n = lm)
Hierarchical CLA with CLB-r and lookahead CGL
Unrealistic: 7 + 2(l − 1) gate delays
Conservative: 1 + 2 lg n + 2l gate delays
Hierarchical CLA with CLB-c and lookahead CGL
Unrealistic: 9 gate delays
Conservative: 3 + 2 lg l + 2 lg n gate delays
Hierarchical CLA with CLB-r and ripple CGL
Unrealistic: 1 + 2m + 2l gate delays
Conservative: 2 lg l + 2(m + l) gate delays
For details see Fall 2013 Homework 2 Solution.
cla-25 cla-25
Hierarchical CLA Cost Analysis
Omitted for now.

Adder Description

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cla-1 Carry Lookahead Adder Notes cla-1

Carry Lookahead Adder (CLA)

A fast but costly adder.

Intended to supplement other sources.

Describe an ordinary (also called flat) and hierarchical CLA.

Provide simple delay and cost estimates.

Carry Lookahead Cell (CLC)

Operands and Carry In

Structure of n-bit Carry Lookahead Adder

Carry Generation Logic

Types of carry generation logic (CGL): lookahead and ripple.

With lookahead CGL adder above is a CLA.

With ripple CGL adder above is equivalent to a ripple adder.

Note: g−1 is used as a synonym for c0 .

Lookahead CGL for first three cells.

Boolean expressions for carry signals c0 to c3 :

Generalization of Lookahead Carry Generation

ci = g−1 p0 p1 · · · pi−1 + g0 p1 p2 · · · pi−1 + g1 p2 p3 · · · pi−1 + · · · + gi−2 pi−1 + gi−1

About These Models

Intended for hand analysis.

These models for making rough comparisons of different kinds of adders.

For example, ripple adder v. carry lookahead adder.

Unrealistic Delay Model

Easiest to use, but exaggerates performance of CLA.

n-input XOR Gate: tg = 2 delay units.

n-input AND, OR, NAND, NOR Gates: tg = 1 delay unit.

Conservative Delay Model

More tedious, understates performance of CLA.

n-input XOR Gate: tg = 2 lg n delay units.

n-input AND, OR, NAND, NOR Gates: tg = lg n delay units.

How To Analyze Delay of Combinational Circuit—A Review

(0) Mark all inputs to the circuit with time t = 0.

Mark the output of the gate with time max{t1 , t2 , . . . , tn } + tg . . .

(2) The circuit delay is the largest time assigned to a wire.

Critical (longest) Path

You can follow along by following the red path!

t=0 Unrealistic Delay

Critical (longest) Path:

pn-1 path to output).

Unrealistic: Delay 2, Total 3 gn-4

Conservative: Delay 2⌈lg n⌉, Total 1 + 2⌈lg n⌉ pn-3

Unrealistic Model Delay: 5 gate delays.

Conservative Model Delay: 3 + 2⌈lg n⌉ gate delays.

n-bit ripple: Delay 2n.

n-bit CLA: Delay 5 or 3 + 2⌈lg n⌉.

8-bit ripple: Delay 16.

8-bit CLA: Delay 5 or 8.

32-bit ripple: Delay 64.

32-bit CLA: Delay 5 or 13.

64-bit ripple: Delay 128.

64-bit CLA: Delay 5 or 15.

CLA looks much better. . .

Cost of a-input AND Gate: a − 1.

Cost of 3-input XOR Gate: 5

n-bit CLA Cost Analysis

Sum Gen. Prop.

Cost of logic to compute ci given p and g signals:

Cost of logic to compute c1 to cn :

Cost of entire n-bit CLA

Carry Gen Logic

Cost of Selected Sizes

n-bit ripple: 10n

n-bit CLA: 7n + 16 n(n + 1)(n + 5)