MICRO PROJECT 3

Thapar University, Patiala

Submitted To: Dr. Sanjay Sharma
Name: Dipin Preet Singh
Class: C-3
Roll No: 401706008
Subject: Electronics
 CERTIFICATE
This is to certify that this project entitled
“Construction of 3-bit up-down counter using JK
flip-flop”. Submitted by “Dipin Preet Singh” of
group “C-3” of “Thapar University” is the
individual work of the candidate submitted for the
fulfilment of the project report for the first
semester of Electronics Engineering.

Signature of Examiner
Mr. Sanjay Sharma
ACKNOWLEDGEMENT:
I would like to express my special thanks of
gratitude to my teacher Dr. Jaswinder Kaur
as well as our lab teacher Mr. Sanjay
Sharma who gave me the golden opportunity
to do this wonderful project on the topic of
analog and digital electronics, which also
helped me in doing a lot of Research and I
came to know about so many new things I
am really thankful to them. Secondly I would
also like to thank my parents and friends
who helped me a lot in finalizing this project
within the limited time frame.
 THEORY

The JK Flip Flop

The basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it
suffers from two basic switching problems.

Number one, the S = 0 and R = 0 condition (S = R = 0) must always be avoided, and number
two, if S or R change state while the enable input is high the correct latching action may not
occur. Then to overcome these two fundamental design problems with the SR flip-flop
design, the JK flip Flop was developed. This simple JK flip Flop is the most widely used of
all the flip-flop designs and is considered to be a universal flip-flop circuit. The sequential
operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same
“Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are both at logic “1”.The JK flip
flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents
the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR bi stable latch except for the addition of a clock input.

The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bi stable have now been replaced by two
inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R. The two 2-input AND gates of the gated SR bi stable have now been
replaced by two 3-input NAND gates with the third input of each gate connected to the
outputs at Q and Q. This cross coupling of the SR flip-flop allows the previously invalid
condition of S = “1” and R = “1” state to be used to produce a “toggle action” as the two
inputs are now interlocked. If the circuit is now “SET” the J input is inhibited by the “0”
status of Q through the lower NAND gate. If the circuit is “RESET” the K input is inhibited
by the “0” status of Q through the upper NAND gate. As Q and Q are always different we can
use them to control the input. When both inputs J and K are equal to logic “1”, the JK flip
flop toggles as shown in the following truth table.
Present State Next State Required Inputs
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby eliminating
the invalid condition seen previously in the SR flip flop circuit. Also when both the J and
the K inputs are at logic level “1” at the same time, and the clock input is pulsed “HIGH”, the
circuit will “toggle” from its SET state to a RESET state, or visa-versa. This results in the JK
flip flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”.
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from
timing problems called “race” if the output Q changes state before the timing pulse of the
clock input has time to go “OFF”. To avoid this the timing pulse period (T) must be kept as
short as possible (high frequency). As this is sometimes not possible with modern TTL IC’s
the much improved Master-Slave JK Flip-flop was developed.
Bidirectional Counters
Bidirectional counters are capable of counting in either the up direction or the down direction
through any given count sequence. As well as counting “up” from zero and increasing or
incrementing to some preset value, it is sometimes necessary to count “down” from a
predetermined value to zero allowing us to produce an output that activates when the zero
count or some other pre-set value is reached. This type of counter is normally referred to as
a Down Counter, (CTD). In a binary or BCD down counter, the count decreases by one for
each external clock pulse from some preset value. Special dual purpose IC’s such as the TTL
74LS193 or CMOS CD4510 are 4-bit binary Up or Down counters which have an additional
input pin to select either the up or down count mode. Both Synchronous and Asynchronous
counters are capable of counting “Up” or counting “Down”, but there is another more
“Universal” type of counter that can count in both directions either Up or Down depending
on the state of their input control pin and these are known as Bidirectional Counters.
Bidirectional counters, also known as Up/Down counters, are capable of counting in either
direction through any given count sequence and they can be reversed at any point within their
count sequence by using an additional control input

Synchronous 3-bit Up/Down Counter

Present State Mode Next State Required Excitations

Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 1 1 1 1 X 1 X 1 X
0 0 0 1 0 0 1 0 X 0 X 1 X
0 0 1 0 0 0 0 0 X 0 X X 1
0 0 1 1 0 1 0 0 X 1 X X 1
0 1 0 0 0 0 1 0 X X 1 1 X
0 1 0 1 0 1 1 0 X X 0 1 X
0 1 1 0 0 1 0 0 X X 0 X 1
0 1 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 1 1 X 1 1 X 1 X
1 0 0 1 1 0 1 X 0 0 X 1 X
1 0 1 0 1 0 0 X 0 0 X X 1
1 0 1 1 1 1 0 X 0 1 X X 1
1 1 0 0 1 0 1 X 0 X 1 1 X
1 1 0 1 1 1 1 X 0 X 0 1 X
1 1 1 0 1 1 0 X 0 X 0 X 1
1 1 1 1 0 0 0 X 1 X 1 X 1
The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0). Generally most
bidirectional counter chips can be made to change their count direction either up or down at
any point within their counting sequence. This is achieved by using an additional input pin
which determines the direction of the count, either Up or Down and the timing diagram gives
an example of the counters operation as this Up/Down input changes state. Nowadays, both
up and down counters are incorporated into single IC that is fully programmable to count in
both an “Up” and a “Down” direction from any preset value producing a
complete Bidirectional Counter chip. Common chips available are the 74HC190 4-bit BCD
decade Up/Down counter; the 74F569 is a fully synchronous Up/Down binary counter and
the CMOS 4029 4-bit Synchronous Up/Down counter.
PROCEDURE:
Using the NI Multi-Sim software we designed the following circuit for the synchronous 3bit
up-down counter using J-K Flip-Flops and necessary logic gates.