Datorarkitektur I Fö 11- 1 Datorarkitektur I Fö 11- 2

Let’s Have a Look into the CPU

THE CONTROL UNIT I/O I/O I/O

1 2 n

System Bus

1. Why is a Control Unit Needed inside the CPU?

Main
CPU
Memory
2. Microoperations and Control Signals

3. The Control Unit - Basic Tasks

System Bus
CPU
4. Hardwired Control

Registers
5. Microprogrammed Control
ALU

Address Bus
Control Bus

Data Bus
IR
PC
Control
Unit

Internal
CPU Bus

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

Datorarkitektur I Fö 11- 3 Datorarkitektur I Fö 11- 4

Instruction Execution
Let’s Have a Look into the CPU (cont’d)
• The CPU executes a sequence of instructions.
• The execution of an instruction is organized as an
instruction cycle: it is performed as a succession of
several steps;
The question that has to be answered:

• How are the elements inside the CPU and the

Fetch
interface to the external datapath controlled in order instruction
to work properly?

Execute
To perform this control, that’s instruction
the task of the Control Unit

• Each step is executed as a set of several

microoperations.

• The task performed by any microoperation falls in

one of the following categories:
- Transfer data from one register to another;
- Transfer data from a register to an external
interface (system bus);
- Transfer data from an external interface to a
register;
- Perform an arithmetic or logic operation, using
registers for input and output.

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

 Datorarkitektur I Fö 11- 5 Datorarkitektur I Fö 11- 6

Instruction Execution (cont’d) Microoperations and Control Signals

PCin Control signals

In order to allow the execution of a microoperation, one

PC

Status&Cond.
or several control signals have to be issued; they allow
the corresponding data transfer and/or computation to

Flags
PCout
Control be performed.
unit
MARin
Examples:
MAR IRin
System bus

Clock
MBRin a) signals for transferring content of register R0 to R1:
IR R0out, R1in
MBR
IRout b) signals for adding content of Y to that of R0 (result in Z):
R0out, Add, Zin
MBRout R0in

Yin c) signals for reading a memory location; address in R3:

R0
R3out, MARin, Read
Clear Y
Y
R0out
• The CPU executes an instruction as a sequence of
Yout control steps. In each control step one or several
microoperations are executed.
Add
• One clock pulse triggers the activities
Rn-1in corresponding to one control step ⇒ for each
XOR ALU Carry-in clock pulse the control unit generates the control
Zin signals corresponding to the microoperations to be
Rn-1
executed in the respective control step.
Z
Zout Rn-1out

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

Datorarkitektur I Fö 11- 7 Datorarkitektur I Fö 11- 8

Microoperations and Control Signals (cont’d)

Microoperations and Control Signals (cont’d)

instruction:
ADD R1,R3 R1 ← R1 + R3 instruction:
BR target unconditional branch (with
control steps and control signals: relative addressing - see lect. 5)
PC←PC+1
fetch ins.

1 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin control steps and control signals:
2 Zout, PCin
PC←PC+1
fetch ins.

3 MBRout, IRin 1 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin

4 R1out, Yin 2 Zout, PCin
5 R3out, Add, Zin 3 MBRout, IRin
6 Zout, R1in, End 4 PCout, Yin
5 (displacement-field)IRout, Add, Zin
6 Zout, PCin, End
instruction:
ADD R1,(R3) R1 ← R1 + [R3]
Comments:
control steps and control signals: • The first (three) control steps are identical for each
instruction; they perform instruction fetch and
PC←PC+1

increment the PC. The following steps depend on

fetch ins.

1 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin

2 Zout, PCin
3 MBRout, IRin
4 R3out, MARin, Read
5 R1out, Yin
6 MBRout, Add, Zin
7 Zout, R1in, End
the actual instruction (stored in the IR).
• If a control step issues a read, the value will be
available in the MBR after one additional step.
indirect addressing
• Several microoperations can be performed in the
same control step if they don’t conflict (for example,
only one of them is allowed to output on the bus)

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

 Datorarkitektur I Fö 11- 9 Datorarkitektur I Fö 11- 10

Control Unit Control Unit (cont’d)

The basic task of the control unit: IR

- for each instruction the control unit causes the
CPU to go through a sequence of control steps;
- in each control step the control unit issues a set Control signals in-
of signals which cause the corresponding ternal to the CPU

Status&Cond.
microoperations to be executed.

Flags
Control Control signals
unit on system bus
• The control unit is driven by the processor clock.
Signals from
The signals to be generated at a certain moment system bus
depend on:
- the actual step to be executed;
- the condition and status flags of the processor; Clock
- the actual instruction executed;
- external signals received on the system bus
(e.g. interrupt signals).

• Techniques for implementation of the control unit:

1. Hardwired control
2. Microprogrammed control

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

Datorarkitektur I Fö 11- 11 Datorarkitektur I Fö 11- 12

Hardwired Control
Hardwired Control (cont’d)
• In this case, the control unit is a combinatorial
circuit; it gets a set of inputs (from IR, flags, clock,
system bus) and transforms them into a set of
control signals. Generation of signal Zin:
- first step of all instructions (fetch instruction)
IR - step 5 of ADD with register addressing
- step 5 of BR
Instruction - step 6 of ADD with register-indirect addressing
decoder - -------------------
I1 I2 I3 In
Zin = T1 + T5 ⋅ (ADDreg + BR) + T6 ⋅ ADDreg_ind + . . .
Status&Cond.
Flags

T1
Generation of signal End:
and decoder
Reset Step counter

T2 Encoder block - step 6 of ADD with register addressing

(combinatorial signal
Clock - step 7 of ADD with register-indirect addressing
generator)
tem bus
From sys-

- step 6 of BR
Tn - -------------------

End = T6 ⋅ (ADDreg + BR) + T7 ⋅ ADDreg_ind + . . .

End

Control signals

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

 Datorarkitektur I Fö 11- 13 Datorarkitektur I Fö 11- 14

Control signals
Hardwired Control (cont’d)

Status&Cond.
Flags
Control
unit
• Hardwired control provides highest speed.
Clock
• RISCs are implemented with hardwired control.
IR

• If the instruction set becomes very complex

(CISCs) implementing hardwired control is very PC
difficult. In this case microprogrammed control units
are used. R0

• In order to allow execution of register-to-register

operations in a single clock cycle, RISCs (and other
Rn-1
modern processors) use three-bus CPU structures
(see following slide).

ALU
MBR

MAR

System bus

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

Datorarkitektur I Fö 11- 15 Datorarkitektur I Fö 11- 16

Microprogrammed Control Microprogrammed Control Unit

• Control word (CW): a sequence of Nsig bits, where Status&Cond.

Nsig is the total number of control signals; each bit Flags
in a CW corresponds to one control signal.
• Each control step during execution of an instruction
defines a certain CW; it represents a combination
of 1s and 0s corresponding to the active and non-
active control signals.
• Microroutine: a sequence of CWs corresponding to Address Control
the control sequence of a machine instruction. An IR generator µPC store
individual CW in a microroutine is called a (AG) (CS)
microinstruction.
INCR
gen. addr

Microprogrammed control - basic idea: IAB

• All microroutines corresponding to the machine
Control buffer/
instructions are stored in the control store.
decoder
• The control unit generates the sequence of control (CB/D)
signals for a certain machine instruction by reading end, end-fetch
from the control store the CWs of the microroutine Clock Sequencer
branch
corresponding to the respective instruction.

Control signals
The control unit is implemented just like another Signals from
very simple CPU, inside the CPU, executing system bus
microroutines stored in the control store.

IAB: Internal Address Bus

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

 Datorarkitektur I Fö 11- 17 Datorarkitektur I Fö 11- 18

Control Store Organization

Microroutine Executed for Conditional Branch

Control store
Addr-fetch
---------------------
--------------------- Fetch A_fetch PCout, MARin, Read, Clear Y, Carry-in, Add, Zin
end-fetch instruction
+1 Zout, PCin
Addr-interr. +2 MBRout, IRin
---------------------
--------------------- Interrupt
+3 end-fetch this produces the jump to A_CB
branch addr-fetch routine
--------------
Addr-instr0
--------------------- A_CB branch to A_CB+2 if N set
--------------------- Execute
instr. code 0 +1 end
end
Addr-instr1 +2 PCout, Yin
---------------------
Execute +3 (displacement-field)IRout, Add, Zin
---------------------
end instr. code 1 +4 Zout, PCin
+5 end

Addr-instrn
---------------------
Execute
---------------------
instr. code n
end • The microroutines contain, beside CWs, also
branches which have to be interpreted by the
microprogrammed controller.
• The sequencer is controlling the right execution
• The control store contains the microprogram sequence of microinstructions. The sequencer is a
(sometimes called firmware). small control unit of the control unit.

Petru Eles, IDA, LiTH Petru Eles, IDA, LiTH

Datorarkitektur I Fö 11- 19

Summary

• The control unit is in charge of coordinating the

activities inside the CPU and the interaction with
the outside. It is doing this by issuing in each clock
cycle the appropriate control signals.
• A set of control signals activates the
microoperations which have to be executed in a
given control step.
• Control units can be implemented hardwired or
microprogrammed.
• A hardwired control unit is a combinatorial circuit
which gets a set of inputs and transforms them into
a set of control signals.
• A microprogrammed control unit is implemented
like another CPU inside the CPU. It executes
microprogrammes stored in the control store.
• Each instruction of the microprogram practically
represents the set of signals which the control unit
has to issue in the respective control step.
• Hardwired controllers are faster then
microprogrammed ones. They are used in all
RISCs.
• If the instruction set is complex, hardwired
controllers become too complicated. Therefore
CISCs are implemented with microprogrammed
controllers.

Petru Eles, IDA, LiTH