CHAPTER03 QUESTIONS

MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.

1) If one input of an AND gate is LOW while the other is a clock signal, the output is 1)
A) a clock signal. B) HIGH.
C) LOW. D) cannot be determined

2) Waveforms A and B represent the inputs to an OR gate. During which time interval(s) will the 2)
output from the gate (X) be HIGH?

A) time intervals 2 and 3 B) never

C) time interval 4 D) time intervals 3 and 5

3) When the indicator lamp of a logic probe glows brightly, it is detecting 3)

A) a HIGH logic level. B) +2 V.
C) 0 V. D) a LOW logic level.

4) Which logic circuit is represented by the Boolean equation ABC = X? 4)

A) Clock B) NAND C) Inverter D) AND

5) The Boolean equation for an OR gate is ________. 5)

A) A/B = X B) A - B = X C) AB = X D) A + B = X

6) Which logic gate is described by the following truth table? 6)

A B X
0 0 1
0 1 1
1 0 1
1 1 0

A) NOR B) AND C) NAND D) OR

7) Which truth table is correct for an inverter? 7)

A) B)
input output input output
0 0 0 1
1 1 1 1

C) D)
input output input output
0 0 0 1
1 0 1 0

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 8) Waveforms A and B represent the inputs to an AND gate. During which time interval will the 8)
output from the gate (X) be HIGH?

A) time interval 1 B) time interval 3 C) time interval 4 D) time interval 5

9) If one input of a two-input NAND gate is tied to +Vcc, the NAND functions as 9)
A) an OR gate. B) an inverter. C) a NOR gate. D) an AND gate.

10) What will be the output of a three-input NOR gate whose inputs are a clock, a HIGH, and a LOW? 10)
A) LOW B) HIGH
C) clock D) cannot be determined

11) In order for an AND gate to be enabled 11)

A) both inputs should be HIGH. B) both inputs should be LOW.
C) one input should be LOW. D) one input should be HIGH.

12) In order to produce a LOW output, an OR gate requires 12)

A) any input to be HIGH. B) all inputs to be LOW.
C) any input to be LOW. D) all inputs to be HIGH.

13) A gate output is supposed to be HIGH. A digital probe indicator lamp is off. This could be caused 13)
by
A) a nonfunctional probe. B) improper gate input.
C) a failed gate. D) all of the above

14) The standard logic symbols that utilize squares with symbols in them are 14)
A) IEEE/IEC. B) CMOS. C) ASCII. D) ANSI.

15) A three-input NAND gate will have a HIGH output whenever 15)
A) one input is HIGH. B) any two inputs are HIGH.
C) one input is LOW. D) three inputs are HIGH.

16) Which logic function can be implemented by connecting an inverter to the output of a NAND 16)
gate?
A) NAND B) AND C) NOR D) OR

17) The Boolean equation for an AND gate is ________. 17)

A) AB = X B) A/B = X C) A + B = X D) A - B = X

18) If one input of an OR gate is HIGH while the other is a clock signal, the output is 18)
A) LOW. B) a clock signal.
C) HIGH. D) cannot be determined

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19) Assume that a logic gate has four inputs. How many possible input combinations will be listed in 19)
its truth table?
A) 16 B) 8 C) 2 D) 4

20) Which logic function is represented by the equation ABCD = X? 20)

A) OR B) clock C) inverter D) AND

21) Which logic circuit is represented by the Boolean equation A + B + C + D = X? 21)

A) OR B) NAND C) Inverter D) NOR

22) Which output is correct for this NAND truth table? 22)

A B X
0 0 ?
0 1 ?
1 0 ?
1 1 ?

A) 0 B) 1 C) 0 D) 1
0 0 1 1
0 0 1 1
1 0 1 0

23) What will be the output of a three-input NAND gate whose inputs are a HIGH, a HIGH, and a 23)
clock?
A) HIGH B) a clock signal
C) an inverted clock signal D) LOW

24) If input A of a NAND gate is connected to a clock and input B is HIGH, the normal output is 24)
A) HIGH. B) a clock signal.
C) LOW. D) an inverted clock signal.

25) If one input of an OR gate is considered to be an enable, it will enable the other input when it is 25)
A) the opposite of the other input. B) HIGH.
C) the same as the other input. D) LOW.

26) A three-input NOR gate will have a HIGH output whenever 26)
A) three inputs are LOW. B) two inputs are LOW.
C) one input is HIGH. D) three inputs are HIGH.

27) Which logic gate is described by the following truth table? 27)

A B X
0 0 1
0 1 0
1 0 0
1 1 0

A) OR B) NOR C) NAND D) AND

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28) Waveforms A and B represent the inputs to an OR gate. During which time interval will the output 28)
from the gate (X) be LOW?

A) time interval 1 B) time interval 3 C) time interval 4 D) time interval 5

29) Which logic function is represented by the equation A + B = X? 29)

A) OR B) clock C) AND D) switch

30) Which output is correct for this NOR truth table? 30)

A B X
0 0 ?
0 1 ?
1 0 ?
1 1 ?

A) 0 B) 1 C) 0 D) 1
0 1 1 0
0 1 1 0
1 0 1 0

31) Waveforms A and B represent the inputs to a NOR gate. During which time interval(s) will the 31)
output from the gate (X) be HIGH?

A) time interval 5 B) time interval 2

C) time intervals 2, 3, and 4 D) time intervals 2 and 3

32) If input A of a NAND gate is connected to a clock and input B is LOW, the normal output is 32)
A) a clock signal. B) an inverted clock signal.
C) HIGH. D) LOW.

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33) Which set of outputs is correct for this AND truth table? 33)

A B X
0 0 ?
0 1 ?
1 0 ?
1 1 ?

A) 0 B) 0 C) 0 D) 0
1 1 0 0
1 0 0 0
1 1 1 0

34) The Boolean equation for a NOR function is ________. 34)

A) X = A + B B) X = A + B C) X = A + B D) X = A + B

35) How many inverters are in a 14-pin DIP integrated circuit? 35)
A) eight B) two C) six D) four

36) In term of digital logic, a one is usually represented by 36)

A) +5 V. B) 0 V. C) +10 V. D) +15 V.

37) How many two-input gates are in a single 14-pin DIP integrated circuit? 37)
A) two B) eight C) four D) six

38) In order for an OR gate to be enabled 38)

A) both inputs should be HIGH. B) one input should be LOW.
C) one input should be HIGH. D) both inputs should be LOW.

39) Which logic function can be implemented by connecting an inverter to the output of an OR gate? 39)
A) NOR B) inverter C) AND D) OR

40) To pass a clock signal through a three-input OR gate 40)

A) the clock must be tied to two of the inputs.
B) the other inputs do not matter.
C) the other inputs must be HIGH.
D) the other inputs must be LOW.

41) Which logic gate is described by the following truth table? 41)

A B X
0 0 0
0 1 1
1 0 1
1 1 1

A) inverter B) OR C) AND D) cannot tell

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42) If one input of an OR gate is LOW while the other is a clock signal, the output is 42)
A) a clock signal. B) LOW.
C) HIGH. D) cannot be determined

43) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the 43)
output from the gate (X) be HIGH?

A) time intervals 4 and 5 B) time interval 5

C) time interval 4 D) time intervals 1, 2 and 3

44) Waveforms A and B represent the inputs to an AND gate. During which time interval will the 44)
output from the gate (X) be HIGH?

A) time interval 1 B) time interval 2 C) time interval 4 D) time interval 5

45) A NAND gate with one HIGH input and one LOW input 45)
A) will not function. B) functions as an AND.
C) will output a LOW. D) will output a HIGH.

46) Waveforms A and B represent the inputs to an OR gate. During which time intervals will the 46)
output from the gate (X) be LOW?

Wa
A) time intervals 1 and 4 B) time intervals 1 and 2
C) time intervals 1 and 3 D) It is never low.

47) If both inputs of an AND gate are normally HIGH but one of them momentarily dips LOW, the 47)
output will
A) be LOW. B) momentarily dip LOW.
C) go LOW and remain LOW. D) stay HIGH.

48) If one input of an AND gate is HIGH while the other is a clock signal, the output is 48)
A) a clock signal. B) HIGH.
C) LOW. D) cannot be determined

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49) If one input of an AND gate is considered to be an enable, it will enable the other input when it is 49)
A) LOW. B) HIGH.
C) opposite of the other input. D) the same as the other input.

50) Which set of outputs is correct for this OR truth table? 50)

A B X
0 0 ?
0 1 ?
1 0 ?
1 1 ?

A) 1 B) 0 C) 0 D) 0
1 1 0 1
1 0 0 1
0 1 1 1

51) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the 51)
output from the gate (X) be HIGH?

A) time intervals 1 and 2 B) time intervals 1, 2, 4, and 5

C) time interval 5 D) time interval 3

52) The Boolean equation for a NAND function is 52)

A) X = A + B B) X = AB C) X = A B D) X = AB

53) Which logic function can be implemented by connecting an inverter to the output of a NOR gate? 53)
A) NOR B) AND C) NAND D) OR

54) If input A of a NOR gate is LOW and input B is HIGH, the output should be 54)
A) unknown. B) HIGH. C) changing. D) LOW.

55) The purpose of a digital pulser is to ________ a circuit. 55)

A) provide digital pulses to B) graph the output of
C) float an output of D) show the logic levels of

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56) Waveforms A and B represent the inputs to a NAND gate. During which time interval(s) will the 56)
output from the gate (X) be LOW?

A) time intervals 2, 3, and 4 B) time interval 2

C) time intervals 2 and 3 D) never

57) Inversion is indicated by 57)

A) a triangle on a gate output. B) a bar (line) over a Boolean equation.
C) a bubble on a gate output. D) all of the above

58) Waveforms A and B represent the inputs to a NOR gate. During which time interval(s) will the 58)
output from the gate (X) be HIGH?

A) time intervals 1 and 2 B) time interval 3

C) time intervals 1, 2, 3, and 4 D) time interval 5

59) If both of its inputs are connected to the same signal, a NOR gate functions as a(n) 59)
A) NOR gate. B) OR gate. C) inverter. D) AND gate.

60) A NOR gate with one HIGH input and one LOW input 60)
A) will output a HIGH. B) will output a LOW.
C) will not function. D) functions as an AND.

61) What is the output of a two-input NAND gate whose inputs are LOW except for narrow HIGH 61)
pulses?
A) HIGH
B) LOW each time a pulse occurs
C) HIGH except when both inputs have a pulse at the same time
D) HIGH each time a pulse occurs

62) If both inputs of an OR gate are normally HIGH but one of them momentarily dips LOW, the 62)
output will
A) momentarily dip LOW. B) be LOW.
C) go LOW and remain LOW. D) stay HIGH.

63) In terms of digital logic, a HIGH voltage usually represents 63)

A) a one. B) an illegal condition.
C) a zero. D) an open.

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64) The truth table for a three-input OR gate contains ________ entries. 64)
A) 6 B) 3 C) 8 D) 9

65) In order to produce a HIGH output, an AND gate requires 65)

A) all inputs to be LOW. B) any input to be LOW.
C) all inputs to be HIGH. D) any input to be HIGH.

66) Which logic function can be implemented by connecting an inverter to the output of an AND gate? 66)
A) OR B) AND C) NOR D) NAND

67) The ground and power pins on a typical TTL 14-pin DIP are 67)
A) pins 1 and 8. B) pins 1 and 14. C) pins 7 and 14. D) pins 7 and 8.

68) When the indicator lamp of a logic probe glows dimly, it is detecting 68)
A) +5 V. B) an open circuit.
C) 0 V. D) a HIGH logic level.

69) In terms of digital logic, a LOW voltage usually represents 69)

A) a one. B) an open.
C) an illegal condition. D) a zero.

70) Waveforms A and B represent the inputs to a NOR gate. During which time intervals will the 70)
output from the gate (X) be LOW?

A) all time intervals B) time intervals 2, 3, and 4

C) never D) time intervals 1 and 5

71) In terms of digital logic, a zero is usually represented by 71)

A) -5 V. B) +2 V. C) 0 V. D) -10 V.

72) How many three-input NOR gates are in a 14-pin DIP integrated circuit? 72)
A) five B) three C) four D) two

73) Which logic function is represented by the equation AB = X? 73)

A) adder B) AND C) OR D) clock

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74) Waveforms A and B represent the inputs to an AND gate. During which time intervals will output 74)
from the gate (X) be LOW?

A) time intervals 2 and 3 B) time intervals 1 and 3

C) time intervals 1 and 4 D) time intervals 1 and 2

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Answer Key
Testname: CHAP03Q

1) C
2) D
3) A
4) B
5) D
6) C
7) D
8) D
9) B
10) A
11) D
12) B
13) D
14) A
15) C
16) B
17) A
18) C
19) A
20) D
21) D
22) D
23) C
24) D
25) D
26) A
27) B
28) B
29) A
30) D
31) A
32) C
33) C
34) C
35) C
36) A
37) C
38) B
39) A
40) D
41) B
42) A
43) A
44) B
45) D
46) D
47) B
48) A
49) B
50) D
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Answer Key
Testname: CHAP03Q

51) B
52) B
53) D
54) D
55) A
56) B
57) D
58) D
59) C
60) B
61) C
62) D
63) A
64) C
65) C
66) D
67) C
68) B
69) D
70) B
71) C
72) B
73) B
74) B

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