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1 1
Compal Confidential
ZAUSA Schematics Document
2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 1 of 40
A B C D E
A B C D E
Compal Confidential
Model Name : ZAUSA
ZZZ1
1 1
Sub-borad
4 Power/B 4
LS8951P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BLOCK DIAGRAMS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 2 of 40
A B C D E
A B C D E
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 5 S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON 6
+3VALW 3.3V always on power rail ON ON ON 7 S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON*
+0.95VALW 0.95V always on power rail ON ON ON Board ID / SKU ID Table for AD channel USB OC MAPPING
+1.35V 1.35V power rail for APU and DDR ON ON OFF Vcc 3.3V +/- 5%
OC# USB Port
+5VS 5V switched power rail ON OFF OFF R1562 100K +/- 5%
+3VS 3.3V switched power rail ON OFF OFF Board ID R1564 V AD_BID min V AD_BID typ V AD_BID max 0 USB20 port0
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V 1 USB20 port1,2,8,9 USB30 port0,1
+1.5VS 1.5V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 2
+0.95VS 0.95V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 3
+0.675VS 0.675V switched power rail for DDR terminator ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
4319OS38L01: EMIP@/ESDP@/SWR@/8106@/TS@/UMA@/43L01@
+VGA_CORE 0.95-1.2V switched power rail PX OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
4319OS38L02: EMIP@/ESDP@/SWR@/8106@/TS@/PX@/43L02@
+VDDCI 0.95-1.2V switched power rail PX OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
4319OS38L03: EMIP@/ESDP@/SWR@/8106@/TS@/PX@/43L03@
2
+3VS_VGA 3.3V switched power rail for VGA PX OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 2
4319OS38L04: EMIP@/ESDP@/SWR@/8106@/TS@/PX@/43L04@
+1.8VS_VGA 1.8V switched power rail for VGA PX OFF OFF
+1.5VS_VGA 1.5V switched power rail for VGA PX OFF OFF
BOM Structure Table
+0.95VS_VGA 0.95V switched power rail for VGA PX OFF OFF
BOM Structure BTO Item
SMBUS Control Table 43L01@
43L02@
X4-5110 BGA APU
X2-3450 BGA APU
WLAN Thermal 43L03@ E1-2210 BGA APU
SOURCE VGA BATT KB9012 SODIMM WWAN Sensor FCH APU RTD2132 APU PCIE PORT LIST X4-4110 BGA APU
43L04@
Port Device ME@ ME part
SMB_EC_CK1
SMB_EC_DA1 KB9012 X V X X X X X X X 0
SWR@
LDO@
LAN Switching mode
LAN LDO mode
+3VALW 1 LAN
2 WLAN
GAS@ Gastube
APU_SCLK0 3
APU_SDATA0
+3VS
APU
X X X V V X X X X PX@ Common VGA circuit
3 3
TS@ Touch Screen
SMB_EC_CK2
SMB_EC_DA2 KB9012 V X X X X V X V X EMIP@ EMI pop component
+3VS EMIU@ EMI Un pop component
ESDP@ ESD pop component
ESDU@ ESD Un pop component
USB Port Table X76@ VRAM
VRAM1@ Samsung 128Mbx16 K4W2G1646E-BC1A
EC SM Bus1 address EC SM Bus2 address 3 External Hynix 128Mbx16 H5TC2G63FFR-11C
USB 2.0 USB 3.0 Port USB Port VRAM2@
VRAM3@ Micron 126Mbx16 MT41J128M16JT-093G:K
Device Address HEX Device Address HEX 0 RIGHT USB Realtek RTL8111GUS-CG (Giga LAN)
8111@
Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH 1 Touch Screen Realtek RTL8106EUS-CG (10/100M)
8106@
SB-TSI (APU) 1001 100X b 98H 2 Unpop
@
3 Camera
VGA Internal Thermal 1000 001X b 82H 4 CardReader
5 WLAN/BT Combo
6 LEFT USB2.0
4 7 4
APU 0 8 LEFT USB3.0
XHCI
SM Bus address 1 9 LEFT USB2.0
Device Address HEX
DDR DIMM1 1010 000Xb A0H
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTES LIST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 3 of 40
A B C D E
A B C D E
2
+1.8VS
AD40 M_VREF UAPU1 R114 RP5 @
+MEM_VREF M_ZVDDIO APU_SVT
AC38 M_VREFDQ M_ZVDDIO_MEM_S AD41 1 2 1K_0402_5% 1 8
+VREF_DQ +1.35V
R74 @ APU_SVC 2 7
FT3 REV 0.51
39.2_0402_1% APU_SVD 3 6
1
2M201079J4461 2G_BGA769P 4 5
43L01@ DP_STEREOSYNC
2M151278J4461 1.5G BGA 769P 1K_0804_8P4R_5%
43L04@ APU_RST# R80 1 2 300_0402_5%
APU_PWRGD R82 1 2 300_0402_5%
+1.8VS
PU +1.8VS + PD APU_BPCLK_L R18 1 2 510_0402_1%
JHDT2 @ +1.8VS
1 2 APU_TCK +1.8VS
HDT+ 3
1 2
4 APU_TMS APU_TDI 1
RP6
8 APU_SCLK 1
RP3 @
8
PD
3 4 APU_TMS APU_CLKINT RP7 @
2 7 2 7
+VREF_DQ 5 6 APU_TDI APU_TCK 3 6 APU_SCLK 3 6 APU_BP2 1 8
5 6 APU_DBREQ# APU_CLKINT APU_BP3
4 5 4 5 2 7
7 8 APU_TDO APU_BP0 3 6
7 8 1K_0804_8P4R_5% 1K_0804_8P4R_5% APU_BP1 4 5
MEMORY VREF 1 2 APU_TRST# 9
9 10
10 APU_PWRGD
1K_0804_8P4R_5%
C342 C164 RP11 11 12 APU_RST#
1U_0402_6.3V6K 11 12 RP8 +1.8VS
0.1U_0402_16V7K 1 8
2 1 2 7 13 14 APU_DBRDY 1 8
13 14 APU_TRST#
3 6 2 7
4 5 15 16 APU_DBREQ# APU_PLLTEST0 3 6
15 16 APU_PLLTEST1 4 5
4 +1.35V +MEM_VREF 10K_0804_8P4R_5% 17 18 APU_PLLTEST0 4
RP2 17 18 1K_0804_8P4R_5%
1 8 19 20 APU_PLLTEST1
RP11, RP6 will @ when MP
19 20 APU_BPCLK_H R19 1
2 7 2 510_0402_1%
3 6 MEM_MAB_EVENT#
4 5 1 2
SAMTE_ASP-136446-07-B
1K_0804_8P4R_1% C337 C163
1000P_0402_50V7K 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
2 1
Issued Date 2013/01/11 Deciphered Date 2013/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT3 DDR3/DISP/MISC//HDT+
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 4 of 40
A B C D E
A B C D E
UAPU1B
PCIE APU POWER SEQUENCE
R10 P_GPP_RXP0 P_GPP_TXP0 L2
R8 P_GPP_RXN0 P_GPP_TXN0 L1 G-A +RTC
R5 P_GPP_RXP1 P_GPP_TXP1 K2 PCIE_ATX_DRX_P1 C19 1 2 0.1U_0402_16V7K EC_ON
19 PCIE_DTX_C_ARX_P1 PCIE_ATX_DRX_N1 PCIE_ATX_C_DRX_P1 19
LAN R4 P_GPP_RXN1 P_GPP_TXN1 K1 C20 1 2 0.1U_0402_16V7K LAN
19 PCIE_DTX_C_ARX_N1 PCIE_ATX_C_DRX_N1 19
G-B +3VALW/+5VALW
N5 P_GPP_RXP2 P_GPP_TXP2 J2 PCIE_ATX_DRX_P2 C17 1 2 0.1U_0402_16V7K
18 PCIE_DTX_C_ARX_P2 PCIE_ATX_DRX_N2 PCIE_ATX_C_DRX_P2 18
WLAN N4 P_GPP_RXN2 P_GPP_TXN2 J1 C18 1 2 0.1U_0402_16V7K WLAN
18 PCIE_DTX_C_ARX_N2 PCIE_ATX_C_DRX_N2 18
N10 P_GPP_RXP3 P_GPP_TXP3 H2 +1.8VALW
N8 P_GPP_RXN3 P_GPP_TXN3 H1
1 +0.95VALW 1
UAPU1E
2 2
CLK/SATA/USB/SPI/LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT3 PCIE/SATA/CLK/USB/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 5 of 40
A B C D E
A B C D E
1 2
C615 UAPU1D
150P_0402_50V8J ACPI/SD/AZ/GPIO/RTC/MISC
1 2 LPC_RST_A# AY4 LPC_RST_L SD_PWR_CTRL BA23
23 LPC_RST#
R602 APU_PCIE_RST#_BUF AY9 PCIE_RST_L SD_CLK/GPIO73 AY22
33_0402_5%
EC_RSMRST#_R AY5 RSMRST_L SD_CMD/GPIO74 AY23
SD_CD/GPIO75 AY20
BA8 PWR_BTN_L SD_WP/GPIO76 BA20 R907
23 PBTN_OUT#
PWR_GOOD_APU AM19 PWR_GOOD 33_0402_5%
T36 AY7 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 BA22 APU_PCIE_RST#_BUF 1 2
APU_PCIE_WAKE# APU_PCIE_RST# 9,18,19
18,19 APU_PCIE_WAKE# AW11 WAKE_L/GEVENT8_L SD_DATA1/GPIO78 AY21
SD_DATA2/GPIO79 AY24 1
AY3 SLP_S3_L SD_DATA3/GPIO80 BA24 C912
1 23 SLP_S3# 1
BA5 SLP_S5_L 150P_0402_50V8J
23 SLP_S5#
SD_LED/GPIO45 AY25
TEST0 AU13 TEST0
2
CS_JTAG_TMS_TEST1 AY10 TEST1/TMS SCL0/GPIO43 AU25 APU_SCLK0
TEST2 APU_SDATA0 APU_SCLK0 8,18
AY6 TEST2 SDA0/GPIO47 AV25 APU_SDATA0 8,18
AR23 KBRST_L SCL1/GPIO227 AY11 APU_SCLK1 If use as SMBUS :
23 KBRST# APU_SDATA1 APU_SCLK1 20 Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of: +3VS
23 GATEA20 AR31 GA20IN/GEVENT0_L SDA1/GPIO228 BA11 APU_SDATA1 20
AN5 LPC_PME_L/GEVENT3_L Qty: 1; Value: 2.2 KΩ; Tol: 5%
23 EC_SCI# If no use :
23 EC_SMI# AL7 LPC_SMI_L/GEVENT23_L GPIO49 AP27
GPIO50 AY28 Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
BT_OFF# 18
1
GPIO51 BA28 Qty: 1; Value: 10 KΩ; Tol: 5%
AP15 AC_PRES/IR_RX0/GEVENT16_L GPIO55 AV23 WL_OFF# 18
AV13 IR_TX0/GEVENT21_L GPIO57 AP21 UMA@ R911
BA9 IR_TX1/GEVENT6_L GPIO58 BA26 10K_0402_5%
BA10 IR_RX1/GEVENT20_L GPIO59 AV19 Board_ID1
2
AV15 IR_LED_L/LLB_L/GPIO184 GPIO64 AY27 PXS_RST#
APU_SPKR PXS_RST# 9 Board_ID1
SPKR/GPIO66 BA27 APU_SPKR 22
AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 AU21 PXS_PWREN
LAN_CLKREQ# PXS_PWREN 11,23,33
19 LAN_CLKREQ# AW29 CLK_REQ1_L/GPIO61 GPIO69 AY26 Board_ID1 Function
1
WLAN_CLKREQ# AR27 CLK_REQ2_L/GPIO62 GPIO70 AV21
18 WLAN_CLKREQ#
T53 AV27 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 AM21 R661 1 @ 2 0_0402_5%
VGA_CLKREQ# APU_GPIO174 H_PROCHOT# 4,23,27,34
AY29 CLK_REQG_L/GPIO65/OSCIN GPIO174 BA3 PX@ R912
10 VGA_CLKREQ#
10K_0402_5%
25 USB_OC0# AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L AV17 GEVENT2# 0 PX5.5
2
24 USB_OC1# AW1 USB_OC1_L/TDI/GEVENT13_L GEVENT4_L BA4
T52
T54
AV1
AY1
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L
GEVENT7_L AR15
GEVENT10_L AP17
1 UMA
GEVENT11_L AP11
HDA_BITCLK AN2 GEVENT17_L AN8
HDA_SDOUT
HDA_SDIN0
AN1
AK2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
BLINK/GEVENT18_L AU17
GEVENT22_L BA6 EC_LID_OUT#
32.768KMHz CRYSTAL
2 22 HDA_SDIN0 HDA_SDIN1 EC_LID_OUT# 23 2
T55 AK1 AZ_SDIN1/GPIO168
T56 HDA_SDIN2 AM1 AZ_SDIN2/GPIO169 GENINT1_L/GPIO32 BA29 32K_X1
T57 HDA_SDIN3 AL2 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AP23 VGA_PWRGD
VGA_PWRGD 33
HDA_SYNC AM2 AZ_SYNC 1 2 32K_X2
HDA_RST# AL1 AZ_RST_L FANOUT0/GPIO52 AV31
FANIN0/GPIO56 AU31 BT_DISABLE# R914
BT_DISABLE# 18
20M_0402_5%
32K_X1 AJ2 X32K_X1
Y3
32.768KHZ_12.5P_1TJF125DP1A000D
RTCCLK AV11 RTC_CLK
RTC_CLK 23
32K_X2 AJ1 X32K_X2 1 2
FT3 REV 0.51
2M201079J4461 2G_BGA769P 1 1
43L01@
C682 C686
PU +3VALW + PD 2
18P_0402_50V8J
2
18P_0402_50V8J
+3VALW
RP13
R691 1 @ 2 10K_0402_5%
HDA_RST#
22
22
HDA_RST_AUDIO#
HDA_SYNC_AUDIO
1
2
8
7 HDA_SYNC STRAPS OF APU
R686 1 2 10K_0402_5% APU_GPIO174 3 6 HDA_BITCLK
22 HDA_BITCLK_AUDIO
4 5 HDA_SDOUT
22 HDA_SDOUT_AUDIO
33_0804_8P4R_5% LPC_FRAME# LPC_CLK0_EC LPC_CLK1 GEVENT2_L RTC_CLK
SPI ROM BOOT FAIL TIMER CLKGEN 1.8V SPI ROM NORMAL POWR
3
PU +3VALW H (DEFAULT) ENABLED ENABLE UP/RESET TIMING 3
(DEFAULT) (DEFAULT)
+3VALW
EC_RSMRST# , POWER_GOOD +1.8VALW Use EC implement? BOOT FAIL TIMER CLKGEN 3.3V SPI ROM FAST POWER
R687 1 2 10K_0402_5% APU_PCIE_WAKE#
follow CRB Must connected to 10 ms RC delay
circuit on +1.8-V S5 power rail.
L LPC ROM DISABLED
(DEFAULT)
DISABLED (DEFAULT) UP/RESET TIMING
FOR SIMULATION
2
RP14 1 2 EC_RSMRST#_R
23 EC_RSMRST#
1
1 8 APU_SCLK1
+3VS 2 7 APU_SDATA1 RB751V-40TE17_SOD323-2 @
3 6 APU_SCLK0 R902 R904 R925 R949
APU_SDATA0 D5
4 5 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1 2 PWR_GOOD_APU
23 SYS_PWRGD_EC
2
2.2K_0804_8P4R_5%
RB751V-40TE17_SOD323-2
5,23 LPC_FRAME#
PU +3VS C209
1 1
C212
5,23 LPC_CLK0_EC
5 LPC_CLK1
1U_0402_6.3V6K 1U_0402_6.3V6K GEVENT2#
1
+3VALW
RP9 @ R929 R950
4 R926 4
1 8
PD R684 1 @ 2 10K_0402_5% HDA_BITCLK
2
3
7
6
2K_0402_5%
2.2K_0402_5% 2.2K_0402_5%
@
2
4 5
1 1
1
C249
C257
C252
C253
C166 CLRP1
0.22U_0402_10V6K SHORT PADS
Need OPEN
1 1 1 1
@
2
2
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2
for Clear CMOS
C925
C949
C923
C926
C927
C928
C929
C931
C930
C932
C211
C210
C208
C207
C230
C231
C258
C259
C161
C256
C254
C255
C232
AG32 VDDIO_MEM_S_18 VDDCR_CPU_18 AA21 C13 VSS_18 VSS_80 L10 AC15 VSS_142 VSS_204 AU1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AJ35 VDDIO_MEM_S_20 VDDCR_CPU_20 AA27 C17 VSS_20 VSS_82 L15 AC25 VSS_144 VSS_206 AU3
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
AL37 VDDIO_MEM_S_22 VDDCR_CPU_22 AC23 C21 VSS_22 VSS_84 L31 AC31 VSS_146 VSS_208 AU19
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AR35 VDDIO_MEM_S_23 VDDCR_CPU_23 AC27 C23 VSS_23 VSS_85 L39 AC39 VSS_147 VSS_209 AU23
VDDCR_CPU_24 AE21 C25 VSS_24 VSS_86 L41 AC41 VSS_148 VSS_210 AU27
VDDCR_CPU_25 AE23 C27 VSS_25 VSS_87 M1 AE3 VSS_149 VSS_211 AU39
VDDCR_CPU_26 AE27 C29 VSS_26 VSS_88 M2 AE7 VSS_150 VSS_212 AV9
C31 VSS_27 VSS_89 N3 AE25 VSS_151 VSS_213 AW3
VDDCR_NB_1 L13 +APU_CORE_NB C33 VSS_28 VSS_90 N7 AE29 VSS_152 VSS_214 AW7
0.7 ~ 1.325V VDDCR_NB_2 L17 C35 VSS_29 VSS_91 N15 AE32 VSS_153 VSS_215 AW13
VDDCR_NB_3 N11 C37 N19 AE39 AW15
13000mA VSS_30 VSS_92 VSS_154 VSS_216
@ @ @ @ @ VDDCR_NB_4 N13 C39 VSS_31 VSS_93 N25 AG3 VSS_155 VSS_217 AW17
VDDCR_NB_5 N17 C41 VSS_32 VSS_94 N29 AG5 VSS_156 VSS_218 AW19
VDDCR_NB_6 R11 D9 VSS_33 VSS_95 N31 AG10 VSS_157 VSS_219 AW21
VDDCR_NB_7 R13 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW23
+0.95VALW/+0.95VS OF APU +1.8VALW/+1.8VS OF APU VDDCR_NB_8 R17
VDDCR_NB_9 U13
D13
E3
VSS_35
VSS_36
VSS_97
VSS_98
P1
P2
AG13
AG15
VSS_159
VSS_160
VSS_221
VSS_222
AW25
AW27
3 VDD_095 VDD_095_GFX VDD_18 VDDCR_NB_10 U17
VDDCR_NB_11 W13
E4
E9
VSS_37
VSS_38
VSS_99
VSS_100
R3
R7
AG19
AG25
VSS_161
VSS_162
VSS_223
VSS_224
AW31
AW33 3
VDDCR_NB_12 W17 E11 VSS_39 VSS_101 R15 AG29 VSS_163 VSS_225 AW35
+0.95VS +0.95VS_APU_GFX +1.8VS VDDCR_NB_13 AA13 E13 VSS_40 VSS_102 R19 AG31 VSS_164 VSS_226 AW37
L22 VDDCR_NB_14 AA17 E27 VSS_41 VSS_103 R25 AG39 VSS_165 VSS_227 AW39
2 1 VDDCR_NB_15 AC13 E31 VSS_42 VSS_104 R29 AG41 VSS_166 VSS_228 AW41
FBMA-L11-201209-121LMA50T_0805 VDDCR_NB_16 AC17 E35 VSS_43 VSS_105 R39 AH1 VSS_167 VSS_229 AY13
C935
C934
C198
C199
C205
C204
C206
C260
C213
C936
C203
C933
C236
C237
C238
C239
C240
C233
VDDCR_NB_17 AE15 E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_NB_18 AE17 E39 VSS_45 VSS_107 U1 AJ3 VSS_169 VSS_231 AY18
VDDCR_NB_19 AE19 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30
100mA VDDCR_NB_20 AG17 G7 VSS_47 VSS_109 U3 AJ15 VSS_171 VSS_233 BA2
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
+1.5VS AL10 VDDIO_AZ_ALW_1 VDDCR_NB_21 AG21 G11 VSS_48 VSS_110 U7 AJ17 VSS_172 VSS_234 BA7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AL11 VDDIO_AZ_ALW_2 G13 VSS_49 VSS_111 U8 AJ19 VSS_173 VSS_235 BA13
G15 VSS_50 VSS_112 U11 AJ23 VSS_174 VSS_236 BA15
+1.8VALW B1 VDD_18_ALW_1 VDD_18_1 A2 +1.8VS G17 VSS_51 VSS_113 U15 AJ25 VSS_175 VSS_237 BA18
B2 500mA
VDD_18_ALW_2 1500mA VDD_18_2 A3 G21 VSS_52 VSS_114 U19 AJ29 VSS_176 VSS_238 BA21
VDD_18_3 B3 G25 VSS_53 VSS_115 U25 AJ31 VSS_177 VSS_239 BA25
VDD_18_4 C3 G29 VSS_54 VSS_116 U29 AJ32 VSS_178 VSS_240 BA31
G35 VSS_55 VSS_117 U31 AJ39 VSS_179 VSS_241 BA35
@ @ +3VALW_APU AL13 200mA
VDD_33_ALW_1 200mA VDD_33_1 AM15 +3VS G37 VSS_56 VSS_118 U39 AL3 VSS_180 VSS_242 BA39
AM13 VDD_33_ALW_2 VDD_33_2 AM17 G39 VSS_57 VSS_119 W3 AL8 VSS_181 VSSBG_DAC A15
G41 VSS_58 VSS_120 W5 AL15 VSS_182 VBURN AL31
+0.95VALW AR5 VDD_095_USB3_DUAL_1 VDD_095_1 AG23 +0.95VS H11 VSS_59 VSS_121 W11 AL17 VSS_183 PSEN AM29
+0.95VALW +0.95VALW +1.8VALW AU4 1000mA
VDD_095_USB3_DUAL_2 VDD_095_2 AG27 H13 VSS_60 VSS_122 W15 AL19 VSS_184
AV7 VDD_095_USB3_DUAL_3 VDD_095_3 AJ21 H23 VSS_61 VSS_123 W19 AL25 VSS_185
AW5 VDD_095_USB3_DUAL_4 VDD_095_4 AJ27 H31 VSS_62 VSS_124 W25 AL29 VSS_186
5000mA VDD_095_5 AL21 FT3 REV 0.51 FT3 REV 0.51
C937
C938
C216
C214
C221
C218
C220
C217
C219
C222
C160
C244
C250
C246
C248
C245
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDD_095_GFX_1 U10
4 +0.95VS_APU_GFX 4
1.5V / 1.5uA 600mA VDD_095_GFX_2 W10
2M201079J4461 2G_BGA769P
43L01@
@ @
15mil JDIMM1
1 VREF_DQ VSS1 2
1000P_0402_50V7K
DDRAB_SDQ[0..63]
0.1U_0402_16VK7
3 4 DDRAB_SDQ4
DDRAB_SDQ0 VSS2 DQ4 DDRAB_SDQ5 DDRAB_SDQ[0..63] 4
2 1 5 DQ0 DQ5 6
C176
C142
DDRAB_SDQ1 7 8 DDRAB_SDM[0..7]
DQ1 VSS3 DDRAB_SDM[0..7] 4
9 10 DDRAB_SDQS0#
VSS4 DQS#0 DDRAB_SDQS0# 4 DDRAB_SMA[0..15]
DDRAB_SDM0 11 12 DDRAB_SDQS0 DDRAB_SMA[0..15] 4
1 2 @ DM0 DQS0 DDRAB_SDQS0 4
13 14
DDRAB_SDQ2 VSS5 VSS6 DDRAB_SDQ6
15 DQ2 DQ6 16
DDRAB_SDQ3 17 18 DDRAB_SDQ7
DQ3 DQ7
19 VSS7 VSS8 20
1 DDRAB_SDQ8 DDRAB_SDQ12 1
21 DQ8 DQ12 22
DDRAB_SDQ9 23 24 DDRAB_SDQ13
DQ9 DQ13
25 VSS9 VSS10 26
DDRAB_SDQS1# 27 28 DDRAB_SDM1
4 DDRAB_SDQS1# DDRAB_SDQS1 DQS#1 DM1 MEM_MAB_RST#
4 DDRAB_SDQS1 29 30 MEM_MAB_RST# 4
DQS1 RESET#
DDRAB_SDQ10
31
33
VSS11
DQ10
VSS12
DQ14
32
34 DDRAB_SDQ14 +1.35V/+0.675VS OF DIMM1
DDRAB_SDQ11 35 36 DDRAB_SDQ15
DQ11 DQ15
37 VSS13 VSS14 38
DDRAB_SDQ16 39 40 DDRAB_SDQ20 +1.35V +0.675VS
DDRAB_SDQ17 DQ16 DQ20 DDRAB_SDQ21
41 DQ17 DQ21 42
43 44
DDRAB_SDQS2# VSS15 VSS16 DDRAB_SDM2
4 DDRAB_SDQS2# 45 DQS#2 DM2 46
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C126
C127
DDRAB_SDQS2 47 48 1
4 DDRAB_SDQS2 DQS2 VSS17 DDRAB_SDQ22
49 50 1 1 1 1 1 1 1 1 1 1 1 1
DDRAB_SDQ18 VSS18 DQ22 DDRAB_SDQ23 C9 +
51 52
DDRAB_SDQ19 DQ18 DQ23 100U_B2_6.3VM_R45M
53 DQ19 VSS19 54
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28 @
DDRAB_SDQ24 VSS20 DQ28 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2 2
57 DQ24 DQ29 58
DDRAB_SDQ25 59 60
DQ25 VSS21 DDRAB_SDQS3#
61 62 DDRAB_SDQS3# 4
DDRAB_SDM3 VSS22 DQS#3 DDRAB_SDQS3
63 64 DDRAB_SDQS3 4
DM3 DQS3
65 VSS23 VSS24 66
DDRAB_SDQ26 67 68 DDRAB_SDQ30
DDRAB_SDQ27 DQ26 DQ30 DDRAB_SDQ31
69 70
DQ27 DQ31 @ @ @ @ @ @
71 VSS25 VSS26 72
DDRA_CKE0 73 74 DDRA_CKE1
4 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 4
75 76
VDD1 VDD2 DDRAB_SMA15
77 78
2
4 DDRAB_SBS2#
DDRAB_SBS2# 79
81
NC1
BA2
A15
A14 80
82
DDRAB_SMA14 VREF for DIMM1 2
2
DDRAB_SMA5 91 92 DDRAB_SMA4
A5 A4 R65 R66
93 94
DDRAB_SMA3 VDD7 VDD8 DDRAB_SMA2 1K_0402_1%
95 A3 A2 96 1K_0402_1%
DDRAB_SMA1 97 98 DDRAB_SMA0
A1 A0
99 100
1
DDRA_CLK0 VDD9 VDD10 DDRA_CLK1
101 102 DDRA_CLK1 4
4 DDRA_CLK0 DDRA_CLK0# CK0 CK1 DDRA_CLK1# +VREF_DQ +VREF_CA
103 CK0# CK1# 104 DDRA_CLK1# 4
4 DDRA_CLK0#
105 106
DDRAB_SMA10 VDD11 VDD12 DDRAB_SBS1#
107 108 DDRAB_SBS1# 4
A10/AP BA1
2
DDRAB_SBS0# 109 110 DDRAB_SRAS#
4 DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# 4
111 112 R67 R68
DDRAB_SWE# VDD13 VDD14 DDRA_SCS0# 1K_0402_1%
113 114 DDRA_SCS0# 4 1K_0402_1%
4 DDRAB_SWE# DDRAB_SCAS# WE# S0# DDRA_ODT0
4 DDRAB_SCAS# 115 116 DDRA_ODT0 4
CAS# ODT0
117 118
1
DDRAB_SMA13 VDD15 VDD16 DDRA_ODT1
119 120 DDRA_ODT1 4
DDRA_SCS1# A13 ODT1
121 122
4 DDRA_SCS1# S1# NC2
123
VDD17 VDD18
124 15mil
125 126 +VREF_CA
NCTEST VREF_CA
127 128
VSS27 VSS28
1000P_0402_50V7K
0.1U_0402_16VK7
DDRAB_SDQ32 129 130 DDRAB_SDQ36
DDRAB_SDQ33 DQ32 DQ36 DDRAB_SDQ37
131 DQ33 DQ37 132 1 2
C134
C167
133 134
DDRAB_SDQS4# VSS29 VSS30 DDRAB_SDM4
4 DDRAB_SDQS4# 135 136
DDRAB_SDQS4 DQS#4 DM4
4 DDRAB_SDQS4 137 138
DQS4 VSS31 DDRAB_SDQ38 2 @ 1
139 140
DDRAB_SDQ34 VSS32 DQ38 DDRAB_SDQ39
141 142
3 DDRAB_SDQ35 DQ34 DQ39 3
143 DQ35 VSS33 144
145 146 DDRAB_SDQ44
DDRAB_SDQ40 VSS34 DQ44 DDRAB_SDQ45
147 148
DDRAB_SDQ41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDRAB_SDQS5#
DDRAB_SDM5 VSS36 DQS#5 DDRAB_SDQS5 DDRAB_SDQS5# 4
153 154 DDRAB_SDQS5 4
DM5 DQS5
155 156
DDRAB_SDQ42 VSS37 VSS38 DDRAB_SDQ46
157 158
DDRAB_SDQ43 DQ42 DQ46 DDRAB_SDQ47
159 160
DQ43 DQ47
161 VSS39 VSS40 162
DDRAB_SDQ48 163 164 DDRAB_SDQ52
DDRAB_SDQ49 DQ48 DQ52 DDRAB_SDQ53
165 166
DQ49 DQ53
167 VSS41 VSS42 168
DDRAB_SDQS6# 169 170 DDRAB_SDM6
4 DDRAB_SDQS6# DQS#6 DM6
DDRAB_SDQS6 171 172
4 DDRAB_SDQS6 DQS6 VSS43 DDRAB_SDQ54
173 174
DDRAB_SDQ50 VSS44 DQ54 DDRAB_SDQ55
175 176
DDRAB_SDQ51 DQ50 DQ55
177 178
DQ51 VSS45 DDRAB_SDQ60
179 180
DDRAB_SDQ56 VSS46 DQ60 DDRAB_SDQ61
181 182
DDRAB_SDQ57 DQ56 DQ61
183 184
DQ57 VSS47 DDRAB_SDQS7#
185 VSS48 DQS#7 186 DDRAB_SDQS7# 4
DDRAB_SDM7 187 188 DDRAB_SDQS7
DM7 DQS7 DDRAB_SDQS7 4
189 VSS49 VSS50 190
DDRAB_SDQ58 191 192 DDRAB_SDQ62
DDRAB_SDQ59 DQ58 DQ62 DDRAB_SDQ63
193 194
DQ59 DQ63
195 VSS51 VSS52 196
197 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# 4
+3VS 199 200 APU_SDATA0 6,18
VDDSPD SDA
201 202 APU_SCLK0 6,18
SA1 SCL
203 204 +0.675VS
VTT1 VTT2
4 4
205 206
G1 G2
+3VS FOX_AS0A626-U4RN-7F
ME@
1 1
C135 C136 Security Classification Compal Secret Data Compal Electronics, Inc.
2.2U_0603_6.3V6K 0.1U_0402_16VK7 2013/01/11 2013/12/31 Title
@ 2 2
DIMM_A H:4mm Issued Date Deciphered Date
DDR3 SODIMM-I Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 8 of 40
A B C D E
1 2 3 4 5
U666A PX@
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
A A
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
TMDP
R29 NC#R29 NC#T26 T26
P28 NC#P28 NC#T27 T27
TXCBP_DPB3P AH20
TXCBM_DPB3N AJ19
P30 NC#P30 NC#T24 T24
N31 NC#N31 NC#T23 T23 TX3P_DPB2P AL21
TX3M_DPB2N AK20
TX5P_DPB0P AL23
M30 NC#M30 NC#P24 P24 TX5M_DPB0N AK22
L31 NC#L31 NC#P23 P23
NC_TXOUT_U3P AK24
NC_TXOUT_U3N AJ23
L29 NC#L29 NC#M27 M27
K30 NC#K30 NC#N26 N26
CALIBRATION
+3VS_VGA
5
U6 PX@
PXS_RST# 2
P
6 PXS_RST# B
4 GPU_RST#
DGPU_HOLD_RST# Y
6,18,19 APU_PCIE_RST# 1 A
G
1
3
R163
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
D D
PX@
2
+3VS_VGA
1
R327 R328 PS_0[5:4]=11
1
10K_0402_5% 10K_0402_5% PS_0[1] ROM_CONFIG[0]
PX@ PX@ AF2 PX@
NC#AF2
2
AF4 R5165 PS_0[2] ROM_CONFIG[1]
2
NC#AF4 8.45K_0402_1%
6 1 VGA_SMB_DA3 1 N9 AG3 PS_0[3] ROM_CONFIG[2]
4,20,23 EC_SMB_DA2 T201
2
DBG_DATA16 NC#AG3 PS_0
T202 1 L9 AG5
Q2416A DBG_DATA15 NC#AG5
T203 1 AE9 DPA PS_0[4] N/A
DBG_DATA14
1
ME2N7002D1KW-G 2N_SOT363-6 1 Y11 AH3
T204 DBG_DATA13 NC#AH3
PX@ 1 AE8 AH1 PX@ PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T205 DBG_DATA12 NC#AH1
5
1 AD9 C=NC R5166
A T206 DBG_DATA11 A
1 AC10 AK3 2K_0402_1%
T207 DBG_DATA10 NC#AK3
3 4 VGA_SMB_CK3 1 AD7 AK1
4,20,23 EC_SMB_CK2 T208
2
DBG_DATA9 NC#AK1
T209 1 AC8 DVO
Q2416B DBG_DATA8
T210 1 AC7 AK5
ME2N7002D1KW-G 2N_SOT363-6 DBG_DATA7 NC#AK5
T211 1 AB9 AM3
PX@ DBG_DATA6 NC#AM3
T212 1 AB8
DBG_DATA5
T213 1 AB7 AK6
EC_SMB_DA2 VGA_SMB_DA3 DBG_DATA4 NC#AK6
1
R162 @
2
0_0402_5%
T214 1 AB4
DBG_DATA3 NC#AM5
AM5 Resistor Divider Lookup Lable
T215 1 AB2 DPB
DBG_DATA2 +1.8VS_VGA
T216 1 Y8 AJ7 PS_1[3:1]=000 Strap Name :
EC_SMB_CK2 VGA_SMB_CK3 DBG_DATA1 NC#AJ7
1 2 T217 1 Y7 AH6 R_pu (ohm) R_pd (ohm) Bitd [3:1]
R164 @ 0_0402_5% DBG_DATA0 NC#AH6
PS_1[5:4]=11
1
AK8 PS_1[1] STRAP_BIF_GEN3_EN_A
NC#AK8 @
AL7 NC 4.75k 000
NC#AL7 R5167
8.45K_0402_1%
PS_1[2] TRAP_BIF_CLK_PM_EN
8.45k 2k 001
W6 PS_1[3] N/A
2
NC#W6 PS_1
V6 4.53k 2k 010
NC#V6
V4 PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
NC#V4
1
AC6 U5 6.98k 4.99k 011
NC#AC5 NC#U5 PX@
AC5 PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6 R5168
W3 4.53k 4.99k 100 C=NC
NC#W3 4.75K_0402_1%
AA5 V2
NC#AA5 NC#V2
AA6 DPC 3.24k 5.62k 101
2
NC#AA6
Y4
NC#Y4
W5 3.4k 10k 110
NC#W5
U1 AA3 4.75k NC 111
NC#U1 NC#AA3
W1 Y2
NC#W1 NC#Y2
U3
NC#U3 0402 1% resistors are equired
Y6 J8
NC#Y6 NC#J8 +1.8VS_VGA
AA1 PS_2[3:1]=000 Strap Name :
NC#AA1
PS_2[5:4]=11
Capacitor Divider Lookup Lable PS_2[1] N/A
R=NC
+3VS_VGA
I2C PS_2[2] N/A
B
Cap (nF) Bitd [5:4] B
R1 PS_2[3] STRAP_BIOS_ROM_EN
SCL PS_2
R3
SDA
680nF 00 PS_2[4] STRAP_BIF_VGA_DIS
1
R1444 1 @ 2 100K_0402_5% ACIN AM26 1
R1445 1 @ R
2 100K_0402_5% VGA_AC_BATT GENERAL PURPOSE I/O AK26 82nF 01 @ PX@ PS_2[5] N/A
GPU_GPIO0 AVSSN#AK26 C5203 R5164
33 GPU_GPIO0 U6
GPIO_0 0.082U_0402_16V6K 4.75K_0402_1%
U10 AL25 10nF 10
GPIO_1 G 2
T10 AJ25
2
VGA_SMB_DA3 GPIO_2 AVSSN#AJ25
U8 NC 11
+3VS_VGA VGA_SMB_CK3 SMBDATA
VGA_AC_BATT 23,27,29 ACIN
ACIN 1 2
U7
T9
SMBCLK
GPIO_5_AC_BATT
B
AVSSN#AG25
AH24
AG25
R165 PX@ 0_0402_5% T8
RP34 @ pull up 23 VGA_AC_BATT
VGA_AC_BATT 1 2 T7
GPIO_6
GPIO_7_BLON
DAC1
HSYNC
AH26
1 8 JTAG_TRSTB R166 @ 0_0402_5% P10 AJ27
JTAG_TDI GPIO_8_ROMSO VSYNC
2 7 P4
JTAG_TMS GPIO_9_ROMSI +1.8VS_VGA
3 6 P2 PS_3[3:1]=000 Strap Name :
JTAG_TCK GPIO_10_ROMSCK
4 5 N6 AD22
GPIO_11 RSET
N5 PS_3[5:4]=11
GPIO_12
1
10K_8P4R_5% N3 AG24 PS_3[1] BOARD_CONFIG[0] (Memory ID)
GPIO_13 AVDD X76@
Y9 AE22
GPU_VID1 GPIO_14_HPD2 AVSSQ R5174
33 GPU_VID1 N1 PS_3[2] BOARD_CONFIG[1] (Memory ID)
GPIO_15_PWRCNTL_0 8.45K_0402_1%
M4 AE23
GPIO_16 VDD1DI
R6 AD23 PS_3[3] BOARD_CONFIG[2] (Memory ID)
2
GPIO_17_THERMAL_INT VSS1DI PS_3
W10
R1446 1 PX@ GPIO19_CTF T29 GPIO19_CTF GPIO_18
2 1 M2 FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_19_CTF
1
10K_0402_5% GPU_VID2 P8 AM12
33 GPU_VID2 GPIO_20_PWRCNTL_1 CEC_1
R1443 1 PX@ 2 VGA_CLKREQ# GPU_VID5 P7 X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
33 GPU_VID5 GPIO_21
10K_0402_5% N8 C=NC R5169
R1439 1 PX@ TESTEN GPU_VID4 GPIO_22_ROMCSB 2K_0402_1%
2 33 GPU_VID4 AK10 AK12
1K_0402_5% GPU_VID3 GPIO_29 RSVD#AK12
33 GPU_VID3 AM10 AL11
2
VGA_CLKREQ#_R N7 GPIO_30 RSVD#AL11
6 VGA_CLKREQ# 1 2 AJ11
R167 @ 0_0402_5% CLKREQB RSVD#AJ11
JTAG_TRSTB L6
JTAG_TDI JTAG_TRSTB
L5
C5213 JTAG_TCK JTAG_TDI
1 L3
68P_0402_50V8J JTAG_TMS JTAG_TCK
L1 AL13
XTALIN R349 1 PX@ 2
10M_0402_5%
XTALOUT RF @ T70 1 JTAG_TDO
TESTEN
K4
K7
JTAG_TMS
JTAG_TDO
GENLK_CLK
GENLK_VSYNC
AJ13
C 2 TESTEN C
AF24
NC#AF24
AG13
Memory ID Memory Type Configuration Size R5174 R5169 X76 P/N
Y6 PX@ SWAPLOCKA
AH12
SWAPLOCKB
4 3 AB13
1
NC OSC
2
W8
W9
GENERICA
GENERICB
(default) 000 SA000068U00 Samsung K4W2G1646E-BC1A 1GB NC 4.75K X7641338L31
OSC NC GENERICC PS_0
W7 AC19
27MHZ 16PF +-30PPM X3G027000FG1H-HX 2 GENERICD PS_0
AD10
C341
2
SJ100009700 C350 AJ9
GENERICE
AD19 PS_1 001 SA000067500 Micron MT41J128M16JT-093G:K 1GB 8.45K 2K X7641338L32
8.2P_0402_50V_NPO 8.2P_0402_50V_NPO NC#AJ9 PS_1
AL9
PX@ PX@ NC#AL9 PS_2
AE17
1 1 AC14
PS_2 010 SA00006H400 Hynix H5TC2G63FFR-11C 1GB 4.53K 2K X7641338L33
HPD1 PS_3
T218 1 AB16 AE20
PX_EN PS_3
011 SA000068R00 Samsung K4W4G1646B-HC11 2GB 6.98K 4.99K X7641338L34
AE19
TS_A
1 AC16
T221 DBG_VREFG 100 SA000065D00 Micron MT41k256M16HA-107G:E 2GB 4.53K 4.99K X7641338L35
DDC/AUX
AE6
PLL/CLOCK DDC1CLK ZZZ2 ZZZ3 ZZZ4
AE5
DDC1DATA
AD2
AUX1P
AD4
AUX1N
AC11
DDC2CLK
AC13
DDC2DATA VRAM1@ VRAM2@ VRAM3@
XTALIN AM28 AD13 1G SAMSUNG 1G MICRON 1G HYNIX
XTALOUT XTALIN AUX2P X7641338L31 X7641338L32 X7641338L33
AK28 AD11
XTALOUT AUX2N
+1.5VS +1.5VS_VGA
U4101 PX@ AA27 A3
AO4354_SO8 370mA (HDMI) No Use GPU Display Port outpud AB24
GND GND
A30
+1.8VS_VGA GND GND
8
7
1
2
188mA (Display Port) AB32
AC24
GND GND AA13
AA16
GND GND
2
0.1U_0402_16V7K
6 3 R319 1 @ 2 +DP_VDDR U666G PX@ U? AC26 AB10
GND GND
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 5 1 1 0_0603_5% AC27 AB15
GND GND
C4105
C4106
C4107
R4102
C446
C447
DP POWER NC/DP POWER AD25 AB6
10_0603_5% GND GND
1 1 AD32 AC9
4
PX@ GND GND
A AG15 AE11 AE27 AD6 A
31
2 PX@ 2 PX@ 2 PX@ DP_VDDR#AG15 NC#AE11 GND GND
AG16 DP_VDDR#AG16 NC#AF11 AF11 AF32 GND GND AD8
AF16 AE13 AG27 AE7
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 DP_VDDR#AF16 NC#AE13 GND GND
AG17 DP_VDDR#AG17 NC#AF13 AF13 AH32 GND GND AG12
@
5 PXS_PWREN# AG18 DP_VDDR#AG18 NC#AG8 AG8 K28 GND GND AH10
AG19 DP_VDDR#AG19 NC#AG10 AG10 K32 GND GND AH28
B+ 1 2 1.5VSG_GATE Q4101B AF14 L27 B10
4
R4101 200K_0402_5% ME2N7002D1KW-G 2N_SOT363-6 DP_VDDR#AF14 GND GND
M32 GND GND B12
PX@ PX@ N25 B14
GND GND
1
1 N27 GND GND B16
R4103 C4109 P25 B18
0.01U_0402_16V7K GND GND
1.5M_0402_5% AG20 DP_VDDC#AG20 NC#AF6 AF6 P32 GND GND B20
PXS_PWREN# 2 @ PX@ AG21 AF7 R27 B22
2 +0.95VS_VGA DP_VDDC#AG21 NC#AF7 GND GND
AF22 AF8 T25 B24
280mA
2
DP_VDDC#AF22 NC#AF8 GND GND
AG22 AF9 T32 B26
1
Q4101A R320 1 @ +DP_VDDC DP_VDDC#AG22 NC#AF9 GND GND
2 AD14 DP_VDDC#AD14 U25 GND GND B6
ME2N7002D1KW-G 2N_SOT363-6 0_0603_5% U27 B8
PX@ GND GND
C450
C451
V32 GND GND C1
1 1 W25 GND GND C32
AG14 DP_VSSR NC#AE1 AE1 W26 GND GND E28
AH14 DP_VSSR NC#AE3 AE3 W27 GND GND F10
AM14 AG1 Y25 F12
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 DP_VSSR NC#AG1 GND GND
AM16 DP_VSSR NC#AG6 AG6 Y32 GND GND F14
@
AM18 DP_VSSR NC#AH5 AH5 GND F16
AF23 DP_VSSR NC#AF10 AF10 GND F18
AG23 DP_VSSR NC#AG9 AG9 GND F2
AM20 DP_VSSR NC#AH8 AH8 GND F20
AM22 DP_VSSR NC#AM6 AM6 M6 GND GND F22
AM24 DP_VSSR NC#AM8 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AG7 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG11 AG11 N18 GND GND F6
AE14 N21 GND F8
DP_VSSR GND GND
P6 GND GND G10
P9 GND GND G27
B
R12 GND GND G31 B
AF17 AE10 R15 G8
+3VS to +3VS_VGA (25mA) DPAB_CALR NC#AE10
R17
GND
GND
GND
GND H14
R20 GND GND H17
T13 H2
+1.8VALW to +1.8VS_VGA (311mA) 216-0841018 A0 SUN PRO? S3
T16
GND
GND
GND
GND H20
T18 GND GND H6
U4103 JG3 @
60mA T21 GND GND J27
+3VS 1 VIN1 VOUT1 14 1 2 +3VS_VGA T6 GND GND J31
2 VIN1 VOUT1 13 U15 GND GND K11
0.1U_0402_16V7K
0.1U_0402_16V7K
1 PAD-OPEN 4x4m 1 U17 K2
GND GND
C4111
C4124
PXS_PWREN 3 12 C4112 1 2 PX@ U20 K22
ON1 CT1 470P_0402_50V7K GND GND
U9 GND GND K6
+5VALW 4 VBIAS GND 11 V13 GND
2 PX@ 2 PX@
V16 GND
PXS_PWREN 5 10 C4126 1 2 PX@ V18
ON2 CT2 2200P_0402_50V7K GND
Y10 GND
JG18 @
6 VIN2 VOUT2 9 818mA Y15 GND
+1.8VALW 7 VIN2 VOUT2 8 1 2 +1.8VS_VGA Y17 GND
Y20 GND
0.1U_0402_16V7K
0.1U_0402_25V6
1 15 PAD-OPEN 4x4m 1 R11 A32
GPAD GND VSS_MECH
C4123
C4125
T11 GND VSS_MECH AM1
TPS22966DPUR_SON14_2X3 AA11 AM32
PX@ GND VSS_MECH
M12 GND
2 PX@ 2 PX@
N11 GND
V11 GND
C C
2
8 1
2
7 2 R4113
2
0.1U_0402_16V7K
6 3 100K_0402_5% R4114
10U_0603_6.3V6M
1U_0402_6.3V4Z
1 5 1 1 PX@ 470_0603_5%
C4113
C4114
C4115
R4107 PX@
3 1
ME2N7002D1KW-G 2N_SOT363-6
ME2N7002D1KW-G 2N_SOT363-6
10_0603_5% PXS_PWREN#
4
6 1
PX@
3 1
1
5 PXS_PWREN# Q4105B
4
B+ 1 2 0.95VSG_GATE R4115 PX@ Q4105A
1
R4109 200K_0402_5% Q4102B 100K_0402_5% PX@
4
1 PX@
2
6
R4104 C4122
1.5M_0402_5% 0.01U_0402_16V7K
D D
@ PX@
PXS_PWREN# 2
2
2
Q4102A
1
ME2N7002D1KW-G 2N_SOT363-6
PX@
+1.5VS_VGA
A
+VGA_CORE 10uF 1uF 0.1uF A
C365
C367
C375
C370
C371
C372
C373
C374
1 1 1 1 1 1 1 1
VDDC TBD 5 (1@) 10 (2@) 0 +PCIE_PVDD:
+1.8VS_VGA
U666D PX@ U? 50mA (PCIE2.0)
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2 2 2 2 2 2 2 2
80mA (PCIE3.0)
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
AM30
VDDCI 3.5A 1 3 0 1A MEM I/O PCIE_PVDD
PCIE
C380
C387
C394
H13 VDDR1 NC#AB23 AB23 1 1 1
H16 VDDR1 NC#AC23 AC23
H19 VDDR1 NC#AD24 AD24
J10 AE24
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
VDDR1 NC#AE24 2 2 2
J23 AE25
+0.95VS_VGA 10uF 1uF 0.1uF VDDR1 NC#AE25
PX@
PX@
PX@
J24 VDDR1 NC#AE26 AE26
J9 VDDR1 NC#AF25 AF25
K10 VDDR1 NC#AG26 AG26
K23
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24
VDDR1
VDDR1
C389
C390
C391
C381
C392
C3719
C3720
C3721
C3722
C3723
K9 L23
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
VDDR1 PCIE_VDDC
2 2 2 2 2 1 1 1 1 1 L11 VDDR1 PCIE_VDDC L24
BIF_VDDC 1.4A 0 0 0 L12
L13
VDDR1 PCIE_VDDC L25
L26
+PCIE_VDDC:
VDDR1 PCIE_VDDC +0.95VS_VGA
L20 M22 1.88A (PCIE2.0)
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 1 1 1 2 2 2 2 2 VDDR1 PCIE_VDDC
PX@
PX@
PX@
PX@
PX@
L21 VDDR1 PCIE_VDDC N22
2.5A (PCIE3.0)
PX@
PX@
PX@
PX@
PX@
L22 N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC
N24
PCIE_VDDC
PCIE_VDDC R22
C384
C386
C398
C399
C383
C403
C388
C3724
C3725
T22
+1.8VS_VGA 13mA LEVEL PCIE_VDDC
U22 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
L56 PX@ TRANSLATION PCIE_VDDC
PCIE_VDDC V22
1 2 +VDD_CT AA20
+1.5VS_VGA 10uF 1uF 0.1uF BLM15BD121SN1D_0402 AA21
VDD_CT
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDD_CT 2 2 2 2 2 2 2 2 2
C404
C405
C422
B
AB20 VDD_CT VDDC AA15 B
CORE
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
1 1 1 AB21 VDD_CT VDDC N15
N17
VDDR1 1.5A 3 5 5 +3VS_VGA VDDC
R13
L24 PX@ 25mA I/O VDDC
R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 +VDDR3 VDDC
1 2 AA17 VDDR3 VDDC R18
PX@
PX@
PX@
BLM15BD121SN1D_0402 AA18 Y21
VDDR3 VDDC
C410
C428
C429
AB17 VDDR3 VDDC T12
+VGA_CORE
+1.8VS_VGA 10uF 1uF 0.1uF 0 ohm P/N 1 1 1 AB18 VDDR3 VDDC T15
VDDC T17
V12 VDDR4 VDDC T20
Y12 U13
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 VDDR4 VDDC
U12 U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC
PX@
PX@
@
VDDC U18
VDDC V21
VDDC V15
MPLL_PVDD 130mA 1 1 1 VDDC V17
V20
VDDC
POWER
VDDC Y13
VDDC Y16
Y18
SPLL_PVDD 75mA 1 1 1 VDDC
AA12
VDDC
M11
VDDC
N12
21A (VDDC + VDDCI (Merged) - PRO S3 (DDR3))
VDDC
VDDR4 (300mA) 0 0 0 VDDC U11
+1.8VS_VGA
L47 PX@ 90mA PLL
1 2 +MPLL_PVDD
VDD_CT 13mA 1 1 1 MBK1608221YZF_2P
C406
C407
C433
1 1 1
1.4A +0.95VS_VGA
R21 R398
BIF_VDDC +BIF_VDDC
U21 1 2
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 0_0805_5%
L8 MPLL_PVDD
+1.8VS_VGA
PX@
PX@
PX@
@
C
L48 PX@ 75mA +VGA_CORE
C
C413
C415
C416
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O 1 1 1
BLM15BD121SN1D_0402
C408
C409
C434 M13
VDDCI
1 1 1 H7 SPLL_PVDD VDDCI M15
M16
+DP_VDDC 0 0 0
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDCI 2 2 2
VDDCI M17
+0.95VS_VGA
@
M18
100mA
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
PX@
PX@
1 2 +SPLL_VDDC H8 M21
BLM15BD121SN1D_0402 SPLL_VDDC VDDCI
C411
C412
C435
VDDCI N20
J7
+3VS_VGA 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1
PX@
PX@
PX@
216-0841018 A0 SUN PRO S3?
D D
M_DA[63..0]
14,15 M_DA[63..0]
M_MA[15..0]
14,15 M_MA[15..0]
M_DQM[7..0]
14,15 M_DQM[7..0]
M_DQS[7..0]
14,15 M_DQS[7..0]
A A
M_DQS#[7..0]
14,15 M_DQS#[7..0]
PX@
U666C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 DQA0_0 MAA0_0/MAA_0 M_MA1
J29 DQA0_1 MAA0_1/MAA_1 J20
M_DA2 H30 H23 M_MA2
M_DA3 DQA0_2 MAA0_2/MAA_2 M_MA3
H32 DQA0_3 MAA0_3/MAA_3 G23
M_DA4 G29 G24 M_MA4
M_DA5 DQA0_4 MAA0_4/MAA_4 M_MA5
F28 DQA0_5 MAA0_5/MAA_5 H24
M_DA6 F32 J19 M_MA6
+1.5VS_VGA +1.5VS_VGA M_DA7 DQA0_6 MAA0_6/MAA_6 M_MA7
F30 DQA0_7 MAA0_7/MAA_7 K19
M_DA8 C30 G20 M_MA13
M_DA9 DQA0_8 MAA0_8/MAA_13 M_MA15
F27 DQA0_9 MAA0_9/MAA_15 L17
M_DA10 A28 DQA0_10
1
1
M_DA11 C28 J14 M_MA8
PX@ PX@ M_DA12 DQA0_11 MAA1_0/MAA_8 M_MA9
E27 DQA0_12 MAA1_1/MAA_9 K14
R363 R365 M_DA13 G26 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 DQA0_13 MAA1_2/MAA_10 M_MA11
D26 DQA0_14 MAA1_3/MAA_11 J13
M_DA15 F25 H11 M_MA12
2
MEMORY INTERFACE
PX@ PX@ PX@ PX@ M_DA21 DQA0_20 MAA1_9/RSVD
F23 DQA0_21
R364 C467 R457 C514 M_DA22 D22 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 DQA0_22 WCKA0_0/DQMA0_0 M_DQM1
F21 DQA0_23 WCKA0B_0/DQMA0_1 E30
2 2 M_DA24 M_DQM2
E21 A21
2
D D
1
PX@ PX@
R452 R463
4.99K_0402_1% U1406 4.99K_0402_1% U1407
2
+FBA_VREF0 M8 E3 M_DA17 +FBA_VREF1 M8 E3 M_DA30
VREFCA DQL0 M_DA23 VREFCA DQL0 M_DA27
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 M_DA21 F2 M_DA31
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA22 1 M_MA0 N3 F8 M_DA24
PX@ PX@ M_MA1 A0 DQL3 M_DA18 PX@ PX@ M_MA1 A0 DQL3 M_DA29
P7 A1 DQL4 H3 P7 A1 DQL4 H3
R453 C472 M_MA2 P3 H8 M_DA19 R464 C540 M_MA2 P3 H8 M_DA26
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 A2 DQL5 M_DA16 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 A2 DQL5 M_DA28
N2 A3 DQL6 G2 N2 A3 DQL6 G2
2 M_MA4 M_DA20 2 M_MA4 M_DA25
P8 H7 P8 H7
2
M_MA5 A4 DQL7 M_MA5 A4 DQL7
P2 A5 P2 A5
M_MA6 R8 M_MA6 R8
M_MA7 A6 M_DA5 M_MA7 A6 M_DA8
R2 A7 DQU0 D7 R2 A7 DQU0 D7
M_MA8 T8 C3 M_DA3 M_MA8 T8 C3 M_DA14
M_MA9 A8 DQU1 M_DA4 M_MA9 A8 DQU1 M_DA9
R3 A9 DQU2 C8 R3 A9 DQU2 C8
M_MA10 L7 C2 M_DA1 M_MA10 L7 C2 M_DA12
M_MA11 A10/AP DQU3 M_DA6 M_MA11 A10/AP DQU3 M_DA10
R7 A11 DQU4 A7 R7 A11 DQU4 A7
M_MA12 N7 A2 M_DA0 M_MA12 N7 A2 M_DA15
M_MA13 A12 DQU5 M_DA7 M_MA13 A12 DQU5 M_DA11
T3 A13 DQU6 B8 T3 A13 DQU6 B8
M_MA14 T7 A3 M_DA2 M_MA14 T7 A3 M_DA13
M_MA15 A14 DQU7 M_MA15 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+1.5VS_VGA +1.5VS_VGA
M_BA0 M2 B2 M_BA0 M2 B2
13,15 M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
13,15 M_BA1 BA1 VDD BA1 VDD
M_BA2 M3 G7 M_BA2 M3 G7
13,15 M_BA2 BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 J7 N9 M_CLK0 J7 N9
B 13 M_CLK0 CK VDD CK VDD B
M_CLK#0 K7 R1 M_CLK#0 K7 R1
13 M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
13 M_CKE0 CKE/CKE0 VDD +1.5VS_VGA CKE/CKE0 VDD +1.5VS_VGA
VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
13 VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8
13 M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
13 M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
13 M_CAS#0 CAS VDDQ CAS VDDQ
M_WE#0 L3 D2 M_WE#0 L3 D2
13 M_WE#0 WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1
M_DQS2 F3 H2 M_DQS3 F3 H2
M_DQS0 DQSL VDDQ M_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 DML VSS M_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1
VSS G8 VSS G8
M_DQS#2 G3 J2 M_DQS#3 G3 J2
M_DQS#0 DQSL VSS M_DQS#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9
13,15 DRAM_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
M_CLK0 PX@ L1 B9 PX@ L1 B9
M_CLK#0 R454 NC/CS1 VSSQ R456 NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
243_0402_1% L9 D8 243_0402_1% L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2
2
VSSQ VSSQ
1
C
VSSQ E8 VSSQ E8 C
R5171 R5170 F9 F9
40.2_0402_1% 40.2_0402_1% VSSQ VSSQ
VSSQ G1 VSSQ G1
PX@ PX@ G9 G9
VSSQ VSSQ
2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
1 X76@ X76@
PX@
C506
0.01U_0402_25V7K
2 +1.5VS_VGA
+1.5VS_VGA
U1406 side
U1407 side
C491
C512
C511
C519
C510
C521
C532
C520
C480
C481
C482
C485
C483
C531
C486
C490
C496
C497
C498
C499
C518
C533
C516
C474
C475
C476
C477
C478
C534
C479
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
D D
+1.5VS_VGA
+1.5VS_VGA
1
1
PX@
PX@ R461
R458 4.99K_0402_1% U1409
4.99K_0402_1% U1408
2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA49 A
13,14 M_DA[63..0]
2
+FBA_VREF2 M_DA38 VREFCA DQL0 M_DA53
M8 VREFCA DQL0 E3 H1 VREFDQ DQL1 F7
M_MA[15..0] H1 F7 M_DA36 F2 M_DA51
13,14 M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA37 1 M_MA0 N3 F8 M_DA54
DQL2 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA35 PX@ PX@ M_MA1 P7 H3 M_DA50
13,14 M_DQM[7..0] A0 DQL3 A1 DQL4
PX@ PX@ M_MA1 P7 H3 M_DA39 R462 C539 M_MA2 P3 H8 M_DA55
M_DQS[7..0] R459 C473 M_MA2 A1 DQL4 M_DA32 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 A2 DQL5 M_DA48
13,14 M_DQS[7..0] P3 A2 DQL5 H8 N2 A3 DQL6 G2
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 M_DA34 2 M_MA4 M_DA52
N2 G2 P8 H7
2
M_DQS#[7..0] 2 M_MA4 A3 DQL6 M_DA33 M_MA5 A4 DQL7
13,14 M_DQS#[7..0] P8 H7 P2
2
M_MA5 A4 DQL7 M_MA6 A5
P2 A5 R8 A6
M_MA6 R8 M_MA7 R2 D7 M_DA60
M_MA7 A6 M_DA41 M_MA8 A7 DQU0 M_DA59
R2 A7 DQU0 D7 T8 A8 DQU1 C3
M_MA8 T8 C3 M_DA44 M_MA9 R3 C8 M_DA63
M_MA9 A8 DQU1 M_DA43 M_MA10 A9 DQU2 M_DA56
R3 A9 DQU2 C8 L7 A10/AP DQU3 C2
M_MA10 L7 C2 M_DA45 M_MA11 R7 A7 M_DA62
M_MA11 A10/AP DQU3 M_DA42 M_MA12 A11 DQU4 M_DA57
R7 A11 DQU4 A7 N7 A12 DQU5 A2
M_MA12 N7 A2 M_DA46 M_MA13 T3 B8 M_DA61
M_MA13 A12 DQU5 M_DA40 M_MA14 A13 DQU6 M_DA58
T3 A13 DQU6 B8 T7 A14 DQU7 A3
M_MA14 T7 A3 M_DA47 M_MA15 M7
M_MA15 A14 DQU7 A15/BA3 +1.5VS_VGA
M7 A15/BA3 +1.5VS_VGA
M_BA0 M2 B2
M_BA0 M_BA1 BA0 VDD
13,14 M_BA0 M2 BA0 VDD B2 N8 BA1 VDD D9
M_BA1 N8 D9 M_BA2 M3 G7
13,14 M_BA1 BA1 VDD BA2 VDD
M_BA2 M3 G7 K2
13,14 M_BA2 BA2 VDD VDD
VDD K2 VDD K8
VDD K8 VDD N1
N1 M_CLK1 J7 N9
M_CLK1 VDD M_CLK#1 CK VDD
13 M_CLK1 J7 CK VDD N9 K7 CK VDD R1
M_CLK#1 K7 R1 M_CKE1 K9 R9
13 M_CLK#1 CK VDD CKE/CKE0 VDD +1.5VS_VGA
M_CKE1 K9 R9
13 M_CKE1 CKE/CKE0 VDD +1.5VS_VGA
VRAM_ODT1 K1 A1
VRAM_ODT1 M_CS#1 ODT/ODT0 VDDQ
13 VRAM_ODT1 K1 ODT/ODT0 VDDQ A1 L2 CS/CS0 VDDQ A8
M_CS#1 L2 A8 M_RAS#1 J3 C1
B 13 M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
13 M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
13 M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 E9
13 M_WE#1 WE VDDQ VDDQ
VDDQ E9 VDDQ F1
F1 M_DQS6 F3 H2
M_DQS4 VDDQ M_DQS7 DQSL VDDQ
F3 DQSL VDDQ H2 C7 DQSU VDDQ H9
M_DQS5 C7 H9
DQSU VDDQ
M_DQM6 E7 A9
M_DQM4 M_DQM7 DML VSS
E7 DML VSS A9 D3 DMU VSS B3
M_DQM5 D3 B3 E1
DMU VSS VSS
VSS E1 VSS G8
G8 M_DQS#6 G3 J2
M_DQS#4 VSS M_DQS#7 DQSL VSS
G3 DQSL VSS J2 B7 DQSU VSS J8
M_DQS#5 B7 J8 M1
DQSU VSS VSS
VSS M1 VSS M9
VSS M9 VSS P1
M_CLK1 P1 DRAM_RST# T2 P9
M_CLK#1 DRAM_RST# VSS RESET VSS
13,14 DRAM_RST# T2 RESET VSS P9 VSS T1
VSS T1 L8 ZQ/ZQ0 VSS T9
L8 ZQ/ZQ0 VSS T9
1
1
R5173 R5172 J1 B1
NC/ODT1 VSSQ
1
2
NCZQ1 VSSQ VSSQ
E2 E8
2
VSSQ VSSQ
VSSQ E8 VSSQ F9
1 VSSQ F9 VSSQ G1
PX@ G1 G9
C507 VSSQ VSSQ
VSSQ G9
0.01U_0402_25V7K 96-BALL
2 96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@
+1.5VS_VGA +1.5VS_VGA
C525
C524
C526
C513
C527
C536
C528
C504
C508
C505
C509
C529
C535
C530
C492
C501
C502
C503
C500
C523
C538
C522
C487
C484
C488
C489
C493
C537
C494
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
@
D D
D
3 1 +3VS_CMOS 10U
1
U46 close to JLVDS1 1 C1153
C1152 10U_0603_6.3V6M
G
2
4 TL_ENVDD 0.1U_0402_16V4Z @
R1458 2
150K_0402_5% 2
1
23 CMOS_ON#
R860 1
100K_0402_5% C1155
0.1U_0402_16V4Z
2
2
2 2
1
@ R1460 1 2
1 1 0_0805_5%
R890 C1158
10K_0402_5% 680P_0402_50V7K C1159
@ 4.7U_0805_25V6-K
2
+LEDVDD 2 2
+3VS +3VS_TS JLVDS2 ME@
1
1
2 2 G1 41
1 TS@ 2 3 42 2A JLVDS1 ME@
R5583 0_0402_5% 3 G2
4 43 1
4 G3 1
5
6
5 G4
44
45
change to EC contorl , 2
3
2
6 G5 3
due to FCH only 16 level
S
3 1 BKOFF# 7 46 4
INVT_PWM 7 G6 4
8
8 Add for protect DISPOFF# damage 5
5
9 9 6 6
Q156 LVDS_ACLK BKOFF#
G
10 7
2
R5581 1 2 100K_0402_5% @ 12 9
23 EC_TS_ON# 12 9
C1322
1 2 LVDS_A2 13 10
LVDS_A2# 13 4 LVDS_ACLK 10
14 4 LVDS_ACLK# 11
3 C1331 LVDS_A1 14 11 3
15 15 12 12
0.1U_0402_16V7K TS@ LVDS_A1# 16 13
2 1 LVDS_A0 16 4 LVDS_A2 13
@ 17 4 LVDS_A2# 14
LVDS_A0# 17 14
18 18 4 LVDS_A1 15 15
EDID_DATA 19 16
EDID_CLK 19 4 LVDS_A1# 16
20 4 LVDS_A0 17
20 17
+3VS 21 4 LVDS_A0# 18
21 18
+LCDVDD_CONN 22 4 EDID_DATA 19
22 19
(60 MIL) 23
23 4 EDID_CLK 20
20
+3VS 24 24 +3VS 21 21
25 25 2A +LCDVDD_CONN 22 22
+3VS_CMOS 26
26 (80 MIL) 23
23
USB20_P3_R 27 24
27 +3VS 24
CMOS USB20_N3_R 28 25 31
28 25 GND1
29 29 500mA +3VS_CMOS 26 26 GND2 32
30 USB20_P3_R 27 33
USB20_P1 30 USB20_N3_R 27 GND3
5 USB20_P1 USB20_N1
31
31 CMOS 28
28 GND4
34
32 R1464 1 EMIP@ 2 0_0402_5% 29 35
5 USB20_N1 32 29 GND5
33 30 36
33 30 GND6
TOUCH SCREEN EC_TS_ON#
34
34
35 L60 EMIU@ STARC_107K30-000001-G2
35 USB20_P3 USB20_P3_R SP010011S00
36 36 5 USB20_P3 1 1 2 2
37
37
38 38
39 5 USB20_N3 USB20_N3 4 3 USB20_N3_R
39 4 3
+3VS_TS 40
40 WCM-2012-900T_4P
STARC_107K40-000001-G2
1 2
R1465 EMIP@ 0_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 16 of 40
A B C D E
A B C D E
+3VS
+5VS_HDMI
UH1
+5VS
W=40mils +5VS_HDMI
3
OUT
1
1 C1161 1
1 IN
1
C R434 0.1U_0402_16V4Z
Q74 2 1 2 HDMI_DET_R 2
MMBT3904_SOT23-3 B 150K_0402_5% GND 2
E
2
4 HDMI_DET AP2330W-7_SC59-3
@
1
R864
200K_0402_5%
R859
1
100K_0402_5%
2
JHDMI1 ME@
HDMI_DET_R 19
HP_DET
+5VS_HDMI 18
+5V
17
HDMIDAT_R DDC/CEC_GND
16 SDA
HDMICLK_R 15
DP2_TXP0 C46 HDMI_TX2P SCL
4 DP2_TXP0 1 2 0.1U_0402_16V7K 14 Reserved
DP2_TXN0 C47 1 2 0.1U_0402_16V7K HDMI_TX2N 13
4 DP2_TXN0 CEC
HDMI_CLKN R1473 1 EMIU@ 2 0_0402_5% HDMI_CLK-_CONN 12 20
DP2_TXP1 C48 HDMI_TX1P CK- GND
4 DP2_TXP1 1 2 0.1U_0402_16V7K 11 21
DP2_TXN1 C55 HDMI_TX1N HDMI_CLKP HDMI_CLK+_CONN CK_shield GND
4 DP2_TXN1 1 2 0.1U_0402_16V7K R1474 1 EMIU@ 2 0_0402_5% 10 CK+ GND 22
HDMI_TX0N R1472 1 EMIU@ 2 0_0402_5% HDMI_TX0-_CONN 9 23
DP2_TXP2 C56 HDMI_TX0P D0- GND
4 DP2_TXP2 1 2 0.1U_0402_16V7K 8
DP2_TXN2 C68 HDMI_TX0N HDMI_TX0P HDMI_TX0+_CONN D0_shield
4 DP2_TXN2 1 2 0.1U_0402_16V7K R1476 1 EMIU@ 2 0_0402_5% 7 D0+
HDMI_TX1N R1477 1 EMIU@ 2 0_0402_5% HDMI_TX1-_CONN 6
DP2_TXP3 C72 HDMI_CLKP D1-
4 DP2_TXP3 1 2 0.1U_0402_16V7K 5
DP2_TXN3 C74 HDMI_CLKN HDMI_TX1P HDMI_TX1+_CONN D1_shield
4 DP2_TXN3 1 2 0.1U_0402_16V7K R1469 1 EMIU@ 2 0_0402_5% 4 D1+
HDMI_TX2N R1480 1 EMIU@ 2 0_0402_5% HDMI_TX2-_CONN 3 D2-
2
HDMI_TX2P R1481 1 EMIU@ 2 0_0402_5% HDMI_TX2+_CONN D2_shield
1
2 D2+ 2
CONCR_099ATAC19NBLCNF
DC232001K00
Close to HDMI connector
RP15
HDMI_TX2N 4 3 HDMI_TX2-_CONN HDMI_TX0-_CONN 1 8
4 3 HDMI_TX0+_CONN
3 2 7
WCM-2012HS-900T HDMI_CLK-_CONN 3 6
TVWDF1004AD0_DFN9 HDMI_CLK+_CONN 4 5
499_0804_8P4R_1%
RP16
+3VS +3VS +5VS_HDMI HDMI_TX2-_CONN 1 8
HDMI_TX2+_CONN 2 7
HDMI_TX1-_CONN 3 6
HDMI_TX1+_CONN 4 5
D69 ESDU@
HDMI_DET_R 6 3 HDMICLK_R 499_0804_8P4R_1%
I/O4 I/O2
2
1
D
Q75A +5VS_HDMI 4 1 HDMIDAT_R +5VS 2 Q76
ME2N7002D1KW-G 2N_SOT363-6 I/O3 I/O1 G 2N7002K_SOT23-3
2
YSUSB2.0-5 SOT-23-6 S
3
HDMI_CLK 1 6 HDMICLK_R
4 HDMI_CLK
Main: SC300001400
5
2nd: SC300001G00
4 HDMI_DATA HDMIDAT_R 4
4 HDMI_DATA 4 3
Q75B
ME2N7002D1KW-G 2N_SOT363-6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 17 of 40
A B C D E
A B C D E
R1518
+3VS_WLAN
2 1
@ 0_0805_5% 1 1
C1170 C1171
0.1U_0402_16VK7 0.1U_0402_16VK7
@
+3VS_WLAN +1.5VS 2 2
Mini-Express Card(WLAN/WiMAX)
JWLAN1 ME@
6,19 APU_PCIE_WAKE# APU_PCIE_WAKE# 1 2
1 WAKE# 3.3V 1
3 4
R1491 0_0402_5% BT_DISABLE#_R NC GND
6 BT_DISABLE# 1 2 5 6
WLAN_CLKREQ# NC 1.5V
6 WLAN_CLKREQ# 7 8
CLKREQ# NC
9 10
GND NC
5 CLK_PCIE_WLAN# 11 12
REFCLK- NC
5 CLK_PCIE_WLAN 13 14
REFCLK+ NC
15 16
GND NC
17 18
NC GND WL_OFF#
19 20 WL_OFF# 6
NC NC APU_PCIE_RST#
21 22 APU_PCIE_RST# 6,9,19
GND PERST#
5 PCIE_DTX_C_ARX_N2 23 24
PERn0 +3.3Vaux R1495 1 0_0402_5%
5 PCIE_DTX_C_ARX_P2 25 26 2 +3VS_WLAN
PERp0 GND
27 28
GND +1.5V R1496 1
29 30 2 @ 0_0402_5% APU_SCLK0 6,8
GND SMB_CLK R1497 1
5 PCIE_ATX_C_DRX_N2 31 32 2 @ 0_0402_5% APU_SDATA0 6,8
PETn0 SMB_DATA
5 PCIE_ATX_C_DRX_P2 33 34
PETp0 GND USB20_N5
35 36 USB20_N5 5
+3VS_WLAN GND USB_D- USB20_P5
37 38 USB20_P5 5
NC USB_D+
39 40
NC GND
41 42
NC LED_WWAN#
43 44
NC LED_WLAN#
45 46
0_0402_5% NC LED_WPAN#
47 48
EC_TX NC +1.5V
23 EC_TX 1 R1498 2 49 50
EC_RX NC GND
23 EC_RX 1 2 EC_RX_R 51 52
R1499 NC +3.3V
0_0402_5% 53 54
GND GND
1
@ R1522 BELLW_80019-1021
1K_0402_5% DC040004X00
2
6 BT_OFF# 1 2 BT_OFF#_R
@ R1520 1K_0402_5%
For EC to detect
BT_DISABLE#_R 1 2
debug card insert.
2
2 @ R1493 1K_0402_5% 2
R1501
100K_0402_5%
0.1U_0402_16VK7 10U_0603_6.3V6M
1
R708
2 Need SHORT
1 1 1 1
@ 0_0805_5%
C1176 C1177 C1178 C1179
2 2 2 2 JSSD1 ME@
1 2
0.01U_0402_16V7K 10U_0603_6.3V6M WAKE# 3.3V
3 4
3 NC GND 3
5 6
NC 1.5V
7 8
CLKREQ# NC
9 10
GND NC
11 12
REFCLK- NC
13 14
REFCLK+ NC
15 16
GND NC
17 18
NC GND
19 20
NC NC
21 22
SATA_DTX_C_ARX_P1 C1180 1 GND PERST#
2 0.01U_0402_16V7K SATA_DTX_ARX_P1 23 24
5 SATA_DTX_C_ARX_P1 SATA_DTX_C_ARX_N1 C1181 1 PERn0 +3.3Vaux
2 0.01U_0402_16V7K SATA_DTX_ARX_N1 25 26
5 SATA_DTX_C_ARX_N1 PERp0 GND
27 28
GND +1.5V
29 30
SATA_ATX_DRX_N1 GND SMB_CLK
5 SATA_ATX_DRX_N1 C278 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_N1 31 32
SATA_ATX_DRX_P1 C2758 1 PETn0 SMB_DATA
5 SATA_ATX_DRX_P1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_P1 33 34
PETp0 GND
35 36
GND USB_D-
37 38
+3VS_SSD NC USB_D+
39 40
NC GND
41 42
NC LED_WWAN#
43 44
NC LED_WLAN#
45 46
NC LED_WPAN#
47 48
NC +1.5V
49 50
NC GND
51 52
NC +3.3V
53 54
GND GND
BELLW_80019-1021
DC040004X00
4 4
Security Classification
2013/01/11
Compal Secret Data
2013/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 18 of 40
A B C D E
A B C D E
+3VALW +3V_LAN
W=60mils
370mA
1 2
R709
0_0805_5%
C1267
1U_0402_16V5K
C1278
0.1U_0402_16VK7
C1313
0.1U_0402_16VK7
C1314
0.1U_0402_16VK7
C1315
0.1U_0402_16VK7
1 1 1 2 @ 1 @ 1 1 1 1
1
C1195 C1196 C1268 C1274 C1277 C1187 SWR@
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16VK7 0.1U_0402_16VK7 0.1U_0402_16VK7 4.7U_0603_6.3V6K C1184
2
SWR@ SWR@ 2 2 2 LDO@ SWR@ 1 0.1U_0402_10V6K 2 2 2 2 2
U47 8111@
C1204
15P_0402_50V8J
1 2 LAN_XTALI
5 PCIE_DTX_C_ARX_P1 C1183 1 2 0.1U_0402_16V7K PCIE_DTX_ARX_P1 17 1 MDI0+ 1
C1186 1 HSOP MDIP0
5 PCIE_DTX_C_ARX_N1 2 0.1U_0402_16V7K PCIE_DTX_ARX_N1 18 2 MDI0-
HSON MDIN0 +LAN_VDD10 Y4
6,9,18 APU_PCIE_RST# 19 3 1
ISOLATEB PERSTB AVDD10 MDI1+
20 4 25MHZ_12PF_7V25000012
R1508 PCIE_WAKE#_R ISOLATEB MDIP1 MDI1-
23 LAN_WAKE# 1 2 0_0402_5% 21 5 2
R1509 @ +LAN_VDD10 LANWAKEB MDIN1 MDI2+ GND
6,18 APU_PCIE_WAKE# 1 2 0_0402_5% 22 6
+3V_LAN DVDD10 MDIP2 MDI2-
23 7
+LAN_REGOUT VDDREG MDIN2 +LAN_VDD10
24 8
+3V_LAN T37 REGOUT AVDD10 MDI3+
25 9 4
LAN_PWRDN LED2 MDIP3 MDI3- GND
23 LAN_PWRDN 26 10
T49 LED1/GPIO MDIN3 +3V_LAN
27 11
+3VS LAN_XTALI LED0 AVDD33 LAN_CLKREQ# 3
2 28 12 LAN_CLKREQ# 6
2
LAN_XTALO CKXTAL1 CLKREQB PCIE_ATX_C_DRX_P1 C1205
29 13 PCIE_ATX_C_DRX_P1 5
+LAN_VDD10 CKXTAL2 HSIP PCIE_ATX_C_DRX_N1 15P_0402_50V8J 3
30 14 PCIE_ATX_C_DRX_N1 5
R2220 @ LAN_WAKE# LAN_RST AVDD10 HSIN CLK_PCIE_LAN LAN_XTALO
1 2 10K_0402_5% 31 15 CLK_PCIE_LAN 5 1 2
RSET REFCLK_P
1
2
1K_0402_5%
R1513
2.49K_0402_1% U47 8106@
2
ISOLATEB
1
1
RTL8111GUS-CG_QFN32_4X4
R1242
15K_0402_5% RTL8106 EUS-CG
SA00006N900
2
T71
MDI0- 3 6 MDI1-
I/O2 I/O4
AZC099-04S.R7G_SOT23-6
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111F/8105E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 19 of 40
A B C D E
A B C D E
INT_KBD Conn.
KSI[0..7]
KSI[0..7] 23
JKB1
SMSC thermal sensor
KSO[0..15]
KSO[0..15] 23
GND1 28
placed near by VRAM
27 +3VS
KSI1 GND2
26 26
KSI7 25 25
1
KSI6 24
KSO9 24 +3VS R1524
1 23 23
1
KSI4 22 10K_0402_5%
KSI5 22 @
21 21
KSO0 20 U49
2
KSI2 20
19 19
KSI3 18
KSO5 18 EC_SMB_CK2
17 17 1 VDD SMCLK 10 EC_SMB_CK2 4,10,23
KSO1 16
KSI0 16 REMOTE1+ EC_SMB_DA2
15 15 2 2 DP1 SMDATA 9 EC_SMB_DA2 4,10,23
KSO2 14
KSO4 14 C1212 REMOTE1-
13 13 3 DN1 ALERT# 8
KSO7 12 0.1U_0402_16V4Z
KSO8 12 1 REMOTE2+
11 11 4 DP2 THERM# 7
KSO6 10
KSO3 10 REMOTE2-
9 9 5 DN2 GND 6
KSO12 8
KSO13 8
7 7
KSO14 6 EMC1403-1-AIZL-TR MSOP 10P
KSO11 6
5 5
KSO10 4
KSO15 3
4 Address 1001_101xb
R91 1 3
+5VS 2 300_0402_5% 2 2
CAP_LED# 1
23 CAP_LED# 1
ACES_88514-02601-071
ME@
Close U49 REMOTE1+
Close to DDR
REMOTE1+ 1
1
1 C
@ C1210 2 Q79
C1211 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2200P_0402_50V7K 2 E
3
2 REMOTE1- REMOTE1-
2 2
REMOTE2+
1
REMOTE2+
Under mSSD
C1213 1
1
2200P_0402_50V7K C
2 REMOTE2- @ C1214 Q80
2
100P_0402_50V8J B MMST3904-7-F_SOT323-3
Touch PAD Module 2 E
3
REMOTE2-
REMOTE1,2+/-:
+3VS 2
R1630 @
1
0_0402_5%
Trace width/space:10/10 mil
+3VALW 2 1 Trace length:<8"
R1631 0_0402_5%
C1301 JTP1
0.1U_0402_16V4Z 8 GND
7 GND
6 6
TP_CLK 5
23 TP_CLK 5
TP_DATA 4
23 TP_DATA 4
1 1 3 3
APU_SCLK1 2
6 APU_SCLK1 2
C1302 C1303 APU_SDATA1 1 H7 H8 H9 H10 H11 H12 H13 H15 H6
100P_0402_50V8J 100P_0402_50V8J
6 APU_SDATA1 1 Screw Hole HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
EMIU@ 2 2 EMIU@ ACES_88514-00601-071
A
3
ME@
3 1 1 SP010014M00 3
1
C1304 C1305
D42 0.1U_0402_10V6K 0.1U_0402_10V6K
PACDN042Y3R C/A SOT23-3 EMIU@ EMIU@ H_5P4X2P5 H_2P5 H_2P5N CHASSIS1_GND
ESDU@ 2 2 H_2P5 H_2P5 H_2P5 H_2P5 H_2P5
1
H_3P0
H18 H19 H20 H29
HOLEA HOLEA HOLEA HOLEA
B
CPU
1
H_4P0 H_4P0 H_4P0 H_4P0
H24 H23 H26 H27
H21 H22 HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA
C D
1
GPU LAN
1
CHASSIS1_GND H_1P5N H_1P5N
H_3P3 H_3P3 H_3P3 H_3P3
PCB Fedical Mark PAD
FAN1 Conn H14
HOLEA
H16
HOLEA
H17
HOLEA
H25
HOLEA FD1 FD2 FD3 FD4
+5VS R
1
JFAN1
1 2 +FAN1 1
R1525 1 H_2P5X3P1N H_2P5X3P1N
23 EC_TACH 2 2
0_0603_5% 23 EC_FAN_PWM 3 H_5P4X2P5 H_5P9X3P0
4 3 4
4 4
2 5 G1
6 G2
C1215
10U_0603_6.3V6M ACES_85204-04001
1 SP02000CW00
10U ME@
1 1
8
3.3V
+3VS 1 2 +3V_HDD 9
R1527 3.3V
10
0_0805_5% 3.3V
11 GND
12 GND
13
GND
14 V5
+5VS 1 2 +5V_HDD 15
R1526 V5
16
0_0805_5% V5
17 GND
18 RSVD
19
GND
20
2 V12 2
21 V12
22
V12
SANTA_192701-1
DC010006J00
+5V_HDD
1 1 1
C1218 C1219 C1221
1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 21 of 40
A B C D E
5 4 3 2 1
1 @ 2 1 @ 2
1U_0402_6.3V6K
0.1U_0402_16VK7
0.1U_0402_16VK7
R1529 1 1 R1530
1
0_0603_5% 0_0603_5%
C1226
C1227
C1228
@
2
2 2
D D
600ohms @100MHz 2A
P/N: SM01000EE00
@ Place near Pin25
R1531
+5VS 1 2 +5VS_PVDD
0.1U_0402_16VK7
0.1U_0402_16VK7
4.7U_0603_6.3V6K
0_0805_5% 2 1 1
+5VDDA_CODEC
C1235
C1236
+5VS
C1234 Place near Pin26
1 2 2
1 2
+1.5VS L37 0_0603_5%
0.1U_0402_16VK7
4.7U_0603_6.3V6K
+3VDD_CODEC +1.5VS
1 1
R1559 @ +3VS +CHGRTC +3VALW
C1231
C1230
1 2
0_0402_5%
1 3V
C1232 2 2 EXT_MIC_SLEEVE
1
1U_0402_6.3V6K
RA22 RA23
2 100K_0402_5% 100K_0402_5%
41
46
26
40
1
1
UA1 @
Place near Pin40 RA19
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
1
100K_0402_5% D
@ 2
G
2
22 S Q5
3
LINE1-L(PORT-C-L) SPK_L- 2N7002K_SOT23-3
21 LINE1-R(PORT-C-R) SPK-OUT-L- 43
1
C
SPK_L+ D C
SPK-OUT-L+ 42
24 HDA_RST_AUDIO# RA17 1 2 2 Q4
wide 40MIL 23
LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R) SPK-OUT-R+ 45
44
SPK_R+
SPK_R-
10K_0402_5%
1
G
S
MESS138-G 1N_SOT23-3
3
EXT_MIC_RING2 SPK-OUT-R- CA29
24 EXT_MIC_RING2 17 MIC2-L(PORT-F-L) /RING2
EXT_MIC_SLEEVE 18 1U_0402_6.3V6K
24 EXT_MIC_SLEEVE MIC2-R(PORT-F-R) /SLEEVE
32 HP_OUTL 24 @
HPOUT-L(PORT-I-L) 2
31 LINE1-VREFO-L HPOUT-R(PORT-I-R) 33 HP_OUTR 24
30 LINE1-VREFO-R
10 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 6
DMIC_DATA SYNC HDA_BITCLK_AUDIO
24 DMIC_DATA 2 GPIO0/DMIC-DATA BCLK 6 HDA_BITCLK_AUDIO 6
DMIC_CLK L21 1 2 SBY100505T-301Y-N 3
24 DMIC_CLK GPIO1/DMIC-CLK
EMIP@
SPDIF-OUT/GPIO2 48
PC_BEEP 12 PCBEEP
MONO-OUT 16
24 PLUG_IN# RA18 1 2 39.2K_0402_1% 13 MIC2-VREFO MIC2-VREFO 24
SENSE A
14 SENSE B
MIC2-VREFO 29
37 CA22 2 1 4.7U_0603_6.3V6K
CA23 2 CBP
1 1U_0402_6.3V6K 35 CBN LDO3-CAP 7 LDO3
LDO2 CA24 2 1 4.7U_0603_6.3V6K
EMI LDO2-CAP 39
27
LDO1-CAP LDO1 CA25 2
+3VS 36 CPVDD 1 4.7U_0603_6.3V6K
DMIC_CLK CA26 2 1 4.7U_0603_6.3V6K
28 CA27 1 2 1U_0402_6.3V6K
VREF
1 20 CPVREF
15 JDREF RA20 1 2 20K_0402_1%
C517 CA28 JDREF
2 1 4.7U_0603_6.3V6K 19 MIC-CAP CPVEE 34 CPVEE
22P_0402_50V8J
B
2
EMIU@
RA21 1 @ 2 0_0402_5% 4 DVSS
2 wide 40MIL JSPK1
B
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1 1 1 1 ACES_88266-04001
SP02000K200
C1248
C1249
C1250
C1251
ME@
R1549
1 2
PC Beep
EMIP@ 0_0402_5% SPK_R+_CONN SPK_L-_CONN
R1550
1 2 SPK_R-_CONN SPK_L+_CONN
EMIP@ 0_0402_5%
R1551 EMI EC Beep 23 BEEP# 1
C1252
2
0.1U_0402_16VK7
2
1 2 C44
EMIP@ 0_0402_5% 1 2 HDA_BITCLK_AUDIO R1557
R1561 APU Beep 6 APU_SPKR 1 2PC_BEEP1 1 2 1 2 PC_BEEP
1 2 R1552 EMIU@ 27_0402_5% C1253 0.1U_0402_16VK7 1K_0402_5%
EMIU@ 0_0402_5% 1 D38 D39
0.1U_0402_16V7K
1
1
C1247 @ ESDU@ ESDU@
33P_0402_50V8J R1558 Main: SCA00002900
2 EMIU@ 10K_0402_5% 2nd: SCA000001I00
2
GND GNDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC259Q-VC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A321PR01
Date: Monday, February 04, 2013 Sheet 22 of 40
5 4 3 2 1
A B C D E
R305 2 1 0_0603_5%
R1562 100K +/- 5%
Board ID R1564 VAD_BID min V AD_BID typ VAD_BID max
L38 +5VALW
0 0 0 V 0 V 0 V MP
FBM-11-160808-601-T_0603 1 1 1 1 1 1
+EC_VCCA 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
C1256
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
C1258
1000P_0402_50V7K
C1261
1000P_0402_50V7K
C1259
+3VLP_EC 1 2 +EC_VCCA
1 1 2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
C1262 C1260 2 2 2 2 2 2 R1266
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
111
125
1 0.1U_0402_16V4Z 1000P_0402_50V7K U51 USB_ON# 1 1
22
33
96
67
2
9
2 ECAGND 2
1 2
L39 10K_0402_5%
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
FBM-11-160808-601-T_0603 +3VALW +3VS
1
6 GATEA20 1 GATEA20/GPIO00 GPIO0F 21
2 23 BEEP# R1562
6 KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 22
3 26 EC_FAN_PWM 100K_0402_5%
5 SERIRQ SERIRQ GPIO12 EC_FAN_PWM 20
4 27 ACOFF
5,6 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF 29
LPC_AD3 5
5 LPC_AD3
2
LPC_AD2 LPC_AD3 EC_TACH R1581 1
5 LPC_AD2 7 LPC_AD2 PWM Output 2 10K_0402_5%
LPC_AD1 8 63 BATT_TEMP
5 LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP 27,28
@ LPC_AD0 BRDID EC_FAN_PWM R1582 1 @ 2 10K_0402_5%
C1263
5 LPC_AD0 10 LPC_AD0LPC & MISC GPIO39 64
2 1 22P_0402_50V8J R1560 2 @ 1 10_0402_5% ADP_I/GPIO3A 65 ADP_I
ADP_I 28,29
5,6 LPC_CLK0_EC 12 CLK_PCI_EC AD Input GPIO3B 66
LPC_RST# 13 75 BRDID
6 LPC_RST# PCIRST#/GPIO05 GPIO42
1
1 2 EC_RST# 37 76 ENBKL
+3VLP_EC EC_RST# IMON/GPIO43 ENBKL 4
R1563 47K_0402_5% EC_SCI# 20 R1564
6 EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 33K_0402_5%
28 BATT_LEN# GPIO1D +5VS
DAC_BRIG/GPIO3C 68
C1264 70
2
0.1U_0402_16V4Z EN_DFAN1/GPIO3D
1 DA Output IREF/GPIO3E 71
KSI0 55 72 TP_CLK R1568 1 2 4.7K_0402_5%
KSI1 KSI0/GPIO30 CHGVADJ/GPIO3F
56 KSI1/GPIO31
KSI2 57 TP_DATA R1570 1 2 4.7K_0402_5%
KSI3 KSI2/GPIO32 EC_MUTE#
58 KSI3/GPIO33 EC_MUTE#/GPIO4A 83 EC_MUTE# 22
KSI4 59 84 USB_ON#
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# 24,25
KSI5 60 85
KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C +3VLP_EC
61 KSI6/GPIO36 PS2 Interface EAPD/GPIO4D 86
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 20
KSO0 39 88 TP_DATA
靠靠EC端
2 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 20 2
KSO1 40 EC_SMB_DA1 R1577 1 2 2.2K_0402_5%
KSO[0..15] KSO2 KSO1/GPIO21
41 KSO2/GPIO22
20 KSO[0..15] KSO3 42 97 EC_TS_ON# EC_SMB_CK1 R1574 1 2 2.2K_0402_5%
KSI[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# 16
KSO4 43 98 EC_SPI_AISO R106 1 2 0_0402_5% APU_SPI_AISO_R
20 KSI[0..7] KSO4/GPIO24 WOL_EN/GPXIOA01 APU_SPI_AISO_R 5
KSO5 EC_SPI_AOSI R107 1 2 0_0402_5% APU_SPI_AOSI_R EC_MUTE# R1565 1 @ 2 10K_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99
NTC_V APU_SPI_CLK_R
APU_SPI_AOSI_R 5
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 NTC_V 28 APU_SPI_CLK_R 5
KSO7 46 SPI Device Interface EC_SPI_CS1# R115 1 2 0_0402_5% APU_SPI_CS1#_R LAN_WAKE# R1585 1 2 10K_0402_5%
KSO7/GPIO27 APU_SPI_CS1#_R 5
KSO8 47
KSO9 KSO8/GPIO28 EC_SPI_AISO
48 KSO9/GPIO29 SPIDI/GPIO5B 119
KSO10 49 120 EC_SPI_AOSI
KSO11 KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_CLK_R
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 1 2 APU_SPI_CLK_R LID_SW# R344 1 2 47K_0402_5%
KSO12 51 128 EC_SPI_CS1# R112 33_0402_5%
KSO13 KSO12/GPIO2C SPICS#/GPIO5A EMIP@
52 KSO13/GPIO2D
KSO14 53
KSO15 KSO14/GPIO2E APU_IMON
54 KSO15/GPIO2F ENBKL/GPIO40 73 APU_IMON 34
81 74 VGATE
KSO16/GPIO48 PECI_KB930/GPIO41 VGATE 34
82 89 SPOK
KSO17/GPIO49 FSTCHG/GPIO50 SPOK 30,31,32
90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# 24
91 CAP_LED#
CAPS_LED#/GPIO53 CAP_LED# 20
EC_SMB_CK1 77 GPIO 92 PWR_LED#
28,29 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# 24
EC_SMB_DA1 78 93 BATT_LOW_LED#
28,29 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# 24 +3VLP
EC_SMB_CK2 79 SM Bus 95 SYSON
4,10,20 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 26,31
EC_SMB_DA2 80 121 VR_ON @
4,10,20 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON 26,31
1
127 095_18ALW_PWR_EN KB9012A2 work around
PM_SLP_S4#/GPIO59 095_18ALW_PWR_EN 31,32
R343
47K_0402_5%
SLP_S3# 6 100 EC_RSMRST#
6 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 6
SLP_S5# 14 101 EC_LID_OUT#
6 SLP_S5# EC_LID_OUT# 6
2
EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 Turbo_V
6 EC_SMI# 15 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 102 Turbo_V 28
CMOS_ON# 16 103 PROCHOT
16 CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT 28
19 LAN_PWRDN 2 1 LAN_PWRDN_R 17 GPIO0B VCOUT0_PH/GPXIOA07 104 MAINPWON_R R1591 2 1 0_0402_5% MAINPWON 30
R1588 @ 0_0402_5% 18 GPO 105 BKOFF#
3 GPIO0C BKOFF#/GPXIOA08 BKOFF# 16 3
19 GPIO 106 PBTN_OUT#
GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 6
25 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 107
EC_TACH 28 108 VGA_AC_BATT
20 EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VGA_AC_BATT 10
LAN_WAKE#
19 LAN_WAKE#
18 EC_TX
EC_TX
29
30
EC_PME#/GPIO15
EC_TX/GPIO16
For share ROM need
EC_RX 31 110 ACIN
18 EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN 10,27,29
SYS_PWRGD_EC 32 112 EC_ON 095_18ALW_PWR_EN 1 2
6 SYS_PWRGD_EC PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 30
NOVO# 34 114 ON/OFF ON/OFF 24 R339 100K_0402_5%
24 NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW# EC_RSMRST# 1 2
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 24
116 SUSP# R340 100K_0402_5%
SUSP#/GPXIOD05 SUSP# 26,31,32
GPXIOD06 117
118 BATT_TEMP 1 2
PECI_KB9012/GPXIOD07
AGND/AGND
C1272 ACIN 1 @ 2
1
69
@ @ R336 100K_0402_5%
2
H_PROCHOT# 4,6,27,34
ENBKL 1 2
1
D R338 100K_0402_5%
ECAGND PROCHOT 2 1
G
Q82 S C1269
3
2N7002K_SOT23-3 47P_0402_50V8J
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 23 of 40
A B C D E
A B C D E
+3VALW
2
R1592
100K_0402_5%
1
D40
NOVO# 2
23 NOVO#
1 NOVO_BTN#
ON/OFF 3
1
23 ON/OFF 1
DAN202UT106_SC70-3
For debug
SW 1
1 2 +3VLP
3 4
2
G
G
NTC017-DA1J-D160T_4P
6
5
DEBUG@ R1593
100K_0402_5%
1
J16
1 2 ON/OFF
SHORT PADS
@
0.1U_0402_10V6K
0.1U_0402_16V7K 1 8
GND VOUT
470P_0402_50V7K
0.1U_0402_10V6K
1 2 2 7 SP01001A900
VIN VOUT ME@
3 VIN VOUT 6 1 1 1
C1324
C1306
C1307
23,25 USB_ON# 4 EN FLG 5 USB_OC1# 6
G547I2P81U
2 2 @ 2 @
+3VS +USB2_VCCA
R1625 1 EMIU@ 2 0_0402_5%
W=80mils
L59 EMIP@ JCR1 ME@
USB20_N4 4 3 USB20_N4_R 1
5 USB20_N4 4 3 1
2 2
Card Reader 3 3
USB20_P4 1 2 USB20_P4_R 4
5 USB20_P4 1 2 4
USB20_P4_R 5
W CM-2012-900T_4P USB20_N4_R 5
6 6
1 2 7 7
R1626 EMIU@ 0_0402_5% USB20_P6_R 8
3 USB20_N6_R 8 3
9 9
10 10
R1614 1 EMIU@ 2 0_0402_5% USB20_P9_R 11
USB20_N9_R 11
12 12
13 13
L57 EMIP@ DMIC_CLK 14
22 DMIC_CLK 14
USB20_N6 4 3 USB20_N6_R DMIC_DATA 15
5 USB20_N6 4 3 22 DMIC_DATA 15
16 16
USB2.0 Port 17 17
USB20_P6 1 2 USB20_P6_R 18
5 USB20_P6 1 2 18
22 PLUG_IN# PLUG_IN# 19
W CM-2012-900T_4P HP_OUTL 19
22 HP_OUTL 20 20
1 2 HP_OUTR 21
22 HP_OUTR 21
R1615 EMIU@ 0_0402_5% 22
EXT_MIC_SLEEVE 22
22 EXT_MIC_SLEEVE 23 23
W=40mils 22 EXT_MIC_RING2 EXT_MIC_RING2 24 24
R1619 1 EMIU@ 2 0_0402_5%
22 MIC2-VREFO R1594 1 2 2.2K_0402_5% 25 GND1
26 GND2
L58 EMIP@
USB20_N9 4 3 USB20_N9_R R1595 1 2 2.2K_0402_5% ACES_88514-02401-071
5 USB20_N9 4 3 SP010015W 00
USB2.0 Port
USB20_P9 1 2 USB20_P9_R
5 USB20_P9 1 2
W CM-2012-900T_4P
1 2
R1624 EMIU@ 0_0402_5%
4 4
+5VALW JLED1
6 6 G2 8
5 5 G1 7
PW R_LED# 4
23 BATT_LOW _LED#
BATT_LOW _LED#
BATT_CHG_LED#
3
4
3
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2013/01/11 2013/12/31 Title
LED Board 23 BATT_CHG_LED#
1
2
1
Issued Date Deciphered Date
KB /SW /LPC Debug Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ACES_51524-0060N-001 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SP010014M10 Custom 0.1
ME@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 24 of 40
A B C D E
A B C D E
1 1
2A/Active Low
+5VALW +USB3_VCCA
W=80mils
5 USB20_N0
R567 1
0_0402_5%
@ 2
JUSB1
LP1
R1605 1 EMIU@ 2 0_0402_5% USB30_TX_R_P0 9
R569 1 @ 2 SSTX+
5 USB20_P0 1 VBUS
2 0_0402_5% USB30_TX_R_N0 8 2
L43 EMIP@ USB30_P8_R SSTX-
3 D+
USB30_N8 1 2 USB30_N8_R 7
5 USB30_N8 1 2 GND
USB30_N8_R 2 10
USB30_RX_R_P0 D- GND
6 SSRX+ GND 11
USB30_P8 4 3 USB30_P8_R 4 12
5 USB30_P8 4 3 GND GND
USB30_RX_R_N0 5 13
WCM-2012-900T_4P SSRX- GND
1 2 TAITW_PUBAU1-09FNLSCNN4H0
R1608 EMIU@ 0_0402_5% ME@
D45 ESDU@
L44 EMIP@ USB30_N8_R 3 6
USB30_MRX_DTX_N0 USB30_RX_R_N0 I/O2 I/O4
5 USB30_MRX_DTX_N0 1 1 2 2
4 4
Security Classification Compal Secret Data For EMI request Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31 Title
USB3.0 ports
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 25 of 40
A B C D E
A B C D E
AO4354_SO8
U3301 J5 @ 4408mA 8 1
+5VALW 1 VIN1 VOUT1 14 1 2 +5VS 7 2
2
10U_0603_6.3V6M
2 VIN1 VOUT1 13 6 3
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 PAD-OPEN 4x4m 1 1 1 5
C3301
C3303
C3310
10U_0603_6.3V6M
1U_0402_6.3V5K
SUSP# 3 12 C3302 1 2 1 1 R3304
ON1 CT1
C3306
C3304
C3305
220P_0402_50V7K 470_0603_5%
4
1 1
+5VALW 4 11 @
3 1
2 VBIAS GND 2 2 2
SUSP# 5 10 C3317 1 2 @ @ 2 2
ON2 CT2 2200P_0402_50V7K
J18 @
6 VIN2 VOUT2 9 1600mA SUSP
+1.8VALW 7 8 1 2 +1.8VS 5
VIN2 VOUT2
0.1U_0402_16V7K
B+ 1 2 0.95VS_GATE
0.1U_0402_25V6
1 15 PAD-OPEN 4x4m 1 R3306 200K_0402_5% Q3301B
4
GPAD
C3315
C3318
ME2N7002D1KW -G 2N_SOT363-6
1
TPS22966DPUR _SON14_2X3 1
6
R3309
2 2 C3307
1.5M_0402_5%
@ 0.022U_0603_50V7K
SUSP 2 2
2
Main: SA00004MM00, TI, TPS22966
1
2nd: SA00006FD00, A-Power, APE8990GN3B Q3301A
ME2N7002D1KW -G 2N_SOT363-6
3rd: AOS, AOZ1331 (engineering sample available on 2013/Jan/18)
2
6 3
10U_0603_6.3V6M
0.1U_0402_16V7K
5 R3321
10U_0603_6.3V6M
1U_0402_6.3V5K
1 1 1 1 470_0603_5%
C3326
C3327
C3328
C3329
4
1
2 @ 2 @ 2 2
3
B+ 1 2 3VS_GATE 5 SUSP
R3322 200K_0402_5%
Q3313B
4
1 ME2N7002D1KW -G 2N_SOT363-6
1
C3330
R3310 0.01U_0603_50V7K
1.5M_0402_5%
SUSP 2 @ 2
2
1
Q3313A
ME2N7002D1KW -G 2N_SOT363-6
3 3
+5VALW +5VALW
+1.35V +0.675VS
2
1
1
R1636
100K_0402_5%
R1627 R1629 R1638
470_0603_5% 470_0603_5% 100K_0402_5%
1
2
2
ME2N7002D1KW-G 2N_SOT363-6
ME2N7002D1KW-G 2N_SOT363-6
ME2N7002D1KW-G 2N_SOT363-6
SUSP SYSON#
ME2N7002D1KW-G 2N_SOT363-6
6
3
2 SYSON# 5 SUSP 2
23,31,32 SUSP#
SYSON 5
23,31 SYSON
1
1
1
Q100B
R1639 @
100K_0402_5% R1640
100K_0402_5%
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 26 of 40
A B C D E
5 4 3 2 1
VIN
@
JDCIN1 PF101 PL101
ACES_87302-0401-003 7A_24VDC_429007.WRML SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
1
2
2
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
3
3
1
D D
4 4
2
GND
PC101
PC102
PC103
PC104
6
GND
+5VS
+3VALW
2
4,6,23,34 H_PROCHOT#
47K_0402_1%
PR106
10K_0402_1%
L2N7002DW1T1G_SC88-6
PU101A
PR108
AS393MTR-E1 SO 8P OP
8
PC105 3 BATT_TEMP 23,28
P
+
PQ101A
1N4148WS-7-F_SOD323-2
2 2 1 1
1
O
2
-
G
1.5M_0402_5%
0.022U_0402_16V7K
100K_0402_1%
100P_0402_50V8J
4
1
PR104
PD105
PR109
PC107
C C
2
2
1
+5VS
+CHGRTC
PD109
- JRTC2 + PR131
560_0603_5%
PR132
560_0603_5%
PU102
Vout 3
RB751V-40_SOD323-2
2 1 +RTCBATT H_PROCHOT#
47K_0402_1%
2 1 1 2 1 2 1
Vin
0.1U_0603_25V7K
GND 2
680P_0603_50VK
PR107
L2N7002DW1T1G_SC88-6
1
PC112
1
3
PC113
@ MAXEL_ML1220T10 AP2138N-1.5TRG1_SOT23-3
8
2
PC106 5
P
2
PQ101B
5 2 1 7
O ACIN 10,23,29
1N4148WS-7-F_SOD323-2
6
RTC Battery -
G
0.022U_0402_16V7K
1.5M_0402_5%
PU101B
4
AS393MTR-E1 SO 8P OP
Need use+3.3V transfer to +1.5V LDO to APU side for Kaibini
PD104
PR105
2
1
1 2
RTCVREF
PD108
RB751V-40_SOD323-2
2
PR127
0_0402_5%
B B
@
1
+3VLP
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 27 of 40
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
PF201 PL201
JBATT2 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2
2 EC_SMCA
3 3 EC_SMDA
4
4
5 5
1
D D
6 6
1
PC201 PC202
7 7
100_0402_1%
100_0402_1%
1000P_0402_50V7K 0.01U_0402_25V7K
GND 8
2
9
@ GND PR201
PR202
SUYIN_200082GR007G201ZR
2
65W(UMA) : PR205=1.65K(SD034165180)
PH1 under CPU botten side :
EC_SMB_CK1 23,29 CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
EC_SMB_DA1 23,29
1 2 +3VALW
PR203
6.49K_0402_1%
+EC_VCCA
23,29 ADP_I
2
1.65K_0402_1%
12.7K_0402_1%
1
1 2 BATT_TEMP 23,27 A/D
PR205
PR206
PR204
10K_0402_5%
@
23 PROCHOT PR212
1
2 1
2
23 NTC_V
C 10K_0402_1% C
100K_0402_1%_NCP15WF104F03RC
+5VL +3VALW 23 Turbo_V
PH201
2
10K_0402_1%
1
PR211
2
+5VL PR215
1
PC204 PR217 100K_0402_1%
2
1
6 1
1
0.01U_0402_25V7K 100K_0402_1%
BATT_OUT 29
PR223 PR214
2
1
2
PC208
PD202
1
1
8
0.068U_0402_16V7K
BATT_TEMP 3 2 PQ202B
P
+ L2N7002DW1T1G_SC88-6
1 1 2 1 5
O
2 3
-
G
1N4148WS-7-F_SOD323-2
PU201A
4
AS393MTR-E1 SO 8P OP
4
BAS40CW_SOT323-3
2
PD201
PR218 PR219
1
100K_0402_1%
1
PC209 1.5M_0402_5%
100P_0402_50V8J
1
+3VLP
2
B B
PR221
+5VL
100K_0402_1%
1
VMB D
1
+3V_LDO 2 PQ206
23 BATT_LEN#
75K_0402_1%
@ PR213
@PR213 G 2N7002KW_SOT323-3
2
47K_0402_1% S
3
@ PR207
@ PC210
2
5 0.068U_0402_16V7K~N
P
+
7 1 2
1
O
6
-
G
2
100K_0402_1%
100P_0402_50V8J
4
1
1N4148WS-7-F_SOD323-2
PU201B
@ PR216
AS393MTR-E1 SO 8P OP
@ PC213
PD203
@PR220
@ PR220
1
1.5M_0402_5%
@
+5VALW
22U_0603_6.3V6M
@PU202
@ PU202
1
@ PC212
1 5 +3V_LDO
IN OUT
2
2
GND
3 SHDN# BYP 4
A A
G9191-330T1U_SOT23-5
1
@ PC211
1U_0402_16V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 28 of 40
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
PR302
VIN 8 1 1 8
0.01_1206_1% CHG_B+
7
6
2
3
2
3
7
6
SH00000MW00
5 5 1 4 1 2 PQ303
AO4407AL_SO8
2 3 PL301 1 8
4
1UH_NRS4018T1R0NDGJ_3.2A_30% 2 7
3 6
2200P_0402_50V7K
PQ304
10U_0805_25V6K
10U_0805_25V6K
D 5 D
47K_0402_5%
1 2
1
2
200K_0402_1%
0.1U_0603_25V7K
PC307
4
1
PR301
PC305
PC306
DTA144EUA_SC70-3 PC304 DISCHG_G
PC301
PR303
5600P_0402_25V7K
1
PR304
@ 200K_0402_1%
2
2
2 1 2
2
ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR305
1DISCHG_G-1
47K_0402_1%
1
2
PD301
P2-1 PR306
0.1U_0603_25V7K
1
2 200K_0402_1%
PQ305 PQ306
1
PC308 PC309 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR307 1 2 2 1 PD302
3
20K_0402_1% 1SS355_SOD323-2
1 2 0.1U_0603_25V7K 2 1 2
6
PQ308
1
1
D
0.1U_0603_25V7K
S
3
1
PC311
VIN G
S
3
390K_0603_1% ACPRN
2
1
P2-2
PACIN2
10_1206_5%
MDS1525URH 1N SO8
2
5
6
7
8
C C
PR314
L2N7002DW1T1G_SC88-6
PQ310
PR319
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR318 23,28 ADP_I PR325
2
1
PACIN TP DH_CHG_1 4
1 2 5 1 2 6 ACDET PC313 1 2
1
3
2
1
1U_0603_25V6K
1
5
6
7
8
1
10K_0402_5% 23,28 EC_SMB_CK1 PR324 PC314
4.7_1206_5%
PQ312
PR322
PR323 2.2_0603_5% 0.047U_0603_16V7M
MDS1521URH 1N SO8
ACOFF
BST_CHG SRP SRN
10U_0805_25V6K
10U_0805_25V6K
1 2 10 ILIM BTST 17 1 2 2 1
1
16251_SN
+3VALW 316K_0402_1%
PD303
3
LODRV
1
PC371
PC372
PR326 16 2 1 4
GND
SRN
SRP
REGN
BM
100K_0402_1%
2
2
PQ313 RB751V-40_SOD323-2
680P_0603_50V7K
11
1 12
13
14
15
1
1
D
PC377
10_0603_5%
6.8_0603_5%
3
2
1
2
PR328
BATT_OUT2 PC376 BQ24737VDD
2N7002W-T/R7_SOT323-3
PR327
G 1U_0603_25V6K
2
S @
3
2
2
PC373 DL_CHG
B 0.1U_0603_25V7K B
2 1
1
1
PC374
0.1U_0603_25V7K @ PC375
2
2 0.1U_0603_25V7K
BQ24737VDD
PR337
10K_0402_1%
1
1 2 ACIN 10,23,27
PR336
PR335 10K_0402_1%
47K_0402_1%
PACIN
2
2N7002KW_SOT323-3
PQ316
1
D PR339
ACPRN 2
G 12K_0402_1%
2
S
3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 29 of 40
5 4 3 2 1
A B C D E
0_0402_5%
PR410
3VALW_EN 1 2 3V5V_EN
4.7U_0402_6.3V6M
PC432 @
1
1 1
2
PR402
499K_0402_1%
ENLDO_3V5V 1 2 B+
1
150K_0402_1%
1U_0603_25V6K
1
PR403
B+ PU401
PC407
PL401 7 1 3VALW_EN
2
HCB2012KF-121T50_0805 IN EN1 PC427 PR416
2
1 2 3V_VIN 8 3 3V_FB 1 2 2 1
IN EN2 PR401 PC402
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0603_25V7K
1
1
PC404
PC406
PL402
10 LX_3V 1 2
@ LX +3VALWP
2
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
4.7_1206_5%
2 5 +3VLP
PG LDO
PC408
PC409
PC410
PC411
PC412
23,31,32 SPOK
PR404
SY8208BQNC_QFN10_3X3
2
1
1
100K_0402_1%
100K_0402_1%
PC414
13V_SN
PR412
PR411
4.7U_0603_6.3V6M @
680P_0603_50V7K
PC415 @
@
2
2 2
2
+3VLP +3VALWP
PC419 PR413
1 2 2 1
B+ PL403 0.047U_0402_25V7K 1K_0402_5%
HCB2012KF-121T50_0805 PU402
1 2 5V_VIN 8 1 3V5V_EN
IN EN1
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
3 PR405 PC421
EN2 0_0603_5% 0.1U_0603_25V7K
1
1
PC420
PC417
PC418
6 BST_5V 1 2 1 2
BS
2
@ PL404 @PJ401
@ PJ401
9 10 LX_5V 1 2 +5VALWP +3VALWP 1 2 +3VALW
GND LX 1 2
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
VCC OUT
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%
1
PR406 @
2 7 +5VL
PG LDO
1
PC422
PC423
PC424
PC425
PC426
PC428
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
1 5V_SN
@PJ402
@ PJ402
2
2
1
PC430
4.7U_0603_6.3V6M
@ +5VALWP 1 2 +5VALW
3 1 2 3
PC429 @
JUMP_43X118
2
22uF*3
PR407
2.2K_0402_5%
1 2
23 EC_ON
@ PR408
1 2
23 MAINPWON
0_0402_5%
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR409
PC431
2
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 30 of 40
A B C D E
A B C D
PL501
1.35V_B+ 1 2 B+
HCB2012KF-121T50_0805
2200P_0402_50V7K
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
0.1U_0402_25V6
4.7U_0805_25V6-K
10U_0805_25V6K
PC522
1
PC521
PC501
S0 Hi Hi On On On
PC509
@
Off
2
@
AON7408L
S3 Lo Hi On On (Hi-Z) +1.35VP
PQ503
PR515 0_0402_5%
UG_1.35V 1 2 UG_1.35V_1 4
S4/S5 Lo Lo Off Off Off
LX_1.35V
3
2
1
1 1
10U_0805_25V6K
10U_0805_25V6K
1
FDMC7692S_MLP8-5
5
20
19
18
17
16
1
1
PC506
PC504
PU501 PR506 @
4.7_1206_5% 1
VTT
VLDOIN
BOOT
UGATE
PHASE
220U_6.3V_M
21
2
PAD +
PQ502
PC526
1 15 LG_1.35V 4
VTTGND LGATE
1
PC510 @ 2
2 14 680P_0402_50V7K
2
VTTSNS PGND PR505
3
2
1
8.06K_0402_1%
3 GND CS 13 2 1
RT8207MZQW _W QFN20_3X3
4 12
+VTT_REFP VTTREF VDDP
5 11 1 2
+1.35VP VDDQ VDD
+5VALW
PGOOD
PR502
1
5.1_0603_5%
1U_0603_10V6K
TON
PC507
FB
S3
S5
0.033U_0402_16V7K
2
1
PC503
2 2
S3_1.35V 7
10
PC511
1U_0603_10V6K
2
PR503
49.9K_0402_5%
23,26,32 SUSP# 1 2
PR501
PR504
@ 0_0402_5% 887K_0402_1%
23,26 SYSON 1 2 1 2 1.35V_B+
PR510
1
1 2
PR508 PJ505
10K_0402_1% 100P_0402_25V8K +1.35VP +1.35V
1 1 2 2
2
JUMP_43X118 @
FB=0.75V
To GND = 1.5V PJ507
To VDD = 1.8V +0.675VSP 1 2 +0.675VS
1 2
JUMP_43X39
@
3 3
PU502
SY8003DFC_DFN8_2X2
PL503
JUMP_43X79 @
4 PGND NC 5
1UH_NRS4018T1R0NDGJ_3.2A_30%
EMI
1 2 3 6 1.8V_LX 1 2
+3VALW 1 2 IN LX +1.8VALWP
22U_0603_6.3V6M
PJ502
100K_0402_1%
22P_0402_50V8J
2 PG EN 7
1
1
@ PR512
4.7_0402_1%
PC515
PR513
PC525
1 FB SGND 8
9
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
PGND
2
1
680P_0402_50V7K
PC514
PC518
PC519
@ PC523
1.8V_FB
1 2
FB=0.8V
2
2
1
Note:Iload(max)=3A @
49.9K_0402_1%
1 2 EN_1.8VSP
2
0_0402_5%
0.1U_0402_10V7K
2
1
PC516 @
1
1M_0402_5%
@ PR614 PR511 EMI Part (47.1)
23,32 095_18ALW_PWR_EN
2
0_0402_5%
2
1 2
@ PJ451
1 1 2 2 +1.8VALW
+1.8VALWP
4 4
JUMP_43X79
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.35VP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 31 of 40
A B C D
5 4 3 2 1
PR615
200K_0402_1%
1 2 SUSP# 23,26,31
1
@ PC632
1M_0402_1%
0.01UF_0402_25V7K
2
PR610
2
@ PR617 @ PC624
4.7_1206_5% 680P_0603_50V7K
PL601 VGA@ 1 2SNB_1.5V_VRAM 1 2 +1.5VSP PJ601
D D
HCB2012KF-121T50_0805 PU601 1 2 +1.5VS
1 2
B+ 1 2 B+_1.5V_VRAM 8
IN EN
1 PR618
0_0603_5%
PC627
0.1U_0603_25V7K JUMP_43X118 @
10U_0805_25V6K
6BST_1.5V_VRAM
1 2 1 2 Vo=1.503V
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
PL602
PC628
LX_1.5V_VRAM
+1.5VSP
PC629
9 10 1 2
GND LX
@ PC631
2
2
1.5UH_PCMC063T-1R5MN_9A_20%
30.1K_0402_1%
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
PR616
4
FB
PC626
PC622
PC630
PC621
PC620
3 7
+3VALW FB=0.6V
2
ILMT BYP
2
2 5
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PG LDO
1
1
SY8208DQNC_QFN10_3X3
PC625
PC623
2
1
2
PR612
20K_0402_1%
2
+3VS
PC616
1U_0402_6.3V6K
2
C C
PU602 UMA@
APL5930KAI-TRG_SO8
6
VCNTL
PC634 need to close VIN 5
VIN VOUT
3
+1.5VSP_UMA
9 4
VIN VOUT
22U_0805_6.3V6M
0.022U_0402_16V7K
1
1
PC634 8
EN
1
4.7U_0603_6.3V6K
PC633
PC615
7 2
GND
POK FB PR619
2
20K_0402_1%
2
FB=0.8V @
1
@ PR627 2
0_0402_5%
SUSP# 2 1 +1.5VSP_UMA_ON FB_1.5VSP_UMA
1
1
1
MDU1516URH_POWERDFN56-8-5
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
5
1
B B
PC610
PC619
PC635
PC617
PR626
PQ601
2
0_0402_5% @
1 2 4
@ PR630
3
2
1
23,31 095_18ALW_PWR_EN 0_0402_5%
1 2 PR628 PC637 PL662
63.4K_0402_1% PU603 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_12A_20%
PR624 1
PGOOD VBST
10 BST_0.95V
1 2BST_0.95V-11 2 1 2 +0.95VALWP
PR629 1 2 0.95V_TRIP 2 9 DH_0.95V
0_0402_5% TRIP DRVH
5
0.95V_EN LX_0.95V
MDU1512RH_POWERDFN56-8-5
1 2 3 8
4.7_1206_5%
23,30,31 SPOK EN SW
1
1
0.95V_FB
PR631
4 7 +5VALW
47K_0402_5%
VFB V5IN
1
+ PC611
.1U_0402_16V7K
PQ602
1 5 6
@PR625
PR625
RF DRVL
1
PC613 @
@ PC636
2
470K_0402_1% 11 1U_0603_10V6K 2
PR621
2
TP
@
680P_0603_50V7K
2
1 2 TPS51212DSCR_SON10_3X3
1
VFB=0.7V
PC618
3
2
1
PR605 reserve 3.74K_0402_1%
1
2
@
PR623
10K_0402_1% +0.95VALWP OCP(min)=15.6A
2
PJ604
1 2
1 2
A A
JUMP_43X118 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP(VRAM)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 32 of 40
5 4 3 2 1
A B C D
+3VS_VGA
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
2
2
@ PR813
0_0402_5%
1
PR802
PR803
PR810
PR805
PR812
10 GPU_GPIO0 2 1
1
10
PR814
10
10
10
10
GPU_VID4
GPU_VID3
GPU_VID5
GPU_VID1
GPU_VID2
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
0_0402_5%
2 1 +VGA_B+
6,11,23 PXS_PWREN
PL801
1
HCB4532KF-800T90_1812 1
1 2 B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
1
1
PC803
PC804
PC805
PC801
PC806
+5VS
2
@
2
PR818
10_0603_1%
MDU1516URH_POWERDFN56-8-5
5
1
3211_EN
+3VS 1
PC807
1U_0603_16V6K
PQ801
4
3211_VCC
1
100K_0402_1%
2
PR821
32
31
30
29
28
27
26
25
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
3
2
1
2
PR820 6 VGA_PWRGD 24 PR822 PC809
100K_0402_1% VCC 0_0603_5% 0.22U_0603_25V7K
1
PWRGD
1 2 23 GPU_BOOST 1 2GPU_BOOST-1
1 2
BST PL802
2
IMON 3211_DRVH 0.36UH_PCMB104T-R36MH1R105_30A_20%
22 1 2
DRVH
PC810 3 PR823
CLKEN# 3211_SW 0_0603_5%
21 1 4
1 2 4
SW +VGA_CORE
FBRTN
1
PC811 ADP3211AMNR2G_QFN32_5X5 20 +5VS 2 3
PVCC
5
1 2 3211_FB 5 @ PR824
1000P_0402_50V7K FB VGA@ PU801 3211_DRVL 4.7_1206_5%
19 2 1
220P_0402_50V7K PC813 3211_COMP 6 DRVL
MDU1511RH_POWERDFN56-8-5
47P_0402_50V8J COMP PC812
2 18 2
2
PC814 3211_VCC PGND 2.2U_0603_10V6K
7
3211_COMP-1 2 GPU
1 2 1 17 4
AGND
1
3211_ILIM 8
PQ802
1 2
CSCOMP
470P_0402_50V8J PR826 ILIM @ PC815
33
CSREF
AGND
RAMP
LLINE
CSFB
PR825 20K_0402_1% 680P_0603_50V7K
IREF
RPM
2
1K_0402_1%
RT
3
2
1
1
10
11
12
13
14
15
16
PR827
3.3K_0402_1%
3211_IREF
3211_RAMP
3211_CSFB
3211_CSCOMP
3211_RT
3211_RPM
2
@ PH801
3211_CSCOMP
220K_0402_5%_ERTJ0EV224J
80.6K_0402_1%
2 1
2
PR828
300K_0402_1%
237K_0402_1%~N
2
0_0402_5%
PR829
1 2
1
422K_0402_1%
2
2
1
1
PR835
PR834
0_0402_5%
PC816 PC817
close to VGA
2
2
1000P_0402_50V7K 560P_0402_50V7K
2
1
PR837 2 1
1K_0402_1%
+VGA_CORE +VGA_B+ 2 1 3211_RAMP-1 PR836
200K_0603_1%
1
3
PC818 PC819 3
1000P_0402_50V7K 1000P_0402_50V7K
2
+VGA_CORE
@ PR839
GPIO21 GPIO29 GPIO30 GPIO20 GPIO15 0_0402_5%
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
VID5 VID4 VID3 VID2 VID1 VDDC 2 1
1
1
PC820
PC821
PC822
PC823
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
0 1 1 1 0 1.15V
2
2
0 1 1 1 1 1.125V +VGA_CORE
1
1 0 0 0 0 1.100V PR838
0_0402_5%
1 0 0 0 1 1.075V
1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
2
1 0 0 1 0 1.050V
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+ + +
PC836
PC837
PC838
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 0 0 1 1 1.025V
1
1
3211_CSCOMP
PC840
PC841
PC842
PC843
PC844
PC845
PC846
PC847
PC848
PC849
PC850
PC851
PC852
PC853
1 0 1 0 0 1.000V 2 2 2
2
2
1 0 1 0 1 0.975V
1 0 1 1 0 0.950V
1 0 1 1 1 0.925V
1 1 0 0 0 0.900V Default
4
1 1 0 0 1 0.875V 4
1 1 0 1 0 0.850V
1 1 0 1 1 0.825V
1 1 1 0 0 0.800V
1 1 1 0 1 0.775V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABIN Schematic
Date: Monday, February 04, 2013 Sheet 33 of 40
A B C D
5 4 3 2 1
CPU_B+
Acoustic
PL901
9W@ PR903 HCB2012KF-121T50_0805
1.07K_0402_1% 1 2 B+
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V5K
MDU1516URH_POWERDFN56-8-5
15W@ PR903 1 1
15U_D2_25VM_R90
15U_D2_25VM_R90
5
1.33K_0402_1%
33U_25V_M
33U_25V_M
1
1
+ +
PC904
PC908
PC1027
PC1030
PC1032
1 1
PC901 PR901
PC1028
330P_0402_50V7K 2K_0402_1% PR954 + +
PC926
PC927
2
2
1 2 1 2 0_0603_5% @ 2 @ 2
UGATE_NB1
PQ905
390P_0402_50V7K 1 2 4
4 APU_VDDNB_SEN PC1033 2 @ 2 @
PR902 25W@ PR903 PR904 @ PR905
10_0402_5% 1.5K_0402_1% 137K_0402_1% 41.2K_0402_1%
1 2 1 2 1 2 1 2 1 2
SH00000OK00 (DCR 1.4+-5%)
+APU_CORE_NB
3
2
1
PL902
PR906 PC1034 PC1035 0.36UH_ETQP4LR36AHM_20A_20%
D 2011/10/21 0_0402_5% 1000P_0402_50V7K 100P_0402_50V8J PHASE_NB1 1 4
D
1
VSUMP_NB PC1037 PR907 0.22U_0603_25V7K
0.01U_0402_50V7K 301_0402_1% BOOT_NB1 1 2 1 2 @ PR910
2.61K_0402_1%
10K_0402_5%_ERTJ0ER103J
1
4.7_1206_5%
5
0.022U_0402_25V7K
PR908
PR909
1 2
0.15U_0603_16V7K
2.2_0603_1%
11K_0402_1%
680P_0603_50V7K
1 2
1
PC1038
PC1039
MDU1511RH_POWERDFN56-8-5
PR912
1
3.65K_0402_1%
PR911
12
VSUMP_NB 1
PH901
2
@ LGATE_NB1 4 @ PC1040
2
2
PQ906
PR914
2
VSUMN_NB 1 2
3
2
1
1
PR915 @ PC1042 @
PC1041 100_0402_1% 220P_0402_50V7K LGATE_NB1
0.1U_0603_50V7K 1 2 1 2
2
PHASE_NB1
2011/10/21 UGATE_NB1
NTC near NB_CORE H/S mos BOOT_NB1
27.4K_0402_1% PR916 20K_0402_1% 2012/10/30
1 2 PR917 Load Line:VDD-->4m
41
40
39
38
37
36
35
34
33
32
31
1 2 1 2 PU901 VDDNB-->4.0m
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
470K_0402_5%_TSM0B474J4702RE
PH902
PC1043 1 30
1000P_0402_50V7K NTC_NB BOOT2
1 2 2 29
IMON_NB UGATE2
C 1 2 4 APU_SVC 3 28 C
133K_0402_1% PR919 0_0402_5% PR920 SVC PHASE2
4,6,23,27 H_PROCHOT# +5VALW
1 2 4 27
VR_HOT_L LGATE2
@ PR922 100K_0402_1% 5 26
4 APU_SVD SVD VDDP
+3VS 1 2 0_0402_5% PR923 ISL62771HRTZ-T_TQFN40_5X5 PR924
+1.35VS 1 2 VDDIO 6 25 1 2
@ PR951 VDDIO VDD 1_0603_5%
1U_0603_25V6K
APU_IMON 0_0402_5% LGATE1
4 APU_SVT 7 24
SVT LGATE1
1
1
1 2 0_0402_5% PR926
1U_0603_25V6K
2 ENABLE PHASE1
PC1046
23 VR_ON 1 8 23
0_0402_5% PR925 ENABLE PHASE1
PC1045
2
2
PR928 PC1044 1 2 9 22 UGATE1 CPU_B+
4 APU_PWRGD PWROK UGATE1
133K_0402_1% 0.1U_0402_25V6
1 2 10 21 BOOT1
IMON BOOT1 +3VS
2
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PGOOD
PC1047
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
1000P_0402_50V7K C1051
NTC
RTN
MDU1516URH_POWERDFN56-8-5
1 2 100P_0402_50V8J
FB
1
1
PC1049
PC1048
PC1050
ESD@
20K_0402_1%
11
12
13
14
15
16
17
18
19
20
27.4K_0402_1% PR930 PR929
PR931
2
1 2 1 2 100K_0402_1% PR955
0_0603_5%
2
+5VS
PQ907
PH903 UGATE1 1 2 4
470K_0402_5%_TSM0B474J4702RE
1 2 VGATE 23
SH00000N900 (DCR 1.1+-5%)
PL903
3
2
1
@ PR932 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1 2 ISEN2
PHASE1 1 4
0_0402_5%
PC1053 2 3
+APU_CORE
1 2 ISEN1 0.22U_0603_25V7K
1
PR934 BOOT11 2 1 2 @ PR935
10K_0402_1% 4.7_1206_5% PR936
PC1054 PR937 PC1055 @PR938
@ PR938 PR933 3.65K_0402_1%
5
B B
1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 32.4K_0402_1% 2.2_0603_1% VSUM+ 1 2
1 2 1 2 1 2 1 2
2011/10/21
1 2
MDU1511RH_POWERDFN56-8-5
MDU1511RH_POWERDFN56-8-5
@ PC1057
330P_0402_50V7K
PC1056
680P_0603_50V7K PR941
NTC near CPU_CORE H/S mos
1
2
10K_0402_5%_ERTJ0ER103J
1
PQ908
PQ904
1 2 1 2 1 2
0.15U_0603_16V7K
@
PR942
11K_0402_1%
PC1059
PC1060
3
2
1
3
2
1
1
2K_0402_1% 330P_0402_50V7K
12
1 2 1 2
357_0402_1% 1.15K_0402_1%
2
2
2
VSUM- 1 2 1 2 +APU_CORE
@ PC1063 @ PR947
1
@ PR949
0_0402_5%
1 2
PR950 APU_VDD_RUN_FB_L 4
0.01U_0402_50V7K
PC1064
10_0402_5%
1
1 2
2
2011/10/21
NTC near phase 1 choke
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
APU_CORE/APU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 34 of 40
5 4 3 2 1
5 4 3 2 1
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC1003
PC1001
PC1002
PC1000
2
2
1U_0402_6.3V6K
D D
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PC1024
1
1
PC1022
1
PC1020
PC1021
PC1023
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
180P_0402_50V8J
1
1
1
PC1004
PC1010
PC1011
PC1012
PC1013
PC1005
PC1007
PC1008
PC1009
PC1103
1 1
330U_D2_2V_Y
330U_D2_2V_Y
2
2
2
+ +
PC1104
PC1105
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@
1U_0402_6.3V6K
PC1108
2 2
1
1
PC1106
1
PC1025
PC1026
PC1107
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1U_0402_6.3V6K
2
1
PC1018
1
1
PC1016
1
PC1014
PC1015
PC1017
2
2
2
C C
+APU_CORE
0.22U_0402_16V7K
180P_0402_50V8J
1
1
PC1006
PC1019
2
1 1 1
2
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
+ + + PC1102
PC1100
PC1101
25W@ PC1102
2 2 2 330U_D2_2V_Y
15W @
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-PROCESSOR DECOUPLING
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A3 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 35 of 40
5 4 3 2 1
5 4 3 2 1
D
2 D
6
7
C C
9
10
11
12
13
14
B B
15
16
17
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-AMD KABINI Schematic
Date: Monday, February 04, 2013 Sheet 36 of 40
5 4 3 2 1
5 4 3 2 1
1 For share rom 28 Change SYS_PWRGD_EC from pin 86 to pin 32 12/17 DVT
D D
3 12,
For VBIAS first raise up Change U1895V, U35P, U1895P VBIAS from +5VALW to VL 12/17 DVT
32
4 For follow VIWGP design 27 Change JUSB3 pin define 12/18 DVT
5 For Audio Precision 31 Change CA36, CA46 from 1U to 2.2U 12/21 DVT
8 For reserve EC +3VL 28 Add J11, J12 and modify +3VALW to +3V_EC 12/24 DVT
05
C C
9 For share ROM 05 modify ROM net-name & resistor value 12/24 DVT
10 For common VIWGP design 22 modify R106, R107 to 22ohm 12/24 DVT
14 For 1.5VS discharge 32 Change R339 to 0ohm, mount Q23 & R1461 12/29 DVT
16 For VGA sequence 12 Delete R123 & C40, change C28, C27 to 2200P 12/29 DVT
B B
18 For ESD request 22 Add C600, C601, PC6601, PC6602 01/03 DVT
28
40
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C38-G series Chief River Schematic
Date: Monday, February 04, 2013 Sheet 37 of 40
5 4 3 2 1
5 4 3 2 1
Power-Up/Down Sequence
"Sun" has the following requirements with regards to power-supply
‧
sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
‧
preferred. The maximum slew rate on all rails is 50 mV/µs.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
D
‧
before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC D
‧
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
要要 +1.8VS_VGA 早
Cold Boot Sequence
<= 0 ~ 20mS => +VGA_CORE
VDDC/VDDCI(+VGA_CORE)
VDDR3(+3VS_VGA)
VDD_CT(+1.8VS_VGA)
VDDR1(+1.5VS_VGA)
C C
Power Down Sequence <== Not Requirements ==>
PCIE_VDDC(+0.95VS_VGA) > 100mS
<== 0 ~ 20mS ==>
PERSTb VDDC/VDDCI(+VGA_CORE)
<== > 100uS ==>
REFCLK VDDR3(+3VS_VGA)
VDD_CT(+1.8VS_VGA)
VDDR1(+1.5VS_VGA)
Warm Boot Sequence
PCIE_VDDC(+0.95VS_VGA)
VDDC/VDDCI(+VGA_CORE) > 100uS
B PERSTb B
VDDR3(+3VS_VGA)
REFCLK
VDD_CT(+1.8VS_VGA)
VDDR1(+1.5VS_VGA)
PCIE_VDDC(+0.95VS_VGA)
<== > 100uS ==>
PERSTb
> 100uS
REFCLK
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A331P
Date: Monday, February 04, 2013 Sheet 38 of 40
5 4 3 2 1
A B C D E
EC_ON
B+ +3VLP
PU401
SY8208BQKC +3VALW
+EC_VCCA
LAN_PWR_ON#
+3V_LAN
P-CHANNEL
PMV65XP
1 1
SUSP#
U35P +3VS
TPS22966DPUR
PXS_PWREN
U315V +3VGS
TPS22966DPUR
SPOK
PU502 +1.8VALW
SY8033BDBC
SUSP#
U1895P +1.8VS
TPS22966DPUR
PXS_PWREN
U1895V +1.8VGS
TPS22966DPUR
2 EC_ON 2
+VL
PU402
SY8208CQKC
+5VALW
SUSP#
U35P +5VS
TPS22966DPUR
SUSP# / SYSON
+0.75VS
PU501
RT8207MZQW
+1.5V
SUSP#
P-CHANNEL +1.5VS
LP2301ALT1G
PXS_PWREN
U315V +1.5VGS
TPS22966DPUR
3 3
SPOK
PU601 +0.95VALW
TPS51212DSCR
SUSP#
U1895P +0.95VS
TPS22966DPUR
PXS_PWREN
U1895V +0.95VGS
TPS22966DPUR
EC_VGA_EN
PU801 +VGA_CORE
ISL62883CHRTZ
VR_ON
+APU_CORE
PU901
ISL62771HRTZ
+APU_CORE_NB
4 4
SPOK
PQ204 +VSB
TP0610K
+3VALW B+ +5VALW
+3VALW / +1.8VALW / +1.5VALW / +0.95VALW
+3VS / +1.8VS / +1.5VS / +0.95VS
+3VLP +3VALW
+APU_CORE / +APU_CORE_NB
+3VGS / +1.5VGS
PU502 PU601 +RTCBATT
+1.8VGS / +0.95VGS
+1.8VALW +0.95VALW
V V V V +3VGS +VGA_CORE
D EC EC_RSMRST# 5 D
V V
3A 3B
PBTN_OUT# 6 APU 22
095_18ALW_PWR_EN PXS_RST# 23
V V
SLP_S3# / SLP_S5# 7 AND GPU_RST# GPU
V
GATE MarsXTX
V V
4A 5
B+ B+
KBRST# 10 20 APU_PCIE_RST#
3B 5
V
3A 3B 18 APU_PWRGD +3VS +1.5VA
PU402 PU401 SPOK
SYS_PWRGD_EC 17
14 VGA_PEWGD
V
+5VALW / VL +3VALW/+3VLP
V
V V
LPC_RST# 19
V
2A 2B EC_ON
WLAN / WiMAX
V
Mini-Express Card
1A ACIN
V V
B+ +5VS +3VS
PXS_PWREN 13
V
C C
ON/OFF
4A 1B
EC_VGA_EN 12
V
+5VS / +3VS / +1.8VS D4
V
+5VALW B+ PU801
AC MODE Diode
+VGA_CORE
VIN
V
095VS_PWR_EN 11
18 +1.8VALW +5VALW
+3V_LAN
APU_PWRGD 16
V
PU901 VGATE
V
BATT MODE 15 +APU_CORE /
VR_ON U1895V
BATT+ +APU_CORE_NB
V
+3VS +5VALW
V
LAN
V
+1.8VGS
SYSON
SUSP#
+5VALW
RTC Battery LAN_PERST# 21
U315V
V
+CHGRTC_R 8 9
+3VGS
+3VALW +0.95VALW +5VALW
V
B
+5VALW +3VALW +5VALW U35P B
B+ +5VS
+CHGRTC_R +3VLP VIN BATT+ U1895V
V
+1.8VALW +5VALW
U35P +1.5V +5VALW
+0.95VGS
V
PU501 +3VS
V
+RTCBATT B+ U315V
V
+1.8VS
+1.5VGS
+3VALW
Q20
V
V
A
PCB NAME: +0.75VS +0.95VS A
REVISION:
DATE: 2011/11/23 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date Title
Power sequence
COMPAL CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size Document Number
Custom
Date: Sheet of
Rev
0.1
5 4 3 2 1