486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.

3, MARCH 2001

A 0.5-m CMOS T/R Switch for 900-MHz

Wireless Applications
Feng-Jung Huang, Student Member, IEEE, and Kenneth O, Member, IEEE

Abstract—A single-pole double-throw transmit/receive switch

for 3.0-V applications has been fabricated in a 0.5- m CMOS
process. An analysis shows that substrate resistances and
source/drain-to-body capacitances must be lowered to decrease
insertion loss. The switch exhibits a 0.7-dB insertion loss, a 17-dBm
power 1-dB compression point ( 1dB ), and a 42-dB isolation at
928 MHz. The low insertion loss is achieved by optimizing the
transistor widths and bias voltages, by minimizing the substrate
resistances, and by dc biasing the transmit and receive nodes,
which decreases the capacitances while increasing the power
1-dB compression point. The switch has adequate insertion loss,
isolation, 1dB , and 3 for a number of 900-MHz ISM band
applications requiring a moderate peak transmitter power level
( 15 dBm).
Index Terms—CMOS integrated circuits, microwave switches,
MOSFET switches. Fig. 1. Circuit schematic of an SPDT RF T/R switch.

I. INTRODUCTION up to 1 GHz. This is the first CMOS switch to have usable

insertion loss, isolation, and for applications at 900 MHz

A high-quality microwave switch is a key building block

of a radio-frequency (RF) front end for time-division
duplexing (TDD) communication systems. In recent years,
and higher.

II. DESIGN AND OPTIMIZATION

GaAs FET-based switches have been the dominant technology
for the RF transmit/receive (T/R) switch due to their low
dc power consumption compared to traditional microwave
p-i-n diode switches. Recent speed improvements of digital
CMOS transistors have made it feasible to implement RF
blocks such as low-noise amplifiers (LNAs), voltage-controlled
oscillators (VCOs), and mixers for operating at 1 GHz and
above in CMOS technologies. However, despite the fact that an
MOS transistor is a natural switch, no MOSFET single-pole
double-throw (SPDT) transmit/receive switches with adequate
insertion loss and power 1-dB compression point for
900-MHz wireless applications have been reported [1], [2].
Potential benefits of using CMOS T/R switches rather than
GaAs T/R switches are the fact that CMOS switches do not
require a negative control voltage. Additionally, if they can
be implemented in a standard digital CMOS process, then the
switches can be integrated with the other RF blocks, and this
should lower cost of radios. In this paper, a SPDT nMOS RF
T/R switch fabricated in a foundry 0.5- m CMOS process [3]
is presented. The switch exhibits less than 0.8-dB insertion
loss, over 40-dB isolation, and 17-dBm for frequencies
Manuscript received July 20, 2000; revised October 16, 2000. This work was
supported by a National Science Foundation Career Development Award (MIP-
9703214) and by a Texas Instrument graduate fellowship.
The authors are with the Department of Electrical and Computer Engineering,
Silicon Microwave Integrated Circuits and Systems Research Group, University
of Florida, Gainesville, FL 32611 USA.
Publisher Item Identifier S 0018-9200(01)01431-7.
0018–9200/01$10.00 © 2001 IEEE
Fig. 1 is a schematic of an SPDT nMOS RF T/R switch. Tran-
sistors and perform the main switching function, while
the shunt transistors and are used to improve the iso-
lation of the switch by grounding RF signals on the side which
is turned off. This switch also contains bypass capacitors
and which allow dc biasing of the TX and RX nodes of
the switch. By applying the same dc voltage on the top plates
of the bypass capacitors and as the dc voltage for
TX and RX nodes, dc power consumption is made negligible.
The gate bias resistances , and are imple-
mented using poly resistors. A typical value for the gate bias re-
sistance is about 10 k . The purpose of the gate bias resistances
is to improve dc bias isolation. If the gate bias resistors are not
present, the fluctuations of and of the transistors due
to the voltage swing at drain and source of the transistors will be
higher. These fluctuations not only affect the MOSFET channel
resistance but also may result in excessive voltage across the
gate dielectric and cause breakdown.
Key figures of merit of a T/R switch are insertion loss and
power handling capability measured by the power 1-dB com-
pression point . On-resistance of the transistor is one
of the dominant factors determining insertion loss. Because of
this, only n-channel MOSFET’s are used in the design. The
drain-to-body and source-to-body junction capacitances of
and , and associated parasitic resistances due to the conduc-
tive nature of silicon substrates, are also critical factors deter-
mining insertion loss.
HUANG AND O: 0.5- m CMOS T/R SWITCH 487

Fig. 2(b) shows the equivalent circuit of the MOSFET switch

shown in Fig. 2(a) [5]. At low frequencies, on-resistance of the
transistor determines insertion loss. As the operating frequency
is increased, due to an increase of capacitive coupling, the
power loss in substrate resistances associated with the tran-
sistors is increased. The circuit in Fig. 2(b), though relatively
simple, unfortunately cannot be easily analyzed to provide
meaningful insights. Because of the fact that the impedance of
the on-resistance of the transistor is usually small compared to
the impedance of the parasitic capacitances of the transistor at
1 GHz, the circuit shown in Fig. 2(b) can be approximated as the
circuit shown in Fig. 2(c). The plots in Fig. 3 show simulated
insertion loss of the circuits in Fig. 2(b) and (c) for the typical
ranges of values for the on-resistance and source/drain-to-body
capacitances of MOS transistors utilized in the RF switches.
Both figures show no difference between the curves for the
two circuits indicating that the circuit in Fig. 1(c) is a good
approximation of the circuit in Fig. 1(b). For this simplified
circuit, insertion loss (IL) is as shown in (2), at the bottom of
the page, where is the radian frequency, is the charac-
teristic impedance, is the transistor on-resistance,
is the substrate resistance associated with the transistor, and

is the equivalent capacitance shown in Fig. 2(c). For 0.5- m

transistors biased in the linear region, is negligible
which yields . IL can also be expressed
in terms of the transistor width , as shown in (3), at the
bottom of the page, where ,
Fig. 2. (a) MOS transistor switch in a 50-
system. (b) Equivalent circuit
diagram of the circuit shown in (a) for small signal analyses. (c) Approximate and R . For a given technology and layout
equivalent of the circuit shown in (b). type, , and can be assumed to be fixed. In
actuality, does not scale linearly with the width and this
A. Insertion Loss and Conductive Substrate will introduce some errors. It is straightforward to see that when
is large, the numerator of (3) becomes large and insertion
In order to quantitatively understand the impact of substrate
loss becomes large. When becomes small, the numerator of
resistances, capacitances, and on-resistances, insertion loss has
(3) also becomes large and insertion loss becomes large. This
been analyzed. To simplify, instead of analyzing a complete
indicates that there is an optimum width for which insertion
switch, the circuit containing a single MOS transistor in
loss is minimized. For fF/ m,
Fig. 2(a) has been analyzed. For this analysis, the transistor is
k - m, and k - m of the 0.5- m CMOS process,
assumed to be biased in the linear region.
insertion loss is near the minimum for widths between 0.6 to
Insertion loss (IL) measures the small signal power loss
0.9 mm. If is zero, IL becomes
through an RF switch when the switch is turned on. Insertion
loss is [4]
IL when (4)
Power Available from Source
IL (1)
Power Delivered to Load
which is the insertion loss at low frequencies. Comparing (2)
This quantity can be shown to be the reciprocal of the magnitude and (4), it is easy to see the detrimental impact of which
square of forward transmission coefficient if both load couples signals to the substrate.
and source are terminated with the characteristic impedance It is also easy to show that according to (2), there is a value
. of for which insertion loss is the maximum. When is

IL (2)

IL (3)
488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001

Fig. 4. Simulated insertion loss versus R plot for the circuits shown in
Fig. 2(a), and an insertion loss computed with (2) versus R plot for the
=
circuit shown in Fig. 2(c) at 1 GHz. The bias condition was V 6:0 V and
V = V = 3:0 V.

is on the order of a picofarad and is on the order of

Fig. 3. (a) Simulated insertion loss versus R for the circuits shown in
Fig. 2(b) and (c) at 1 GHz. (b) Simulated insertion loss versus C
for the circuits shown in Fig. 2(b) and (c) at 1 GHz.
infinite, IL becomes the low-frequency insertion loss given in
(4). When , IL is
IL
when
Fig. 4 shows IL versus plots for the circuits in Fig. 2(a)
and (c). The plot for the circuit in Fig. 2(a) is obtained using
HSPICE, while that for the circuit in Fig. 1(c) has been com-
puted using (2). Once again, the plots are very close. As dis-
cussed, there is a maximum point. By maximizing (2), it can
be shown that the maximum insertion loss occurs as shown in
(6), at the bottom of the page. To achieve low insertion loss in
RF switches fabricated with CMOS technologies, special atten-
tion must be paid to avoid transistor substrate resistances near
. For typical CMOS RF switches operating at 1 GHz,
a few ohms. Under these conditions, (6) can be simplified to
. In hindsight, this is an obvious result. The
power loss associated with the - series network is max-
imized when . When this occurs, insertion loss
is maximized. For the 0.5- m transistors utilized in 1-GHz RF
switches, as mentioned, is generally 1–2 pF and the corre-
sponding is 80–160 . Unfortunately, this is in the
typical range of ’s for transistors in RF switches if nothing
has been done to control the substrate resistance.
These results have shown that insertion loss can be reduced
by increasing to a very large value or by decreasing
to near zero. Insertion loss for the case when is larger
and C
than the case for infinite because of the
term in the numerator of (2). Once again, must be reduced in
order to decrease insertion loss. As discussed earlier, if
, insertion loss will become the low frequency loss in (4). In
terms of the underlying physical mechanism, when becomes
large, signals cannot couple to and the power consumption
associated with is small. When is zero, there is no loss
associated with , and the power loss is once again reduced.
(5) B. Insertion Loss of SPDT T/R Switch
Fig. 5 shows the simulated insertion loss as a function of the
width of in the SPDT T/R switch. For a given bias
condition, as the transistor width is increased, on-resistance de-
creases and insertion loss decreases. However, if the transistor
width is increased excessively, as discussed earlier, the signal
loss through capacitive coupling to the substrate becomes signif-
icant and insertion loss increases with the increasing width. For
the bias conditions used to generate Fig. 5, should be 0.6
to 0.8 mm wide to minimize insertion loss. This agrees well with
the optimal width range estimated for a transistor by itself. The

(6)
HUANG AND O: 0.5- m CMOS T/R SWITCH 489

Fig. 5. Effects of the transistor width on insertion loss of an SPDT T/R switch.
W =W = 2 2 W 2
=2 W . Fig. 7. Effects of the transistor substrate resistances (resistances from
source/drain to the substrate node) on insertion loss of an SPDT T/R switch at
928 MHz. R =R 2
=2 R 2
=2 R .

Fig. 6. Circuit schematic of an SPDT T/R switch including key substrate

resistances (R ).

widths of shunt transistors and and are

chosen to be half of . According to simulations, the chosen
and can improve the isolation of the switch by more
than 10 dB with negligible impact on insertion loss.
Fig. 6 is a schematic of the SPDT switch including impor-
tant substrate resistances. Fig. 7 shows the simulated insertion
loss of the switch versus parasitic substrate resistance associ-
ated with the drain-to-body and source-to-body junction capac-
itances of and at 928 MHz. As seen with a transistor
by itself, there is a maximum insertion loss point at . using an inexpensive polysilicon-to-n-well capacitor structure
When is very large or very close to zero, insertion loss is
reduced. From the implementation point of view, as reported in
the context of a bipolar LNA [6], it is not easy to get large ’s
in bulk silicon ICs, and also this depends on surrounding cir-
cuits and their substrate contacts. Because of this, lowering the
resistance is the preferred approach.
Fig. 6 also includes a list of the measured values of the key
substrate resistances , , , and ).
These resistances were measured using a test switch im-
plemented using the same technique reported in [6]. The
substrate resistances of 14.2 and 20.6
are sufficiently low to significantly reduce
the substrate losses. The low substrate resistances are achieved
by fully surrounding the transistors with large area p substrate
Fig. 8. Micro-photograph of the SPDT nMOS T/R switch.
contacts and filling in any open spaces with substrate contacts.
Fig. 8 is a microphotograph of the SPDT switch, which inte-
grates the transistors, resistors, and capacitors. The total chip
area is 560 m 560 m. The capacitors are implemented
[7]. The substrate contacts occupy approximately 36% of the
chip area which is about 0.1 mm .
C. DC Bias for TX and RX Nodes
TX and RX nodes, or the drain nodes of and , are
dc biased to 3 V. This reverse biases the source/drain-to-body
junctions which reduces the junction capacitances and RF signal
coupled to the substrate and thus decreases insertion loss. An-
other purpose of the 3-V dc bias for TX and RX nodes is to
improve the power handling capability measured by . If
the dc voltage for TX, RX, and is zero, then an RF
input voltage with an amplitude of 0.5 V forward biases the
source/drain-to-body junctions in some portion of a cycle. This
clips the RF signal and causes the output power to compress.
490 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001

Fig. 10. Measured insertion loss and isolation for the SPDT T/R switch.
Fig. 9. Measured insertion loss versus drain/source-to-body bias (V ;V )
when V = 3:3 V and V = 0 V.

When is on, with the 3-V dc bias, is limited by un-

intentional turning on of . The dc gate voltages for and
are set to 6 V and those for and are set to 2 V
to set the switch in a transmit mode. If an RF input voltage
with an amplitude of around 2.7 V is applied, then the minimum
voltage at the drain and source nodes of will be 0.3 V, and
the source/drain-to-body junctions are reverse biased. The min-
imum gate voltage of is 1.1 V which is 0.9 V lower than
the dc bias voltage due to the RF voltage capacitively fed for-
ward from TX [8]. The maximum gate-to-drain voltage
of is 0.8 V, and the transistor starts to turn on. This clips
the output waveform and once again makes the output power
of the switch compress. However, as will be discussed, the RF
power handling capability for the 3-V dc-bias case is signifi-
cantly higher than that for the 0-V dc bias case.
Fig. 11. Output 1-dB compression point measurement for both on and off
states, and I P measurement for on state at 928 MHz when V = 6 :0
III. EXPERIMENTAL RESULTS AND DISCUSSION V, V = 2:0 V, and V = V = 3:0 V.

Fig. 9 shows the measured insertion loss versus

drain/source-to-body bias of when the for operating frequencies up to 1 GHz at or of
gate control voltage is 3.3 V. The measurements were 6.0 V, of 2 V, and drain/source-to-body reverse bias
made in an SOIC-like test package with an exposed paddle. and of 3.0 V. The insertion loss and isolation at
The exposed paddle was directly soldered to board ground. The V and V are 0.2 dB
on-chip ground is connected to board ground using five down higher and 2 dB lower than those at V and
bonds to reduce the inductance. When the gate-to-drain/source V, respectively. The 6.0-V can be
voltages and of are 3.3 V, on-resistance is the attained by using a voltage doubler.
lowest. However, insertion loss is not the minimum because Fig. 11 shows the power measurement results of the switch
the drain-to-body and source-to-body capacitances and in both on- and off-states at 928 MHz. Table I summarizes the
are at their maximum. This results in lower impedance to switch performance. When V and
the substrate and higher loss in the substrate. Raising and V and the switch is on, is 17.2 dBm. This corre-
levels increases the reverse bias of the junctions, which sponds to TX and ANT voltage amplitudes of 2.8 and 2.3 V
decreases the capacitances. Despite the accompanying decrease with a 50- output load. As discussed earlier, the compression
in and increase of the on-resistance, this capacitance is caused by turning on by the applied RF input voltage.
reduction lowers insertion loss. If and are further Output third-order intercept point was measured using
increased, eventually the decrease of results in a sharp a two-tone test. The frequencies of the two tones ( and )
increase of insertion loss. These measurements indicate that at are 928 and 927 MHz, respectively, and the third-order har-
1.0–1.2 V and , insertion loss is minimized for the monics are measured at and which are 929
3.3-V . As discussed, applying positive and and 926 MHz, respectively. Because the mechanisms respon-
also increases . sible for and are different, this also makes the dif-
Fig. 10 shows the measured insertion loss and isolation. In- ference between and around 20 dB instead of the
sertion loss is less than 0.8 dB, and isolation is more than 40 dB theoretical 10-dB difference [9]. Measured is 38.2 dBm,
HUANG AND O: 0.5- m CMOS T/R SWITCH 491

TABLE I
PERFORMANCE SUMMARY OF THE SPDT T/R SWITCH AT 928 MHz

which is excellent. The higher power handling capability of

the 6.0-V case compared to the 3.3-V is due to
the fact that it takes a larger input swing to forward bias the
M M M
Fig. 12. Simulated voltages across the gate-oxide layer of 1, 2, and 3,
source/drain-to-body junctions and turn on . During this set
of measurements, a maximum RF input voltage amplitude of
andV M M
of 2 and 3 when the switch is on and the output load is an open.
The available input power is 16.7 dBm, and the maximum voltage across the
4.2 V or a peak voltage of 7.2 V has been applied without dam- gate oxide is 4.0 V.
aging the switch.
The reliability of SPDT T/R switches is crucial. The 6.0-V dc maximum of is about 3.2 V, which should not stress
gate voltage is acceptable in the 3.3-V 0.5- m CMOS process the gate oxide. In addition, the 2.0-V sets the maximum
because when the transistors are on, the dc voltage across the of and to 4.0 V which should be acceptable from
gate oxide is 3.0 V, because of the 3.0-V and and the reliability point of view. The 2.0-V keeps the transis-
the formation of an inversion layer in the channel region. When tors within the safe voltage range for the 3.3-V CMOS process
the transistors are off V and at the input power of 16.7 dBm even when the output load is an
V), the maximum dc voltage across the gate oxide is 2.0 V. open.
Because of these facts, the dc voltage across the gate oxide does The 2.0-V degrades only by 1 dB in comparison
not exceed 3.0 V. with 0-V case. The 1-dB degradation is due to the
Another reliability issue for a T/R switch is a large RF RF signal loss through which is turned on instead of
input voltage in combination with the output mismatch. The being limited by the forward biasing of the source/drain-to-body
output node of a T/R switch is connected to an antenna, and junction diodes. Fig. 12 also shows the drain-to-source voltages
the impedance looking into the antenna varies depending on for transistors and . The maximum is about 5.0 V
structures near the antenna. The worst case mismatch occurs which is significantly lower than the 10-V . This should
when the load is an open, which results in total reflection of not pose a reliability problem since and are turned off
the input RF signal. In this case, if the impedance of the input during the high- portion of a cycle.
source is 50 , the RF output voltage will be the maximum,
and approximately two times the voltage of that when the load
IV. CONCLUSION
is 50 . For applications with the maximum transmit power of
10 dBm, the output voltage amplitude with a 50- load is 1 V. A single-pole double-throw transmit/receive switch has
Thus, the maximum RF voltage amplitude at the output will be been presented. The switch was fabricated in a foundry
2 V (peak voltage of 5 V) when the output load is an open, and 0.5- m CMOS process. It exhibits a 0.7-dB insertion loss, a
the switch will operate in the safe voltage range. 42-dB isolation, and a 17-dBm at 928 MHz. At 1 GHz,
Assuming that the maximum allowable voltage across the the insertion loss of this switch is comparable to several
9.5-nm gate oxide limited by the reliability requirement is about transmit/receive switches implemented in GaAs technologies,
4.0 V, simulations have been used to estimate the maximum while the isolation of this switch is about 15 dB better than
power handling capability of the switch. The 4.0-V limit is more those of GaAs switches. The of this switch is about 15 dB
conservative than that suggested by [10]. On top of this, a sig- lower than those of GaAs switches [8], [11], [12]. The effects
nificant portion of the stress is ac rather than dc, which makes of substrate resistances and source/drain-to-body capacitances
the 4.0-V limit even more conservative. Fig. 12 shows simu- associated with MOS transistors on insertion loss of RF
lated of and of and when is turned switches have been analyzed. The substrate resistance and
on and and are turned off. These terminals are chosen source/drain-to-body capacitance must be lowered to decrease
because they are exposed to the largest voltage drops. The avail- insertion loss. The low insertion loss of the transmit/receive
able input power is 16.7 dBm (e.g., output power is 15.6 dBm switch is achieved by optimizing the transistor widths and bias
16.7 dBm - IL - Power Compression with a 50- load) and the voltages, by minimizing the substrate resistances, and by dc
output load is an open. The corresponding peak voltage at TX biasing the TX and RX nodes which decreased the capacitance
is 7.35 V. Because a significant part of the RF voltage between while increasing the power 1-dB compression point. The switch
the source/drain of to ground is dropped across , the has adequate insertion loss, isolation, , and for a
492
number of 900-MHz ISM band applications requiring moderate
maximum transmit power. The switch should be able to handle
15.6-dBm output power with a sufficient reliability margin
even with the output open. Because the switch is implemented
in a foundry CMOS process, this work suggests that a T/R
switch could be integrated with the other transceiver circuits.
ACKNOWLEDGMENT
The authors also wish to thank C. Hazelton for packaging and
B. Wellman for the SOIC-like test packages.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001
Feng-Jung Huang (S’98) was born in Taipei,
Taiwan. He received the B.S. degree in electrical
engineering from National Tsing Hua University,
Hsinchu, Taiwan, in 1993, and the M.S. degree
from the University of Florida, Gainesville, in 1998,
where he is currently working toward the Ph.D.
degree.
From 1995 to 1996, he worked as a Research
Assistant developing intelligent power integrated
circuits for a university and industry cooperated
research project at National Tsing Hua University,
Hsinchu, Taiwan. Since 1997, he has been with the Silicon Microwave
Integrated Circuits and System Research Group (SiMICS), Department of
Electrical and Computer Engineering, University of Florida, Gainesville. His
current research interests include developing devices and circuits to implement
RF analog and digital systems using silicon IC technologies.
Kenneth O (S’86–M’89) was born in Seoul, Korea,
in 1960. He received the S.B, S.M, and Ph.D degrees
in electrical engineering and computer science
from the Massachusetts Institute of Technology,
Cambridge, in 1984, 1984, and 1989, respectively.
Between 1984 and 1985, he worked as a Process
Engineer at Harris Corporation, Melbourne FL.
From 1989 to 1994, he worked at Analog Devices
Inc. developing sub-micron CMOS processes for
mixed signal applications and high-speed bipolar
and BiCMOS processes for RF and mixed signal
applications. He is currently an Associate Professor at the University of Florida,
Gainesville, and teaches digital, analog, and microwave circuits courses at both
the undergraduate and graduate levels. His research group [Silicon Microwave
Integrated Circuits and Systems Research Group (SiMICS)] is developing
circuits and components required to implement analog and digital systems
operating between 1 and 20 GHz using silicon IC technologies. He has authored
and co-authored 65 journal and conference publications and holds four patents.
Dr. O served as a member of the technical program committee for the IEEE
Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) between 1992 and
1994. In 1995 and 1996, he served as the Short Course Chairman and he is
currently serving as the Chairman of the technical program committee for the
same conference. In 1996, he has also served as the Guest Editor of the special
issue for 1996 BCTM in IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is an
Associate Editor for IEEE TRANSACTIONS ON ELECTRON DEVICES. He has also
served as the Publication Chairman of the 1999 IEEE International Electron De-
vices Meeting and currently he is a Technical Program Committee Member for
the same conference. He received the 1995 and 1997 IBM Faculty Development
Awards and the 1996 NSF Early Career Development Award.