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Lecture 1: Introduction to Embedded Systems and ARM7TDMI Architecture

ELEC 2142 Embedded System Design Session 2 - 2016, Week 1

Introduction

Outline

ARM7TDMI Programmer’s Model

Instructions & Tools

1 Introduction to Embedded Systems

2 ARM7TDMI Programmer’s Model

3 ARM Instructions and Tools

4 Assembly Language Examples

Assembly Examples

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Introduction to Embedded System

An embedded system is a microprocessor based system (often with limited resources) dedicated to a specific task. Computers are also microprocessor based systems, however they are general purpose devices. Embedded systems are typically

single purpose cost and resources sensitive supported by a wide range of processor architectures (4-bit, 8-bit, 16-bit, 32-bit, and 64-bit) limited by real-time constraints limited by power, speed, and area constraints of small code size (e.g. CD player 20KB)

Expanding system features and resolving bugs can be achieved by means of embedded software updates. Embedded software - low level vs. high-level

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Embedded Systems - Applications

Application Area Aerospace Automotive Children’s Toys Communications peripherals Computer Home Industrial
Application Area Aerospace Automotive Children’s Toys Communications peripherals Computer Home Industrial
Application Area
Aerospace
Automotive
Children’s Toys
Communications
peripherals Computer
Home
Industrial
Instrumentation
Medical

Examples

Navigation space exploration systems, (e.g., automatic the Mars landing Pathfinder) systems, engine controls,

Fuel injection control, air bag controls, GPS mapping,

Nintendo’s “Game Boy”, Xbox,

Satellites; network routers, switches, hubs, …

Printers, scanners, modems, hard disk drives, …

Dishwashers, microwave ovens, VCRs, televisions,…

Elevator controls, robots, …

Data collection, oscilloscopes, signal generators…

Imaging systems (XRAY, MRI etc), patient monitors, heart pacers

Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …
Automation Office FAX machine, telephones … Personal PDAs, cell phones, portable MP3 players, GPS …

Automation Office

FAX machine, telephones …

Personal PDAs, cell phones, portable MP3 players, GPS …
Personal
PDAs, cell phones, portable MP3 players, GPS …

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Embedded Systems - Microprocessors

The brain of an embedded system is a microprocessor A microprocessor consists of

Arithmetic and Logic Unit (ALU) Registers and internal bus structure Control unit (CU) - can be hardwired or microprogrammed

What is a microcontroller?

Micro-architecture and Instruction Set Architecture (ISA) Havard vs. Von-Neuman architectures

Data Memory Central Address Input Processing Output Data Unit (CPU) Program Memory Von Neumann Architecture
Data
Memory
Central
Address
Input
Processing
Output
Data
Unit (CPU)
Program
Memory
Von Neumann Architecture
Address Data Memory Data Central Input Processing Output Unit (CPU) Program Memory
Address
Data
Memory
Data
Central
Input
Processing
Output
Unit (CPU)
Program
Memory

Havard Architecture

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Embedded Systems - Levels of Abstraction

Assembly Examples Embedded Systems - Levels of Abstraction Applica1ons and OS High level languages Instruc1on Set

Applica1ons and OS

High level languages

Instruc1on Set (ISA) Architecture

Microarchitecture

Gates

Transistors
Transistors
Transistors

In this course:

ARM7TDMI processor architecture ARMv4T instruction set LPC2478 microcontroller and QVGA development board Keil
ARM7TDMI processor
architecture
ARMv4T instruction set
LPC2478 microcontroller
and QVGA development
board
Keil Microvision 4 IDE
Assembly language
programming

Apple iphone 3 had ARM7 processor core ARM7TDMI - T:Thumb, D:on-chip debug, M:multiplier, I:in-circuit emulation

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Embedded Systems - RISC vs CISC Processors

RISC: Reduced Instruction Set Computer CISC: Complex Instruction Set Computer

RISC (Reduced Set Computer) Instruction CISC (Complex Computer) Instruction Set e.g ARM Processors e.g Motorola
RISC (Reduced Set Computer) Instruction
CISC (Complex Computer) Instruction Set
e.g
ARM Processors
e.g Motorola MC68000
Instruction Set e.g ARM Processors e.g Motorola MC68000 Single-cycle execution Multiple-cycles to execute a
Instruction Set e.g ARM Processors e.g Motorola MC68000 Single-cycle execution Multiple-cycles to execute a

Single-cycle execution

Multiple-cycles to execute a single

instruction

A fixed instruction size

Variable length of instructions

Instructions decode are simple to

Use instructions large microcode ROMs to decode

Load-store architecture

Data in memory processing is allowed on values stored

Large size register bank of the same

Smaller register bank of variable size

Poor code density

Less code

Shorter development time

Hard to design and easy for programmer

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

ARM7TDMI Programmer’s Model

Programmer’s model is a description about the microprocessor in programmer’s perspective including

Internal structure (data path and control)

Features available - such as what registers are accessible and when

Details about exceptions - how the processor responds to an invalid instruction

You need to know about the programmer’s model and the instruction set of the underlying architecture to start writing programs.

ARM7TDMI - Processor Core

ARM7TDMI - Processor Core

Introduction

Memory

ARM7TDMI Programmer’s Model

Memory hierarchy includes

Instructions & Tools

Assembly Examples

Registers (general purpose and special purpose) Internal cache External cache Main (primary) memory - data and program Secondary memory, virtual memory - hard disks etc

Typically, the low-level programmer needs to access registers and main memory Caches are managed automatically by the hardware Virtual memory is handled by the operating system

Speed Size

Speed

Size

Speed Size
Speed Size
Speed Size
Speed Size
Speed Size

Registers

On-chip Cache

2 nd Cache

Main Memory

Virtual (Hard disk) memory

A few ns

128

bytes

Ten ns

8-32 Kbytes

A few tens of ns

Hundreds of Kbytes

100ns

Mega bytes

milliseconds tens of

100

Gbytes

8-32 Kbytes A few tens of ns Hundreds of Kbytes 100ns Mega bytes milliseconds tens of
8-32 Kbytes A few tens of ns Hundreds of Kbytes 100ns Mega bytes milliseconds tens of
8-32 Kbytes A few tens of ns Hundreds of Kbytes 100ns Mega bytes milliseconds tens of
8-32 Kbytes A few tens of ns Hundreds of Kbytes 100ns Mega bytes milliseconds tens of

Introduction

Memory

ARM7TDMI Programmer’s Model

Introduction Memory ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples Memory is organized as a

Instructions & Tools

Assembly Examples

Memory is organized as a group of storage elements (typically byte level, 8-bits)

Each memory location has an address

N -bit address bus 2 N address space

ARM7TDMI architecture has 32-bit address bus 2 32 = 4 × 2 30 = 4GB of memory space

Memory content is 8-bits

Introduction

Memory

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Memory access is limited to LOAD (loading data from the memory into the registers inside the processor core) and STORE (storing the register values into memory locations) operations. Direct manipulation of memory content such as adding two variable in the memory is not permitted. This is known as a load-store architecture. Some CISC processors have instructions to directly manipulate contents in the memory.

Example: A+B=C has to be performed in the following manner, where A, B, C are variables in memory.

1 Load A and B from the memory into internal registers, say R0 and R1.

2 Perform the ALU operation R1+R2

3 Store the result in location corresponding to C.

Introduction

Data Types

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Basic element is a binary digit (a bit) Bits are organized into

Byte - 8 bits Halfword - 16 bits or 2 bytes Word - 32 bits or 4 bytes

ARM instructions are 32 bits wide. The alternative instruction set known as Thumb instructions are 16 bits wide Data is typically handled at word, halfword, and/or byte levels Reading or writing data at word level must occur at word-aligned memory addresses. i.e. addresses aligned to 4-byte boundaries such as 0xXXXXXXX0, 0xXXXXXXX4, 0xXXXXXXX8,

0xXXXXXXXC.

Reading or writing data at halfword level must occur at halfword-aligned memory addresses. i.e. addresses aligned to 2-byte boundaries such as 0xXXXXXXX0, 0xXXXXXXX2.

Introduction

ARM7TDMI Programmer’s Model

Processor Modes

Instructions & Tools

Assembly Examples

ARM7TDMI processor core has 7 processor modes. 6 privileged modes and 1 unprivileged mode.

Mode

Description

Supervisor (SVC)

Entered (SWI) instruction on reset and is executed when a Software Interrupt

FIQ

Entered raised when a high priority (Fast) interrupt is

IRQ

Entered when a low priority (normal) interrupt is

raised

Abort

Used to handle memory access violations

Undef

Used to handle undefined instructions

System

Privileged mode mode using the same registers as User

instructions System Privileged mode mode using the same registers as User Privileged modes/ Exception modes

Privileged modes/

Exception

modes

User Mode under which most applications/OS tasks run
User Mode under which most applications/OS tasks run
User Mode under which most applications/OS tasks run

User

Mode under which most applications/OS tasks run

Unprivileged

Introduction

ARM7TDMI Programmer’s Model

Processor Modes

Instructions & Tools

Assembly Examples

User mode is the normal mode of operation where most applications run. Operational mode of the processor can be changed due to external events such as interrupts, exceptions (such as trying to access invalid memory location, trying to execute an undefined instruction) or due to a software trigger within the program. Low priority interrupts - IRQ mode Fast (high priority) interrupts - FIQ mode Supervisor mode - allows the processor to access restricted resources Undefined mode - can be used to software emulate an instruction not in the instruction set Abort mode - allows the processor to recover from memory access violation

Introduction

Registers

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Basic storage unit within the data path of the processor. An N-bit register is a series of N D-type flip-flops. Each register is 32 bits wide (1 word or 4 bytes). There are 37 physical registers in total, divided as

30 general purpose registers

6 status registers

1 program counter (PC)

These registers are organized in a partially overlapped configuration among the different processor modes.

That is, at any given time, the programmer can access 15

general purpose registers (r0,r1,

or r15), and one/two status registers. User mode and system mode share the same set of registers When the processor mode is changed some of the registers are swapped with a set of physically different registers dedicated to the new mode.

,r14),

program counter (PC

Introduction

Registers

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

R5, V2 R5 R5 R6, V3 R6 R6 R7,V4 R7 R7 R8,V5 R8 R8 R9,
R5, V2
R5
R5
R6, V3
R6
R6
R7,V4
R7
R7
R8,V5
R8
R8
R9, V6
R9
R9
R10,V7
R10
R10
R11, V8
R11
R11
R12, ip
R12
R12
R13, sp
R13_ SVC
R14, lr
R14 _SVC

Mode

User/System

Supervisor

Abort

Undefined

Interrupt -IRQ

Fast Interrupt - FIQ

R0 , A1

R0

R0

R0

R0

R0

R1, A2

R1

R1

R1

R1

R1

R2, A3

R2

R2

R2

R2

R2

R3, A4

R3

R3

R3

R3

R3

R4, V1

R4

R4

R4

R4

R4

  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
  R5 R5 R5 R6 R6 R6 R7 R7 R7 R8 R8 _FIQ R9 R9
 

R5

R5

R5

R6

R6

R6

R7

R7

R7

R8

R8 _FIQ

R9

R9

R9_ FIQ

R10

R10

R10_ FIQ

R11

R11

R11_ FIQ

R12

R12

R12_ FIQ

R13_ ABORT

R13 _UNDEF

R13_ IRQ

R13_ FIQ

R14_ ABORT

R14 _UNDEF

R14_ IRQ

R14_ FIQ

R8
R8
R8

R8

R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8
R8

Introduction

Registers

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Program counter (PC or R15) is accessible to all the modes. PC points to the instruction being fetched from the memory. PC is incremented by 4 after each instruction fetch.

Mode
Mode
Mode User/System Supervisor Abort R15(PC) R15(PC) R15(PC) Undefined Interrupt Fast
User/System Supervisor Abort R15(PC) R15(PC) R15(PC) Undefined Interrupt Fast Interrupt R15(PC)
User/System Supervisor Abort R15(PC) R15(PC) R15(PC) Undefined Interrupt Fast Interrupt R15(PC)
User/System Supervisor Abort R15(PC) R15(PC) R15(PC) Undefined Interrupt Fast Interrupt R15(PC)
User/System Supervisor Abort R15(PC) R15(PC) R15(PC) Undefined Interrupt Fast Interrupt R15(PC)
User/System Supervisor Abort R15(PC) R15(PC) R15(PC)

User/System

Supervisor

Abort

R15(PC)

R15(PC)

R15(PC)

Undefined

Interrupt

Fast Interrupt

R15(PC)

R15(PC)

R15(PC)

Undefined Interrupt Fast Interrupt R15(PC) R15(PC) R15(PC)

Current Program Status Register (CPSR) is visible to all the modes. CPSR stores useful information about the current status of the processor. All 5 privileged modes except the system mode have their own Saved Program Status Register (SPSR) whose purpose is to preserve the current status of the processor during switching between modes.

Mode User/System Supervisor Abort Undefined Interrupt Fast Interrupt CPSR CPSR CPSR CPSR CPSR CPSR SPSR
Mode
User/System
Supervisor
Abort
Undefined
Interrupt
Fast Interrupt
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR _SVC
SPSR_ABORT
SPSR _UNDEF
SPSR_ IRQ
SPSR_ FIQ
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples Registers Example 1 If the
Introduction
ARM7TDMI Programmer’s Model
Instructions & Tools
Assembly Examples
Registers
Example 1
If the processor switches from user mode to supervisor mode (e.g.
due to a power reset or software interrupt)- R0-R12 will be kept
intact, R13 and R14 in the user mode will be swapped with two
different registers R13 SVC and R14 SVC, respectively. PC will be
the same. CPSR is copied to SPSR SVC for later retrieval.
the same. CPSR is copied to SPSR SVC for later retrieval. Example 2 Now, while the

Example 2 Now, while the processor is in the supervisor mode, if a fast interrupt comes along the mode will be switched to FIQ. R0-R7 will be kept intact, R8-R14 will be swapped with R8 FIQ - R14 FIQ, respectively, and CPSR will be saved in the SPSR FIQ.

FIQ, respectively, and CPSR will be saved in the SPSR FIQ. Q: Why does the FIQ
Q:
Q:

Why does the FIQ mode have more registers swapping?

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Some Special Purpose Registers

Assembly Examples

Program Counter (PC/R15) - holds the 32-bit address of the instruction being fetched. PC is incremented by 4 upon each instruction fetch.

Stack Pointer (SP/R13) - holds the address of the top of the stack in the memory. Stack is a special data structure in the memory that is used during function/sub-routine calls. Each mode has its unique stack pointer.

Link Register (LR/R14) - holds the return address during branching and sub-routine calls.

Current Program Status Register (CPSR) - holds useful information about the current status (what happened during the last ALU operation, what is the current mode, interrupts enabled/disabled) of the processor.

Program Counter (PC) and 3-Stage Pipeline

Pipelining is the process of dividing a given task into a number of sub-tasks of lower complexity that can be performed in parallel to achieve increased real-time throughput. ARM7TDMI is a 3-stage pipelined architecture. The 3 stages are Fetch, Decode, and Execute. During cycle i, instruction pointed by PC is fetched, while the instruction fetched during the cycle i 1 is being decoded and the instruction decoded during cycle i 1 (that is fetched during the cycle i 2) is being executed. Upon each fetch, PC is automatically incremented by 4.

PC-8 PC FETCH 11 Fetched from memory 00 E1A02081 A0 PC-4 E3 PC-4 DECODE Decoding
PC-8
PC
FETCH
11
Fetched from memory
00
E1A02081
A0
PC-4
E3
PC-4
DECODE
Decoding the instruction in
80
the control unit
10
E1A01080
A0
E1
PC
PC-8
EXECUTE
Executing the instruction in
81
the datapath
20
A0
E3A00011
E1

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Program Status Registers - CPSR/SPSR

31 30 0 29 28 27 26 25 24 23 22 21 20 19 18

31

31 30

30

0

29

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
28
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7
6
5
4
3
2
1

M

N Z C V Do not modify / Read as Zero I F T M

N Z

C

V Do not modify / Read as Zero

N Z C V Do not modify / Read as Zero I F T M M

I

F

T M M

M

M

The Mode bits

PSR[4:0]

Mode

The Mode bits PSR[4:0] Mode
The Mode bits PSR[4:0] Mode
10000 User mode 10001 FIQ mode 10010 IRQ mode 10011 Supervisor mode 10111 Abort mode
10000 User mode 10001 FIQ mode 10010 IRQ mode 10011 Supervisor mode 10111 Abort mode

10000 User mode

10001

FIQ mode

10010

IRQ mode

10011

Supervisor mode

10111

Abort mode

11011

Undefined mode

11111

System mode

CPSR and SPSR have the same format. Condition code flags bits [31:28]

N

- negative

Z

- zero

C

- carry out

V

- overflow

Mode bits [4:0]

I - IRQs are disabled if set

F

- FIQs are disabled if set

T

- ARM/Thumb instructions - 0 for ARM

Introduction

ARM7TDMI Programmer’s Model

Vector Table

Instructions & Tools

Assembly Examples

Vector table contains vector addresses that contain instructions relevant to exception handling. When an exception occurs, the PC is changed to the corresponding vector address, thereby fetching the next instruction from the vector table. For ARM7TDMI architecture, these vector addresses contain branch instructions to the corresponding exception handler, except for the exceptions of type fast interrupt (FIQ).

The Exception Vector Table Exception Type Mode Vector Address Reset SVC 0x00000000 Undefined instructions UNDEF
The Exception Vector Table
Exception Type
Mode
Vector Address
Reset
SVC
0x00000000
Undefined instructions
UNDEF
0x00000004
Software Interrupt (SWI)
SVC
0x00000008
Prefetch abort (instruction fetch memory
ABORT
0x0000000C
abort)
Data abort (data access memory abort)
ABORT
0x00000010
IRQ (interrupt)
IRQ
0x00000018
FIQ (fast interrupt)
FIQ
0x0000001C

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Vector Table - Example

Following series of actions will happen if a low priority interrupt (IRQ) is triggered while the processor is in user mode. Since the processor is going to switch the mode from user to IRQ, PC is saved in R14 IRQ (link register in IRQ mode) and CPSR is saved in SPSR IRQ. Such house keeping is essential to make sure that you are able to return back to the user mode and continue execution, once the interrupt is handled. PC is changed to the IRQ vector address 0x00000018 and processor mode is switched to IRQ. The next instruction fetched from IRQ vector address is typically a branch instruction that will point the PC to the IRQ handler (also known as the interrupt service routine) located elsewhere in memory. IRQ exception handler will be executed. PC and CPSR will be restored and processor will be switched back to user mode.

Introduction

ARM7TDMI Programmer’s Model

ARM Instruction Set

Instructions & Tools

Assembly Examples

ARM instructions are 32 bits wide. Thumb instructions are 16 bits wide. We will stick with 32-bit ARMv4T instruction set which contains 48 instructions. These are elemental machine instructions which are coded with mnemonics (assembly language) for human readability. Four main categories

Data processing instructions - ADD, MOV, SUB, Data transfer instructions - LDR, STR Control flow instructions - B, BL Special instructions - MSR, MRS

ARM instructions must be aligned to 4-byte boundaries. Most instructions support conditional execution. Each instruction has an

Opcode - specifies the operation Operand - can be immediate, register, shifted register

Introduction

ARM Tools

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Examples

Compilers are used to map high-level instructions (such as C/C++) into processor specific element instructions (assembly language instructions)

Assembly instructions are converted to machine instructions by the assembler

Typically, output of the assembler is one/many object files which contain debugging and relocation information, and are used to build a larger executable file.

During assembly, the linker will combine the object files into an executable program. A debugger can be used to

access internal registers view memory contents set and clear break points for troubleshooting

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

An assembly program consists of ARM assembly language instructions, assembler directives, and comments.

[label]

[instruction/directive/pseudo-instruction]

[;comments]

Directives AREA ENTRY Prog1, CODE, READONLY MOV ; ; Shift load 1 initial bit to
Directives
AREA ENTRY Prog1, CODE, READONLY
MOV
; ; Shift load 1 initial bit to value left
; Shift 1 bit to left
MOV r0, #0x11 r0, LSL #1 r1, MOV r2, r1, LSL#1 stop B stop Directive
MOV
r0, #0x11 r0, LSL #1
r1,
MOV
r2,
r1, LSL#1
stop
B stop
Directive
END
label

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

Assembler directives are instructions for the assembler. They are not part of the actual ARM instructions. AREA - a new assembly section is to be created

section name is Prog1 section is for code (i.e. instructions) the section is read-only

ENTRY - specifies the starting point of the source file. A program must have at least one ENTRY. A single source file should not have multiple ENTRY directives.

END - declares the end of the source file.

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly to machine code mapping

Assembly Examples

(stop)
(stop)
MOV r0, #0x11 0x00000000 0x00000011 0x00000000 MOV r1, r0, LSL #1 0x00000022 0x00000011 0x00000000 MOV
MOV
r0, #0x11
0x00000000 0x00000011 0x00000000
MOV
r1, r0, LSL
#1
0x00000022 0x00000011 0x00000000
MOV
r2, r1, LSL
0x00000011
#1
0x00000022
0x00000044
B
stop

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

MOV r0, #0x11 from Onto B BUS decode ( shift barrel stage) occurs shifter through
MOV
r0, #0x11
from Onto B BUS decode (
shift barrel stage) occurs shifter through in ( this No a
case)
then
ALU to through r0 and ALU 32-bit BUS
MOV
r1, r0, LSL #1

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

MOV r1, r0, LSL #1 r0 from register occurs shifter through bank onto a in
MOV
r1, r0, LSL #1
r0 from register
occurs shifter through bank onto a in B barrel (shift BUS this
position then through to left) 32-
bit BUS ALU to r1 and ALU
case, shift by one

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

MOV r2, r1, LSL #1 r1 from register occurs shifter through bank onto a in
MOV
r2, r1, LSL #1
r1 from register
occurs shifter through bank onto a in B barrel (shift BUS this
position then through to left) 32-
bit BUS ALU to r2 and ALU
case, shift by one

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

B stop
B
stop
Tools Assembly Language Examples Assembly Examples B stop 0xFFFFFE onto B barrel left BUS by shifter
0xFFFFFE onto B barrel left BUS by shifter 2 through positions) ( shift a and
0xFFFFFE onto B
barrel left BUS by shifter 2 through positions) ( shift a
and PC value onto A
BUS then through

32-bit ALU and ALU register BUS to the address Assembler uses to create that replaces an address label) (

the PC value
the
PC
value

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Explanation on branch instruction stop

stop B stop

B

stop

Address

0x0000000C

0x00000010

0x00000014

EAFFFFFE
EAFFFFFE

Execu4ng at PC-8 Decoding at PC-4 Fetching at PC

Assembly Examples

Note that the label stop refers to the memory address 0x0000000C (labels are resolved into actual addresses by the linker). In order to branch back to the label stop, PC should be changed to 0x0000000C from its current value 0x00000014. That is, PC should become PC-8. We call this as a PC relative branch with effective offset -8.

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

& Tools Assembly Language Examples Assembly Examples During execution, the 24-bit signed offset is left shifted

During execution, the 24-bit signed offset is left shifted twice (i.e. multiplied by 4) and added to the PC to obtain the new value of the PC.

Therefore, in order to perform PC=PC+(-8), the 24-bit signed offset within the B instruction should be -2.

What is the 2’s compliment of -2?

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Computation of factorial of n. n! = n(n 1)

1

Assembly Examples

AREA ENTRY Prog2, CODE, READONLY MOV r6, r4, #10 r6 loop SUBS MOV r4, r4,
AREA ENTRY Prog2, CODE, READONLY
MOV
r6, r4, #10 r6
loop
SUBS MOV
r4,
r4, #1
Get the value of n
Copy n to n_factorial
n = n - 1
n_factorial = n_factorial * n
MULNE r6, r6, r4
BNE
loop
is n = 0?
Yes
stop
B
stop
No
END
END

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Things to note:

Assembly Examples

Appending letter S to data processing instruction forces the condition code flags (N,Z,C,V) to be saved into CPSR. In fact, this is one way of updating the condition flags. Why is it important to save the condition code flags? One can conditionally execute ARM instructions based on the output of a previous ALU operation. In this example, MULNE and BNE refer to conditional multiplication and conditional branch, respectively, and the condition NE refers to not equal (to zero). Therefore, both MULNE and BNE will be executed normally if the Z flag is 0. If Z flag is set (i.e. previous ALU operation resulted in a 0) both MULNE and BNE will be treated as no operations (nops).

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Assembly Examples

Write down the contents of registers R4 and R6 (in hexadecimal format) for the first two iterations of the above factorial calculation program.

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Swapping the contents of two registers.

Assembly Examples

AREA ENTRY Prog1, CODE, READONLY LDR LDR r0, r1, =0xF631024C =0x17539ABD ; ; load load
AREA ENTRY Prog1, CODE, READONLY
LDR LDR
r0, r1, =0xF631024C =0x17539ABD
; ; load load some some data data
EOR
r0, r0, r1
; r0 XOR r1
EOR
E0R
r0, r1, r0, r0,r1 r1
; ; r0 r0 XOR XOR r1 r1
stop
B
stop
END

Introduction

ARM7TDMI Programmer’s Model

Instructions & Tools

Assembly Language Examples

Swapping the contents of two registers.

Assembly Examples

0xF631024C LDR r0, =0XF631024C LDR 0x00000000 0xF631024C r1, =0X17539ABD 0x17539ABD 0xE16298F1 EOR r0, r0, r1
0xF631024C
LDR r0, =0XF631024C
LDR
0x00000000
0xF631024C
r1, =0X17539ABD
0x17539ABD
0xE16298F1
EOR r0, r0, r1
0x17539ABD
0xE16298F1
EOR r1, r0, r1
EOR r0, r0, r1
0xF631024C
0x17539ABD 0xF631024C