Lecture 1: Introduction to Embedded Systems and

ARM7TDMI Architecture

ELEC 2142 Embedded System Design

Session 2 - 2016, Week 1
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Outline

1 Introduction to Embedded Systems

2 ARM7TDMI Programmer’s Model

3 ARM Instructions and Tools

4 Assembly Language Examples

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Introduction to Embedded System

An embedded system is a microprocessor based system (often

with limited resources) dedicated to a specific task.
Computers are also microprocessor based systems, however
they are general purpose devices.
Embedded systems are typically
single purpose
cost and resources sensitive
supported by a wide range of processor architectures (4-bit,
8-bit, 16-bit, 32-bit, and 64-bit)
limited by real-time constraints
limited by power, speed, and area constraints
of small code size (e.g. CD player 20KB)
Expanding system features and resolving bugs can be achieved
by means of embedded software updates.
Embedded software - low level vs. high-level
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EMBEDDED
Embedded Systems SYSTEMS
- Applications
Application Area Examples

Aerospace Navigation systems, automatic landing systems, engine controls,

space exploration (e.g., the Mars Pathfinder)
Automotive Fuel injection control, air bag controls, GPS mapping, …
Children’s Toys Nintendo’s “Game Boy”, Xbox, ..
Communications Satellites; network routers, switches, hubs, …
Computer Printers, scanners, modems, hard disk drives, …
peripherals
Home Dishwashers, microwave ovens, VCRs, televisions,…
Industrial Elevator controls, robots, …
Instrumentation Data collection, oscilloscopes, signal generators…
Medical Imaging systems (XRAY, MRI etc), patient monitors, heart pacers
Office FAX machine, telephones …
Automation
Personal PDAs, cell phones, portable MP3 players, GPS …
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Embedded Systems - Microprocessors

The brain of an embedded system is a microprocessor
A microprocessor consists of
Arithmetic and Logic Unit (ALU)
Registers and internal bus structure
Control unit (CU) - can be hardwired or microprogrammed
What is a microcontroller?

Micro-architecture and Instruction Set Architecture (ISA)

Havard vs. Von-Neuman architectures
Data
Address
Memory Data
Memory
Central Address Data
Input Central
Processing Output Input
Data Processing
Unit (CPU) Output
Unit (CPU)
Program Program
Memory Memory
Von Neumann Architecture Havard Architecture
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Embedded Systems - Levels of Abstraction

In this course:
Applica1ons  and  OS  
ARM7TDMI processor
High  level  languages   architecture
Instruc1on  Set  Architecture   ARMv4T instruction set
(ISA)   LPC2478 microcontroller
and QVGA development
Microarchitecture  
board
Gates   Keil Microvision 4 IDE
Assembly language
Transistors   programming
Apple iphone 3 had ARM7 processor core
ARM7TDMI - T:Thumb, D:on-chip debug, M:multiplier,
I:in-circuit emulation
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Embedded Systems - RISC vs CISC Processors

RISC: Reduced Instruction Set Computer
MICROPROCESSORS
CISC: Complex Instruction Set Computer
RISC (Reduced Instruction CISC (Complex Instruction Set
Set Computer) Computer)
e.g ARM Processors e.g Motorola MC68000
Single-cycle execution Multiple-cycles to execute a single
instruction
A fixed instruction size Variable length of instructions
Instructions are simple to Use large microcode ROMs to decode
decode instructions
Load-store architecture Data processing is allowed on values stored
in memory
Large register bank of the same Smaller register bank of variable size
size
Poor code density Less code
Shorter development time Hard to design and easy for programmer
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ARM7TDMI Programmer’s Model

Programmer’s model is a description about the microprocessor in

programmer’s perspective including
Internal structure (data path and control)
Features available - such as what registers are accessible and
when
Details about exceptions - how the processor responds to an
invalid instruction
You need to know about the programmer’s model and the
instruction set of the underlying architecture to start writing
programs.

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 THE PROCESSOR
ARM7TDMI - Processor Core (ARM7TDMI)

ARM 7
Thumb
On-chip
Debug
Multipl
Embedd
ICE ( In
Circuit
Emulat
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Memory
Memory hierarchy includes
Registers (general purpose and special purpose)
Internal cache
External cache
MEMORY SYSTEM
Main (primary) memory - data and program
Secondary memory, virtual memory
• The caches are managed automatically by the- hard disks etc
hardware and effectively
Typically, invisible
the low-level to the
programmer needs to access registers
application.
and main memory
Caches are managed automatically by the hardware
• VirtualVirtual
memory is handled
memory by Operating
is handled by the system
operating system
Speed Size
Registers A few ns 128 bytes
On-chip Cache Ten ns 8-32 Kbytes
2nd Cache A few tens of ns Hundreds of Kbytes
Main Memory 100ns Mega bytes
Virtual memory tens of 100 Gbytes
(Hard disk) milliseconds

Fast memory
• Introduction is Systems
to Embedded moreand expensive per bitELEC
ARM Architecture than2142slow
- Week 1 10/40
ments that hold
Introduction
data, where each element
ARM7TDMI Programmer’s Model
has a
Instructions & Tools Assembly Examples

edMemory
number of bits and an address.

niversally adopted width of each memory

ment is 8bits (bytes)
Memory is organized as a
group of storage elements
(typically byte level, 8-bits)
Each memory location has
an address
N -bit address bus ⇒ 2N
address space
ARM7TDMI architecture
has 32-bit address bus ⇒
232 = 4 × 230 = 4GB of
memory space
Memory content is 8-bits

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Memory

Memory access is limited to LOAD (loading data from the

memory into the registers inside the processor core) and
STORE (storing the register values into memory locations)
operations. Direct manipulation of memory content such as
adding two variable in the memory is not permitted. This is
known as a load-store architecture.
Some CISC processors have instructions to directly manipulate
contents in the memory.
Example: A+B=C has to be performed in the following manner,
where A, B, C are variables in memory.
1 Load A and B from the memory into internal registers, say R0

and R1.
2 Perform the ALU operation R1+R2

3 Store the result in location corresponding to C.

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Data Types
Basic element is a binary digit (a bit)
Bits are organized into
Byte - 8 bits
Halfword - 16 bits or 2 bytes
Word - 32 bits or 4 bytes
ARM instructions are 32 bits wide.
The alternative instruction set known as Thumb instructions
are 16 bits wide
Data is typically handled at word, halfword, and/or byte levels
Reading or writing data at word level must occur at word-aligned
memory addresses. i.e. addresses aligned to 4-byte boundaries
such as 0xXXXXXXX0, 0xXXXXXXX4, 0xXXXXXXX8,
0xXXXXXXXC.
Reading or writing data at halfword level must occur at
halfword-aligned memory addresses. i.e. addresses aligned to
2-byte boundaries such as 0xXXXXXXX0, 0xXXXXXXX2.
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PROCESSOR
Processor Modes MODES
• Version 4T (ARM7TDMI) cores support seven
processorprocessor
ARM7TDMI modes: User,
core has 7FIQ, IRQ
processor , Supervisor,
modes. 6 privileged
Abort, Undef, and System.
modes and 1 unprivileged mode.

Mode Description
Supervisor Entered on reset and when a Software Interrupt
(SVC) (SWI) instruction is executed
FIQ Entered when a high priority (Fast) interrupt is Privileged
raised modes/
IRQ Entered when a low priority (normal) interrupt is Exception
raised modes
Abort Used to handle memory access violations
Undef Used to handle undefined instructions
System Privileged mode using the same registers as User
mode
User Mode under which most applications/OS tasks run Unprivileged

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Processor Modes
User mode is the normal mode of operation where most
applications run.
Operational mode of the processor can be changed due to
external events such as interrupts, exceptions (such as trying
to access invalid memory location, trying to execute an
undefined instruction) or due to a software trigger within the
program.
Low priority interrupts - IRQ mode
Fast (high priority) interrupts - FIQ mode
Supervisor mode - allows the processor to access restricted
resources
Undefined mode - can be used to software emulate an
instruction not in the instruction set
Abort mode - allows the processor to recover from memory
access violation
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Registers
Basic storage unit within the data path of the processor.
An N-bit register is a series of N D-type flip-flops.
Each register is 32 bits wide (1 word or 4 bytes).
There are 37 physical registers in total, divided as
30 general purpose registers
6 status registers
1 program counter (PC)
These registers are organized in a partially overlapped
configuration among the different processor modes.
That is, at any given time, the programmer can access 15
general purpose registers (r0,r1,...,r14), program counter (PC
or r15), and one/two status registers.
User mode and system mode share the same set of registers
When the processor mode is changed some of the registers are
swapped with a set of physically different registers dedicated
to the new mode.
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REGISTERS
Registers
Mode
User/System Supervisor Abort Undefined Interrupt -IRQ Fast Interrupt - FIQ
R0 , A1 R0 R0 R0 R0 R0
R1, A2 R1 R1 R1 R1 R1
R2, A3 R2 R2 R2 R2 R2
R3, A4 R3 R3 R3 R3 R3
R4, V1 R4 R4 R4 R4 R4
R5, V2 R5 R5 R5 R5 R5
R6, V3 R6 R6 R6 R6 R6
R7,V4 R7 R7 R7 R7 R7
R8,V5 R8 R8 R8 R8 R8 _FIQ
R9, V6 R9 R9 R9 R9 R9_ FIQ
R10,V7 R10 R10 R10 R10 R10_ FIQ
R11, V8 R11 R11 R11 R11 R11_ FIQ
R12, ip R12 R12 R12 R12 R12_ FIQ
R13, sp R13_ SVC R13_ ABORT R13 _UNDEF R13_ IRQ R13_ FIQ
R14, lr R14 _SVC R14_ ABORT R14 _UNDEF R14_ IRQ R14_ FIQ

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Registers
REGISTERS
REGISTERS
Program counter (PC or R15) is accessible to all the modes. PC
• Program
points counter being
to the instruction is seen by allfrom
fetched modes
the memory. PC is
Programbycounter
•incremented is
4 after eachseen by all
instructionmodes
fetch.
Mode
User/System Supervisor Mode
Abort Undefined Interrupt Fast Interrupt
User/System
R15(PC) Supervisor
R15(PC) Abort
R15(PC) Undefined
R15(PC) Interrupt
R15(PC) FastR15(PC)
Interrupt
R15(PC) R15(PC) R15(PC) R15(PC) R15(PC) R15(PC)

• Current Program Status Register isisseen bytoallall the

Current
•Current Program
Program
modes. Status
Status Register
Register (CPSR)is seen by all
visible

•modes.
modes. CPSR stores useful information about the current status of
the Supervisor,
processor. All 5Abort, Undefined,
privileged Interrupt,
modes except the systemand Fasthave
mode
Supervisor,
•theirInterrupt Abort,
modes Undefined,
have their Interrupt,
own Saved
own Saved Program Status Register (SPSR) whose
and
ProgramFast
Interrupt
Status
purpose
modes have their
is toRegister(SPSR)
preserve the current
own Saved
in status
addition Program
to processor
of the access toduring
Status
CPSR,
switching
Register(SPSR)
whichmodes.
between
in addition
common to all modes. to access to
CPSR, which common to all modes.
Mode
User/System Supervisor Mode
Abort Undefined Interrupt Fast Interrupt
User/System
CPSR Supervisor
CPSR Abort
CPSR Undefined
CPSR Interrupt
CPSR FastCPSR
Interrupt
CPSR CPSR
SPSR _SVC CPSR
SPSR_ABORTCPSR
SPSR _UNDEF CPSR
SPSR_ IRQ CPSR
SPSR_ FIQ
19 SPSRSystems
_SVC and ARM
SPSR_ABORT
Introduction to Embedded Architecture SPSR ELEC
_UNDEF
2142 - SPSR_
Week 1IRQ SPSR_ FIQ 18/40
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Registers

Example 1
If the processor switches from user mode to supervisor mode (e.g.
due to a power reset or software interrupt)- R0-R12 will be kept
intact, R13 and R14 in the user mode will be swapped with two
different registers R13 SVC and R14 SVC, respectively. PC will be
the same. CPSR is copied to SPSR SVC for later retrieval.

Example 2
Now, while the processor is in the supervisor mode, if a fast
interrupt comes along the mode will be switched to FIQ. R0-R7
will be kept intact, R8-R14 will be swapped with R8 FIQ -
R14 FIQ, respectively, and CPSR will be saved in the SPSR FIQ.
Q: Why does the FIQ mode have more registers swapping?

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Some Special Purpose Registers

Program Counter (PC/R15) - holds the 32-bit address of

the instruction being fetched. PC is incremented by 4 upon
each instruction fetch.
Stack Pointer (SP/R13) - holds the address of the top of
the stack in the memory. Stack is a special data structure in
the memory that is used during function/sub-routine calls.
Each mode has its unique stack pointer.
Link Register (LR/R14) - holds the return address during
branching and sub-routine calls.
Current Program Status Register (CPSR) - holds useful
information about the current status (what happened during
the last ALU operation, what is the current mode, interrupts
enabled/disabled) of the processor.

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Program Counter (PC) and 3-Stage Pipeline
Pipelining is the process of dividing a given task into a number
of sub-tasks of lower complexity that can be performed in
parallel to achieve increased real-time throughput.
ARM7TDMI is a 3-stage pipelined architecture. The 3 stages
are Fetch, Decode, and Execute.
During cycle i, instruction pointed by PC is fetched, while the
REGISTERS
instruction fetched during the cycle i − 1 is being decoded and
The ARM7TDMI
the• instruction decodedisduring
a pipelined
cyclearchitecture,
i − 1 (that isthat is,
fetched
while one instruction is being fetched,
during the cycle i − 2) is being executed. another is
being decode, and yet again another one is being
Uponexecuted
each fetch, PC is automatically incremented by 4.

PC-8 11 PC FETCH Fetched from memory

00 E1A02081
A0
E3 Decoding the instruction in
PC-4 80 PC-4 DECODE the control unit
10
E1A01080
A0
E1 Executing the instruction in
PC 81 PC-8 EXECUTE the datapath
20
A0 E3A00011
E1
 Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Program
Program Status
Status Registers Register
- CPSR/SPSR
• Both CPSR and SPSR have the following format
gram 31Status Register
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N Z C V Do not modify / Read as Zero I FT MMMMM

:0] of PSRs are called the control bits
• Bit [31:28] - conditional
:0] of PSRs are called the Mode bits
flags
CPSR and SPSR have the same format.
The Mode bits – N - Negative Condition code flags bits [31:28]
PSR[4:0] – Z -Mode Zero N - negative
10000
C -mode
– User Carry over Z - zero
10001 FIQ mode
10010 V -mode
– IRQ Overflow C - carry out
10011
• BitSupervisor
[4:0]mode- Current Mode V - overflow
10111 Abort mode
11011 • I -Undefined IRQmode ( disable Mode IRQ bits if it[4:0]
is set)
11111
• F - FIQ ( disable FIQ
System mode
I - IRQs if are
it is set) if set
disabled
F - FIQs are disabled if set
• T -that
de bit pattern setistonot0 valid
for ARM code the
is requested,
T - ARM/Thumb
( otherwise THUMB code)
instructions - 0 for ARM
is unpredictable.
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Vector Table
Vector table contains vector addresses that contain instructions
relevant to exception handling. When an exception occurs, the PC
is changed to the corresponding vector address, thereby fetching
the nextTHE VECTOR
instruction TABLE
from the vector table. For ARM7TDMI
architecture, these vector addresses contain branch instructions to
• The vector table ( exception vector table) shows
the corresponding exception
external memory handler,
address except for
locations thatthe exceptions of
hold
type fastinformation that is necessary to handle exceptions.
interrupt (FIQ).
The Exception Vector Table
Exception Type Mode Vector Address
Reset SVC 0x00000000
Undefined instructions UNDEF 0x00000004
Software Interrupt (SWI) SVC 0x00000008
Prefetch abort (instruction fetch memory ABORT 0x0000000C
abort)
Data abort (data access memory abort) ABORT 0x00000010
IRQ (interrupt) IRQ 0x00000018
FIQ (fast interrupt) FIQ 0x0000001C
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Vector Table - Example

Following series of actions will happen if a low priority interrupt
(IRQ) is triggered while the processor is in user mode.
Since the processor is going to switch the mode from user to
IRQ, PC is saved in R14 IRQ (link register in IRQ mode) and
CPSR is saved in SPSR IRQ. Such house keeping is essential
to make sure that you are able to return back to the user
mode and continue execution, once the interrupt is handled.
PC is changed to the IRQ vector address 0x00000018 and
processor mode is switched to IRQ.
The next instruction fetched from IRQ vector address is
typically a branch instruction that will point the PC to the
IRQ handler (also known as the interrupt service routine)
located elsewhere in memory.
IRQ exception handler will be executed.
PC and CPSR will be restored and processor will be switched
back to user mode.
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ARM Instruction Set

ARM instructions are 32 bits wide.
Thumb instructions are 16 bits wide.
We will stick with 32-bit ARMv4T instruction set which
contains 48 instructions.
These are elemental machine instructions which are coded
with mnemonics (assembly language) for human readability.
Four main categories
Data processing instructions - ADD, MOV, SUB,...
Data transfer instructions - LDR, STR
Control flow instructions - B, BL
Special instructions - MSR, MRS
ARM instructions must be aligned to 4-byte boundaries.
Most instructions support conditional execution.
Each instruction has an
Opcode - specifies the operation
Operand - can be immediate, register, shifted register
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ARM Tools

Compilers are used to map high-level instructions (such as

C/C++) into processor specific element instructions
(assembly language instructions)
Assembly instructions are converted to machine instructions
by the assembler
Typically, output of the assembler is one/many object files
which contain debugging and relocation information, and are
used to build a larger executable file.
During assembly, the linker will combine the object files into
an executable program.
A debugger can be used to
access internal registers
view memory contents
set and clear break points for troubleshooting

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Assembly Language Examples

An assembly program consists of ARM assembly language
ASSEMBLY
instructions, PROGRAM
assembler directives, and comments.EXAMPLE
• Consists of ARM instructions, directives, and
[label] comments
[instruction/directive/pseudo-instruction] [;comments]

Directives AREA Prog1, CODE, READONLY

ENTRY

MOV r0, #0x11 ; load initial value

MOV r1, r0, LSL #1 ; Shift 1 bit to left
MOV r2, r1, LSL#1 ; Shift 1 bit to left

stop B stop

Directive END label

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Assembly Language Examples

Assembler directives are instructions for the assembler. They are

not part of the actual ARM instructions.
AREA - a new assembly section is to be created
section name is Prog1
section is for code (i.e. instructions)
the section is read-only
ENTRY - specifies the starting point of the source file. A
program must have at least one ENTRY. A single source file
should not have multiple ENTRY directives.
END - declares the end of the source file.

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ASSEMBLY
Assembly PROGRAM
Language Examples EXAMPLE
• After
Assembly being assembled
to machine and converted to machine
code mapping
code,
0x00000011
MOV r0, #0x11 0x00000000
0x00000000

MOV r1, r0, LSL 0x00000011

#1 0x00000022
0x00000000

MOV r2, r1, LSL 0x00000011

#1 0x00000022
0x00000044
(stop)
B stop

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Assembly Language Examples

ASSEMBLY PROGRAM EXAMPLE
MOV r0, #0x11

Onto B BUS (
from decode
stage) through a
barrel shifter ( No
shift occurs in this
case) then
through 32-bit
ALU and ALU BUS
to r0

MOV r1, r0, LSL #1

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Assembly Language Examples

ASSEMBLY PROGRAM EXAMPLE
MOV r1, r0, LSL #1

r0 from register
bank onto B BUS
through a barrel
shifter (shift
occurs in this
case, shift by one
position to left)
then through 32-
bit ALU and ALU
BUS to r1

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Assembly Language Examples

ASSEMBLY PROGRAM EXAMPLE
MOV r2, r1, LSL #1

r1 from register
bank onto B BUS
through a barrel
shifter (shift
occurs in this
case, shift by one
position to left)
then through 32-
bit ALU and ALU
BUS to r2

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Assembly Language Examples

ASSEMBLY PROGRAM EXAMPLE
B stop

0xFFFFFE onto B
BUS through a
barrel shifter ( shift
left by 2 positions)
and PC value onto A
BUS then through
32-bit ALU and ALU
BUS to the address
register

Assembler uses
the PC value to
create an address (
that replaces label)

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Assembly Language Examples

Explanation on branch instruction stop B stop

stop    B    stop  
Address  
0x0000000C   EAFFFFFE   Execu4ng  at  PC-­‐8  
0x00000010   Decoding  at  PC-­‐4  
0x00000014   Fetching  at  PC  

Note that the label stop refers to the memory address 0x0000000C
(labels are resolved into actual addresses by the linker). In order to
branch back to the label stop, PC should be changed to
0x0000000C from its current value 0x00000014. That is, PC
should become PC-8. We call this as a PC relative branch with
effective offset -8.

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SEMBLY PROGRAM EXAMPLE

Assembly Language Examples
w?
C( new value) = PC(at the moment) + effective
fset

Bit pattern for branch

During execution, the 24-bit signed offset is left shifted twice
ffective offset = 24_bit_signed_offset
(i.e. multiplied * 4PC to obtain the new
by 4) and added to the
he processor shifts offset provided in the
value of the PC.
structionTherefore,
patterninleft orderby two bits
to perform and effectively
PC=PC+(-8), the 24-bit
ultiplying it by four. Therefore, the offset in-2.the
signed offset within the B instruction should be
structionWhat
pattern
is the of
2’s B should be
compliment -2 to produce the
of -2?
equired effective offset of -8
s complement of -2 in 24 bits is FFFFFE

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 ASSEMBLY PROGRAM EXAMPLE
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Assembly Language Examples

• Factorial calculation (n!)
n! = n(n-1)…(1)
Computation of factorial of n. n! = n(n − 1)...1
Get the value of n
AREA Prog2, CODE, READONLY
ENTRY Copy n to n_factorial

MOV r6, #10 n=n-1

MOV r4, r6
loop SUBS r4, r4, #1 n_factorial = n_factorial * n
MULNE r6, r6, r4
BNE loop
is n = 0?
Yes

stop B stop No
END

END
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Assembly Language Examples

Things to note:
Appending letter S to data processing instruction forces the
condition code flags (N,Z,C,V) to be saved into CPSR. In
fact, this is one way of updating the condition flags.
Why is it important to save the condition code flags? One
can conditionally execute ARM instructions based on the
output of a previous ALU operation. In this example, MULNE
and BNE refer to conditional multiplication and conditional
branch, respectively, and the condition NE refers to not equal
(to zero).
Therefore, both MULNE and BNE will be executed normally if
the Z flag is 0.
If Z flag is set (i.e. previous ALU operation resulted in a 0)
both MULNE and BNE will be treated as no operations
(nops).
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Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Assembly Language Examples

Write down the contents of registers R4 and R6 (in hexadecimal

format) for the first two iterations of the above factorial
calculation program.

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 ASSEMBLY PROGRAM EXAMPLE
Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Assembly Language Examples

• Shuffle data around – swap the contents of two
registers
Swapping the contents of two registers.

AREA Prog1, CODE, READONLY

ENTRY

LDR r0, =0xF631024C ; load some data

LDR r1, =0x17539ABD ; load some data
EOR r0, r0, r1 ; r0 XOR r1
EOR r1, r0,r1 ; r0 XOR r1
E0R r0, r0, r1 ; r0 XOR r1

stop B stop

END
46
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Introduction ARM7TDMI Programmer’s Model Instructions & Tools Assembly Examples

Assembly Language Examples

ASSEMBLY PROGRAM EXAMPLE
Swapping the contents of two registers.

0xF631024C
LDR r0, =0XF631024C 0x00000000
0xF631024C
LDR r1, =0X17539ABD
0x17539ABD
0xE16298F1
EOR r0, r0, r1
0x17539ABD

EOR r1, r0, r1 0xE16298F1

0xF631024C
EOR r0, r0, r1 0x17539ABD
0xF631024C

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