ARTICLE IN PRESS

G Model
AEUE 51076 1–5

Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

1 Design of ultra-low voltage integrated CMOS based LNA and mixer for
2 ZigBee application
3 Q1 Wei-Keat Chong a , Harikrishnan Ramiah a,∗ , Gim-Heng Tan b , Nandini Vitee a ,
4 Jeevan Kanesan a
a
5 Department of Electrical Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia
b
6 Department of Electrical and Electronic Engineering, University Putra Malaysia, 43400 Serdang, Malaysia
7

8 a r t i c l e i n f o a b s t r a c t
9
10 Article history: This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differ-
11 Received 9 May 2013 ential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application.
12 Accepted 19 July 2013 An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which
13 is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 ␮m
14 Keywords: standard CMOS technology. With a power consumption of 905 ␮W at a voltage headroom of 0.5 V, the
15 LNA
proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB,
16 Mixer
1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of
17 Ultra-low voltage
18 Ultra-low power
−10.8 dBm.
19 CMOS © 2013 Published by Elsevier GmbH.
20 ZigBee

21 1. Introduction The continuous downscaling of channel length in deep- 41

submicron CMOS technology in proportion to the voltage 42

22 The development of low power transceiver is driven by the headroom limitation up to 1.2 V and below, outlays design chal- 43

23 need of prolonging battery life time in the implementation of wire- lenges in the construction of RF front-end block [4]. This has driven 44

24 less systems catering towards mobile application. The simplicity the need in the exploration of new design technique for current RF 45

25 in protocol, along with high density of nodes, has prompted IEEE architecture. As an aftermath of voltage headroom limitation, series 46

26 802.15.4, ZigBee as a preferred wireless personal area network (LR- stacking is alleviated. Often folded cascode topology is preferred as 47

27 WPAN) standard targeted towards low cost, low power and low it sits well into the implementation of low-voltage headroom real- 48

28 data rate implementation [1]. With a regulated operating band- ization. Addressing the need in reduced power consumption, active 49

29 width of ZigBee from 2.4 GHz to 2.4835 GHz, supporting a data chip area and production cost, the lossy and bulky integration of 50

30 rate 250 kbps, coupled with a sensitivity requirement of −85 dBm power hungry buffers, balun and inter-stage matching networks 51

31 [2], the standard fit well into the applications such as medical to the main blocks is discarded through single chip integration of 52

32 devices in personnel health care sector, home automation, con- LNA-mixer at the front-end receiver. As a bench of comparison, 53

33 sumer electronic devices and video games, highlighting minimal recent reported works of low power LNA-mixer implementation 54

34 power dissipation requirement [3]. still observe high voltage headroom and power consumption [5–7]. 55

35 The conventional architecture of receiver generally integrates This work reports the design and analysis of ultra-low voltage, 56

36 discrete, independent low noise amplifier (LNA), mixer and voltage ultra-low power fully differential integrated LNA-mixer in com- 57

37 control oscillator (VCO) coupled together with inter-stage match- pliance to IEEE 802.15.4 regulation. The integrated architecture is 58

38 ing network, balun or filters. These interleaving circuits lead to extracted, simulated and verified on a 0.13 ␮m standard CMOS plat- 59

39 additional power consumption and unwanted parasitic compo- form. The preference towards a differential architecture is derived 60

40 nents due to the increased complexity of the system. upon the ability in rejecting common-mode noise [8]. This feature 61

sets a perquisite of symmetrical physical realization, thus improv- 62

ing the noise figure of the architecture deemed to be critical in low 63

noise amplifier design. The differential realization also improves 64

Q2 ∗ Corresponding author. Tel.: +60 37967 5262; fax: +60 37967 5316. the linearity performance of the mixer due to even order nonlin- 65

E-mail address: hrkhari@um.edu.my (H. Ramiah). earity cancellation. This paper is organized as follows. Section 2 66

1434-8411/$ – see front matter © 2013 Published by Elsevier GmbH.

http://dx.doi.org/10.1016/j.aeue.2013.07.009

Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application.
Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009
 ARTICLE IN PRESS
G Model
AEUE 51076 1–5
2 W.-K. Chong et al. / Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx

VDD

Cc
Cb M2

Lr
Ld
VLO+ VLO-
VO,LNA M3 M4
Vin Lg
M1
VO+ VO-
Cex
RL RL
Fig. 1. Proposed LNA-mixer architecture. Ls

Fig. 3. Ultra-low power LNA-mixer topology adapted from [7].

Fig. 2. Small signal equivalent circuit of LNA.

67 of this work addresses the insight of the LNA-mixer design and

68 operation. Section 3, reveals the RC-extracted post layout simula-
69 tion results from the implemented design. Finally in Section 4, the
70 overall development work is summarized.

71 2. Proposed ultra-low voltage LNA-mixer design

72 The design of the integrated LNA-mixer architecture, which

73 operates at ultra-low power supply headroom of 0.5 V is based
74 on a fully differential inductive degenerative cascode LNA topol-
75 ogy coupled with a double balanced PMOS based mixer in a folded
76 configuration. A folded architecture is a preferred solution over
77 the conventional series stacking topology in addressing voltage
78 headroom limitation. However, the increase in dc current con-
Fig. 4. Simulated input return loss of RF input.
79 sumption flow between the switching and transconductance stage
80 has promoted in the exploration of complementary current-reuse
81 technique [9]. The optimization of power consumption through limited as in Eq. (1). The setback in voltage headroom limitation 98

82 current-reuse technique in adapted as the dc current ICR(1,2) from is alleviated by integrating a PMOS input switching stage coupled 99

83 the switching stage is fed into the LNA stage as shown in Fig. 1. The with an inductive load Ld(1,2) as described in Fig. 1. Adapting the 100

84 architecture of Fig. 1 illustrates the integration of the LNA-mixer principle of current-reuse in optimizing the power consumption, 101

85 while the simplified small signal representation of the integrating the output current from the LNA is sourced into the input of current 102

86 LNA is given in Fig. 2. mixer. This integration also reduces the complexity of the architec- 103

87 As a bench of comparison, a recent proposed architecture on an ture. As a result, the DC voltage required to turn ON the LO switching 104

88 ultra-low power LNA-mixer [7] is shown in Fig. 3. Accounting that stage is no longer dependent on the overdrive voltage, Vds2(sat) of 105

89 the gate of LO switching stage in Fig. 3 is biased slightly above the transistor M2 as in Fig. 3. The proposed topology fits well into 106

90 threshold voltage (Vth3 ) of transistor M3 , the minimum DC voltage the adaptation of ultra-low voltage integration, as the minimum 107

91 required to bias the LO transistor can be expressed as below: gate bias voltage of the switching LO is reduced to only VDD − Vth5 , 108

neglecting the fractional voltage drop across the inductor due to 109
92 VLO = VDD − Vds2(sat) − Vth3 (1) internal series resistance. The minimum voltage headroom of the 110

93 where Vds2(sat) is the overdrive voltage of transistor M2 and Vth3 is proposed topology is approximated as: 111

94 the threshold voltage of transistor M3 . VDD(min) ≈ Vds1,2(sat) + Vds3,4(sat) (2) 112

95 Due to the limitation of the overdrive voltage in transistor M2
96 and the threshold voltage of transistor M3 , the switching input in The LNA is realized through the integration of common source 113

97 Fig. 3 would not enable a voltage headroom down to 0.5 V evidently inductive degenerative transistor M1 and M2 . Capacitor Cex plays 114

Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application.
Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009
 ARTICLE IN PRESS
G Model
AEUE 51076 1–5
W.-K. Chong et al. / Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx 3

Table 1
Summary results and performance comparison of other LNA-mixer.

Specification [5]a [6]a [7]b [14]a [15]b [16]a [17]b [18]b [19]b This work

Frequency (GHz) 1.55 2.4 2.4 5.8 0.9 2.4 2.1 2.6 2.4 2.4
S11 of RF input (dB) – −27.7 −24 −8 −13 – −11 <−10 <−17 −37.1
Gain (dB) 26 −3.3 21 15.7 10 25.7 23 23 20.5 22.3
P1 dB (dBm) −26 −18.6 −24 – −15 – – −15 −20 −22.3
IIP3 (dBm) – −10.3 −18 −20.56 −5 – −1.5 −7.4 −7.8 −10.8
NF (dB) 4.3 16.5 6 7.8 2.5 5.2 3.2 5.7 13.2 7.2
Supply voltage (V) 1.8 1.2 1.8 1.5 1.8 1.7 2.7 1.2 1.2 0.5
Power (mW) 10.8 7.6 1.62 17.25 3.6 13.8 21.6 7.2 1.08 0.905
Technology (␮m) 0.18 0.13 0.18 0.18 0.18 0.25 0.35 0.18 0.18 0.13
a
Simulation results.
b
Measurement results.

Fig. 5. Simulated noise figure of the integrated architecture.

Fig. 7. Simulated IIP3 with 100 kHz frequency offset.

a pivotal role in the optimization of noise and input matching. 115

The approach is in the realization of a small value of the parasitic 116

capacitance, Cgs in proportion to a small size of transistor yielding 117

in the feasibility of manipulating Cex , accordingly. The dimension 118

of M1 , Lg , Ls , Cex and the voltage, vgs1 are optimized to achieve 119

maximum power and noise matching through the design princi- 120

ple of power-constrained simultaneous noise and input matching 121

(PCSNIM) technique [10]. 122

From Fig. 2, the load resistor RL is connected to AC ground when 123

the capacitance C1 and C2 are sufficiently large at the IF output. The 124

analysis at the input results in: 125

 1

vin = iin jωo Lg + + (iin + gm1 vgs1 )jωo Ls (3) 126
jωo Ct

where the total capacitance is Ct = Cgs + Cex , ωo is the operating fre- 127

quency, while gm1 and vgs1 is the transconductance and gate source 128

voltage of transistor M1 , respectively. 129

From the ac equivalent circuit of LNA stage in Fig. 2, gate source 130

voltage of transistor M1 can be derived as vgs1 = iin /jωo Ct . Hence, the 131

input impedance of LNA can be expressed as: 132

vin 1 gm1 Ls
Zin = = jωo (Ls + Lg ) + + (4) 133
iin jωo Ct Ct

Fig. 6. Simulated total conversion gain versus IF output frequency. From Eq. (4), the source degeneration constitutes the real part at 134

the input impedance. At resonance, only the real part of the input 135

Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application.
Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009
 ARTICLE IN PRESS
G Model
AEUE 51076 1–5
4 W.-K. Chong et al. / Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx

The RF input voltage, vRF generates an AC input current at node 172

Vx1 , given as: 173

gm1 vRF sin ωRF t

ix1 = gm1 vgs1 = (8) 174
4jωo Rs Ct
At node Vx(1,2) , there is small amount of AC current flowing 175

through the resistor RL(1,2) and parasitic capacitance Cgs(3,4) which 176

is negligible as the impedance of RL(1,2) and Cgs(3,4) at 2.4 GHz are 177

10 times greater than 1/gm(3,4) . In the worst case scenario, the high 178

frequency RF signal leaking through resistor RL(1,2) can be still sup- 179

pressed and filtered out by capacitor C1 and C2 at the IF output. For 180

simplicity, assuming that there is no AC current leakage through 181

RL1 and Cgs3 , the AC current delivered to node Vy1 through transis- 182

tor M3 which operates as a unity gain buffer can be expressed as: 183

184

gm1 vRF sin ωRF t

iy1 = ix1 = (9) 185
4jωo Rs Ct
whereas, the AC current at node Vy2 which is 180◦ phase shifted 186

respective to the AC current at node Vy1 , is given as: 187

Fig. 8. Physical layout of LNA-mixer circuits including RF ESD pads. gm1 vRF sin ωRF t
iy2 = − (10) 188
4jωo Rs Ct
The mixing points of RF and LO signals are located at node Vy1 189
136 impedance exists, an input impedance matching up to 50  can be
and Vy2 , respectively. The differential output current can be derived 190
137 achieved by equating:
as below: 191

gm1 Ls gm1 vRF sin ωRF t

138 Rin = = 50 (5) iIF = (iy1 − iy2 ) · sq(ωLO t) = × 192
Ct 2jωo Rs Ct
4  sin 3ωLO t

sin ωLO t + + ··· (11) 193
139 ωo2 Ct (Ls + Lg ) = 1 (6)  3
where sq(ωLO t) is the square wave for LO signal. 194
140 Since the input impedance is purely resistive at resonance,
Considering only the desired intermodulation frequencies 195
141 inductor Lg has an additional degree of freedom in maintaining this
and neglecting the unwanted spurs such as cos(ωRF ± 3ωLO )t, 196
142 condition [11].
cos(ωRF ± 5ωLO )t and other higher order terms, the differential out- 197
143 While providing the path of current bleeding, transistor M3 and
put current from Eq. (11) can be simplified as below: 198
144 M4 in Fig. 1 are cascoded in enhancing the reverse isolation of
gm1 vRF
145 the LNA. The RF choke inductor Ld(1,2) resonates with the para- iIF = [sin(ωRF − ωLO )t − sin(ωRF + ωLO )t] (12) 199
146 sitic capacitance at node Vy(1,2) , thus presenting high impedance jωo Rs Ct
147 path at 2.4 GHz to prevent RF signal leakage to the power supply, The respective differential output voltage can be expressed as 200
148 VDD [12], while driving all the RF signal into the switching quad. below: 201
149 Alternately the low frequency components leakage from IF output gm1 vRF RL
150 through resistor RL(1,2) sinks to AC ground (VDD ) through inductor vIF = iIF · RL = [sin(ωRF − ωLO )t − sin(ωRF + ωLO )t] (13) 202
jωo Rs Ct
151 Ld(1,2) . The switching quad M5 –M8 is biased in the vicinity of the
152 threshold voltage to achieve low bias current, thus reducing the where RL is the load resistance from the mixer stage. 203

153 DC offset, thermal noise, flicker noise, and gate-source capacitance, The resistor RL(1,2) along with capacitor C1 and C2 presents a 204

154 Cgs . This results in a substantial increase in the switching efficiency low pass filter at the IF output, which suppresses the fundamental 205

155 [13]. In the implementation aimed at draining low current flow, component of sin(ωLO )t, sin(ωRF )t leaking from LNA stage and other 206

156 the switching quad allows the integration of larger load resistance, higher-order mixing spurs such as sin(ωRF + ωLO )t. Ultimately, the 207

157 thus increasing the conversion gain (CG) of the mixer and relaxing overall voltage conversion gain of LNA-mixer at the desired output 208

158 the constraint of voltage headroom consumption. Capacitors, C1 spectrum is given by: 209
 
159 and C2 couples with the load resistance, RL(1,2) in attenuating the  vIF  gm1 RL
fundamental tone of LO and RF at the output while filtering out the AV =   = ω R C · [sin(ωRF − ωLO )t] (14) 210
160 vRF o s t
161 higher order output spurs. The adapted complementary current-
162 reuse technique enroutes the DC current from the switching quad
163 into the transconductance stage of LNA. This results in an increase 3. RC extracted results 211

164 of the transistor (M1,2 ) transconductance, which in turn boost up

165 the overall gain without using additional power consumption. The proposed architecture of Fig. 1 is verified on a 0.13 ␮m stan- 212

166 The detailed operation of LNA-mixer in Fig. 1 is described dard CMOS process for the regulated application of 2.4 GHz. The 213

167 through the following mathematical expression. When the RF input layout parasitic extraction (LPE) is executed and validated adapt- 214

168 signal VRF (t) = vRF ·sin(ωRF )t is applied, the gate source voltage of ing Cadence Spectre-RF and Calibre platform. Post simulation result 215

169 transistor M1 , vgs1 can be derived as: shows that the design draws 1.81 mA of current from 0.5 V of supply 216

voltage headroom. The RF input of the LNA is matched to 50  ter- 217

1
v sin ωRF t
 vRF sin ωRF t mination through source inductive degeneration and the respective 218
RF
170 vgs1 = = (7) simulated input return loss is described in Fig. 4. The input reflec- 219
2jωo Rs Ct 2 4jωo Rs Ct
tion S11 of −37.1 dB at about 2.4 GHz operating frequency confirms 220

171 where (vRF sin ωRF t)/2 is the differential RF input signal. the matching achieved. The simulated noise figure of the integrated 221

Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application.
Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009
 ARTICLE IN PRESS
G Model
AEUE 51076 1–5
W.-K. Chong et al. / Int. J. Electron. Commun. (AEÜ) xxx (2013) xxx–xxx 5

222 architecture is 7.2 dB at 1 MHz, where the selective 1/f noise cor- [17] Henrik S, Ali K-S, Asad AA. A merged CMOS LNA and mixer for a WCDMA 290

223 ner is taken to be at 30 kHz as illustrated in Fig. 5. Fig. 6 shows the receiver. IEEE J Solid-State Circ 2003;38(6):1045–50. 291
[18] Hong E-P, Hwang Y-S, Yoo H-J. A folded RF front-end with low flicker noise for 292
224 conversion gain versus IF output frequency plot, the total gain is Bluetooth and ZigBee application. In: Proceedings of Asia-Pacific Microwave. 293
225 indicated to be 22.3 dB at 1 MHz. With an input LO power of 0 dBm 2007. p. 1–4. 294
226 at 2.4 GHz, the 1 dB compression point of the design is achieved [19] Lee S-Y, Wang L-H, Chen T-Y, Yu C-T. A low-power RF front-end with merged 295
LNA, differential power splitter, and quadrature mixer for IEEE 802. 15.4 (Zig- 296
227 as −22.3 dBm. The two-tone test with 100 kHz frequency offset in Bee) applications. In: Proceedings of IEEE International Symposium on Circuits 297
228 the linearity verification results in an IIP3 point of −10.8 dBm as and Systems. 2012. p. 1492–5. 298
229 described in Fig. 7. The physical layout of the circuit incorporated
230 with RF ESD pads is illustrated in Fig. 8, with a respective chip area Wei Keat Chong received the B.S. degree in Electronic 299

231 of 1.35 mm × 1.31 mm being consumed. The performance summary Engineering from University Malaysia Perlis, Malaysia, in 300
2008. Currently, he is working towards the M.S. degree 301
232 of the proposed architecture along with the simulated performance in the University of Malaya, Kuala Lumpur, Malaysia. His 302
233 comparison with other recent reported works is given in Table 1. current research interest includes analogue and Radio Fre- 303
quency Integrated Circuit design. 304

234 4. Conclusion

235 In this paper, a new architecture of ultra-low voltage, ultra-

236 low power fully differential LNA integrated with a double-balanced
237 mixer for ZigBee applications was successfully designed and veri-
238 fied in 0.13 ␮m standard CMOS platform. Post extraction simulation Harikrishnan Ramiah is currently a Senior Lecturer 305
at Department of Electrical Engineering, University of 306
239 result reports 22.3 dB of the overall conversion gain, 7.2 dB of noise
Malaya, Malaysia, working in the area of RFIC design and 307
240 figure at 1 MHz, −37.1 dB of RF input return loss (S11), −22.3 dBm Electromagnetic Modelling. He received his B.Eng(Hons), 308
241 of 1 dB compression point and −10.8 dBm of input-referred third- M.Sc. and Ph.D. degrees in Electrical and Electronic Engi- 309
neering, in the field of Analogue and Digital IC design 310
242 order intercept point, IIP3. The proposed LNA-mixer single chip
from University Science Malaysia, Malaysia in 2000, 2003 311
243 integration operates at ultra-low voltage supply headroom of 0.5 V and 2008 respectively. He was the recipient of Intel Fel- 312
244 while consuming only 905 ␮W of power deemed as a favourable lowship Grant Award, 2000–2008. He received the Best 313

245 requirement for low power ZigBee application. Paper Awards from ICAST (International Conference on 314
Advances in Strategic Technologies), 2003 Conference. His 315
research work has resulted into various technical pub- 316
246 References lications. His main research interest includes Analogue 317
Integrated Circuit Design, RFIC Design, VLSI system design and Electromagnetic 318

247 [1] IEEE 802.15.4 Standard: Part 15.4: Wireless Medium Access Control (MAC) Modelling. Dr. Harikrishnan is a Chartered Engineer member of Institute of Electrical 319

248 and Physical Layer (PHY) Specification for Low-Rate Wireless Personal Area Technology (IET), member of IEEE and IEICE. 320

249 Networks (WPANs); September 2006.

250 [2] Seo H-M, Park Y-K, Park W-C, Lee M-S, Kim H-S, Choi P. System design consider- Gim Heng Tan received the B.S. and M.S. degree in Elec- 321
251 ations for a ZigBee RF receiver with regard to coexistence with wireless devices tronic Engineering from University Putra Malaysia in 1999 322
252 in the 2.4 GHz ISM-band. KSII Trans Internet Inform Syst 2008;2(1):37–49. and 2001 respectively. Currently, he is working towards 323
253 [3] Liu B, Wang C, Ma M, Guo S. An ultra low voltage and ultra low power 2.4 GHz the Ph.D. degree in University Putra Malaysia, Malaysia. 324
254 LNA design. Radioengineering 2009;18(4):527–31. His current research interest includes analogue and Radio 325
255 [4] Heiberg AC, Brown TW, Fiez TS, Mayaram K. A 250 mV, 325 ␮W GPS receiver Frequency Integrated Circuit Design. 326
256 RF front-end in 130 nm CMOS. IEEE J Solid-State Circ 2011;46(4):938–49.
257 [5] Lai D, Chen Y, Wang X, Chen X. A CMOS single-differential LNA and current
258 bleeding CMOS mixer for GPS receivers. In: Proceedings of ICCT 2010. 2010. p.
259 677–80.
260 [6] Martins MA, Oliveira LB, Fernandes JR. Combined LNA and mixer circuits for 2.
261 4 GHz ISM band. In: Proceedings of IEEE international symposium on circuits
262 and systems. 2009. p. 425–8.
263 [7] Le VH, Han S-K, Lee J-S, Lee S-G. Current-reused ultra low power, low noise Nandini Vitee received the B.S. degree in Industrial 327
264 LNA + mixer. IEEE Microwave Wireless Compon Lett 2009;19(11):755–7. Electronic Engineering from University Malaysia Perlis, 328
265 [8] Hwang Y-S, Wang S-F, Chen J-J. A differential multi-band CMOS low noise Malaysia, in 2012. Currently, she is working towards the 329
266 amplifier with noise cancellation and interference rejection. Int J Electron Com- M.S. degree in the University of Malaya, Kuala Lumpur, 330
267 mun 2010;64(10):897–903. Malaysia. Her current research interest includes analogue 331
268 [9] Hsieh H-H, Lu L-H. Design of ultra-low-voltage RF frontends with comple- and Radio Frequency Integrated Circuit design. 332
269 mentary current-reused architectures. IEEE Trans Microwave Theory Tech
270 2007;55(7):1445–58.
271 [10] Nguyen T-K, Kim C-H, Ihm G-J, Yang M-S, Lee S-G. CMOS low-noise ampli-
272 fier design optimization techniques. IEEE Trans Microwave Theory Tech
273 2004;52(5):1433–42.
274 [11] Noh NM, Zulkifli TZA. A 1.4 dB noise figure CMOS LNA for W-CDMA application.
275 In: Proceedings of RFM 2006. 2006. p. 143–8.
276 [12] Tan GH, Sidek RM, Ramiah H, Chong WK. Design of ultra-low voltage 0.5 V CMOS Jeevan Kanesan received his B.S. degree in Electrical 333
277 current bleeding mixer. IEICE Electron Exp 2012;9(11):990–7. & Electronics Engineering from University Technology 334
278 [13] Choi J-Y, Lee S-G. A 2.45 GHz CMOS up-conversion mixer design utilizing the Malaysia, Malaysia, in 1999, M.S. degree and Ph.D. 335
279 current-reused bleeding technique. Int J Electron 2004;91(9):537–50. degree in mechanical engineering from University Science 336
280 [14] Zuezhen W, Robert W. A novel low power low voltage LNA and mixer for WLAN Malaysia, Malaysia in 2003 and 2006 respectively. From 337
281 IEEE 802. 11A standard. In: Proceedings of IEEE Topical Meet SIRF. 2004. p. 2000 to 2001, he has worked as equipment engineer at 338
282 231–4. Carsem Semiconductor, Malaysia and IC Design engineer 339
283 [15] Nguyen T-K, Oh N-J, Le V-H, Lee S-G. A low-power CMOS direct conver- in the thermo-mechanical department, Intel Technology 340
284 sion receiver with 3-dB NF and 30-kHz flicker-noise corner for 915-MHz Sdn. Bhd., Malaysia from 2006 to 2008. He has been 341
285 band IEEE 802.15.4 ZigBee standard. IEEE Trans Microwave Theory Tech with University of Malaya, Malaysia as a Senior Lecturer 342
286 2006;54(2):735–41. in the electrical engineering department since 2008. His 343
287 [16] Hwang Y-S, Yoo H-J. A low power folded RF front-end with merged LNA and research interests include CAD of VLSI circuits and design 344
288 mixer for ZigBee/Bluetooth. In: Proceedings of IEEE radio and wireless sympo- and analysis of algorithms. 345
289 sium. 2007. p. 85–6.

Please cite this article in press as: Chong W-K, et al. Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application.
Int J Electron Commun (AEÜ) (2013), http://dx.doi.org/10.1016/j.aeue.2013.07.009