VHDL ASSIGNMENT

III

Andrew Menezes
BT13ECE088
 1) PACKAGE

AIM: To create a package containing all basic gates using

component style, a function for detecting rising edge and for
converting integer to binary.

CODE:
library ieee;
use ieee.std_logic_1164.all;

package packed is
component ANDTWO is
port(a,b:in bit;
y:out bit);
end component;
component ORTWO is
port(a,b:in bit;
y:out bit);
end component;
component NORTWO is
port(a,b:in bit;
y:out bit);
end component;
component NANDTWO is
port(a,b:in bit;
y:out bit);
 end component;
component XORTWO is
port(a,b:in bit;
y:out bit);
end component;
component XNORTWO is
port(a,b:in bit;
y:out bit);
end component;
function risingedge (wave:std_logic) return std_logic;
function convert (digit:integer) return std_logic_vector;
end packed;

package body packedbody is

function risingedge (wave:std_logic) return std_logic is
variable temp: std_logic;
begin
return (wave'event and wave='1');
end function;

function convert (digit:integer) return std_logic_vector;

begin
return (TO_STDLOGICVECTOR(digit));
end function;
end package body;
-------------------------------------------------------------
entity ANDTWO is
port(a,b:in bit;
y:out bit);
end ANDTWO;
architecture archone of ANDTWO is
begin
y<=a and b;
end archone;
------
entity ORTWO is
port(a,b:in bit;
y:out bit);
end ORTWO;
architecture archtwo of ORTWO is
begin
y<=a or b;
end archtwo;
----
entity NORTWO is
port(a,b:in bit;
y:out bit);
end NORTWO;
architecture archthree of NORTWO is
begin
y<=a nor b;
end archthree;
------
entity NANDTWO is
port(a,b:in bit;
y:out bit);
end NANDTWO;
architecture archfour of NANDTWO is
begin
y<=a nand b;
end archfour;
-------
entity XORTWO is
port(a,b:in bit;
y:out bit);
end XORTWO;
architecture archfive of XORTWO is
begin
y<=a xor b;
end archfive;
-------
entity XNORTWO is
port(a,b:in bit;
y:out bit);
end XNORTWO;
architecture archsix of XNORTWO is
begin
y<=a xnor b;
 end archsix;

CONCLUSION:
The package and package body for gates and both functions
were written using VHDL code.
 2) 4 BIT BINARY UP COUNTER

AIM: To design a 4 bit binary up counter using if…else

CODE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity upcounter is
port(CLOCK,RESET : in std_logic;
COUNT : out std_logic_vector(3 downto 0));
end upcounter;

architecture arch of upcounter is

signal temp: std_logic_vector(3 downto 0);
begin
process (CLOCK,RESET)
begin
if (RESET='1') then
temp <= "0000";
elsif (CLOCK'event and CLOCK='1') then
temp <= temp + 1;
end if;
end process;
COUNT <= temp ;
end arch;
RTL VIEW:

WAVEFORMS:
TECHNOLOGY MAPS:

CONCLUSION:
A four bit binary up counter was designed using if…else
statements.