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SAMSUNG PROPRIETARY

SAMSUNG PROPRIETARY

D D

C C

B B

A A

THIS DOCUMENT CONTAINS CONFIDENTIAL

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

PROPRIETARY INFORMATION THAT IS

SAMSUNG SAMSUNG ELECTRONICS ELECTRONICS CO’S CO’S PROPERTY. PROPERTY.

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS

EXCEPT EXCEPT AS AS AUTHORIZED AUTHORIZED BY BY SAMSUNG. SAMSUNG.

4

Table of Contents

Sheet 1. COVER

Sheet 2-6. DIAGRAM (Block/Power) & ANNOTATIONS Sheet 7. CLOCK GENERATOR

Sheet 8-10. Merom 800

Sheet 11. THERMAL SENSOR / FAN CONTROL

Sheet 12-16. RS600ME

Sheet17. DDR II SODIMM

Sheet18. DDR II TERMINATION

Sheet19-22. SB600

Sheet23. SB600 STRAPS

Sheet24. SPI ROM & DEBUG CARD CONN

Sheet25. LCD

Sheet26. CRT

Sheet27. EXPRESS CARD

Sheet28. 2 IN 1

Sheet29. MINICARD

Sheet30-33. AUDIO

Sheet34. HDD(SATA) & ODD(IDE)

Sheet35. MICOM

Sheet36. LOM WITH COMBO

Sheet37. USB & MDC & CAMERA

Sheet38. LED & BLUETOOTH & TOUCHPAD & KEYBOARD & LID S/W

Sheet39. CHARGER

Sheet40. P3.3V_AUX & P5.0V_AUX

Sheet41. P1.2V & P1.2V_AUX & VCCP

Sheet42. DDR2 POWER

Sheet43. CPU VRM

Sheet44. P1.5V POWER & SWITCHED POWER & MICOM RESET

Sheet45. ICT PORT

Sheet46. POWER DRAW & MOUNT HOLE

Sheet47-49. TP

USE ICT PORT Add Camera/Mic (2007.12.28)

PRAHA (SRI-CAMERA)

CPU

Chip Set : RS600ME & SB600

Remarks : Mobility Platform

: Intel Merom/Penryn SRR (800MHz)

Model Name : PRAHA

PBA Name

: MAIN

PCB Code

: TPT : BA41-00875A

GCE : BA41-00874A

NAN : BA41-00876A

Dev. Step

: MP (8-Layer)

Revision

: 1.0

T.R. Date : 2008.01.28

DRAW

CHECK

APPROVAL

: 1.0 T.R. Date : 2008.01.28 DRAW CHECK APPROVAL Owner : SEC Mobile R & D

Owner :

SEC Mobile R & D

Signature :

X

SAMSUNG ELECTRONICS
SAMSUNG
ELECTRONICS

www.vinafix.vn

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DRAW CHECK APPROVAL Owner : SEC Mobile R & D Signature : X SAMSUNG ELECTRONICS www.vinafix.vn

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1 1

4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CPU
FAN
Mobile Processor
VRM
System DC/DC
PG 11
D
IMVP-6
MEROM
Connector
Charging
CPU
(800MHz)
PG 42
Thermal
Circuit
LCD
Sensor
PG 11
L2 Cache : 2 MB, 4MB
30P
PG 38
PG 8, 9,10
478pin
PG 25
ANT
DDR II
Switched PWR
LVDS
1ch
VRM
Wireless LAN
PG 43
PG 41
DDR II
PG 17
CRT
Channel A
Mini Card
North Bridge
CRT
SODIMM 0
PG 29
PG 26
DDR II 667/533
PG 17
PCI Express
Channel B
DDR II
RS600ME
SODIMM 1
Express Card
PCI Express
10/100 LOM
707 FCBGA
PCI Express
88E8039
PG 27
RJ45
C
PG 35
PG 12 ~ 16
PG 35
Internal Graphics
4-Lane
A-Link Express
Clocking
CK-410 for ATI
64 PIN
PG 7
USB 1
2 IN 1
SD/MMC
PG 28
USB 4
South Bridge
AU6371
USB 0,8,9
PG 28
PG 39
USB 0,8,9
PG 30
ANT
SB600
USB 5
USB 2
CAMERA
AUDIO
Bluetooth
PG 37
PG 37
Audio
564 BGA
AZALIA
AZALIA Primary
AMP
Codec
SPI ROM
B
ALC262
12P
PG 24
PG 31
PG 30
AZALIA
AZALIA Secondary
RJ11
PG 19 ~ 22
PG 37
MDC 1.5
HP
PG 35
MIC-IN
PG 36
Touch
PG 32
MICOM
PAD
3.3V LPC, 33MHz
Hitachi H8S
4P
2110B
KBD
PG 31
PG 34
PG 37
SATA
PG 33
HDD
SPKR
R
2P
PATA
SPKR
L
PG 32
PG 33
ODD
A
SAMSUNG
MIC

4

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1

ELECTRONICS

D

C

B

A

R 2P PATA SPKR L PG 32 PG 33 ODD A SAMSUNG MIC 4 3 2

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4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
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1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Power Diagram
KBC3_SUSPWRON
KBC3_PWRON
KBC3_VRON
P1.2V_PWRGD
D
D
AC Adapter
P1.05V
CPU
VCC_CORE
NB
(VCCP)
SB
CPU
VDC
P1.2V
P1.8V_AUX
P1.8V
Battery DC
P0.9V
C
C
P12.0V_ALW
P5.0V_AUX
P5.0V
P5.0V_ALW
P1.2V_AUX
MICOM_P3.3V
P3.3V_AUX
P3.3V
P1.2V_ALW
P2.5V_LAN
P1.5V
B
B
P1.2V_LAN
Rail
+V*Always
+V*AUX
+V
SUSPWR
PWRON
VRON
State
Full On
ON
ON
ON
H
H
H
MEM1_REF
S3
ON
ON
OFF
H
L
L
S4
ON
ON
OFF
H
L
L
S5
ON
OFF
OFF
L
L
L
S5 / S4
S3
S0
A
A
SAMSUNG
ELECTRONICS
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ON ON OFF H L L S5 ON OFF OFF L L L S5 / S4
4 3 2 1 15 POWER SEQUENCE 11) P3.3V 15) CLK3_PWRGD# MICOM_P3.3V Rev. 0.1 4
4
3
2
1
15
POWER SEQUENCE
11) P3.3V
15) CLK3_PWRGD#
MICOM_P3.3V
Rev. 0.1
4
CLOCK
P1.2V_ALW
CHIP
16
4) P1.2V_ALW
16) Clock Running
MIC5258-1.2
17) CLK3_PWRGD#
Sheet 8
P12.0V_ALW
Sheet43
10) KBC3_PWRON
1
D
11) P1.5V
D
MIC5219B
MICOM_P3.3V
2
15) CLK3_PWRGD#
VDC
RTC
1) PRTC_BAT
Sheet 44
MMBT3904
AP4435GM
Battery
CPU
Sheet43
7) P3.3V_AUX
18
2) VDC
Sheet38
18) VRM3_CPU_PWRGD
Sheet 19
VRM
14) VCC_CORE
V5FILT
14
13) P1.2V_PWRGD
3
3) MICOM_P3.3V
3) MICOM_P3.3V
Sheet 45
MICOM_P3.3V & P5V_ALW
TPS51120
11) P5.0V
CPU
POWER
11) P1.5V
RHU002N06
(1/2)
(KBC3_RST#)
S/W
4) P1.2V_ALW
Sheet39
12) VCCP
Sheet43
18) VRM3_CPU_PWRGD
20) CPU1_PWRGDCPU
20) CPU1_PWRGDCPU
5
20
19
19) KBC3_PWRGD
Sheet 8-10
21) CHP3_ALINK_RST#
21-1) CHP3_NBRST#
17) CLK3_PWRGD#
21
17
11) P3.3V
9) CHP3_SLPS5#/S3#
9
22
SB
11) P1.8V
KBC
21)PEX3_RST#_CTRL
21-1) PEX3_RST#
8) KBC3_RSMRST#
C
7) P1.8V_AUX
NB
C
8
12) VCCP
7) P3.3V_AUX
12) VCCP
7) P3.3V_AUX
RS600ME
11) P3.3V
18) KBC3_NBPWRGD
10) KBC3_PWRON
10-1) KBC3_VRON
10
12) P1.2V
12) P1.2V
11) P5.0V
11) P5.0V
SB600
21-2) CHP3_NBRST#
Sheet 12 - 16
6) KBC3_SUSPWRON
7-1) P1.2V_AUX
Sheet 20-23
6
21-1) PLT3_RSTF#
21-1) PLT3_RSTF#
11) P5.0V
18) KBC3_NBPWRGD
Thermal
Sheet34
7) P3.3V_AUX
7) P5.0V_AUX
12) P1.2V
P1.2V & VCCP
4) P1.2V_ALW
12
19) KBC3_PWRGD
Sensor
12) VCCP(1.05V)
P1.2V_AUX
10-1) KBC3_VRON
SC415
7-1) P1.2V_AUX
11) P3.3V
SI3456
Sheet 11
Sheet43
13
13) P1.2V_PWRGD
Sheet 43
21-1) PLT3_RSTF#
2-in-1
V5FILT
Controller
6) KBC3_SUSPWRON
11) P3.3V
P5.0V_AUX & P3.3V_AUX
Sheet 28
7) P5.0V_AUX
11) P5.0V
TPS51120
DDR2 POWER
11) 0.9V
11) P0.9V
B
10) KBC3_PWRON
B
(2/2)
7) P3.3V_AUX
SC486
7) MEM1_REF
7) MEM1_REF
DDR2
Sheet39
7
7) P1.8V_AUX
7) P1.8V_AUX
Memory
Sheet 41
11) P3.3V
11
Sheet 17 - 18
7) P5.0V_AUX
AP4435GM
11) P5.0V
11-1) VDD_AUD
Audio
10) KBC3_PWRON
7) P3.3V_AUX
Sheet 43
11) P3.3V
Codec
Sheet 30
P12.0V_ALW
20-1) PEX3_RST#
7-1) P1.2V_LAN
BCP69-16
7) P3.3V_AUX
LOM
11) P3.3V
11) P3.3V
AP6680AGM
Sheet 35
10) PWRON#
Express
88E8039
Sheet 43
7-1) P2.5V_LAN
BCP69-16
Card
7) P3.3V_AUX
Sheet 35
Sheet 35
P12.0V_ALW
11) P1.5V
7) P1.8V_AUX
Sheet 27
21-1) PEX3_RST#
11) P1.8V
AP6680AGM
A
10) PWRON#
A
11) P3.3V
Sheet 43
Mini Card
20-1) PEX3_RST#
WLAN
7) P3.3V_AUX
11) P1.5V
Sheet 29
4
3
2
1
5)KBC3_PWRSW#
22) CPU1_CPURST#
Card 20-1) PEX3_RST# WLAN 7) P3.3V_AUX 11) P1.5V Sheet 29 4 3 2 1 5)KBC3_PWRSW# 22)

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SAMSUNG PROPRIETARY

THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO’S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

D

C

B

A

D

C

B

A

CLK0_HCLK0 CPU CLK0_HCLK0# (YONAH/MEROM) CLK1_AMCLK1 CLK0_HCLK1 CLK0_HCLK1# CLK1_AMCLK1# SODIMM1 CLK1_AMCLK2
CLK0_HCLK0
CPU
CLK0_HCLK0#
(YONAH/MEROM)
CLK1_AMCLK1
CLK0_HCLK1
CLK0_HCLK1#
CLK1_AMCLK1#
SODIMM1
CLK1_AMCLK2
DDR2
CLK1_PCIEICH
CHANNEL A
CLK1_AMCLK2#
CLK1_PCIEICH#
RS600ME
CLK1_BMCLK1
CLK1_NBSRC
CLK1_BMCLK1#
CLK1_NBSRC#
SODIMM2
CLK1_BMCLK2
DDR2
CLK3_NB14M
CLK1_BMCLK2#
CHANNEL B
CLK1_PCIERCLK
CLOCK GENERATOR
CLK1_PCIERCLK#
SPI3_CLK
SPI ROM
ICS951461
CLK3_USB48
SB600
SLG84610
CLK3_PCLKMICOM
MICOM
10MHz
CLK3_ICH14
32.768KHz
25MHz
(FOR RTC)
(FOR SATA)
CLK1_PCIELOM
25MHz
CLK1_PCIELOM#
LAN Controller (88E8039)
CLK1_MINIPCIEA
CLK1_MINIPCIEA#
MINI CARD
CLK1_EXPCARD
CLK1_EXPCARD#
Express CARD
12MHz
2-in-1 (AU6371)
14.318 MHz

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ELECTRONICS
CLK1_EXPCARD CLK1_EXPCARD# Express CARD 12MHz 2-in-1 (AU6371) 14.318 MHz www.vinafix.vn 3 2 SAMSUNG ELECTRONICS 4 1

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4 4

C C

SAMSUNG PROPRIETARY

SAMSUNG PROPRIETARY

D D

C C

THIS DOCUMENT CONTAINS CONFIDENTIAL

THIS DOCUMENT CONTAINS CONFIDENTIAL

PROPRIETARY INFORMATION THAT IS

PROPRIETARY INFORMATION THAT IS

SAMSUNG ELECTRONICS CO’S PROPERTY.

SAMSUNG ELECTRONICS CO’S PROPERTY.

DO DO NOT NOT DISCLOSE DISCLOSE TO TO OR OR DUPLICATE DUPLICATE FOR FOR OTHERS OTHERS

EXCEPT AS AUTHORIZED BY SAMSUNG.

EXCEPT AS AUTHORIZED BY SAMSUNG.

D D

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

PCI Devices

Devices

IDSEL#

REQ/GNT#

Interrupts

USB Hub to PCI LPC bridge/IDE/AC97/SMBUS Internal MAC

AC Link

Voltage Rails

AD30(internal)

AD31(internal)

AD31(internal)

AD31(internal)

-

VDC VCC_CORE Primary DC system power supply (7 to 21V) Core voltage for YONAH (0~1.5V)
VDC
VCC_CORE
Primary DC system power supply (7 to 21V)
Core voltage for YONAH (0~1.5V)
VCCP
YONAH Processor System Bus(PSB) Termination (1.05V)
P0.9V
0.9V switched power rail (off in S3-S5)
P1.2V
1.2V switched power rail (off in S3-S5)
P1.5V
P1.5V_AUX
1.5V switched power rail (off in S3-S5)
1.5V power rail (off in S4-S5)
P1.8V
P1.8V_AUX
1.8V switched power rail (off in S3-S5)
1.8V power rail(off in S4-S5)
P1.8V_ALWS
1.8V power rail (Always On)
P2.5V_LAN
2.5V power rail (off in S4-S5)
MICOM_P3.3V
3.3V always on power rail for MICOM
P3.3V
3.3V switched power rail (off in S3-S5)
P3.3V_AUX
3.3V power rail (off in S4-S5)
P5V
5.0V switched power rail (off in S3-S5)
P5V_AUX
5.0V power rail (off in S4-S5)
P5.0V_ALWS
P12V_ALWS
5.0V power rail (Always On)
12V power rail (Always On)

I 2 C / SMB Address

Devices

Address

Hex

Bus

SB600

SODIMM0

SODIMM1

CK-410 (Clock Generator)

Master

1010

1010

1101

0100

0110

001x

-

A4h

A6h

D2h

USB PORT Assign

PORT NUMBER

ASSIGNED TO

SMBUS Master

-

-

Clock, Unused Clock Output Disable

0

1

4

5

8, 9

Left side USB Port

USB Express Card

2-in-1 Memory Card

Bluetooth Rear side USB Port

System Power States

CHP3_SLPS1*

S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped. The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems. Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected for either Deep Sleep or Deeper Sleep. In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power. S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock.

Externally appears same as S5, but may have different wake events.

CHP3_SLPS3*

CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume.

CHP3_SLPS5*

Crystal / Oscillator

TYPE

FREQUENCY

DEVICE

USAGE

Crystal

Crystal

Crystal

Crystal

Crystal

Crystal

32.768KHz

25MHz

10MHz

14.318MHz

25MHz

12MHz

SB600

SB600

MICOM

CLOCK-Generator

LAN

2-in-1

Real Time Clock SATA

H8S-2110B

CK-410M

LOM

2-in-1 (SD/MMC)

CPU Core Voltage Table

IMVP-6

Active Mode

Active/Deeper Sleep

Dual Mode Region

Deeper Sleep/Extended Deeper Sleep Dual Mode Region

VID(6:0)

Voltage

VID(6:0)

Voltage

VID(6:0)

Voltage

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1 1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1 1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

DPRSLPVR

DPRSTP*

PSI2*

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1 1

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

Active

0

1

0 or 1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

V

1.4250

1.4125 V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

1.3250

1.3125

1.3000

1.2875

1.2750

1.3375

1.3500

V

V

V

V

V

V

1.4375

1.4000

1.3875

1.3750

1.3625

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1 0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1 1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

DPRSLPVR

DPRSTP*

PSI2*

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1 1

0

0

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

0

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Deeper Slp

1

0

0 or 1

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

1 V

0

1

0

0

0

1

0.4875

1 V

0

1

0

0

1

0

0.4750

1 V

0

1

0

0

1

1

0.4625

1 V

0

1

0

1

0

0

0.4500

1 V

0

1

0

1

0

1

0.4375

1 V

0

1

0

1

1

0

0.4250

1 V

0

1

0

1

1

1

0.4125

1 V

0

1

1

0

0

0

0

0.4000

1 V

0

1

1

0

0

1

0.3875

1 V

1 1

V

1 V

0

0

1

1

0

0

1

1

1

0

1

0

0

1

1

0

1

0.3750

0.3625

0.3500

1 V

0

1

1

1

0

1

0.3375

1 V

0

1

1

1

1

0

0.3250

1 V

0

1

1

1

1

1

0.3125

1 V

1

0

0

0

0

0

0.3000

1 V

1

0

0

0

0

1

0.2875

1 V

1

0

0

0

1

0

0.2750

1 V

1

0

0

0

1

1

0.2625

1 V

1

0

0

1

0

0

0.2500

1 V

1

0

0

1

0

1

0.2375

0

1 V

1

0

1

1

0

0.2250

1 V

V

1 1 0

1

1

0

0

0

0

1

1

0

1

0

1

0.2125

0.2000

1 V

1

0

1

0

0

1

0.1875

0

1 V

1

1

0

1

0

0.1750

1 V

1

0

1

0

1

1

0.1625

0

1 V

1

1

1

0

0

0.1500

1 0.1375 V

1

0

1

1

0

1

1 V

1

0

1

1

1

0

0.1250

1 V

1

0

1

1

1

1

0.1125

1

1 V

1

0

0

0

0

0.1000

1 V

1

1

0

0

0

1

0.0875

1 V

1

1

0

0

1

0

0.0750

1 V

1

1

0

0

1

1

0.0625

1 V

1

1

0

1

0

0

0.0500

1 V

1

1

0

1

0

1

0.0375

1 V

1

1

0

1

1

0

0.0250

1 V

V

1 1 1

1 V

1

1

0

1

1

1

1

1

1

0

0

0

1

1

1

1 0

0

0.0125

0.0000

0.0000

1 V

1

1

1

0

1

0

0.0000

1 V

1

1

1

0

1

1

0.0000

1 V

1

1

1

1

0

0

0.0000

1 V

1

1

1

1

0

1

0.0000

1 V

1

1

1

1

1

0

0.0000

1 V

1

1

1

1

1

1

0.0000

*"1111111" : 0V power good asserted.

*Yonah Processor (2.33 GHz / 800 MHz : TBD)

SAMSUNG ELECTRONICS
SAMSUNG
ELECTRONICS

S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.

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3 3

2 2

4 4

1 1

B B

A A

3 3

2 2

1 1

B B

A A

logic required to restart. A full boot is required when waking. www.vinafix.vn 3 3 2 2
logic required to restart. A full boot is required when waking. www.vinafix.vn 3 3 2 2
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P3.3V
BLM18PG181SN1
Pt decoupling CAPS close to Clock Chip power pin
B506
C574
10000nF
P3.3V
D
6.3V
D
P3.3V
B505
BLM18PG181SN1
C572
C586
U8
10000nF
10nF
C587
C589
C588
ICS951461
6.3V
4700nF
100nF
100nF
VCCP
56
50
6.3V
10V
10V
VDDCPU
VDDA
44
49
VDD_SRC1
GNDA
nostuff
28
VDD_SRC2
Route all CLK1 signal as different pair rule
23
58
R59
33
9-D4
VDD_SRC3
CPUT0
CLK0_HCLK0
14
57
R64
33
9-D4
VDD_SRC4
CPUC0
CLK0_HCLK0#
4
54
R63
33
15-B4
VDD_48
CPUT1
CLK0_HCLK1
R905
0
39
53
R36
33
15-B4
CPU1_BSEL0
VDD_ATIG
CPUC1
CLK0_HCLK1#
48-B4
9-C4
7-B1
1
52
VDD_REF
CPUT2
R907
1K
51
CPU1_BSEL1
CPUC2
48-B4
9-C4
7-B1
R906
0
55
47
R34
33
CPU1_BSEL2
GND_CPU
SRCCLKT0
CLK1_PCIEICH
48-B4
9-C4
7-B1
45
46
R33
33
13-B3
GND_SRC1
SRCCLKC0
CLK1_PCIEICH#
nostuff
29
43
R38
33
13-B3
nostuff
GND_SRC2
ATIGCLKT0
CLK1_NBSRC
22
42
R37
33
13-B3
nostuff
GND_SRC3
ATIGCLKC0
CLK1_NBSRC#
15
41
13-B3
GND_SRC4
ATIGCLKT1
7
40
GND_48
ATIGCLKC1
To support Penryn SRR 800MHz (2007.11.21)
38
37
GND_ATIG
ATIGCLKT2
64
36
C
GND_REF
ATIGCLKC2
C
35
ATIGCLKT3
34
ATIGCLKC3
2
30
R42
33
X1
SRCCLKT1
CLK1_PCIELOM
31
R43
33
36-D4
SRCCLKC1
CLK1_PCIELOM#
3
26
R45
33
36-D4
X2
SRCCLKT2
CLK1_MINIPCIEA
27
R44
33
29-C4
SRCCLKC2
CLK1_MINIPCIEA#
24
R568 1M
29-C4
SRCCLKT3
25
SRCCLKC3
20
SRCCLKT4
nostuff
60
21
ITP3_DBRESET#
RESET_IN*
SRCCLKC4
9-B2
20-A4
20-C3
48-D3
8
18
R39
33
CLK3_PWRGD#
VTTPWRGD*_PD
SRCCLKT5
CLK1_PCIERCLK
35-C3
43-C4
48-B4
59
19
R40
33
19-D4
14.31818MHz
CHP3_CPUSTP#
CPU_STOP*
SRCCLKC5
CLK1_PCIERCLK#
19-A4
16
19-D4
SRCCLKT6
17
Y501
SRCCLKC6
12
R67
33
SRCCLKT7
CLK1_EXPCARD
9
13
R41
33
27-C4
SMB3_CLK
SMBCLK
SRCCLKC7
CLK1_EXPCARD#
C54
C53
17-B2
17-B420-A4
20-C3
27-C4
29-C2
29-C2
49-C3
49-C3
10
27-C4
SMB3_DATA
SMBDAT
0.022nF
0.022nF
17-B2
17-B420-A4
20-C3
27-C4
48
6
R66
33
IREF
48MHZ_1
CLK3_USB48
5
48-B4
20-D2
48MHZ_0
R65
0
11
EXP3_CLKREQ#
CLKREQA*
27-C4
48-B4
R28
0
32
63
R62
2.2K
MINIPCIE3_CLKREQ#
CLKREQB*
FSLA_REF0
CPU1_BSEL0
29-C4
48-D1
33
62
R60
2.2K
48-B4
9-C4
7-C4
CLKREQC*
FSLB_REF1
CPU1_BSEL1
61
R61
2.2K
48-B4
9-C4
7-C4
FSLC_REF2
CPU1_BSEL2
48-B4
9-C4
7-C4
R58
33
R35
CLK3_NB14M
R57
33
48-B4
15-B4
475
CLK3_ICH14
B
1%
48-B4
20-C3
B
Compatible Components
Silego : SLG84610
C590
0.022nF
Place all te serias termination resistor as close as Clock Chip as possible
FSA, FSB, FSC of Clock chip are low thershold inputs
FSA
FSB
FSC
Vih_fs_min = 0.7V
HOST CLK
CPU
BSEL0
BSEL1
BSEL2
Vil_fs_max - 0.35V
0
0
0
266
MHz
0
0
1
333
MHz
A
A
0
1
0
200
MHz
0
1
1
400
MHz
SAMSUNG
1
0
0
133
MHz
1
0
1
100
MHz
ELECTRONICS
1
1
0
166
MHz
Merom, Penryn SRR 800MHz
Celeron 533MHz
Merom 667MHz
1
1
1
RSVD
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4
3
2
1
2
1
100nFC575
100nFC576
100nFC571
100nFC573
100nFC577
B504
BLM18PG181SN1
49.9 1%R545
1%49.9R567
1%49.9R546
1%49.9R547
49.9R550
1%
49.9 1%R551
49.9 1%R549
1%49.9R548
49.9 1%R542
49.9 1%R540
1%49.9R541
49.9 1%R543
49.9 1%R544
1%49.9R562
49.9R564
1%
49.9 1%R563
1%R549 1%49.9R548 49.9 1%R542 49.9 1%R540 1%49.9R541 49.9 1%R543 49.9 1%R544 1%49.9R562 49.9R564 1% 49.9 1%R563
1%R549 1%49.9R548 49.9 1%R542 49.9 1%R540 1%49.9R541 49.9 1%R543 49.9 1%R544 1%49.9R562 49.9R564 1% 49.9 1%R563
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
VCCP
D
D
CPU500-1
R169
CPU500-2
MEROM-SOCKET
56
12-D2
1 / 4
MEROM-SOCKET
CPU1_A#(16:3)
J4
H1
48-C4
2 / 4
A3*
ADS*
CPU1_ADS#
CPU1_D#(15:0)
CPU1_D#(47:32)
L5
E2
12-C2
12-D1
E22
Y22
12-D1
A4*
BNR*
CPU1_BNR#
D0*
D32*
L4
G5
48-C4
48-C4
12-C2
F24
AB24
A5*
BPRI*
CPU1_BPRI#
D1*
D33*
K5
12-C2
E26
V24
A6*
D2*
D34*
M3
F1
48-B4
G22
V26
A7*
BR0*
CPU1_BREQ#
D3*
D35*
N2
12-B2
8-B2
F23
V23
A8*
D4*
D36*
J1
H5
48-B4
G25
T22
A9*
DEFER*
CPU1_DEFER#
D5*
D37*
N3
F21
12-C2
E25
U25
A10*
DRDY*
CPU1_DRDY#
D6*
D38*
P5
E1
48-B4
12-C2
E23
U23
A11*
DBSY*
CPU1_DBSY#
D7*
D39*
P2
48-B4
12-C2
K24
Y25
A12*
D8*
D40*
L2
D20
G24
W22
A13*
IERR*
D9*
D41*
P4
B3
48-D4
J24
Y23
A14*
INIT*
CPU1_INIT#
D10*
D42*
P1
19-A4
J23
W24
A15*
D11*
D43*
R1
H4
H22
W25
A16*
LOCK*
CPU1_LOCK#
D12*
D44*
M1
48-D4
12-C2
F26
AA23
CPU1_ADSTB0#
ADSTB0*
D13*
D45*
12-D2
C1
K22
AA24
RESET*
CPU1_CPURST#
D14*
D46*
F3
48-B4
45-C2
48-C4
12-C2
12-B2
H23
AB25
RS0*
CPU1_RS0#
D15*
D47*
12-D2
F4
48-C4
12-B2
J26
Y26
CPU1_A#(33:17)
RS1*
CPU1_RS1#
CPU1_DSTBN0#
DSTBN0*
DSTBN2*
CPU1_DSTBN2#
Y2
G3
48-C4
12-B2
12-D1
H26
AA26
12-B1
A17*
RS2*
CPU1_RS2#
CPU1_DSTBP0#
DSTBP0*
DSTBP2*
CPU1_DSTBP2#
U5
G2
48-C4
12-D1
H25
U22
12-B1
A18*
TRDY*
CPU1_TRDY#
CPU1_DBI0#
DINV0*
DINV2*
CPU1_DBI2#
R3
12-B2
12-D1
12-D112-B1
A19*
CPU1_D#(31:16)
CPU1_D#(63:48)
W6
G6
12-D1
N22
AE24
A20*
HIT*
CPU1_HIT#
D16*
D48*
U4
E4
48-D4
12-B2
K25
AD24
A21*
HITM*
CPU1_HITM#
D17*
D49*
Y5
48-D4
12-B2
P26
AA21
A22*
D18*
D50*
U1
A6
48-C4
R23
AB22
C
A23*
A20M*
CPU1_A20M#
D19*
D51*
C
R4
A5
19-A4
L23
AB21
A24*
FERR*
CPU1_FERR#
D20*
D52*
T5
C4
48-D4
48-D4
19-A4
8-B2
M24
AC26
A25*
IGNNE*
CPU1_IGNNE#
D21*
D53*
T3
19-A4
L22
AD20
A26*
D22*
D54*
W2
D5
M23
AE22
A27*
STPCLK*
CPU1_STPCLK#
D23*
D55*
W5
C6
48-D4
19-A4
P25
AF23
A28*
LINT0
CPU1_INTR
D24*
D56*
Y4
B4
48-D4
19-A4
P23
AC25
A29*
LINT1
CPU1_NMI
D25*
D57*
U2
A3
19-A4
P22
AE21
A30*
SMI*
CPU1_SMI#
D26*
D58*
V4
48-C4
12-D2
19-A4
T24
AD21
A31*
CPU1_REQ#(4:0)
D27*
D59*
W3
K3
R24
AC22
A32*
REQ0*
D28*
D60*
AA4
H2
L25
AD23
A33*
REQ1*
D29*
D61*
AB2
K2
T25
AF22
A34*
REQ2*
D30*
D62*
AA3
J3
N25
AC23
A35*
REQ3*
D31*
D63*
V1
L1
L26
AE25
CPU1_ADSTB1#
ADSTB1*
REQ4*
CPU1_DSTBN1#
DSTBN1*
DSTBN3*
CPU1_DSTBN3#
12-C2
12-C1
M26
AF24
12-A1
CPU1_DSTBP1#
DSTBP1*
DSTBP3*
CPU1_DSTBP3#
12-C1
N24
AC20
12-A1
005344461
CPU1_DBI1#
DINV1*
DINV3*
CPU1_DBI3#
VCCP
12-C1
12-B1
005344461
R148
R149
1K
1K
**NOTE
R147
R146
VCCP
nostuff
1K
1K
B
nostuff
CPU Bracket Hole
B
nostuff
nostuff
Pad for SRI Model
R180
56
48-D4
CPU1_FERR#
19-A4
8-C3
MT503
MT502
RMNT-38-70-1P
RMNT-38-70-1P
R167
200
CPU1_BREQ#
48-B4
12-B2
8-D3
MT500
MT501
RMNT-38-70-1P
RMNT-38-70-1P
A
A
SAMSUNG
ELECTRONICS
4
3
2
1
0
ADDR GROUP 1
ADDR GROUP
ICH
CONTROL
DATA GRP 1
DATA GRP 0
DATA GRP 3
DATA GRP 2

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4

 

3

 

2

 

1

 

SAMSUNG PROPRIETARY

     

THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO’S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

D

 

CPU500-3

 

D

 

CLK0_HCLK0

 

7-D1

A22

A21

MEROM-SOCKET

BCLK0

 

VCCA_1

B26

C26

P1.5V

CPU Core Voltage Table

IMVP-6

 
 

C195

CLK0_HCLK0#

7-C1

BCLK1

H CLK

VCCA_2

C199

10nF

25V

C184

10000nF

6.3V

       

270pF

CPU1_CPUSLP#

   

D7

SLP*

VCCP_1

K6

               
 

nostuff

CPU1_DPSLP#

CPU1_DPRSTP#

CPU1_DPWR#

CPU1_PWRGDCPU

CPU1_PSI#

 

19-C1

19-A4

19-A4

12-B2

19-A4

19-D1

19-D1

48-B4

48-B4

19-D1

48-B4

45-C2

48-D4

B5

E5

D24

D6

AE6

DPSLP*

DPRSTP*

DPWR*

PWRGOOD

PSI*

VCCP_2

VCCP_3

VCCP_4

VCCP_5

VCCP_6

J6

M6

N6

T6

R6

K21

VCCP

 

VID(6:0)

Active Mode

Voltage

Active/Deeper Sleep Dual Mode Region

VID(6:0)

Voltage

 

Deeper Sleep/Extended Deeper Sleep Dual Mode Region

VID(6:0)

Voltage

   
 

CPU1_VID(6:0)

43-B4

43-B4

48-D4

48-C4

 

AE2

AF3

AE3

AF4

AE5

VCCP_7

VCCP_8

VCCP_9

VCCP_10

VCCP_11

J21

M21

N21

T21

R21

 

0

0

0

0

0

0

0

1.5000

V

0

1

0

1

0

0

0

1.0000

V

 

1 V

0

1

0

0

0

1

0.4875

 
 

VCCP

 

VID_6

0

0

0

0

0

0

1

1.4875

V

0

1

0

1

0

0

1

0.9875

V

1 V

0

1

0

0

1

0

0.4750

 

VID_5

0

0

0

0

0

1

0

1.4750

V

0

1

0

1

0

1

0

0.9750

V

1 V

0

1

0

0

1

1

0.4625

VID_4

0

0

0

0

0

1

1

1.4625

V

0

1

0

1

0

1

1

0.9625

V

1 V

0

1

0

1

0

0

0.4500

VID_3

0

0

0

0

1

0

0

1.4500

V

0

1

0

1

1

0

0

0.9500

V

1 V

0

1

0

1

0

1

0.4375

C

 

R168

56

AF5

AD6

VID_2

VID_1

VID_0

3 / 4

VCCP_12

VCCP_13

VCCP_14

V21

W21

V6

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

1

1

1

1

0

1

1

1.4375

1.4250

1.4125

V

V

V

0

0

0

1

1

1

0

0

0

1

1

1

1

1

1

0

1

1

1

1

0

1

1

0.9375

0.9250

0.9125

V

V

V

1 V

0

1

0

1

1

0

0.4250

1 V

0

1

0

1

1

1

0.4125

1 V

0

1

1

0

0

0

0

0.4000

C

   

D21

PROCHOT*

THERMAL

 

VCCP_15

VCCP_16

G21

0

0

0

1

0

0

0

1.4000

V

0

1

1

0

0

0

0

0.9000

V

1 V

0

1

1

0

0

1

0.3875

 

A24

0

0

0

1

0

0

1

1.3875

V

0

1

1

0

0

0

1

0.8875

V

1 V

0

1

1

0

1

0

0.3750

 

CPU2_THERMDA

 

11-C2

11-C2

11-B4

48-C4

48-C4

48-C4

 

B25

C7

THRMDA

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

AC1

AC2

AC4

AD1

AD3

AD4

 

0

0

0

1

0

1

0

1.3750

V

0

1

1

0

0

1

0

0.8750

V

1 V

0

1

1

0

1

1

0.3625

 

VCCP

 

CPU2_THERMDC

THRMDC

0

0

0

1

0

1

1

1.3625

V

0

1

1

0

0

1

1

0.8625

V

1 V

0

1

1

1

0

0

0.3500

CPU1_THRMTRIP#

THERMTRIP*

0

0

0

1

1

0

0

1.3500

V

0

1

1

0

1

0

0

0.8500

V

1 0

0

1

1

1

1