The B0BBand 8086

Microprocessors
and
TheirMemoryand
fnput/OutputInterfaces

INTRODUCTION
Up to thispointin thebook,we havestudiedthe 8088and8086microprocessors fiom a
software pointof view.We havecovered their softwarearchitectufe, instructionset,how
to wdte,execute, anddebug programs in assenbly language, and found thatthe 8088 and
8086were identicalfrom the software point of view. This is no! lrue of the hardware
architectures
of the8088and8086microcomputer systems. Now we beginexamining the
8088 and 8086nicrocomputel from the hardwarc point of view In this chapter,we cover
the 8088/8086\ signal interfaces,memory interfaoes,inputoutput interfaces,and bus
cycles.The chaptersthat fbllow coverotherhardwareand intedacingaspectsof these
Focessors. This chapterincludesthe followingtopics:

8.1 8088and8086Microprocessors
8.2 Minirnum-Mode andMa.{imum-Mode Systems
8.3 Min;rnum-Mode InterfaceSignals
8.4 Maxinum Mode InterfaceSignals
8.5 Elecirical Characteristics
8.6 SystemClock
8.7 Bus CycleandTime States
8.8 Hadware organizarionof ihe Memory Addres$Space
8.9 AddressBus StatusCodes

3t5
 8.10 Memory Control Signals
8-11 ReadandWrite Bus Cycles
8-12 Memory InterfaceCircuiis
8.13 ProgrammableLogic Arrays
8.14 Typesof Input/Output
8.15 IsolatedInput/Outputlnterface
8.16 Input/OutputData Transfers
8.17 lnput/Ou.putInstructions
8.18 Input/OuiputBus Cycles

a 8.1 8088 AND 8086 MTCROPROCESSORS

Tte 8086, amounced in 1978, was tLe filst 16-bit miqoprocessorintroducedby Intel
Corporation.A secondmemberof rhe 8086 family, fte 8088 midoprocessor followed it
in 1979.The 8088 is tuny softwarecompatiblewilh its predecessorthe 8086. The dif-
ferencebetweenthesetwo devicesis in their hardwarearch;tecture.Justlike the 8086.the
8088is intemally a lGbit MPU. However,extemally the 8086 hasa 16-bit databus,and
the 8088 hasan 8-bit databus.This is the key hardwareditrerence.Both deviceshave.he
ability 1oaddressup to lMb)te of nemory via their 20-bit addrcssbuses.Moreover they
can addressup to 64K of b'te-wide irput/output ports.
The 8088 and 8086 are borh manufactued ]usittqhish-petomance metul oide
semiconductor(HMOS) technolog), and the circuitry on their chips is equivalent to
apFoximately 29,0,mtransistors.They arc housedin a 40 pin dual in line package.This
packagecanbe mountedinto a socketthat is solderedto the circuit boardor haveits leads
inserteddrough hole.sin the board and soldered.The signalspinnedoui to eachlead arc
shownin Figs. 8-1(a) and (b), respectively.Many of iheir pins have multiple funclions.
For example,in lhe pin layout diagrarnof the 8088, we see thal addressbus lines A0
drough A? and databus lines Do throughD7 are multiplexed.For this rcason,theseleads
arelabeledADo throughAD?. By nubiplered we meanthat the samephysicalpin canies
an addftss bit at one time and the databit at anothertime.

EMMPLE8.I

At what pin location on the 8088's packageis addressbit A16 output?With what other
signal is it multiplexed?What tunction do€sthis pin serveon the 8086?

Solution
Looking at Fig. 8-1(a), we find that the signal,t16 is l()catedat pin 38 on the 8088 and
that it is multiplexed wirh signal L. Fipre 8 1(b) showsus that pin 38 servesthe same
functions on the 8086.

335 Thea08a and aO86Microprocessors Chao.I

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8,2 MINIMUM-MODE
AND I\,4AXIMUM-MODE
SYSTEMS
Tle 8088and 8086nicroproces
,fiorscan I

lf*i;i.trilT',ffi
t*:tfrHfi,l'd,ils!.;
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sec.8.2 Mjnimum-Mode
an ci MaximumMooesystems
337
 The signalsof the 8088 microprocesr;or commonto both modesof operation,those
uniqueLominimurnmodednddroseuniqu€I to maximummode,are lisLcdnr Figs. 8 2(a).
(b), xnd (c). resp€ctively.
Hefewe lind the name,tunclion, and type lor each signal.For
example, the signalRD is in ihe commong roup. lt tunctionsas a rcxd control ouiput and
is usedlo signalmemoryor I/O deviceswl 1enthe 8088'ssystembusis setup to readin
data. Moreover, note that the signals ho ld reqnest (HOLD) and hold achowledge
(HLDA) a.reproducedonly in the minimun r-modesystern-If the 8088 is set up for mar-
imum mode,they arc replacedby the reque svgrant bus accesscontrol lines RQ/GToand
RQ/GT,.

Mlnim0mmod. riqnalr(MN/MX=
Ve)

HOLD

wn-
IO/M

DT/F-

DEN

sso

INT'A

MN/MX

FD

modesiqnah(MN/fit= GNo)
l\raximum

NMI
LOCK

sr-so
+5V
GND
os1,oso

Fieure 8-2 (a) Signalscormo! ro borh min inun and narinum modcs.(b) Unique
minlnum-modesiendls(c) Ulique maximunj

334 The 808 rg and 8086 Microprocessors Chap. I

 EMMPLE8.2

Which pins provide ditrerentsignalfunctionsin the minimun-mode 8088and rninimun-

node 8086?

Solution
Conparingthe pin layoutsofthe 8088and8086in Fig. 8-i, we find thefbllowing:
1. Pins 2 ihrough 8 on the 8088 are addresslines Ara tbroughAs, but on the 8086 they
are address/dalalines ADia throughADs.
2. Pin 28 on rhe8088i' lhe lO,M ourpu,andon $e 8080iri5 lhe M,4-0ourpur.
3. Pin 31 of rhe8088rs $e SSOouFur.aodon lhe 808brhicpin cupplie.rheBHE/\?
output.

A 8.3 MINIMUM-MODEINTERFACE
SIGNATS

When minimum modeoperationis select€d,the 8088 or 8086 itself plovides a[ rhe con,
aol signalsne€dedto implementthe memory and I/O interfaces.Fignres 8-3(a) and (b)
show block diagramsof a minimum-modeconfigurationof the 8088 and 8086, resp€c-
tively. The minimum-mode signals can be divided into the following basic groups:
address/databus,status,control. intenupt, and DMA.

Address/DataBus
Let us first look at the address/data
bus. In an 8088-basedmicrocomputersysten,
theselines sene two turctions. As n adnrcssbus, they are usedto carry addressinfor
nation to the memory and l/O ports. The addrcssbus is 20 bits long and consistsof sig-
nal lines A0 tbroush Are. Of ihese.Are representsthe MSB and A{r the l-SB. A 20-bit
addressgivesthe 8088 a lMbyte memory addressspace.However.only addressLinesA0
throughAr5 are usedwhen accessingI/O. This givesthe 8088 an independentyO address
spacethat is 64Kbytesin length.
The eight ddta ,rr lines D0 though D? are actually multipiexedwith addresslines
A0 tbroughA7, respectivell For this reason.they are denotedasADo tlrough AD7. Data
LineD7 is the MSB in the byte of data and D0 the LSB. Wben acting as a databus,rhey
carry readwrite data for memory input/output data for l/O devices,and interrupttype
codesfrom an interruptcontroller
Lookine at Fig. 8-3(b), we seethat the 8086 has 16 databus lines insreadof 8 as
in the 8088.Data fines aft rnultiplexedwith addresslines Ao tbroughAr5 and aft there-
tore denotedasADo throughADr5.

5ec. 8.3 Minimum-ModelnterfaceSignals 339

 ADo-AD?.A16/S3-Ao/sa
!trTA
TEST

RES€T

IO/M

HOLD
RO
wB-
DEN

CLK

INTR
aD o-AD,r.A 6/S!-A,r/36
ifTA

NMI
AIE
RESET
BnE/S?
M/Io
DMA HOLD Dl/R
RD
WR
DEN

cL(

(b)

I'tgue E-3 (a) Block diagrm of the minimum'mode 8088 MPU (b) Btock
diagran of the mininum-mode 8086MPU
 s4 5l

0 AlrgrnareG6rariv.
rorheESse!men0
srackterarive
b rness s.qm€.o
Cod.lNonelrelalivslo lhe CS seg
menr or a del.rrr ol z€ro) FigurEE-4 Addre$ bussiarur
DalatGlaliveto lh€ os segm€ )
codas.(Repiint€dwilh pernissionof
I el Corporaliotr,
@ 1979)

Status
Signals
The foul most significantaddresslines,Are drough A16of both the 8088 atrd8086
are also multiplexed,but in lhis casewilh stdt r stgrals 56 through53. Thesestaos bits
are output on the bus at the sametime thal dataare hansfered over the other bus lines.
Bits Saand Sr togetherform a 2 bit binary codethat identifieswhich of the intemal seg-
ment registerswas usedto geneBtethe physical addressthat was output on the addrcss
bus during the cunent bus 'Jycle.The,sefour codesand the regisren they representare
shownin Fig. 8-4. Note that the code SaS3= 00 idenrifieslhe extra segmentrcgister as
the sourceof ihe segmentaddrcss.
Stalusline Sj rcflectsthe statusof anotherinternalchrmcteristicof the MPU- It is the
logic levelof theintemalintempt enableflag.The statusbir 56is alwaysat the0 logic level.

Control Signals

T\e contml siqnals arc ltrovided to suppod the memory and I/O interfacesof the
8088 and 8086. They control functions such as when the bus carries a valid addrcss,
which direcdon data are transferredover lhe bus. when valid write data are on the bus.
andwhen to put readdataon the systembus.For example.addrcsslatch etnble (ALE\ is
a pulse to iogic 1 that siglals extemalcircuitry when a valid addrcssis on the bus.This
addresscan be latchedin extemrl circlitry on the I to 0 edgeofthe pulse at ALE. _
Using the IO/M (lo/nenoO line. D' R (data transmit/receiye\line, and SSO
(statusoutput) line, the 8088 signalswhich type of bus cycle is in progressand in which
directiondataare to be tsansfenedoverthe bus.The logic level of IO/M tells extemalcn-
cuiry wherler a memory or UO trdnsferis taking placeover the bus.lngic 0 at this out-
put signalsa memory operalion,and logic I signals an VO operatioi. The direction of
datatansfer over the busis sienaledby rne logic level ouFut at DT/R- When this line is
logic I during the datatransferpan of a bus cycle, the busis in the transmitmode.There
fore. dataare either written into memory or output to an UO device.On the other halrd.
logic 0 at DT,R signalsthat drc bus is tu the rcceivemode.This conespondsto .eading
datafmm memory or inpur of dataftom an input porl
ComparingFigs. 8 3(a) and 8 3(b), we find two differencesbefv/e€nthe minimum-
mode8088 and 808b microproce,ssors. Fi^L rhe 8086 s memoryno conFotrMI-Or 'isnal
is the complementof the equivalentsignaloflhe 8088.Secondthe 8088\ SSOstatussig-
nal is rcplacedby bdnt /,ish e able (BtE\ M tre 4086.l-ogic 0 on tlis line is usedas a
mernoryenablesignalfof r}le nosr sienmcantb)'te har of the databus, Ds drough Drs.
This line also carriesstatusbit 57.

Sec-8.3 Minimum-ModelntedaceSionals t4l

 The si$als r.€dd(RD) and n/itu (WR) indjcate that a readbuscycle or a write b[s
c)cle. respeclel). i, in progress. The MPU suilchesWR-ro log;c0 ro 5ignalexremal
devicesthat valid write or outputdataare on the bus On the otherhand,RD indicatestl|i
fte MPU is perforning a readof dataoff the bus.During rcad operations,one othercon-
aol signal,DEN (data €r.rbla), is also supplied.It enablesextemaldevicesto supplydaE
to the miuoprocessor.
One other control signalinvolved with the memory and I/O interface,the READY
signal,can be usedto insert wait statesinto the bus cycle so ihat ir is extendedby a num
ber of ciock periods-Th;s signalis providedby way of an extemalclock generatordevice
andcan be suppiiedby tbe memoryor I/O subsystemto signal the MPU whenit is ready
io pemit the datatsansferto be completed.

InterruptSignals
The keyinterrupt interface signals arc intettupt r€q&€rt (INTR) and intenwt
acknowledSe(INTA). INTR is an input to the 8088 and 8086 that can be used by an
externaldeviceto signalthat it needsto be seNiced.This inpur is sampledduring the final
clock period of eachtfftroction acquisition cyck. Logic I at INTR representsan active
interrupt request.Wlrcn the MPU recognizesan interupt request,it indicatesthis fact to
exrematcircuirs with pulsesto logic 0 at the INTA outpur.
The TEST input is also relatedto the exiemal interruptinterface.For example,exe-
culion of a WAIT instructioncausesthe 8088or 8086to checkthe logic level at the TEST
input. If logic I is found at this iDput,the MPU suspendsopention and goesinto what is
known as the idle rtdt?. The MPU no.longerexecutesinstructions;instead,ir repeatediy
checksthe logic level of the TEST input waiting for its transition back to logic 0. As
TEST switchesto 0, executionresumeswith the nexi instruction in the program. This
feanre can be used to synchonize the opemtion of lhe MPU to an eveni in exremal
hardware.
There are fwo more inpuis in the irtenupt inretface: nonnaskable interrupt
(NMl) and,'€rer(RESET).On the 0{o-1 t ansitionof NMI, controlis passedto a ron-
maskableintenupt serv;ceroutineat completionof executionof the currentinstruc,
tion. NMI is the interrupt requestwith highesr pdority and cannot be maskedby soft-
ware.The RESETinput is usedto providea ha.dwareresetfor the MPU. Switchirg
RESETto logic 0 initializesthe intemalregistersof ihe MPU andinitiatesa resetser

DMA InterfaceSignals

T\e diect memory dcc?rr (DMA) inreface of the 8088/8086minimum-mode

microcomputersystem consists of the HOLD and HLDA signals. When an extemal
devicewantsto take control of the systembus, it signalsthis fact io drc MPU by switcb
ing HOLD to the 1 logic level. For €xample,when the tlOLD inpur of the 8088becomes
active, it enten the hold state at the completion of the cnrrent bus cycle. When in the
hold state,signallinesADo throughAD7.As tbroughAr5,A16/5rthroughArr/56,SSO,

342 The 8088 and 8086 MicroDrccessofs ChaD.8

 IOA4. DT/R, RD, WR, DEN, and INTR are all put into tlle high-Z state.The 8088 sig-
nals exremaldevices.hat it is in this stateby switching its HLDA output to the I logic
level.

8.4 MAXIMUM-MODEINTERFACE
SIGNAIS

Wlen the 8088 or 8086 microprocessoris set for the maximum-modeconfigfation, it

producessignalsfor implelnentlng^ nuhprccessor/coptuc.ssorslstem enrimnment-By
nulnprccessot eNionnen. we mean that multiple microprocessorsexist in the system
and that eachprocessorexecutesits own proglam. Usually in this t)?e of systemenvi-
ronment, some systemresouces arc commonto all processors.They are caled gldb"l
Effu'.er. There are also other resomcesthat are assignedto specitrcpmcessors.These
dedicatedresourcesare kt(t\\rn as local or pilate resources-
rn the maximun-mode system,facilities are provided for inplementing allocation
of global resourcesand passingbus conFol to other microprocessorssharingthe systen

8288 BusController;BusCommandsand ControlSignals

Looking at &e maximum-modeblock diasramin Fig. 8-5(a), we seethat the 8088
doesnot directly provide all the s+nak rnat arerequnedto control ft€ memory I/O, and
intenupt inlerfaces.Specifically, the WR, IO/M, DT/R, DEN, ALE, and INTA signals
are no_longerproducedby the 8088. Instead,it outputs a statuscode on three signals
lines. S0.Sr, and S,, prior to the inidation of eachbus cycle. This 3 bit b!..rrtdt r co./e
identifieswhichtype ofbus cycleis to follow. SrSrS0areinput to the extemai,rs cor-
trollel device,the 8288, which decodesthen to ideniry fte type of MPU bus cycle. The
block diagramandpin Iayoutoflhe 8288 are shownin Figs- 8 6(a) and (b), respectively.
In response.the bus controller generatesthe appropriatelytimed commandand control
sisnals.
Figure 8-7 showsthe relationshipbetweenthe busstatuscodesandthe typesof bus
cycles.Also shown are the output signalsgeneratedto tefl extemal cncuitry which type
of bus cycle is taking place.Theseoutput signalsare neDory read comtnnd (MRDC),
nenorJ x)rik comnandO,tw'lc), adrancednenory wik convand (t\MwC\. I/O read
comand IORC), I/O wfte conafund (rOwC), advared xO wntu conoMnn (NOWC),
audinterrupt acknowledqe(INf A).
The 8288 producesone or two of rhesesevetrconunandsignalsfor eachbus cycle.
For instance,when the 8088 outputsthe code SrSrS0: 001, it indicatesthat an I/O read
cycle is to be perfonned.In turn, the 8288 makesits IORC output switch to logic 0. On
the orherhand,if the code 1I I is outputby fte 8088,it is signalingtlat no bus activiry is
to takeplaceithe 8288produces no commandsignals.
The other contol outputsproducedby the 8288 consi:rtof DEN, DT,R, and ALE.
Thesettuee signalsprovidedle sane tunctionsasthosedessibed for the minimum mode.
Figure 8-5(b) showsthat the 8288 bus corto er conne€tsto the 8086 in the sameway
as the 8088,and it also producesthe sameoutput signals.

Sec 8.4 InterfaceSrgnals

fMaxrmumMocle 343
 M36a
M'E
t'
ozee
ar.
EEd
otN @d
DT/i AIOWC-
tnra
MCE/FEEfr

DT/R-
DEN

ADo-AO?,
Ar.A,-A01S.

R6

-- -- Lo6lbu.
FO/Glr RO/Glo 6nrol
(a'

FtguE 8-5 (a) 8088nardmuxn-node

blockdiagram.(b) 8086rnerimum-mode
block

EMMPLE8.3
ff the bus statrs codeSrSlS0equals101,what g?e of bus activity is taking plac€?Wlich
conmand ouFut is Fodrced by the 8288?

Solution
Lookingat thetablein Fig.8 Z we seethatbusstatuscode101identifies
a readmemory
bnscycleandcauses theMRDCoutputof thebuscontrollelto be switchedto logic 0.

344 The8088 and a0a6 Microorocessofs Chao.I

 AIN

MRD'
MlrTC
s. 3233 ^Mra
io-Rc-
'o-*:c
RESET AIOWC
iMI
MCE/FDEN

DT/i

a-ft
BHE

RD

EoicT, Ra/cL
(b)

FigurEE-s (cortinued)

Lock Signal

To implement a multiprocessorsystem,a signal called lock (LOCK) is provided

on the 8088and 8086.This signalis meantto be output(logic0) wheneverthe ploces-
sor wants io lock ont the other processon from using the bus. This would be the case
when a sharedresourceis accessed.The LOCK signal is compatiblewith the Mrltibrr,
an industry standard for interfacing microprocessor systems in a multiprocessor

sec 8.4 Maximum-lvlode

lnterfaceSrgnals 345
 -'l.

o-id

iFiI n a

iit
la -iE
i6ta
fiic
6i-4

tbt

Figure 8-6 (.) Blocl diagrM of the 82E8.lReprjited tith permisjon of

E 1919)(b) Pin layout.(Rcprhtedwnh pemissionof htcl
lnLelCorporation,
O i979)
Corporation.

OueueStatus
Signals
Two orhersignalsproducedby the 8088and 8086.in the naxinum-modemicro
computersysrem,are queuestatusoutputsQSoand QSr tharfon ^2bjt queuestatus
.,1e, QSlQSo.This code tells lhe extemalcircuitry whal type of informationwas
rcmovedtiom the inltructionqueneduringthe previousclockcycle.Figure8 8 shows
thefour dillerentqueuesiatuscodes.Note tharQSlQSo= 0l indicatesthatthe first byte
of an insfirctioD was taken off the queue.As shown. the feich of the Dextbyte of lhe
instmclionis identiliedby the codeil. Whenevefthe queueis reseldueto a t|,tnsferof
codc10 is ouiput.
control,|hereiniiialization

CPUCycle E2!6Comm.nrl
s2 s1 s0
0 0 Inlerupt Acknowledge
0 1 -----to--o
s9-
0 0
0 1 Hall
0 M_RDC
I lvlFDC
0 frfrJaA-Mwc
1 1

Figure8-7 Bus staiuscodes.(Repnnbdwnh permisior of l.rel CoiPoratiotr.

O 1979)

t46 The 8088 and 8086 Mjcroprocessors Chap I

 os1 osn OuaueSlrlur

0 No Operalion. Ourin! lhs

clock cycl€, nolhing was

0 Firsl Syle.The bylstakan lrom lhe

qleue wss the lirsl byle ol the

1(high) 0 Ou€ue Emply.The queue has

be€nreinilisliredasa rssultollhe
sreculionol a transferinslruction.

l Subssqusnl Byte.Thebytelaken
Iromths queuewasa subsequ€nl figure 8-8 Queuestatuscodes.
byleol theinslrucllon. (Reprintedlith pernisslon of lntel
Corporanon,
O 1979)

LocalBusControlSignals

In a maximum mode configuration,the minimum-modeHOLD and HLDA inter-

face of the 8088/8086is also changed.Thesetwo signalsarc rcplacedby requen/qrunt
l,r€r RQ/CToand RQ/GTj. They provide a prioritized bus accessmechanismfor access-
ing the local bus.

CHAMCTERISTICS
8.5 ELECTRICAL

ln the precedingsections,the pin layout and minimum- and maxinum-mode interface

signalsof the 8088 and 8086 microprocessorswere intoduced. Herc we will firsl look at
the power supply ratings of theseprocessorsand then their input and output electricel
characteristics.
Looking at Fig. 8 l(a), we find that poweris appliedbetweenpin 40 (V".) andpins
I(GND) and 20(GND). Pins I and 20 should be connectedtogether.The nominal value
of V.. is specifiedas +5 V dc with a toleranceof =10EoThis ineansthatthe 8088or
8086 will operateconectly as long as the ditrerencein voltagebetweenV"" and GND is
greaterthan4-5V dc andlessthan5.5V dc.At roomtemperature (25oC),bothtbe 8088
and 8086 draw a maximum of 340 mA from the supply.
Let us now look at the dc yO characteristicsof ihe microprocessor-that is. its
input and output logic levels.Theseratingstell the minimun and ma{imum vollagestor
the 0 and I logic statesfor which the circuit witl opente corectly Different valuesare
speciliedfor the inputs atd outputs.
Figure 8-9 showsthe I/O voliage specificationsfor the 8088 Notice thal the min-
imumlogic I (highlevel)voltageai an ouQut(VoH)js 2.4V This voltageis speciliedfor
a test condition thai identifiesthe arnountof currentbeing sourcedby the ou@ut(IoJ as
-,100 pA. Al1 processorsmust be tesledduring manufacturingto ensurethat under ths
lest condition the vollagesat all outputswill remain abovethe value of VoH-i"

sec.8.5 ElectricalCharacteristics 347

 +2.0v v.. + 0.5v

+2,4V
Figure 8-9 I/O voltagelevels.

lnput voltagelevels are specifiedin a similar way; exceptherethe raringsidentify

the rangeof voltagethat will be correctly identified as a logic 0 or a logic 1 a1an input.
For inslance,voltagesin therangeVn = -0.5 V to VL,,"* = +0.8 V represent a vilid
",i.
logic 0 (lowerlevel)dt an inputofthe 8088.
The I/O voltage levels of the 8086 microprocessorare identicai to ihose for ihe
8088asshownin Fig. 8-9. However, thercis onedifference in theiestconditions.For the
8086,VoL is measuedat 2.5 mA insteadof 2,0mA,

A 8,6 SYSTEM
CLOCK
The dme basefor synchronizationof the internal and extemal operationsof the micro-
pro.essorin a microcompuiersystemis providedby the cl.rc* (CLK) input signal,At pfe-
sent,the 8088 is availablein two different speeds.Tbe standardpan op€rutesot 5 MHz and
the8088-2operales at 8 MHz.On theolberhand,the8086microprocessor is manufactuled
in threesp€edsr the s-MHz 8086,the 8-MHz 8086-2,anddle lo-MHz 8086-1.The 8284
clockgenerator anddriverIC generate$ CLK, Figul€8-I0 is a blockdiagramofthis device.

Iigu.e 8-10 Block diagam of the 8284clock generator(Repnntedwilh peF

misslonof Intel Corporation.@ 1979)

348 The8088 and 8086 Microorocessors chao-8

 - CLK

Ftd IigN E-ll Connetingthe8284lo

the 8088. (Reprintedwith penission
of lntei Cor?oration.@ 1979)

The standardway in which this clock chip is usedwith the 8088is to connecteither
a 15- or 24-MHz crystal betweenits Xr and X2 inputs.This circuir connecrionis shown
in Fig. 8 11.Note that a seriescapacitorCL is also required.trs lpical value when used
with the 15-MHz crystal is 12 pF The funnanental crystal frcquerry is divided by 3
within tbe 8284 to give either a 5- or 8-MHz clock signal. This signal is internally
bufferedandoutput at CLK. The CLK outputof the 8284canbe dnectly connectedto the
CLK input of the 8088.The 8284 connectsto the 8086 in exacdythe sameway.
Figure 8-12 showsthe wavefom of CLK. Here we seethat the signal is specified
at metal onde semiconductorO4os)-compatiblevoltagelevels andnoi transistortransis-
ior logic (TTL) levels.Its minimu.n and maximun low logic levels a.e VLdi : -0.5 V
andVlda = 0.6 Y respectively.Moreover the minimum and marimum high logic levels
areVs-i" = 3.9 V andVHms : Ve + 1 Y respectively.Thepetrd of the clo€k signalof
a 5 MHz 8088 can rangefroln a nininum of 200 ns to a mrximum of 500 ns, and the
maxilj.u.mrise andfatl tines of its edgesequal 10 ns.
Figure 8-10 shows two morc clock outputs on the 8284i tte peripheml cLock
(PCLK) and oscilLdtorclo.* (OSC).Thesesignalsare provided to drive peripheraiICs.
The clock signal output at PCLK is half the frequencyof CLK. For instance,if an 8088
is operatedat 5 MHz, PCLK is 2.5 MHz. Also, it is at TTl-compatible levelsratherthan
MOS levels.On dre otherhand,the OSC output is at the crystal frequency,which is thre€
times that of CLK. Figure 8-13 illustratestheserelationships.
T]le 8284 can also be driven from an extemalclock sourcejhe extemalclock sig-
nal is applied to ihe exiemal frequencyinput (EFI). Input F/C is provided for clock
sourceselection.Wlen it is strappedto the 0 Iogic level, the crystal betweenXr and X,
is used.On the otherhand.applyins logic I to F/C selectsEFI as the sourceof the clock.
The clock sync (CSYNC) input can be usedfor extemalsynchronizationin systemsthat
employ multiple clocks.

Figue E-12 CLK voltageand

timing chdacteristicsfor a 5-MHz
processor(Reprintedwilh permissjon
of Intel Corpontion, O 1979)

s e c . 8 - 6 SystemClock 341)
 Figure 8-13 RelationshjpbelweenCLK and PCLK. (Reprintedwith pennis-
sion of lntel Coryonrlon, O I 979)

EMMPLE8,4
If theCLK inputofan 8086MPU is to be ddvenby 4 9-MHz signat,wha!speedversion
of the 8086mustbe usedandwhatfrequency crystalmustbe attnchedto the 8284?

Solution
The 8086-l is the versionof the 8086that canbe run at 9 MHz. To createrhe 9-MHz
clock,a 27-MHzcrystalmustb€ usedon the 8284,

A 8,7 BUSCYCLE
AND TIMESTATES
A Dlli c)cb definesth€ basicopemlionthat a microproces$or pertbrmsto communicate
with externaldevices,Examplesof bus cyclesare the memorylead, Demoly write,
input/outputread,and inpuvoutputwrite.As shownin Fig. 8-14(a),a buscycleco e-
spondsto a sequence of eventsthatstall with an address beingoutputon the systembos
followedby a reador write datatransferDuringtheseoperations, the MpU produces a
seriesof controlsigralsto conlrolrhedirectionandtinringof thebus.
The buscycleof the 8088and8086microprocessors consistsof at leastfour clock
p€riods.Thesefour time statesarecalledT , T2,Tj, rnd Td.DuringTr, theMpU puB an
addrcss on the bus,For a write memorycycle,dataareput on thebusduringstateT, and
maintained throughT3 andTa.Whena readcycleis ro be pedomed,the b s is first pur
in the high-ZstateduringT, and thenihe datato be readmusrbe availableon the bus
dudngT1 andTa. ThesefoLrrclock staLes gi\e a bus .jlle durationof 125ns X 4 =
500ns in an 8-MHz 8088system.
If no bus cyclesare reqxired,the microFocessorperforns whal are knowr as td?
rrat€r. During thesestates,no bus activiry takesplace.Eachidle staGis one clock period
long,andanynumberol themcanbe inserredberween buscyctes.Figure8-14(b)shows
two buscyclesseparatedby idle states.Idle staresare perfomed if the insrructionqueue
in.idelhe nicroproce*,'r i. tLll dnd ir aoe.nor neea,o'e,,dor wrireoperrnd.from

Waitnoks .al also be insededinto a bus c),cle.This is donein response ro a

requestby an eventin extemalhardwareinsteadof an internal evenrsuchas a full queue.

350 The 8088 rnd 8086 MrLroproce\o.\ Chdp. 8

 -"-r"t"t"-]*"--l
*-ru
tl
--___________x__]@-
JL J _""r","."".
"."."*,*....- *'
J 1-;';y;,".pgi**
FisuE E-r4 (a) Bus cycle ctock periods.(Reprinkn wirh lemisior of Inlel
Corporation,O 1979) (b) Bus cycle with idle states.(Retrtured with pemis-
siotr of Iltel Corporaliorr O 1979) (c) Bus cycle with wait states.(Reprinted
wirh pemi$ion of Intel CorpoEtion, O 19?9)

ln fact, the READY input of the MPU is Fovided spe.ificaly for rhis pupose. Figwe
8 14(c) showsthat logic 0 at this input indicatesthar tlle cuneni bus cycle shouldnot be
completed.As long as READY is held at the 0 leve], wait statesare inserredberween
statesT3 andTa of the curent bus cycle, and the dararhar were or the bus during T3 are
maintained.The bus cycle is not completeduntil rhe extemalhardwarereturnsREADY
back to the 1 logic level. This extendsthe duration of the bus cycle, therebypermitring
the use of slower memory and I/O devicesin the system.

EMMPLE8.5
What is the duration of the bus cycle in the 8088-basedmicrocomputerif the clock is
8 MIIZ and two wait statesare iDserted?

Solution
The duration of the bus cycle in an s-MHz systemis give, in generalby

ty.=500ns+Nx125ns

5 e c .8 . 7 BusCycleand llme States 35t

 In this expressionN standsfor the numberof wait states.For a bus cycle wirh two wair

t y"= 500rs+ 2 x 125ns = 500ns+ 250ns

= 750ns

8.8 HARDWAREORGANIZATIONOF THE MEMORY

ADDRESSSPACE

From a hardwarepoint of view.the memory addressspacesof the 8088 and 8086-based

microcomputersare organizedditrerently.Figure 8-i5(a) showsrhat the 8088'smemory
subsystemis irnplementedas a single 1M X 8 memory bank. Looking ar &e block dia
gram in Fig. 8-15(a), we seethat thesebyte-wide storagelocationsare assignedlo con-
secutiveaddressesover the rangefrom 0000016throughFFFFFT6.During rnemoryoper-
ations,a 20,bit ad&essis appliedto the memorybank over addresslines Ao ttuoughA,,
It is this adahess
that selecrsthe storagelocation thar is to be a.cessed.Bltes of dataare
trdnsferredbeiweenihe 8088 and memory over databus lines Do throughD7.
On the other hand, the 8086's lMbyte memory addressspace,as shown in Fis.
8 l5(b), is implenented as rwo independenr512Kbyte banks: the torr (et)en)bank and
6e high (odd) bank Data.bltes associatedwith an evenaddress(0000016,0000216.etc.)
residein thelow bant, andthosewith oddaddresses (0000116, 0000316,
etc.)residein rhe
hish bank.

.]IMSYTES 5 1 2 tl Y t E s srrEs
t12r(

2 !
i

(b)

Fisur€ 8-15 (a) lM x 8 hemory bank of rhe 8088. (b) Hish and low
memory banks of tle 8086. (Reprintedwirh permision of Intel Corporation,
o 1979)

352 The4088 and 8086 Microorocessors ChaD.8

 The diagramin Fig. 8 l5(b) showsthat for the 8086 ad&essbits, A1 throughAre
selectthe storagelocation that is to be accessed.They are appliedto both banksin paral-
lel. A0 and bank high enable(BHE) are usedas bank-selectsignals.lngic 0 at A$ idenn-
fies an even-addressed byte of dataandcausesthe low bant of memoryto be enabled.On
the othgi hand,BHE equalto 0 enablesthe high bank to accessan odd'adahessed byte of
data. Eachof the memorybanl6 provideshalf of the 8086's 16-bi! databus. Notic€ that
the lower bank transfersbytes of dataover datalines Do throughD7,while datatransfers
for a high bant(useDs throughD,5.
We iust saw that the memory subsystemof the 8088-basedmicrccomputersystem
is actuallyorganizedas 8_bitbytes,not as 16-bit words However'the contentsof any two
consecutivebyte storagetocationscan be accessedas a word The lower-addressed b)4e
byte is its most signifi-
is the least significantbyte of the word. and the higher-addressed
capt byte- I€t us now look at how a b)4e and a wod of dataare readfrom memory.
Figure 8-16(a) showshow a byte-memoryoperationis perfomEd to the storage
Iocation at addrcssX. As shown in the diagram,the adahessis suppliedlo the memory

(x+1t

Figue E-16 (a) B}'te trdsfer bY the

(b1 8088. (b) word tmsfer by the 8088

Sec-8.8 Space
HardwarcOrganjzationof the MemoryAddress 35
 bank over lines A0 throughAre, and the byre of datais wrilten into or read from storage
locarion X orerline.Do-hrough D-. D cdJries rhe\4SBo, rheoyteotdara.dnd D0c;-
riestheLSB. This showsthara byteof datais accessed by rhe 8088jn onebuscvcle.A
memorycJ(le lor an F088rLrnning ar 5 MH,, w t- no $aiL.rare.rate. 800n..
When a word of data is ro be transfer"edberweenrhe 8088 and mernorv.we must
Derformrso acce$e.ofremor). readjogor sriling a bytFin eacnacce-. Figure8 r6lbl
illustates how the word storagelocarionstartingal addressX is accessed. Two bus cycles
are requred ro accessa word of data.During the fusr bus cycle, the leastsignificanrbyte
of the word, locatedat addressX. is accessed. Again the addressis appliedro the mem
oD banxoverA. lhroughAro.and.heb)reot datai. Fan.feredto o, irolnuo"g.'o.u.
tron X over Do tbroughD?.
Next, the 8088 automaticallyincrementsrhe addressso rhat it now points to bvte
dddre$X + L hi. addre$poin..lo lhene\rcon.ecutive b)re.lorage tocalionin men
ory, which conespondsro the most significantbyte of the word of daraat X. Now a sec-
ond memory buscycle is initiated. Durirg rhis secondcycte,daraare writren inro or read
l?om the storagelocation at addressX + 1. Sinceword accesses of memorytake two bus
cyclesinsteadof one,it takes1.6ms to access a word of datawhenthe 80S8is oDerarins
dr r 5 MH,, cloc,(ralew h ao wail !!ares.
The 8086 .nicroprocessorperforms byte and word data transfe$ differently from
the 8088.Lel us next examinethe daratransfersthar can take placein an 8086-based

Fignre 8 17(a)showsthat whena byte-memoryoperarionis pedorhed ro addressX,

an even-addrcssed storagelocarion in dle low bank is accessed.Therefbre.A" is sei ro
.ogic0 ro enJblerhe lo$ bant of nemoD drd BHE-lo togrc I ru di.abrernehrshbao*.
45 \houn ia rheblockdiJgran.d d arenan.renedro or rromrhe toser bdnl ;\ er ddrd
buslinesD0tbroughD?.Line D? carriesrheMSB of thebyte,andDo rheLSB.
On the other hand.to accessa byte of dataat an odd addresssuchas X + I in Fig.
8 l7,br.q0 r".el lo log,cI andBHFro logic0. Thi. enable,rnehighbanxof memor)
and disablesthe low bank. Daia are transfered betweenrhe 8086 dnd the hish bant over
Du,rine(DsdTough D.. He? Dr, repre.enrr rheMSB andDRrheLSB.
Wheneveran even,addressed word of datais accessed,both the high andtow banks
areaccessed at the sametime.Figure8-17(c)iltusrraies how a wordar evenaddress X is
accessed.Nole that both A0 and BHE equat0; therefore,both bants are enabled.In rhis
case,bytes of data are ransfefed from or to borh banks at rhe samerime. This l6_bit
word is aansfeffed over the comp]etedata bus Do through Dr5. The byres of an even_
addressedword are said io be aligned and can be rransfenedwith a memorv oDeration
_ndlale\,rst onebuscycte.
A word at an odd-addressed boundaryis said to be unaligned.That is, the leastsig_
nificanl byte is at the lower addresslocation in rhe high memory bank. This is demon-
stratedin Fig. 8 17(d).Here we seethat the odd byte of the word is locaied ar ad&ess
X + I andthe evenbyreat address X + 2.
Two buscyclesarerequiredto accessan unalignedword. Dwing the first buscycle,
theoddbyteof ihe word,whichis locaredaraddrcss X + 1 in thehish bank.is accessed.
Pr'. h rccompan'eJ b) \etecr.ignaloAo- t andBtU - 0 anda Jararan,reroverD"
throughDr5. Even thoughrhe datatransferusesdatatines Ds throughDr5, to the proces"
,or ;_i. thelow b\te of lhedddre,,ed oard$uro

354 The 8088 dna 8086 V.(rop.o.es\or5 Chap. 8

 (d)

Figue 8-17 (a) Even-address byte transfd by the 8086.(Reprlnredwith per

nision of Intei Corporariotr,O 1979) (b) Odd'addres byte tmsfer by ihe
8086. (Reprinted with permision of Inte] Corloetion. O 1979) (c) Even
addres word transferby the 8086.(Reprintedwith permision of Iniel Corlo-
ration, O i979) (d) Odd addres wod iransfer by ihe 8086. (Reprhted wilh
pemission of Int€l Cor?oration.O 1979)

355
 Next, the 8086 auromaricallyincrementsthe addressso tharA. = 0. This reDresenrs
lhe nerl addreq,in memoryuhich ,s eren.Thena \econdmemon bu. c\cte L iniridred.
Duringrhi,,econdclcle.rhee\enb)re localed ar X - 2 in rheto\ banl is acces,ed.
The datatransfertakesplace over,buslines D0 throughD7. Tbis tansfer is accomDanie.d
b)& 0and BHE - l. lo rheproce.soj. dri, ie rhehighblreofrheuordol daia.

EMMPLE 8.6

Is theword at memoryaddress
0123116 of an 8086basedmicrocompureratignedor mis
aligned?How manybus cyclesare requiredto read it ftom memory?

Solution
The first byte of the word is rhe secondbyre ar the aligned-wordaddress0123016.There_
fore, the word is misalignedand requirestwo bus cyclesto be read from memory

8.9 ADDRESSBUS STATUS

CODES
Whenevera memory bus cycle is in plogress,an addressbus statuscode S,S. is outDut
b) rl'eprccessor The5rdru,coders n utripte\ed wirhaodre..birsAr- andqr".'ftr. ruo.
bit codeis outpur aathe samerime the daraare caded ov€r the daralines.
Bits Sr and53 togetherfom a 2,bir binary codethar idenrilieswhich one of the four
segmentregrters was used to generaterhe physical addressthar was oumur duinq ihe
addresrperiodin rhecurrenrbur c)cle. The tow add,"ssbut snru,,oae, are lisreain
Fig. 8-4. Here we find thar codeSaSr= 00 idenrifiesthe exrrasegmenrregister 01 ide.r
tifies the stacksegmentregister,l0 identifies the code sesmentregisret and 11 identifies
the datasegrnentregisrer
Thesestatuscodesare ourput in both the minimum and rhe maximum modes.The
codes can be examinedby external circuifty. For example,they can be decodedwith
extemal circuirry ro enableseparatetMbyte adatressspacesfbr ES, SS, CS, and DS. In
this way, the menory addressreachof the microprocessorcan be expandedto 4Mbytes.

8.I O MEMORYCONTROLSIGNATS

Earlier in the chaprerwe saw rhat similar control signatsare producedin rhe maximum
andminimum mode.Moreover,we found ihat in rhe ninimum mode,the 8088 and 8086
microprocessonproduceall the conrrotsignals.But in the maximum mode,the g288 bus
contoller producesthem. Here we wiil look morc closely ar each of thesesisnais and
rbeirtunctjonsu irh re,pecrlo memoryinlerfaceoperdrion.

Minimum-Mode
MemoryControlSignals
In the 8088 rnicrocompurersysrernshown in Fig. 8_18, which is configurealfor
Lheminimummodeotoperarion. $e tindlhartheconnotsrgnat( prorjdedro.upDonrhe
inrerfacero rhe memory\ub\ysremare ALL, tOA4, Dt/R, RLi. WR. arl nf|,r. T|*"

356 The80aa and 8086 Microprocessors Chap.I

 8@8

Io/i

DEN

sso

Figure8-18 Mininun-no.le 8088remory hterface.

control signalsarerequiredto tefl the memorysubsysiemwhen the bus is carrying a va]id

address,in which dircction dataarc to be tansfen€d over the bus, when valid write data
are on the bus,and when to pur read dataon the bus.Fot example,ad.dresslatch enable
(ALE) signalsextemal circuit y that a valid addressis on the bus. It is a pnlse to the I
logic level alrd is usedto latch the addressin extemalcircuitry.
T\e input-ouput/memory AO/ll{) and d^ta tnnsmit/rece e (DT/R) lines signal
extemalcircuitry whethera menory or I/O buscycle is itr progressand whetherthe 8088
will transmit or receivedataover the bus-Dudng all memory bus cycles,IO/M is held at
the 0 logic level. The 8088 switchesDT/R to Iogic I during the datatransferpart of the
buscycle, the bus is in the transmitmode,anddataare written into memory On the oaher
hand, it setsDT,.Rto logic 0 to signal that the bus is in the rcceive mode, which corle-
spondsto readingof memiry.
The signarsr"d/ (RD) and lrn& (WR) identit that a read or write bus cycle,
respectively,is in progess. The 8088 switchesWR to logic 0 to signal memory that a
write cycle is taking place over the bus. On the other hand, RD is svritchedto logic 0
whenevera read cycle is in progess. During a[ memory operations,the 8088 produces
one other control signal, ddta enable@El0.l.og:,c O at &is outPutis usedto enablethe
databus.
Slrtus l;n" SSOis alsopart ofthe minimum-modememoryinterface.The logic level
tbat outputon this line during Iead buscyclesidentfies whethera codeor dataaccessis
is
in progress.SSOis setto logic 0 wheneverinstmctioncodeis readfrom memory
The contol signalsfor the 8086'smidmum-node memoryinterfacediffer in three
ways.First, the 8088's IO/M signal is replacedby the m€mory/input-output(M/IO) sig-
nal. Whenevera memorybuscycle is in plogress,ihe M/IO output is switchedto logic 1.
Second,the si$al SSO is removedfiom the interface.Thftd. a new signal, ,anft tlgll
enable(BHE), hasbeen addedto the interface.BHE is usedas a selectinput for the high
bant of memory in the 8086'smemory subsystem-That is, logic 0 is output on this line

Sec.LI0 MemoryControlSignals 357

during the ad&esspart of all rhe bus cyclesin which darai, the hish-bank Darrof mem
ory is to be accessed.

Maximum-Mode
MemoryControlSignals
W}len the 8088 is conligured to work in rhe maximum mode. it does nor diectlv
pro\ideall rl.econtrol.ignal( ro supponrhe memor)inrerface. Incread.an exremalbu'
controllet the 8288,providesmemoryconmandsandcontol signats.Figure 8 19 shows
an 8088connected in thiswav
Specificalt).rhe WR. tOA4. DT,R.bLN. ALE. andSSOrignat rine.on rhe8088
are Lhanget.The) dre replacedvirh nultiproce\\ot /or* rlOCKr signat.a b,l \rdrar
!94e (SrS1SJ,anda 4rar? rrarrr cod?(QSreS0).The 8088stitl doesproducerbesisnal
RD.whichprovides lhe.amelJnclionasil did in minimummode
The 3-bil busstatuscodeqS,Sn is nutputprior to the iritiation of eacbbuscycle.
It identjfieswhichlype ofbus cycleis to follow This codeis inputto the g2ggbuscon_
troller Here it is decodedto identify which type of bus cycle commandsignalsmust be
generaled,
Figure8-20 showsthe relationship belweenthe busstatuscodesandthe typesof
buscyclesproduced, Also shownin this chartare the namesof the co$esDondins com-
mandsignalsrharare generaedar the ourputsof the 8288.For instance,rhe inprircode
S:SrSoequalto 100fldicaresrhatan inerruction ferchbuscycleis ro takeplace.Sincefie
insructionferchis a memoryread.lhe 8288makesthenenory readconnand (fr-RDC1
outputswitchto logic0.
Anorherbuscommandprovrdedtbr thememorysubsystem is SrSl56equalro I J0.
This represents a memorywrite cycleand it causesboth the memorywrite conmand

8288

Figure E-19 Mdimun-mod€ 8088menory interface.

358 The8088 and 8086 Microprocessors Chap. 8

 s! sr
iflrA
0 I toRc
0 rovc-,A-i6Fa
I
MRDC
I MIDc
Mwlt. AMwc

Figure 8-20 Memory bus cycle stalus codesp.oduc€d in ffiimum mode.

(Reprintedwith pemission of lntel Corporation,@ 1979)

(MWTC) and advancedmenary \rfte command(|\NN{C) outputs to slvitch to the 0

logicle\e'.
The other control oulputs producedby the 8288 arc DEN, DT,/R.andAlE These
signalsprovidethe sane tunctionsasthoseprcducedby dle conespondingpins on the 8088
in the minimun systemmode.
The two statussignals.QSoand QSr, lorm an instruction queuecode This code
tells the exlernalcircuitry what type of infomation was removedfrom the queueduring
the previousclock cycle. Figure 8-8 sholvsthe four diffetent queuestatuses-For instance'
QSTQSo = Ol indicatesthat the lirst byte of an instructionwas ta.kenfrom the qneue The
nextbyte of the instructionthat is letchedis identifiedby queuestatuscode 1l Whenever
the queueis reset(e.g.,due to a transferof control) the reinitialization code 10 is output
Simitarly, il no queueoperatio occurred,statuscode00 is outpur.
The bus prioriD lock (LOCK) signal, as shownin the inteface, can be usedas an
input to a bus arbiter.The bus arbiier is usedto lock otherprocessoffoff the systembus
during accesses of conmon sysGmresourcessuchas glordl nendD' in a muldprocessor
system.The READY signalis usedto intedaceslow memory devlces.
A11of the memorycontrol si$als we just describedfor lhe 8088'basedmicrocom-
puter systemservethe samefunction in the maximum-mode8086 microcomputerHow
ever thereis one additionalcontol signalin the 8086'smemoryinlerface,the BHE. The
BHE performs the samefunction as it did in fie ninimum-mode svstem That is, it is
usedas an enableinput to the high ban&of memory'

8.I1 READAND WRITEBUSCYCLES

In the precediry sectionwe introducedlhe slatusand contml signalsassociatedwith tl'e

memory interface.Here we continueby studyingthe sequencein which thev occur dur-
ing the read and write bus cyclesof memory

sec.8.1I Readand write Buscycles 35t

ReadCycle
Figure 8-21 showsthe memoryinterfacesignalsof a minimum-mode8088 system.
Here their occurenceis illustraredrelarivero the four time staresTr, Tz, Tr. andT1 of the
8088'sbus cycle. Let us trace ihe eventsthat occur as dataor instructionsare read from

The rcad bus q,cle begtnswith srateTr. During this period, the 8088 ourputsrhe
20'bit addressof fie memorylocation to be accessedon its mulriplexedaddress/data bus
ADo through AD?, As throughAr, and multiplexed lines A6/51 tbrough Arr/56. Nore
that al the sametime a pulseis also producedat ALE. The rrailing edgeor the high level
of this pulse shouldbe usedto latch the addrcssin extemll circuitry.
Al.o \^e ceelhalar he {a1 ofT.. siCnal,lO/\4lld DT,Rare,et to rhe0logic
level. This indicaresto circuitry in rhe memory subsystemihar a memory cycle is in
p,!,sre\\anarha,,he8088; lornr ro recei\ed d from,bebu..Srdru. SSOr. at.oour-

IO/M

RO

DT/F
-- -t

figure E-21 Minimum,modememoryreadbus rycte of the 8088.(Reprinted

with lemision of intel Corporation,O I 979)

360 The 8088 and 8086 MicroDrocessors Chao. I

Dut at this time. Noie thai all tkee of thesesignalsare maintainedat theselogic levels
ihroughoutall four periodsof the buscycle.
Beginning with stale T2, statusbits 53 through 56 are outPut on the upper foul
ad{tressbus lines A16throughArr. Rernemberthat bits 53 and S1identifv to extemalcir-
cuitry which segrnentregister was used to generatethe addressjust output. This status
information is maintainedttuough periodsT3 and T+ The part of the ad&essoutput on
addressbuslines As tlrough Ars is naintained tfuough statesTr. Tr, andT4. On the other
hand.address/data bus lines ADo throughAD? are put in the high-Z statedu.ing Tr'
Larein penodT. RD i. 'qilchedro logic0 Ttu' indjcarec ro $e memoDsrbsls-
re.rl|ndrr rerd clc,e r' in progess DE\ I' ssirchedro'ogic 0 'o enable erkmal circuirr)
to allow the datalo move from memory onto the midoprocessor's daia bus.
As shownin the lvaveforms,input data are readby the 8088 during T3. The mem-
ory must provide valid dataduring T3 and maintainit until after the processorterminates
the rcad operation.As Fig. 8-21 shows,ir is in T! that the 8088 switchesRD to the inac-
tive I logic level to lerninate the read operation.DEN retums to its inactive logic level
late during Ta to disablethe exiernalcircuitry, which aliows datato move from memory
ro the processor.The readcycle is now complete.
A timing diagramfor the 8086'smemoryreadcvcle is Sivenin Fig 8-22(a) Com-
paring thesewaveformsto lhoseof the 8088 in Fig. 8-21' we ind just four differencesi
BHE-is output along with lhe addressdudng Tr; the datarcad bv the 8086 during T3 can
be carriedover a[ 16 databus lines; M,4O. which replacesIOA4, is switchedto logic I

Fisur€ s-22 (a) Minimum-mode memory read bus cvcle of dre 8086'
o loTq''b' \4drmum_mode
I R ; o r i ne d + t r np e m i . . i o no l l n r e l C o r p o r a l i O
mr:^ry ead bu, cycleof .he d08{-.,ReprInredwirl. Derris,ionol lnrelCoF
poralior O 1979)

Sec.8.1 I Readand Write Bus Cycles 361

 FigureS-22 (continued)

at the beginningofTr andis held at this levelfor the durationof the buscycle;andthe
SSO statussignal is not produced.
Fignre 8-22(b) showsa read cycle of s-bit data in a Ina\ilnum mode 8086 based
microcomputersystem.Thesewavefoms are similar ro those given for the minimun-
modereadcyclein Fig. 8 22(a).Comparingthesetwo timingdiagrams, we seethatthe
addressand datatnnsfers that take place are identical. In fact, the only differencelbund
in the maximummodewaveformsis that a buscycleslatuscoite,SrSrS0,is outputjFsr
prior to the beginningof the buscycle. This statusinformation is decodedby the 8288to
producecontrol signalsALE, MRDC. DT/R, and DEN.

V/riteCycle
Figure8-23(a)illustratesrhetnite bus clcie trmingofthe 8088in ninimummode.
It is similarto thatgivenfor a rcadcyclein Fig. 8-21. Lookjngat the write cyclewave-
forms. we find that dudng Tr the addressis output and latchedwitb the ALE pulse.This
is identical to lhe read cycle. Moreover,IO/l'{ is set to logic 0 to indicate that a memory
cycle is in progressand statusinformation is ouiput at SSO.However.this time DT,&. is
switchedto logic L This signalsextemal circuits that lhe 8088 is going to tansmit data

362 The8088 and 8086 Microprocessors Chap.I

 ro/ti

w3

ora__j L.

DEN
_-J
--1 r-
sso r, (a)

Figure E-23 (a) MitriDDmmodemmory wite b6 cycle of the 8088.

(Repiinledwith p€missionof Intel Corporatior@1979)(b) Mdimum-node
memorywrile buscycleof the 8086.(Reprinted with penission of IntelCoF
poration,@ 1979)

As T, starts,the 8088 switchesWR to logic 0. This tells the memorysubsystemthat

a write operationis to follow over the bus. The 8088 puts the dataon the bus late in T,
and maintainsthe data valid though Ta. The writing of data into memory startsas WR
becomes0, and continuesas it charyes to I early'in Ta. DEN enablesthe extemal cir-
cuitry to provide a path for data ftom the processorto the memory.This completesthe

Just as we describedfor the readbus cycle, the write cycle of the 8086 ditrers from
that of the 8088 in four ways; agaia SSOis not prcduced!Bm isiutput along with the
addressidata ,re canied over a 16 databl]s lines: and fnally, M/IO is the complement
of dle 8088'sIO/M signal.The wavefoms in Fig. 8-23(b) ilustrate a wrjte cycle of word
datain a ma,\imum-mode8086 system.

sec. 8.1 I Readand Write Bus Cycles 363

 FiguE E-23 (co lnued)

^' 8.i2 MEMORYINTERFACE

CIRCUITS

This section describesthe memory interface circuits of an 8086-basedmicrocomputer

system.The 8086 systemwas selectedinsteadof an 8088 microcomputerbecauseit is
more complex. Figue 8-24 shows a menory interface diagram for a ma,\imum-mode
8086-basedmicrocomputersyslem.Here we find that the interfaceincludesthe 8288bus
contoller, addressbus latchesand an addressdecoder.data bus transceiver/buffers.and
bank read and w.jte control logic. The 8088 microcompuGris simpler in that the inter-
facedoesnot rcquire bank wdte control logic becauseits addressspaceis organizedas a
sinelebanl.
Lookingat Fig. 8 24, we seethatbusshruscodesignalsSz,Sr, andSo,whicharc
outputs of the 8086, are supplied direcdy to the 8288 bus controller. Here ftey are
decodedto producethe commandand conhol signalsneededto coordinatedatatransfers
over the bus.Figure 8-2o]ighlights the slaluscodesthat reiateto the memoryinterface.
For example,the codeS2S]S0 : 101indicatesthai a datamemoryreadbus cycleis in
progress.This codemakesrhe MRDC conmand output of the bus control logic slvitch to
logic 0. Note in Fig. 8-24 that MRDC is applied to the banh read control logic.
Next let us look at how the addressbus is latched,buffered,and decoded.Looking
at Fig. 8-24, we seethat addresslines Ao throughAD are latchedalong with contlol sig-
nal Bm in the ad&ess bus latch. The latched addrcsslines AjrL tlrough ArrL are

t64 The8088 and 8086 Microprocessors chap. 8

 -cE"
cE-,

BHE

wR,
WR.

Fd

Figure8-Z Memoryinterfaceblockdiagram.

decodedlo producechip enableoutpubCq Lhrough eE . Notice$ar lhe 8288buscon-

troller producesthe addresslatch enable (ALE) control signal from SrSlSo.ALE is
appliedto lhe CLK input of the lalchesad strobesthe bits of the addressand bank high
€nablesignalinto the ad&essbuslatches.The addresslatch devicesbuffer thesesignals.
Latchedaddress linesArL tbmughAr6LandCq tuough CE7areapplieddirectlyto the
memory subsystem.
Du.ing readbuscycles,the MRDC ouqut of the buscontrol logic enablesihe bytes
of dataat the outputsof the memorysubsystemonto databus lines Do tbroughD15.Dur-
ing read operationsfrom memory fte batrk read control logic determineswhether the
dataare readIiom one of the two memorybanksor ftom bolh. This dependson whether
a byt€- or word-datatransferis taling place over fte bus.
Similarlyduring wrile brtscycles.rhe IvfwTC ourpurof he bu. coDtrollogic
erablesbyt€sof datafrom the databusDo drough DE to be written into the memory.The
bank wnte conaol logic determtuesto which memory bank the da(aare wdtten-

5ec.8.12 Memory lnteriaceCjrcuits t6t

 Note in Fig. 8 24 that in ihe baDl write control logic the latched bad( high enable
{g4LBmL and address l;ne AoL are galed wilh lhe memory $rile conmand signa]
MWTC toTroduce 4 leparale wrile enable signal for each bank. These signals are
denotedas WRL' and WRL. For dample, if a word of dala is Io be wriLlcn|o memory over
data bus lines D0 tbrougl Drr, both WRu and WRL-are switched to their acrive 0 logic
level. Similarly the memory read control logic uses MRDC, AoL. and BIIEL to gene te
RDu and RDL sisnals for bank read control.
The bus transceiven conirol the direction of dala ransfer between the MPU md
memory subsysten In Fig. 8 24, we see that the opoation of the t ansceiver is con
trolled by the DT/R and DEN ouFuts of thc buJi controllcr DEN is applied to the EN
input of the transceiverjdnd enablesthen fo. operatioD.This happensduring all read and
wriie bus cycles. DT/R selects the direction of data transfer ttuough the devices. Note that
it is supplied ro lhe DIR input of lhe dala bus ransceiYels- W})en a read cycle is in
progress. DT/R is \et to 0 and dala are passed from thc memory subsystem 10 the MPU.
On dre other hand. when a write cycle is taking place. DT/R is switched to logic I and
data are carried from the MPU to the memory subsyslem.

AddressBus tatches and Buffers

The 7,lFl73 is xn examplc of an octal latch dcvicc that can be used to implement
the ddr.€rr /d.., section of the 8086 s memor) i erface circuit. A block diagram of this
device is shown m Fig. 8-25(a) and fts intemal circuit] is shown in Fig. 8-25(b). Note
that ii accepF eight inpuis: lD through SD. As long as the clock (C) inpnt is ar logic I,
the outpxts of fte D-t-vpe ltip-flops follow fte logic level of the data applied to their cor
respondinginputs.When C is swilchedro logic 0, fte current contenlsof tbe D type fiip
flops de latched. The laiched inrbmation in the flip flopr is not output at data outputs 1Q
through 8Q unless the output'control (OC) irpu. of the buffers that fo ow dre larches is
at logic 0.IfOC is at logic l, fte outpulsare in ihe high-impedancesrare-Figure 8 25(c)
summdizes this operation.
In the 8086 microcomputer system, the 20 addresslines (ADo AD 5, A 6 Ar,)
and the bank higlr enable signal BHE a.e nomally la.ched;n ihe addressbus latch. The
circuit configuration shown in Fig. 8 26 can be used to latch these signals.Fixing OC
at the 0 logic le\€l permanendyenableslalched outputs AoL rhrough AreL and BHEL.
Moreover. thc addressinformation is latched at the outputs as the ALE signal ffom the
bus controller returns to losic 0 that is, when the CLK itrput of all devices is switched
io logic 0.
In general.it is importail to m;nimize the propagationdelay ofihe addresssignals
as they go through the bus in erface circuit. The switching propeny of the 7,1F373latches
that deternine this delay for.he cncuit of Fig. 8 26 is called enableao-output propaga-
tion d?ldJ and has a maxirnum value of 13 ns. By selecting fasi latches that is, iatches
with a shoner Fopagation delay time a maximum amount of the 8086's bus cycle tirne
is preservedfor fte accesstimc of the memory deviccs.In this way slower. lower cost
memory ICs can be used. These latches also provide bulTering for the 8086 s address
lines. The outpuis of the latch can sint a maxnnum of 2,1 lnA.

356 lhe 80aa and 4086 Microorocesso6 Chao I

 0c
iD 10
c
m 20
1D
o 30
Ito

m
ao

80

O-C Enabl€C D o
L I.] H
LHL L

Figure 8-25 (a) Block diaSm of d @ta] D'rype latch. (b) Circuit diagm of the
74F373. (CouJtesyof Texas lnstrumentsIncorporated)(c) Operation of the 74F373.
(Courtesyof TexasInstrum€ntshcorpoFted).
 ''lll t-Tv
oc
|]l
tl
Ir*
I r---L t
f"'v

iLl -[

AHE
oa

Figurc 8-26 Addresslatch cjrcuit.

Bank V/rite and Bank ReadControl Logic

The memoryof the 8086 nicrocomputer is organizedin upper andlower banks.Il

requiressepdratewrire dnd read control signaisfor the rwo banks.The logic circuit in
Fig. 8 27 showshow the bank wdte contlol signals.wRu lbr the upper bank and wR!
for the lower bank can be generaiedfrom lhe bus controller signalsWRTC, the address
buslarchsignalsAoLandBmL. Two OR gatesareusedfor thispurpose.
Similar io the bank wdte conirol logic circuit. the bant rcad contol logic circuii
can be designedto generaleRDu. the read for the upperbank of memory.and RDb the
readfor the lower bank. Figure 8 28 illustratessuch a circuit. Note that ihe circuit uses
the MRDC signalfrom the bus controller

DataBusTransceivers
'lhe
dala bush lnsceiNerblock of the busintertacecircuir cm be implementedwith
74F245octalbustransceiver ICs-Figure8 29(a)showsa blockdiagramof this device.
Nole thati1sbidirectionalinput/ourputIinesarecauedAj throughAs andB I drough Bs.
Lookingat the circuitdiagramin Fig. 8 29(b).we seedut the G inputis usedto enable

t6a The 8088 and 8086 Microprocessors Chap. I

 1432

Figurc 8-27 Ba'k wite controllogic.

the buffer for op€ration.On the other h'ind, the logic level at the direction (DIIR) input
selectsthe direction in which data are transfen€dthroughthe device.For instarrce,logic
0 at this input setsthe transceiverto passdata{iom the B lines to the A lines. Siwitching
DIR to logic I reversesthe direction of datatlansfer.
Figure 8-30 showsa circuit that implementsthe databus transceiverbl,ock of the
businterfacecircuit using the 74F245.For the 16-bit databusof the 8086micr(rcomputer,
two devicesarerequired.Here the DIR input is ddven by the signaldatatransr"ioit/receive
(DT/R), and G is supptiedby data bus effable(DEN). Thesesignalsaie outlputs of the
8288 busconholler
Another key function of the data bus hansceivercircuit is to buffer t.loe &ta bus
lines.This capability is definedby how much currentthe devicescan sint at rheir outputs.
Ihe IoL rating of the 74F245is 64 mA.

BHEL

MRDC

7432

FigureE-2E Banl readcontrollogi..

5e..a.l2 Memory Interface Circuits 36t

 Figure 8-29 (a) Block diaeramof
the 74F2450cl2l bidirecrionalbus
tmsceiver (b) Circuir diagramof tle
74F245.(Coudesyof Texaslnstro-

Addft 3ssDecoders

A s shownin Fig. 8-31, the adnrcssdecodern Ae 8086 micrdcomput€rsystemis

located at the output side of the addrcsslatch. A typicat device used to pelfolm this
de.ode1:unctionis fte 74F139dual2line to 4line decoderFigures8 32(a)and(b) show
a block diagrarnand circuit diagram for tbis device, respectively.When the enable(G)
input is r at its actrve0 logic level, the output conespondingto the code at the BA inputs

t70 The 8088 and 8086 Micfoprocessors Chap. 8

 :N

iR

G
Mic,op@s$d d.ta b6
] I
DBo-D8,

74F245

Figm 8J0 Databustransceiver

circuit.

switches.o the 0logic level. For instance,whenBA : 01, outputYr is logic 0. The table
in Fig. 8-32(c) summarizesthe operationof the 74F139.
The circuit in Fig. 8 33 employsthe addrcssdecoderconfigurationshown in Fig.
8 31. Note that addressLinesArTL and ArsL are applied to the A and B inputs of the
/,1flJq decoder.fte addressline Aror i( usedro erableone ol rbedecoders and {r,r.
obtainedusing an inverter,enablesthe seconddecoderol the 74F139.Eachdecodergen-
eratesfour chip enable(CE) outruts. Thus both decodersof the 74F139togetherFoduce
the eight outputsCEottuough CE7.

M crop'@e$r dddr* bus

Figure 8-31 Addressbus connguation with ad.liessdecoding.

Sec.8.12 Memory Inteface Circuits 371

 Y2
Y3

e,*I'^

L2B

Ftgure 8-32 (a) Block diasrm of th€ 74F139 2line to 4line decoder/
denu|iplexer (b) circuit diagrm of the 74F139. (Counesy of TexasInslru-
nents Incoryorated)(c) oleration of the 74F139 de.oder. (counesy of Texas
InstrumentsInco@rated)

372
 c&

cEr

cEr

1Y3 cE3
74F139
. 2Y0 cE4

2v1 cE5

2\2 cE€

2\3 CF,

Figur€8-33 Add.ress
de.odercircuit.

The block diagram of anothercornmonly used d€coder,the 74F138,is shown in

Fig. 8-34(a). The 74F138is similar to the 74F139,exceptthat it is a single three-Iineto
eight-line decoder The circuit usedin this deviceis shown in Fig. 8-34(b). Note that it
can be usedto produceeight CE ouQuts.The table in Fig. 8-34(c) descdbesthe opera
tion of the 74F138.Here we find that when enabled,only the output that corespondsto
the codeat rhe CBA inputs swirchesto the active0 logic level.
The circuit in Fig.8 35 usesthe 74F138to generatechip enablesignalsCEotbrough
CE7by decodingaddresslinesAr7L.ArsL, andArrL. Connectingthe enableinputsto +5V
and groundpermanentlyenablesthe decoder.The advantageof using the 74F138overthe
74F139for decodingis that it does not re4uire an extra inverto to genemteeight chip
enablesisnals.

sec.8.12 MemorylnterfaceCkcuits 313

 YO

\2

Y3

Y5
dzA Y6
GzE
Y7

'*t*'

(c)

Frsure8-34 ol-:T:::
- d' qb.kdT.cr-al,-
rcorp"rar'"' '''lf .ff"iJ,i'"T'iii
tc;unes\ of Te\as Ins!ruments
'
(CounesyofTe\as ln\mments licorPonre! |
"ifll,T
 cBz

cE3

cE4

c1 cEj

c2B @1
Figure E-35 Addres decodercircuit
using74Fi38.

B. i3 PROGRAMMABLE
LOGICARMYS

In the last section we found that brsic logic devicessuch as latches,tiansceivers.and

decodersare rcquired in the bus interfacesectionof the 8086 microcomputersystem.We
showedthat thesefunctionswercperformedwith standardlogic devicessuchasthe 74F373
octal imnsparenilaich,74F245 ocral bus tansceiver and 74F139 two-tne ro four-line
decodet respectively.Todayprcgrunnable logic aftay (PLA) devicesare becomingvery
impotant ir the desigr of microcomputersystems.For example,addressandcontrolsignal
decodingin the memoryinterfacein Fig. 8-24 canbe inplemenled with PLAS.insteadof
with sepaEtelogic ICs. Unlike the earlier mentioneddevices,PLAS do not implementa
specificlogic function.Instead,rlEy arc general-purpose logic devic€sdlat havefie abiliry
to perfonn a wide variety of specializedloglc tunctions.A PLA containsa general-purpose
AN'D OR NOT aray of logic gate circuits. The user has the ability to interconnectthe
inputs to the AND gatesof this array.The defnition of theseinputs determinesthe logic
functionthat is implemented.The processusedto connector disconnectinputsof lhe AND
gateanay is known asprosldnm,n& which leadsto the nameprogrammablelogic array.

PLA5.GAt"s.and EPLD5

A variety of different types of PLA deviceslre available-Early deviceswere atl

manufacturedwith the bipolar semiconductorprocess,Thesedevicesare referred to as
PALi aDdrenain iD usetoday.Bipolar devicesarc programmedwith an interconnectpal
tem by burningout fuse links widin the device.ln the initial state,all of thesetuse links
are intact. During pmgramming.unwantedlinls are open-circuitedby injecting a current

sec 8.13 ProgrammableLogicArrays 375

tlmugh the fuse to bum it out. For this reason,once a device is programned it cannot
be reused.If a design rnodificaiion is required in the pattem, a new device must be
prograrnrnedand substitutedfor the original device.Since PALSare madewith an older
bipolar technology,they lre limited to sinpler funcrions and characrerizedby slower
operatingspeedsandhiSh power consumption.
Newer PLA devicesare manufacturedwith the CMOS process.With this Focess'
very complex, high-speed,low-power devicescan be made.Two kinds of CMOS PLAS
arein wialeusetoday; the GA, andthe tPrD. Thesedevicesdiffer in the type of CMOS
technologyusedin their design.GALS are designedns:j..gekcti&ll, erasableftttd'onlv
r1?r,orl (E':ROM) technology.The inpuroutput operationof this device is determined
by rhe p.ogranming of cells. Theseetectricallyprogrannnablecells are also electricallv
efasable.For this reason,a GAL can be used for one apPlication'erased,and then re-
programmedfor anotherapplication.EPLDS are similar io GALS in that thev can be
programmedreraseal,and reused;however,the erasemechanismis different. They are
manufacturedwith electricallr prcSrannable read onb memory(EPROM) technologv
That is, they employ EPROM cells inst€adof E'zROMcells. Therefore,to be erasedan
EPLD must be exposedto ultraviolet lighi. GALS and EPLDS are cunently the mosa
rapidly growing segmentsof the PLA marketplace.

Block Diagram of a PLA

The block diagramh Fig. 8 36 rcprcsentsa typical PLA Looking at this diagram,
we seethal it has 16 input leads,marked Io through IL5 There are eight output leads'
labeledF0 lhrough F7.This PLA is equippedwith ttue€-stateoutputs For this reason.ii
hasa chip-enableconaol lead.In the block diagram.fiis control input is narked CE. The
logic level of CE determinesif the outputsare enabledor disabled.
When a PLA is used to implement random logic firnctions. the inPuts represent
Booleanvariables,and the outputsare usedto provide eight separaterandomlogic func_
tions. The intemal AND OR-NOT army is programmedto definea sum-of-productequa-
tion for eachof lheseoutputsin tems of the inputs and their complemenlsln this way,

Figure E-36 Block diacIm of a

PLA. (Reprlited wilh the permission
of WalterA. Tri€bel)

376 The 8088 and a086 Microprocessors chap. 8

 we seethat the logic levels applied at inputs I0 tbrough Ir5 and the Progaaming of the
AND arraydeterminewhat logic levels areproducedat outpul'tFotbroughF7.Therefore,
the capacityof a PLA is measwedby thee Fopertiesr the numberof inputs,the number
of outputs,and the numberof productterms (P-tems).

Architectureof a PtA
Wejust pointed out that the circuitry of a PLA is a generalpurPoseAND-OR-NOI
aray. Figue 8 3?(a) showsthis architecture.Herc we seethat the input buffen supply
input signalsA andB andtheir complemenisA andB. Programmableconnectionsin the
AND aray permit any combinationof these inputs to b€ combinedto form a product
term. The Foduct term outputs of the AND array are supPliedto fixed inputs of the

*".,1
*t
t-

I
I

F=AB+AB

(b) =
44E l!:_37 G) BasicPLA archilectue. Inllenenting the losic tunctionF
(AB + AB).

sec.a.l3 Programmable
LogjcAfays 317
OR array.The output of the OR gateproducesa sum-of-productsfutction. Finally, the
r n l e r t e fc o m p l e m e n ttsh i s f u n d j o n .
The circuit in Fig. 8 37(b) showshow dre functionF - (AB + AB) is implemented
widl the AND OR NOT aray. Notice that an X markedinto theAND arraymeansthat th€
fuseis left intact,andno markingmeans!ba!it hasbeenblown to folm an opencircuii. Rr
ihis reason.the upperAND gateis connectedto A and B and Foduces the productterm
AB. The secondAND gatefrom the top connectsto A andB to producethe Foduct term
AB. The bottomAND gaG is markedwith an X to indicatefiar it is not in use.Cateslike
this that arc not to be activeshouldhaveaI of their input tuseLinksleft inlact.
Figurc 8 38(a) shows the circuit structurethat is most $ridely used in PLAS. It
differs from the circuit shownin Fig. 8-37(a) in two wals. First, the inverterhas a pro-
grammablethre€-statecontrol and can be usedto isolate the logic function Aom the oul_
put. Second,the bnffered output is fed back to fbnn anolherset of inputs to the AND
array.This new output conligumlion permitsthe outputpin to be progJallllrcdto wo* as
^ standardautput, standad input, or logic-cantrcllzd inputlor,tput For instance,if the
upperAND gate.which is the control gatefbr the output buffer is set up to permanendy
enablethe inverter and the fuse links for ils inputs that arc fed back from lhe outputsare
all blown open,the output functions as a standardoutput.

OIJTPUT

Kt-

CLOCK

INPUT

FEEOSACK
(b)

rigu.e 8-38 (a) Tylical PLA archltecture.(Counesy of Teaaslnslrunents Incorpo-

Eted) (b) PLA *nb output larch. (courlesy of TexasI.strunent$ Incorporated)

374 lhe 8088 dnd 8086 Vr.'op.ocessoA Chcp. 8

 PLAS are also available in {'hich the ou9uts are Iatched with registers Figure
8-38(b) showsa circuit for this rypeof device.Here we seethat the ouFut of $e OR gate
is appliedto the D input of a clockedD t)?e flip-flop In this wav' the logic level produced
by the AND OR array is not presentedat the ouiput until a pulse is first applied at the
CLOCK input. Futherrnore,the feedbackinput is Foduced ftom the complement€dout
pui of ihe flip-flop, not the outputofthe inverterThis configurationis known asa PL4 unn
re|isteredoutputs atrdis designedto sirnpliry implenentationof state,?4.*r,e designs'

StandardPALruDevices

Now that we bave introducedthe rypesof PLAS, block diagram of tlle PLA' and
internal drchitectureof the PLA, let us continueby examini4 a few of the widely used
PAL devices.A PAl, or a programmableanay logic, is a PLA in which the OR arav is
fixed; only the AND array is programmable
The 16L8 is a widely used PAL IC. lts intemal circui.rv and pin numberingare
shown in Fig. 8-39(a). This device is housedh a 2Gpin package'as shown in Fig
8-39(b). Looking at this diagam. we seerhat it employsthe PLA drchitectue illustrated
in Fig. 8-38(a). Note that it has 10 dedicatedinput pins. All of.hese pins are labeledI'
There are also two dedicatedoutputs,which are labeled with the letter O' and six pro
grarnmableI/O lines,which are labeledyO Using fte programmableI/O lines' rhe num
ber of input lines canbe expandedto as many as 16 inputs or the Nmber of outputscan
be increasedto a5 many as eigh. lines-
All the 16L8's inpuLsare bufferedand produceboth the original form of the signal
and its complement.The outputsof the butrer are appliedto the inputs of the AND arrav'
This array is capable of producing 64 product terms- Noie that the AND gates are
arrangedinto eight groupsof eiglt. The outputsof sevengatesin eachof thesegoups are
usedas inputs 1oan OR gate, and the eighth ouFut is used to p.oduce an enablesignal
for the correspondingtlEee-stateoutputbuffer' In this way. we seethd rhe 16L8 is capa-
ble of producingup to sevenFoduct termsfor eachourpu! andthe Foduct ierms canbe
formed using any coqbination of lie 16 inputs
The l6L8 is manufacturedwith bipolar t€chnology-It operates{iom a +5V :l:109'
dc power supply and drawsa maximum of 180aA. Moreover,all it! inpuis and outputs
are at TTL compatiblevoltagele\€ls. This deviceexhibitshigh-speedinpui-outputprop-
agationdelays.In fact, the maximum l-to-O Fopagation delay is ratedas 7 ns
Anotherwidely usedPAL is the 20L8 devic€.l-ooking at the circuitv of this device
in Fig. 8-40(a), we seethat it is similar to that of the 16L8jusr described Howeve! the
20L8 has a maxim m of 20 inputs, eight outpuls, and 64 P terms. The device's24-pin
packaseis sllown in Fig. 8 40(b)
The 16R8is also a popular20 pin PLA. The circuit diagramal}dpin lavout for this
device;re shown in Figs. 8-41(a) and O), rcspectively.FIom Fig. 8 41(a), we find that
its eight fixed I inpursand AND-OR array are essedially the sameas thoseof the 16L8'
Thereiii oDechnge. The outputsof eight AND gates.insteadof seven,are suppliedto
the inputs of eachOR gare.
A numberof changeshavebeenmadeat the ouiput side of the 16R8-Note thai the
outputsof the OR gatesare fiIst latchedh D type flip-flops wirh the CLK signal Thev
are then bufferedand suppliedto the eight Q outputs-Another charge is tbat the enable

Sec.8.l3 ProgrammableLogicAffays 37t

 tE vo

tll]
"o

!l 'o

rigure 8-39 {a) l6L8 circuit diaSrd. (Counesy of Texar lnslrumentsIncor?orated)

(b) 16L8 pin layout. (Couliesy ofTexas Ilstrumenis Incorporated)

380
Figure 8-40 (a) 20L8 ctcuit diagram. (Courtesyof TexasInstrumentsIncorporated)
(b) 20L8 lin layout. (Courtesyof Texashstrumenls lncorporaled)

3Al
6,:':

Figure 8-41 (a) 16R8 cncuir dia81am.(Couresy of TexasInstrutnerts lncorporated)

(b) 16R8pin layout. (Couresy of TexasInstrunents lncorporated)

342
 srgnalsfor the ootput invertersale no longer prognmmable. Now the logic level of the
OE control input enablesa[ three-stateoutputs
The last changeis in the part of the circuit that Foduces the feedbackinpuis ln the
16R8,theseeight inpu! signalsare derivedftom ihe complementaryoutput of the colle-
spondinglarch insteadof the output of the buffer' Fo. this rcasoq the ouq)utleadscanno
longer be pro$ainmed to work as direct inputs.
The 20R8is the registeroutputvenior of the 20L8 PAl Its circuit dia$am andpin
layout are give! in Figs. 8 42(a) atrd(b). respectively

ExpandingPtA CaPacity
Sone appiicationshaverequimmentsthat exceedthe capacityof a singlePLA IC- For
instance,a 16L8 devicehasthe abiliry to supply a rnaximumof 16 inputs' 8 outputs.and
64 productterms.ConDectingseveraldevicest€erher canexpandcapacityLei us now look
a! the way in which PLASare intercomectedto expand$e numberol inputsandoutputs.
ff a single PLA does not have enoughoutputs,two or more devicescan be con-
nectedtogelher into the configurationof Fig. 8 43(a) Here vr'esee that the inputs I0
through Ir5 on the two devicesare individualy connectedin parallel This connection
doesnot changethe numberof inputs.
On the olher hand, the eight outputsof the two PLAS are separatelyusedto form
the upper and lower btaes of a 16-bit output word. The bits of this wod are denotedas
OothroughOr5.So with this conneciion,we havedoubledthe numberof outputs.
\vhetr data are appliedto the inputs, PLA I outputsihe eight leart significantbits
of data.At the sameinstantPLA 2 outputsthe eight most significantbits Theseoutputs
can be usedto representindividual logic tunctions.
Another limitation on the apPlicationof PLAS is the numberof inplrts-The ma,\r
mum numberof inputs on a single 16L8 is 16.Howevet additionallcs can be connecled
to expandthe capacityof inputs Figue 8-43(b) showshow oneadditionalinput is added
This permits a 17-bit input denoredasIo through116The new bit 116is suppliedtbrough
invertersto the CE inputs on the two PLAS.At the output side of the PLAS, outputsOo
through 07 of the two devicesare individually connectedin paralel. To inplemenl this
coMeclion.PLA detrce'$i!h open-colle{lor or three-\tale ourpulcmuslbe rsed
When 116is logic 0, CE on PLA 1 is logic 0. This embles the devicefor operation'
andthe oulput functionscodedfor input I0 tfuough Ir5 are output at Ootbrough07- At the
sameinstant,CE on PLA 2 is iogic 1 and it rernains disabled Making the logic level of
116equalto 1 disablesPl-A 1 aDdenablesPLA 2 Now ihe input at Io through Ir5 causes
the output function definedby PLA 2 to be output at Oo through 07 Actually, this con-
nection doublesthe numberof Foduct terms as well as increases the number of inputs

OF INPUT/OUTPUT
8,I4 TYPES

The input/output system of the microprocessorallows peripheralsto provide data or

receiveresults of processingtbe data.This is done using I/O ports The 8088 and 8086
microcomputerscan employ two diffemnt types of input/output (I/O): isolakd I/O at].d
menory-mappedI/O. Thesel/O methodsdiffe. in how I/O pofts are mappedinto the
8088/8086'saddressspaces.Somemicrocomputersystemsemploy both kinds of I/O-

sec 8.14 Typesof Input/Output 383

 6---i--i----1t-- t;
3{

(a) {b)

Figure 8-,12 (a) 20R8 circuit diaelam. (Couiresy of TexasInstrumentsIncorporated)

(b) 20R8 pin lalour. (Courtesyof Te{as Insrtunents Incorporated)

344
 :

llL
..-i_
I
I

(a)

Figure8-43 (a)ExPanding outPutwordlength.(Reprifiedwirh tbepenis;

sid of WarlerA. Tnebel)(b) Exlandingin?ut woid len$l. (Reprirtedwith
thepermissionof WalierA. Triebel)

that is, some peripherallcs are treatedas isolaied I/O devicesand oihers as memory-
rnappedI/O devices.Let us now look at eachof theseryPesof I/O.

lsolatedInput,/OutPut
Wlten using isolatedI/O in a microcomputersystem,the I/O devicesare treated
separatefrom memory.This is achievedbecausethe so{iwarcand hardwaxearchitectures
oithe 8088/8086supportsepamtememory and I/O addressspaces.Figure 8-zg illus-
tratesthesememory and I/O addressspaces.
In our study of 8088/8086softwarearchitectue in Chapter2, we exarninedthese
addressspacesfrom a softwarepoint of view.We found that infbrnation in memoryor at

sec.Li4 Typesof lnput/Output 345

 nemoryand
Figure8-44 8088/8086

I/O pofs is organizedas bytes of data; that lhe memory addressspacecontainslM con-
,".uilu" Uyt" iaa..ttes io the range 0000016through FFFFFL6Iand that the I/O address
.o,...oniuin' O+K.on..cuLi\e blre add'e'se. In Ineran8e0000r' tuoughFFFF"
Figure8 45,ar iho\\s a more derailel]map of rhi' l/O add'e'csp:ce Herc$e find
that the;ltes of data in rwo consecutiveI/O addrcssescould be accessedas word-wide
data.For instance,l/O addresses 000016,000116' 000216, and 000316 canbe treatedas
independenr byte-widel/O ports.ports0. 1, 2, and3, or pons0 and 1 mavbe considered
togetheras word-wide Pot 0.
Note that the pan of the I/O ad&essspacein Fig 8-45(a) from address000016
nhrough00FFr6is refered to aspdg€ a Cedain UO inslructionscan only perform oper-
ations'topots in this part ofrhe addressrarge Olher I/O instruciionscaninput or output
datafor pons anywherein the I/O addressspace
This isolatedmerhodof I/O offers someadvantagesFirst, the complete lMbyte
memory addressspaceis available for use urith memory' Second' special instuctions
havebeenprovided in *re instruction set ol the 8088/8086to perforn isolated I/o inp'rt
pedor-
and ouD; operations.These instruciions have been tailored to maximize I/O
mance.i dis;dvantageof this rype of I/O is that all input and output datatransfersmusl
take piacebetueen the AL or AX register and dre UO port

lnPut/OutPut
Memory-MapPed
I/O devicescan be placedin the memory addressspaceof the microcomputeras
pon
well as in the independentI/O addressspace.In this cdse,lhe MPU looks at the UO
as though it is a storagelocation in memory.For this reason'the methodis known as
netnory napped I/O.
ln a microcomputersystemwith menory-mappedI/O' someof the memoryaddress
m
spaceis dedicatedtol/O ports For example'in Fig. 8 45(b) the 4096 memoryaddresses
tire rangefrom E0000r6throltgh E0FFFL'jare assignedto I/O devices Here the contents
of a<trtrlssE0000r6representb)'te-widel/O port 0, andthe conlentsof addressesE0000t6
and8000116 correspondto word-wide por 0

346 Theaoaa and 8086 Microprocesso6 Chap S

 :

va :
E0oo316
E0004s (16-bilpod
Eooolls
0000i6 (15-bilpo't)

(b)

risur€ 8-4s (a) IsolaiedI/o ports. (b) Menory-napped I/o ports

347
 Wllen I/O is configuredin this way,inslructionsthat affect datain memoryare used
insteadof ihe specialinput/outputinslructions This is an advantagein that many more
instructionsand addrcssjngmodesare availableio perform I/O operations For instance'
the contentsof a memory-mappedl/O poll can be directly ANDed with a value in an
intemal register.In addition, l/O tansfers cannow take placebetweenan l/O port andan
in@mal registerother than ju$ Af or A,I. However,lhis also leads to a disadvantage.
That is, the memory instructionstgnd to exe.ute slower than thosespecifically desigrcd
for isolatedUO. Therefore,a memory mappedI/O routine may take longer to perform
than an equivalentprogrl]musing the inputoutput tnstructlons.
Anolher disadvantage of usingthis methodis drat part of the memo.y addressspace
is lost. For instance,in Fig. 8-45(b) addresses in the range from 8000016ihrough
E0FFFI6.allocatedto I/O, cannotbe usedto jmplement memory

8.I 5 ISOLATEDINPUT/OUTPUTINTERFACE

The isolatedinput/outputt,?t€dac€of the 8088and 8086 microcomputerspermitsthem to

communicatewith the outsideworld. Tlre way in whicb the MPU dealswith inpuvoutput
circuitry is similar to the way in which il interfaces with memory circuitry. That is'
input/output data transfersalso lake place over lhe multiplexed address/databus. This
parallel bus permits easy interface to LSI peripheralssuch as Parallel I/O expanders.
interval timers. and serial cornmunicationcontrollers. Through this UO interface, lhe
MPU caninput or outputdatain bit, byte, or word (for ile 8086) formats Let us continue
by looking at how an isolatedUO interfaceis implementedfor minirnum- and maxirnum-
mode 8088 and 8086 microcomputersystems.

Interface
Minimum-Mode
Let us beginby looking at the isolatedI/O interfacefor a minimum-mode8088 sys-
tem. Figure 8-46(a) showsthis minimum-modeinterface.Here we find the 8088' inter-
faceciicuity, andVO poris for devices0 tbroughN I/O devices0 throughN can repre-
sent input devicessuch as a keybo.rd, output devicessuch as a printer' or inpuvoutpui
devicessuchas an asynchronousserial communicationsport An exampleof a rypical I/O
device usedin the l/O subsystemis a programmableperipheralinterface(PPI) IC' such
as the 82C55A.This type of deviceis usedto implementparallel input and output poris
The circuiis in the interface seclion must perform functions such as selectthe I/O port'
lalch output data. sampleinput dgta, synchronizedata transfers,and translatebetwe€n
TIL voltagelevels and ihoserequiredto operatethe I/O devices.
The data path between the 8088 and l/O interface circuiis is the multiple)Gd
address/data bus.Unlike the memory interface,fiis time just dre 16 least significantlines
of the bus, ADo tlrough AD? andAs rhough Ar5, are in use This interfacealso involves
the control si$als that we discussedas pad of the memory interface-that is ALE, SSO.
RD. WR. IO,M. DTA.. and DEN.
Figure 8-46(b) showsthe isolaredI/O intedace of a minimum-mode8086-based
micrccomputersystem.Looking at this diagram.we find thai the interface differs from
tbat of the 8088 microcomputerin severalways.First, the compleiedatabusADo through

384 The8088 and 8086 Microorocessors chap B

 vo
sso

, aDo-aD, !o
)
\---------------

Aa-A,a
---------------- ) uo
8@8
FD

IO/M

MN/MX OEN uo

tHE

' ADo-ADr5 l I
\-,/
3036 RD
VE
M/id
DT/F
MNA,IX tEN
N

(b)

risue 8-46 (a) Minimum-node8088syslemVO interface.(b) MinimDm-

mode8086systemI/O inlerface.

AD;. is u.ed for inpurandourpurdararran'ter'r'econd.rbe V,4Oconrol .igal rs rhe

lg4llenent of the equivalentsignalIOA4 in the 8088'sinterface;and third, statussignal
SSOis replaced by BHE.

Maximum-Mode
lnterface
tvhen fie 8088rs .trappedro opemrern rhe ma{mum moder\4J\/M} corurecred
to gound), rhe inteface to the I/O circuihy changes.Figure 8 47(a) illustrates this
configura.ion.

Sec.Ll5 lsolatedlnput/OutputInterface 349

 8233

vo

3133

Figure 8-47 (a) Ma-\imumnode 8088 systen I/O interface.(b) Mdlmum

mode8086 systen I/O interface.

3to
 s: 5,
0 iNlA
I
rorvc.A-idwa
I
iliSt
0 MRDC
I fuwrc,AMw'c
I

Figure8-4E l/O buscycleslatuscodes(Reprinledwith pernision of Intel

copyight/Intelcory. 1979)
Corporalion,

As in the naximum-modememory interface.lhe 8288 bus conholler produceslhe

control signalsfor the yO subsystem-The 8288 decodesbus commandslatuscodesout-
put by the 8088 at S,SIS0.Thesecodestell which type of bus cvcle is in Fogless. If the
code corespondsto an I/O read bus cycle, the 8288 generatesthe /O rcad colllAll
dl/tprr (IORC) andfor an I/O write cycleit generacsl/O wite mnma n ouQutsGOWC)
an,l (AIOWC). The 3288 also Foduces the control signalsALE, DT,&.' and DEN The
addressand datatransferpath between8088 and ma\imum node UO intedaceremains
address/data bus lin€s ADo throughAD? andAs throughAr i
Figure 8-47(b) showsthe maximum-modeisolatedI/O intedaceof an 8086micro-
processorsyslem.Therc are only two differencesbetweenthis intedacediagramandthal
for the 8088microprocessorAs in the minimum mode,the tu1l 16-bit darabusis the path
for datatransfers,andlhe signal BHE, which is not suppliedby the 8088' is includedrn
the interface.
The table in Fig. 8 48 showsthe busconmand statuscodestogetherwith the com-
mand signalslhat they produce.Thosefor I/O bus cyclesare highlighted The MPU indi-
catesthat dataare to be inpul (readI/O pori) by codeS2SrS0= 001-This codecausesthe
buscontrollerto producecontroloulputI/O readcommandoORC) Thereis oneotler code
that representsan ouQutbus cycle,the write UO polt codeS,SrSo: 010.It producestwo
outputcommandsrgnals:I/O \rrite cycle (IOWC) andadvancedUO \lTite cycle (AIOWC)
Thesecommandsig:nalsareusedto enabledataftom the l/O ports ontothe systembusdur-
rngal irpul operalion Jnofrom theMPU lo lhe l/O porl' duringan ouFul operalion

DATATRANSFERS
8,I6 INPUT/OUTPUT

Input/outputdatatransfersin the 8088 aid 8086rnicrocomputerscanbe either byte-wide

or word-wide.The pon that is a(essed for input or outpui of daia is selectedby an /o
drldr€rs.This addressis specifiedaspalt of the instructionthal performsthe I/O operation'
I/O addressesare 16 bits in length and are output by the 8088 to the l/O interface
over bus linesADo throughAD? andAs tl oughAr5.ADo representsthe LSB andAr5 the

sec.Ll6 lnpuvoutput DataTransfers 3.rl

 MSB. The mostsignificantaddresslines,A16throughArr, are held at the 0 logic lerel
duringtlre sddressperiod(Tr) of all I/O buscvcles Since16 address linesareusedto
address I/O oorts,the 8088's1/Oaddress space consistsof 64K byte-wide I/O ports
The 8088signalsro extemalcircuitrv thai rheaddress on the bus is for an I/O pon
insleadof a memorylocationbv switchingthe IO,M control line to the I logic level This
js
signal heldat the I leveldxringthecomplete inputor ouQut bus cvcle For th's reason'
it;an be usedto enablethe addresslatch or address decoder in external I/o circuit$'
Data transfersbetweenthe 8088 and I/O devicesafe performedover the databui'
Data tfttnslersto byte-wideI/O poris alwaysrequire onebus cycle Byle datatransten to
a pon dreperformedover buslines DothroughD? Word transfeNalso takeplaceoverthe
databus,16througl17. However,thisivpeofoperationis pedormedastwo consecuiive
byte-widedatatrinsfersandlakestwo buscycles.
For the 8086 microcomputer, I/O a{ldresses ale outputon iddress/data bus lines
ADo lhroughADrr' The logic levelsof signalsA0 andBHE delermine whether dataare
inpuVoutput for an odd-addressed byte-widepon, even-addressed byte"wide-pttt'or a
word-wi;eport For example,if A0BHE = l0' an odd-addrcssed byte-wideI/O pon is
accessed, to a pol,tai an evenaddress
Byle datatransfers are perfbrmed overbuslinesD0
throughD?;nd lhoseio an odd_addtessed pon areperformedoverDs lhrcughD 5 Data
lrAnsfers to byte-wideI/O ponsalwaystakeplacein onebuscycle
word dalatmnsLers between lhe 8086andI/O devicesarcsocompanied by lhe code
A0BE = 00 andareperfoDred overthecomplete databur' DothroughD 5 wordirans'
A
fer canrequheeitheroneol two buscycles,To ensure thatjustonebuscycleis requircdfor
theworddatatrmsfer,word'wldeI/O pofisshouldb€ alignedal even-address bouudaries

INSTRUCTIONS
A 8, I7 INPUT/OUTPUT
Input/outpul operations ale pefbrmedby the8088and8086micrcprocessols thatemploy
isolatedllO usingspeclalinputAndoltput iDslructions logether wilh theI/O p-ortaddress-
i:rg motles.Thes=e instructions, ir (IN) and o&r (OUT), are lisied in Fig S-49' Tbeir
rnienonicsandforrnatsareprovidedtogetherwith a brjef description of theiroperations
Note tha! there arc two diilbrent forms of IN and OUT instructionslthe dircct 1/O
be
instluclio s andvariahleI/O /tntt?rclr",{t.Either of thesetwo rypesof instrxrclionscan
used1()tansfer a byte or word of data.All dau anslers takePlace between an I/O dev;ce
andtheMPU'SaccumulatofregisterFor thisreason,this nethod of perfoming l/O is known
^s arumulat.tr t/O Byte nansfersinvolvetheAL rEgister,andnod transfeNtheAX r€8is-

IN ( A . O€ l P o r r ) A c .= A L o r A x

o!rT
Outputindn€ci(v.dable)

Fieure 8-49 Inputoutput nstructom

3q2 The8088 and 8086 l\4icroprocessorschap. 8

ter.In fac! specjlyingAl asthe sourceor destinationregisterin an I/O instuction indicates
that ii correspondsto a byte transfer.That is, b)te-wide or word-word input/output rs
setectedby specifyingthe accumulator(Acc) in the instuction asAL or AX' respectivetv.
ln a dire.t I/O instruction, the addressof the I/O polt is specifiedas part of tbe
instruction.Eight bits areprovidedfor this direct address.For this reason,its valueis lim-
ited to the addressrangefrorn 010equals00b to 25510equalsFFr6 This raageis referred
to as page0 in the l/O addressspace.
An exampleis the instruction
IN AI,, OFEH

As Fig. 8-49 shows,executionof this instrucaioncausesihe contentsof ihe byte_wideI/O

porr at addressFEr6 of the I/O addressspaceto be input lo the AL register This data
transfertakesplace in one input bus cycle

EMMPLE8.7

Write a sequenceof instroctionsthat will output the dataFF16to a byte'wide outputport

at addressAB L6of dre I/O addressspace.

Solution
First, the AL registeris loadedwith FFr6 as an immediateoperandin the instuction
MOV AL, OFFH

Now the datain AL can be ouFut to dle byte-wide outpLrtport with the instruction
OUT OABH, AL

The differencebetwe€nthe direct alrd variablel/O inslructionslies in the way in

which the addressof the I/O port is specified.We jusi saw that for direct I/O instructions
an 8 bit addrcssis specifiedas part of the instruction.On the otherhand.the variableI/O
instmctionsusea 16 bit addressthai residesin the DX registerwithin the MPU The value
in DX is not an offset.It is the actualaddressthat is to be outputon ADo tfuoughAD7 and
As throughAr5 during the I/O buscycle. Sincethis addressis a tulI 16 birs in length vari-
ableI/O instuctions can accessportslocatedanywherein the 64K-byteVO addresssPace.
When usingeirher type of I/O instruction,the datamusl be loadedinto or rcmoved
from theAL or AX registerbeforeanotherinput or output operaiioncanbe pefomled ln
the caseof variable I/O instructions,the DX registermust be toadedwith (he addrcss
This requiresexecutionof additionalinstructions.For instance,the instructionsequence
MOV DX, 0A00011
IN AL, DX
MOV B'-, AL

inputsthe contentsof lhe byte-wideinput port at A000i6 of the I/O addressspaceinto AL

and then savesil in BL.

sec.8.17 lnnftrcnons
InPuVOutPut 3rt
 EMMPLE8.8
Write a s€riesof irsrructions that will output FFr6 ro an outpur port locatedat address
B00016of the I/O addressspace.

Solution
The DX registermust firsr be loadedwith the addressof rhe ouFur port. This is donewith
theinstruction

MOV DX,0B000H

Next, the dararhat are to be output must be loadedinto AL with the insruction

MOV AL, OFFH

Finally. the dataare outpui with the insrrucrion

OUT DX, AI-

EXAMPLE
8,9
Data are to be read in from rwo blre-wide input polts at addrcssesAA16 and A916and
thenoutpui as a word to a word-wideoutput port ar addressB00016.Wrire a sequenceof
insiruciionsto perfom this input/ourputoperarion.

Solution
We can firsr read in the byte from the pot at addressAA16 inio AL and move it to AH.
This is done fith the instructions

IN AL, OAAII
MOV AI{, Ni

Now the other byte, which is at port A96, can be read into AL by the instrucrion

IN AL, OA9H

The word is now held in AX. To wrile our the word of data,we load DX with rhe aaldress
800016and usea variableoutpurinsruction. This teadsto rhe following:

MOV DX, OBOOOH

ouT Dx, ax

l. 8.IB INPUT/OUTPUT
BUSCYCLES
In Section8.15, we found that the isolatedUO interface signatsfor the minimum mode
8088 and 8086 miffocomputer sysremsare essentially rhe same as rhose invotved in
the memory interface.In fact. dle function, logic levels. and riming of a signalsother

3t4 The 8088 dnd 8086 lvr'L.ooro.esrori Chap. 8

$an IO/M (M^O) are identical to those already describedfor the memory interface in
Section8.11.
Waveformsfor the 8088'sXO input (l/O rcad) bus ctcte andUO output (XO lt'rite)
,&r c],.lz are shownin Figs. 8 50 a 8-51, respectively.l,ookiry at the input and out-
put bus cycle waveforms,we see that the timing of IO/M does not change.The 8088
switchesit to logic I to indicate that an I/O bus cycle is in progress.It is mai ained at
the I togic level for fte duration of ihe UO bus cycle. As in memory cycles,the adahess
is output together with AIE dudng clock period Tr. For the jnput bus cycle, DEN is
switchedto logi€ 0 to signal the UO ifierface cncuitry when to put the dataonto the bus
and rhe 8088 readsdataoff the bus during period Tr.
On fte other hand,for the output bus cycle in Fig. 8-51, dre 8088 puts write data
on the bus late in T2 and maintains it during th€ rest of the bus cycle. This time WR
switchesto logic 0 to signalthe I/O systemthat lalid dataare on the bus.
The waveformsof the 8086's inpul and output bus cycles are shownin Figs. 8-52
and 8 53, rcspectively.Let usjust look at the differencesbetweenthe input cycle of the
8086 andriat of the 8088.Conpariry the waveformsin Fig. 8-52 to thosein Fig. 8 50,
we seethat the 8086outputsthe signalBHE alongwith the addrcssin T-stateTr. Remem-

I on. b$ cvil.
r'lr,

IO/M

F6

DT/F

$o --J

Fig@ 8-50 Inpd bns cycle of the 8088.

sec.8.l8 Inpuvoutput Bus Cycles 395

 ro/fi

WU

DT/R-

DEN
---t

Figure 8-51 Outpulbuscycleolth€ 8088.

^',.iitrd:l@

Figurc 8-52 Inputbuscycleofthe 8086

 Figure8-53 OutPutbuscycleof the8086

ber that for the 8086 microprocessorthis signal is usedaloDgwith Ao to selectrhe byte-
wide or the word-wide porr. Next, lhe 8086'sdatalransferpath to the I/O intedaceis the
16-bit address/dafa bus, not 8 bjts as in the 8088 system.Thercfore.datatransfels,which
rakeplaceduring T3,cantake placeoverthe lower 8 databuslines, upper8 databuslines,
or all 16 databus lines. Thhd, dre 8086 outpuislogic 0 on the M/IO 1ine,while the 8088
outputslogic 1 on the IO/M line. Thar is, the M,{O contol signalof the 8086is the con
plementof that of the 8088.Finally, the 8086doesrot producean SSOoutput signallike
the onein the 8088.

R E V I E WP R O B L E M S

Section8.l
1. Nameihe tecbnologyusedto fabricalethe 8088 and 8086 rnicroprocessors.
2. wlat is the transistorcount of the 8088?
3. Wlich pin is usedastheNMI inputon the 8088?
4. which pin providesthe BHE/S?outpntsignalson the 8086?
5. How much memory can dle 8088 and 8086 direcily address?
6. How large is ihe I/O addressspaceof fie 8088 and 8086?

Section8.2
7. How is minimurn or naximum modeof operationselected?
8. Describeihe differencebetweenthe minimum-mode8088 syst€mand ma,\imum_
mode8088system.

tq7
 9, What ouFut funciion is performedby pin 29 of dle 8088 when i" the minimum
mode?Maximummode?
10. Is the sienalN4,/I'O
an input or output of the 8086?
11. Nameonesignalthatis suppliedby lhe 8088but not by the 8086.
12. Are the signalsQSo and QSL producedin lhe minimum mode or maximum

Section8.3
13. Wlar are rhe word lengths of the 8088\ addrcssbus and data bus? The 8086's
address busanddatabus?
14. Does$e 8088havea multiplexedaddress/dara bus or independentaddressanddata
buses?
15. What mnemonicis usedto identifythe leastsignificanibit of the 8088'saddress
bus?The most significantbir of the 8088'sdatabus?
16. \l/llat does statuscode SlSr : 01 mean in terms of lhe memory segmentbeing

17. Which output is usedto signal exiemal circuity fiat a byte of datais availableon
the upperhalf of the 8086'sdatabus?
18, What doesthe logic level on M,{b signal to extemal circuitry in an 8086 micro,

19. Which outputis usedto signalexternalcircuity in an 8088-based microcomputer

lhat valid datais on the bus during a write cycle?
20. What signal does a nininun-mode 8088 respondwith when it acknowledgesan
aciive inlerupt request?
21. Wlich sigr)alsimplement the DMA interface in a mininun-mode 8088 or 8086 l
microcomputersystem?
22. Lisi the signalsof the 8088 that are put in the high-Z staie in responseto a DMA

Section8.4
23. ldentify the signal lines of tbe 8088 that are different for the minimum-modeand
ma,{imummodeinterfaces.
24. Wharsiatusoutputsof the 8088areinputsto rhe8288?
25, Whar maximun'mode contol signalsare generatedby the 8288?
26. What function does the LOCK signal serve in a ma{imum mode 8088 micro-
computersystem?
27. What statuscode is output by the 8088 to rhe 8288 if a memory read bus cycle is
takingplace?
28. What connand output becomesactiveif the statusinpursof the 8288 are 1002?
29. ff lhe 8088 executesa julnp instruction,what queuestatuscode would be output?
30. What signalsare provide.dfor local bus control in a ma{imum-mode8088 system?

394 The 8088 and 8086 Micfoprocessors Chap. 8

Section8.5
31. ffiat is the range of power suppty voltage over which rhe 8089 is guarant€edto
work correcily?
32. What is the maxinum valueof volragerhatis considereda valid togic 0 ar bit D0 of
the 8088'sdatabus?Assumerhat the oueut is sintdng2 InA.
33, What is the mininum value of voltage that would rcpresenra vatid togic 1 at rhe
INTR input of rhe 8088?
34. At what value curent is Volmd measuredon the 8086?

Section8.6
35. At v,hat speedsare 8088sgenerallyavaitable?
36. What frequencycrystal must be connectedberweenihe Xr and X? inputs of rhe
clock generatorif an 8088-2is ro run ai tul1 speed?
37. What clock ourputsare produce.dby the 8284?Wlat would be their frequenciesif
a 30-MHz crystal were used?
38. What are the logic levels of the clock waveformsapplied ro the 8088?

Section8.7
39. How many ciock sraresare in an 8088 bus cycte that has no wait states?How are
thesestatesdenoted?
40. Wlat is the durationofthe bus cycle for a 5 MHz 8088 that is running at tuI1speed
and with no wait stares?
41. What is an idle srate?
42. Wlat is a wait stare?
43. If an 8086running at 10 MHz perfonnsbus cycleswith two wail states,wharis the
durationof the buscycle?

Section8.8
44. How is the memory of an 8088microcompurerorganizedfrom a hardwarepoinr ot
view? An 8086 microcompurer?
45, Give an overviewof how a byte of datais readfrom memoryaddrcssB0003t6of an
8088-basedmicrocornpute! and list the memory control signals along with their
activelogic leveis that occur during the memoryreadbus cycle.
46. Give an overview of how a word of data is wriften to memory starting ai actdress
A000016of an 8088 basedmicrocompute! ,nd tisi the memory conaol signats
togetherwith their acrivelogic levelsthat occur dwing the mernorywrite cycle.
47. In which banl of memoryin an 8086-basedmicroconputer areodd-adatressed byres
of datastored?Whar bank selectsignalis usedto enablethis bant of memory?
48. Over which of the 8086'sdarabus lines areeven addressedbyresof daratransferred
and which bank selecrsignal is active?
49, List the memory control signalsrogetherwith their active logic levels that occur
when a word of data is writter io memory addressA000016in a minimum,mode
8086microcomputer system.

399
 50. List the memory conlrol signals togetherwith their active logic levels that occur
when a byte of data is wditen to memory address8000316in a minimum-mode
8086 miffocompurer Over which datalines is the byte of datatransfered?

Section8.9
51. In a naximum-mode 8088 microcomputer,what code is oulput on SaSrwhen an
iDs.ruction'fetchbus cycle is in progress?
52. What is the value of SaS3if the operandof a pop instruction is being read from
memory?Assumethe microcomputeremploysthe 8088 in the maximumnode.

S e c t i o8n. 1 0
53. mich of dre 8088'smemory control signalsis the complementof the correspond-
ing signalon the 8086?
54. What memorycontrol ouipur of ihe 8088 is not providedon the 8086! What signal
replaces it on ile 8086?
55. In a maxirnum-node 8088 basedmicrocornpuie! what memory bus statuscode is
output when a word of instruction code is fetchedfrom memory?Wbich memory
control outputG)is (are) Foduced by the 8288?
56. In ma{mun node, what memory bus statuscode is output when a destination
operard is writlen to memory?Wlich memory control output(s)is (are) produced
by the 8288?
57. When the instruciion PUSH AX is executed,what addressbus status code and
memorybuscycle codeare outputby the 8088 in a rnaximum,modemiffocomputer
system?Which conlmandsignalsare output by the 8288?

Section8. i I
58. How mary clock statesare in a readbus cycle that hasno wait states?What would
be the duraiion of this bus cycle if the 8086 were operatingat 10 MHz?
59. What happensin the TL part of the 8088'smemory reador wrire bus cycle?
60. Descdbethe bus activity that takesplace as an 8088, in minimurn mode, wites a
byte of datainio memory address8001016.
61. Wtich two signalscan be used to determinethat the current bus cycle is a write

62. Which signalcan be usedto identil' the stmt of a bus cycle?

Section8. i 2
63. Give an ove iew of the function of each block in the memory interfacediagram
shownin Fig. 8-24.
64, When the instructionPUSH AX is executed,what bus statuscodeis output by the
8086 in maximun mode, whal are the logic levels of Ao and BHE, and what
rcad/write control signalsaft producedby the bus controller?
65. Wlat type of basic logic devicesis providedby the 74F373?
66. Specilythe logic .ererrol Bl-tLL.lTwRC. raRDC.aodAa $hen rJre808bIn l-r8.
8 24 rcadsa word of datafrom address12340H.

400 The 8088 and 8086 ^,licroorocessoE Chao. I

67. Make a truth tab1e.using the circuits in Figs. 8 27 and 8 28, to speciryine logic
levels of RDu, RDr, wRu, wRb BIIEL, MRDC. MWTC, and AoL when the

(a) readsa byte from address01234H

(b) writesa byteto address 01235H
(c) readsa word from address 01234H
(d) writes a word to address01234H
68. wlat logic devicesare Fovided by the 74F245?
6c. lD lhe circuirof Fig. 8 30. $ha' logic level.muqrbe dpptiedro the DE\ and DT/R
inputs to causedata on the systemdatabus to be transferredto the microprocessor

70, MaLe a drawing lite ihat shownin Fig. 8-30 to illustrate the data bus tansceiver
circuit neededin an 8088-basedmicrocomputersystem.
71. How nany addressiines must be decodedto generatefive chip selectsignals?
72. Name an IC that implementsa twoline to tbur-Linedecoderlogic tuncrion.
7 3 . I f l h e i n p u r " r o7r 4 F l l 8d e c o d ea 'r eC L C , ^ 0 . G . 8 0 . a n a C B q- l 0 l
, which output is active!
7,1. MaLe a drawing for a ninimum-mode 8088-base.dmicrocomputerfor which a
74F138 decoderis used to generateMEMR and MEMW from the RD, WR, and
IO,M sigftls.

Section8. | 3
75. What doesPLA standfor?
76. List tkee properies that measue the capacityof a PLA.
77. wlat is the programmingmechanismusedin the PAL called?
78. What doesPAL standfor? Give the key diftbence betweena PAl- and a PLA.
79. Redmw the circuit Eol,n in Fie. 8-3?(b) to illostrate how it can implement lhe
logictunctionF: (AB + AB).
80. How many dedicatedinputs, dedicatedoutputs, prograrnmableinput/outpuis.and
Foduct tems are suppoftedon the 16L8 PAl?
81. what is the rnarimun numberof inputs on a 20L8 PAL? The maximun Dunber of

82. How do the outputsof dre 16R8differ ftom thoseof the 16L8?
83. Usea lol8 ro decodeaddre- line' ArTLLluougn Arqr to generaFCh throughCLa.

SectionB.l4
84. Name the two types of inpuUoutput.
85. What type of I/O is in use when peripheraldevicesare rnapp€dto the 8088's l/O
address space?
86. Which type of I/O hasthe disadvantagethat part of the addressspacemus.be giYen
up to implementI/O ports?
87. wlich type of I/O has the disadvantageihat all I/O datatransfersmust take place
rhrcughthe AL or AX register?

401
 8.l5
Section
lires relaiilc to an iso-
St Wr.ata.. tle runctionsof the 8088s addressandd'itabus
latedl/O operation l
indicatesto Dxremal
89. In a mininun-node 80118microcompulerwhich lignal
nol lhe menory
cifcuiry that the curent bus cycle is lbr rhe t/O inledaceand

l/O inrerlacein Fig'

90. List the differencesbetweenrhe 8088'snininun-mode
8-46(a) andtharofthe 8086in Fig s-46(b)
beiwecnrhesignalsIO/M andM OI
91. Whatis lhe logic relationship
92. In a m.tiimum-modcsvstem'whichdeviceprcduces theinput(rexd)output(wnte)'
.mdbuscontd sign.tlsfor LheI/O interlace?
circuit in Fig
93. Briefly describethe functionof eachblock in the I/O inteiface
817(a).
94. ln a maximum'node80i16microcomputer what statuscodeidentificsan inputbus

95. ln rhemax.mum-rn.d< Lo,nrerla.eJrownin l:a c 4-'ur' whJlarethcloSr(lev-

.r' ot ibnC, iOrr,C.ara atOuC d rins31uurpur bJ' clcle'l

8.I 6
Section
96. How manybits arei)r the 8088'sI/O address'l
9?, wblt is therangeof byte addresses in lhe 8088'sI/o addressspdce?
spacein lermsol wotd-wideI/o porls?
98. What is the sizeof ihe 8086'sI/o 0ddr€ss
99, ln rn 8086-based lnicrocomPuter syslem,whatArethe logic levelsol Ao 4ndBHE
*lr"n o tyr" ul aomis beilu written to l/O addrcssA00016lIf a word of dalais
beingwriltento address A000r6?
100. In an 8088 microco[]puter$yslem,how mrny buscyclesare I equired-to outputa
wordof datato I/O address AOO0ld? In aI1801t6microcomputef system?

8.l7
Section
101, Describethe operalionperfornedby the instfuctionIN AX' 1AH
102. Write an instluclionsequence to pedbrn the sameoperutionas thatof theinstruc
tion in problem101.but this tinreusevariableor indirec!I/O
AL'
103. Delcribethe operationpertbrncdbv the instructionOUT 2AH
104. Write an insirltctionsequence thatoutputs the byie of dala 0Fr6 to an dutpulpod at
address10006
105. Write a sequencc of insructionsthatinputsthebvteof darafion1inputpofs at l/O
in
aaaresses A.OOO*and 800016.addsthesevaluestogether'and savesthe sun
lnemorylocationlO SUM.
r h e i n p Jpl o n a r l / O
1 0 6 .W r : r e J' e q u e r t r \ 'ionl' r r t r c L rruhnl 'r r l i n T ulrn c c o n l e n l ' o l
d o d r e '8 0 J n Jj l m p r o r h eh ( e r n r g i r o J e n h ( r o J l i n e e n l i h <hdv l h eL r b e l
d
"
ACTIVE INPUT if the lcastsignilicanlbit of the datais I

The 8088 and 8086 Microprocesso6 Chap S

4|J2
Section
8.l8
10?. In the 8088's input bus cycle, during which T siate do the IO/M, ALE. m. and
DEN control signalsbecomeactive?
108. During which T statein the 8088'sinput buscycle is the ad&essoutputon the bus?
Arc darareadftom the busby rhe MPU?
109. If an 8088is midne at 5 MHz, wharts tte durationof the outputbusoperationper-
lbrmed by executingthe insEuctionOUT 0C0H, AX?
110. If an 8086 running at l0 MIIZ tusertstwo wai. statesinto aI UO bus cycles,what
is the duation of a bus cycle in which a byte of daia is being output?
111. If the 8086 h problem 110 ouFuis a wod of dala to a \yod-wide porr ar I/O
address1A116,whar is the dumrion of the bus cycle?

4|)3