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Abstract— In chip manufacturing technology, reduction in LFSR is used in BIST for generating pseudo random
chip size possess great concern for power dissipation. Low power sequences. Advantage of pseudo random testing is that it has
testing has become an important issue as power dissipation very simple hardware which can be implemented for on chip
during testing mode is very high as compare to normal mode. test generation. Low power LFSR has gained importance
LFSR is used in testing of ASIC chips by generating pseudo because besides BIST, it has wide usage in encryption
random patterns. This paper deals with design of low power circuitry, data compression circuitry and cryptography.
LFSR by using GDI technique. GDI technique is one of the low
power technique used for implementing various digital circuits. Power dissipation in digital circuit is mainly by three
This technique uses only two transistors to design fast and low main sources [3]. In the below equation (1) , Pswitching
power circuits with improvement in power characteristics. LFSR constitutes dynamic power dissipation while Psc + Pleakage
has been implemented by conventional and GDI technique in constitutes static power dissipation. Static power contributes
Cadence Virtuoso at 90nm technology. Comparative analysis is negligible to the power dissipation, therefore only dynamic
carried out between the two methods showing upto 45.4 % and power dissipation is considered for analysis. Average power
20 % reduction in power and area respectively in GDI technique. Pavg is given by:
Simulation and variation of power with frequency and voltage is
also discussed. Pavg = Psc + Pleakage+ Pswitching (1)
Fig 8: GDI based LFSR Table 2: Comparison of CMOS and GDI based DFF
Fig 9 shows Layout of GDI based LFSR where DFF and Xor Power(µw) 14.2 7.31
is implemented using GDI technique. Transistors 40 25
Area(µm2) 128.88 103.5
150
Power(µw)
50
60
[4] Balwinder Singh and Arun Khosla “Power Optimization of Linear
40 Feedback Shift Register (LFSR) for Low Power BIST” 2009 IEEE
International Advance Computing Conference (IACC 2009) Pages: 311
20 - 314
[5] Doshi N. A., Dhobale S. B., and Kakade S. R. “LFSR Counter
0 Implementation in CMOS VLSI” World Academy of Science,
Engineering and Technology 48 2008
0.7 0.75 0.8 0.9 1 1.1 1.15
[6] LaxmiKumre, Ajay Somkuwar , Ganga Agnihotri3 “Design of Low
Vdd(volt) Power 8 bit GDI Magnitude Comparator” International Journal of
Emerging Technologies in Computational and Applied Sciences, 4(1),
March-May 2013, pp. 102-108
CMOS GDI
[7] Gowthami, M.R.; Kiran, N.R.; Harish, G.; Yellampalli, S., "Test power
aware STUMP BIST," in SmartTechnologies and Management for
Computing, Communication, Controls, Energy and Materials (ICSTM),
Fig 12: Power variation with change in supply voltage 2015 International Conference on , Vol., No., pp.434-438, 6-8 May2015.
[8] Seongmoon Wang; Gupta, S.K., "DS-LFSR: a new BIST TPG for low
heat dissipation," in Test Conference, 1997. Proceedings., International ,
200 Vol., No., pp.848-857, 1-6 Nov 1997
[9] E. Abiri, M. R. Salehi and A. Darabi, "Design and simulation of low-
150 power and high speed T-Flip Flap with the modified gate diffusion
input (GDI) technique in nano process," 2014 22nd Iranian
100 Conference on Electrical Engineering (ICEE), Tehran, 2014, pp. 82-
87.
50 [10] M. Soundharya and R. Arunkumar, "GDI based area delay power
efficient carry select adder," 2015 Online International Conference on
0 Green Engineering and Technologies (IC-GET), Coimbatore, India,
CMOS GDI 2015, pp. 1-5.
[11] Michael L.Bushnell, VishwaniD.Agawal," Essentials of electronic
NMOS PMOS testing for digital, memory and mixed-signal VLSI circuits," Kluwer
Academic Publishers, 2000.
[12] Morgenshtein, A. Fish, I. A. Wanger, “Gate-Diffusion Input (GDI): A
power efficient method for digital combinational circuits,” IEEE Transl.
Fig 13: Comparison for the No. of Transistor in CMOS and GDI based on Very Large Scale Integration (VLSI), vol. 10, No. 5, 2002, pp. 566-
LFSR 581
[13] Atul Kumar Nishad,RajeevanChandel “Analysis of Low Power High
Performance XOR Gate Using GDI Technique”. 2011 International
Conference on Computational Intelligence and Communication
VI. CONCLUSION Networks, pp.187-191.
In this paper we have implemented LFSR by CMOS and GDI [14] Morgenshtein, A.; Fish, A.; Wagner, I.A., "An efficient implementation
technology at 90nm in Cadence Virtuoso. Simulations as well of D-Flip-Flop using the GDI technique," in Circuits and Systems, 2004.
ISCAS '04. Proceedings of the 2004 International Symposium on, Vol.2,
as different parameter comparison were carried out between No., pp.II-673-6 Vol.2,23-26 May 2004
CMOS and GDI based LFSR. Results are compared in table 2.
Based on transistor level simulation, GDI technology reduces
power dissipation and hardware by 45.4% and 20%
respectively. Therefore, as scaling of devices is increasing, the
proposed LFSR design can be used in low power testing.
REFERNCES
[1] R. VaraPrasadaRao, N. AnjaneyaVaraprasad, G.SudhakarBabu, C.
Murali Mohan “Power Optimization of Linear Feedback Shift
Register(LFSR) for Low Power BIST implemented in HDL” 2013
International Journal of Modern Engineering Research (IJMER) Vol 3,
Issue.3, May-June. 2013 pp-1523-1528J. Clerk Maxwell, A Treatise on
Electricity and Magnetism, 3rd ed., Vol. 2. Oxford: Clarendon, 1892,
pp.68-73.
[2] P. Balasubramanian and J. Joh, "Low power digital design using
modified GDI method," International Conference on Design and Test of
Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., Tunis,