Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Course
Course Class & Batch Semester Course Faculty
code
Linear Integrated Circuits and II BE-EEE
EE6303 III
Applications (2017 Batch)
UNIT I IC FABRICATION
5. Find the input voltage of an ideal op-amp. Its one of the inputs and output voltages are
2v and 12v. (Gain=3)
a. 8v
b. 4v
c. -4v
d. -2v
6. Which factor determine the output voltage of an op-amp?
a. Positive saturation
b. Negative saturation
c. Both positive and negative saturation voltage
d. Supply voltage
7. Free running multivibrator is also called as
a. Stable multivibrator
b. Voltage control oscillator
c. Square wave oscillator
d. Pulse stretcher
8. At which state the phase-locked loop tracks any change in input frequency?
a. Free running state
b. Capture state
c. Phase locked state
d. Uncontrolled state
9. Match the list I with list II which represents the three stages of phase locked loop.(PLL)
List I List II
1.Before input frequency applied i. PLL-Phase locked state
2.When the input frequency applied ii.PLL=Free running state
3.After input frequency applied iii. PLL-Capture mode
a. 1-ii, 2-iii, 3-i
b. 1-iii, 2-ii, 3-i
c. 1-i, 2-ii, 3-iii
d. 1-ii, 2-i, 3-iii
15. What is the purpose of differential amplifier stage in internal circuit of Op-amp?
a. Low gain to differential mode signal
b. Cancel difference mode signal
c. Low gain to common mode signal
d. Cancel common mode signal
16. In LM317 voltage regulator, what is the minimum value of voltage required between its
input & output in order to supply power to an internal circuit?
a. 1V
b. 3V
c. 5V
d. 10V
17. For a PLL IC 565 with timing resistor & timing capacitor of about 15 k & 0.02F
respectively, what would be the value of output frequency (f0)?
a. 433.33 Hz
b. 833.33 Hz
c. 1000 Hz
d. 2500 Hz
18. In VCO IC 566, the value of charging & discharging is dependent on the voltage applied
at__________
a. Triangular wave output
b. Square wave output
c. Modulating input
d. Sine wave output
19. According to transfer characteristics of PLL, the phase error between VCO output &
incoming signal must be maintained between _______ in order to maintain a lock.
a. 0 &
b. 0 & /2
c. 0 & 2
d. & 2
20. In DACs, gain error occurs due to _________.
a. offset voltages of op-amps
b. leakage current in the switches
c. error in feedback resistor value
d. error in current source resistance values
21. In a peak detector circuit, which component holds the peak value till a higher peak
value is detected?
a. Diode
b. Inductor
c. Capacitor
d. MOSFET switch
22. In hysteresis width, the hysteresis voltage is equal to _______ upper & lower threshold
voltages (VUT & VLT).
a. sum of
b. difference between
c. product of
d. division of
23. In an inverting Schmitt Trigger circuit, the hysteresis ________ is also known as
'hysteresis width'.
a. voltage
b. current
c. resistance
d. power
24. Which among the following circuits is known as ' Threshold Detector '?
a. Window detector
b. Over voltage indicator
c. Level detector
d. Zero crossing detectors
25. In absence of any applied AC input signal, what would be the gain of an ideal
integrator?
a. Zero
b. Unity
c. Infinity
d. Unpredictable
26. In an inverting ideal integrator, which component exhibits the feedback path
connection?
a. Resistor
b. Inductor
c. Capacitor
d. Diode
27. Which performance parameter of a regulator is defined as the change in regulated load
voltage due to variation in line voltage in a specified range at a constant load current?
a. Load regulation
b. Line regulation
c. Temperature stability factor
d. Ripple rejection
28. Which among the following characteristics of D/A converter occur/s due to resistor and
semiconductor aging?
a. Speed
b. Settling time
c. Long term drift
d. Supply rejection
29. For reducing the effects of input offset in comparator, what would be the possible value
of input offset voltage?
a. Low
b. Moderate
c. High
d. Zero
30. Zero crossing detector circuit plays a crucial role in conversion of input sine wave into a
perfect _________at its output.
a. triangular wave
b. square wave
c. saw-tooth wave
d. pulse wave
UNIT IV SPECIAL ICs
Functional block, characteristics & application circuits with 555 Timer Ic-566 voltage
controlled oscillator Ic; 565-phase lock loop Ic ,Analog multiplier ICs.
32. For non-inverting adder, which theorem is applicable to determine the expression for
output voltage?
a. Thevenin's
b. Norton's
c. Miller's
d. Superposition
39. On which of the following does the conversion depend in ladder-network conversion?
a. Comparator
b. Control logic
c. Digital counter
d. Clock
40. How many Vcc connections does the 565 PLL use?
a. 0
b. 1
c. 2
d. 3
41. When is the counter set to zero in the dual-slope method of conversion?
a. Prior to the charging of the capacitor of the integrator
b. While the capacitor is being charged
c. At the end of the charging of the capacitor
d. During the discharging of the capacitor
42. Which of the following best describes the output of a 566 voltage-controlled oscillator?
a. Square-wave
b. Triangular-wave
c. Sine-wave
d. Both square- and triangular-wave
a. distortion
b. negative feedback
c. positive feedback
d. open-loop
46. The ratio between differential gain and common-mode gain is called:
a. amplitude
b. common-mode rejection
c. differential-mode rejection
d. phase
47. One input terminal of high gain comparator circuit is connected to ground and a
sinusoidal voltage is applied to the other input. The output of comparator will be
a. a sinusoid
b. a full rectified sinusoid
c. a half rectified sinusoid
d. a square wave
48. The most commonly used amplifier in sample and hold circuit is
a. a unity gain inverting amplifier
b. a unity gain non inverting amplifier
c. an inverting amplifier with a gain of 10
d. an inverting amplifier with a gain of 100
1. c
2. a
3. b
4. a
5. d
6. c
7. b
8. c
9. a
10.b
11.a
12.a
13.d
14.a
15.d
16.b
17.b
18.c
19.a
20.c
21.c
22.b
23.a
24.c
25.c
26.c
27.b
28.c
29.a
30.b
31.a
32.d
33.b
34.c
35.a
36.b
37.b
38.c
39.a
40.c
41.c
42.d
43.a
44.d
45.b
46.b
47.d
48.b
49.b
50.c