CSE 493/593 Fall 2011

Solution 1

1. The voltage transfer characteristics for an inverter is shown in Fig. 1. What

are NML and NMH of the inverter?

Vo

3V

0V 1V 2V 3V Vi
Fig. 1 Transfer characteristics of an inverter

Answer:
VIL=1V, VOL=0V, so NML=1V
VIH=2V, VOH=3V, so NMH=1V

2. Draw the transistor level schematic diagram of the CMOS gate that
implements function Z:
a. Z = A B C + D + E'
b. Z = (A B C + D)
Assume that the Primary Inputs available are A, B, C, D and their
complements.

1
Answer:

3. For the following NMOS and PMOS transistors, determine the region of
operation (saturation, triode, cutoff) and the drain current ID for each of the
biasing configurations given below: (assume, for NMOS: direction of ID is Drain
to Source, PMOS: direction of ID is Source to Drain). Use the following
transistor data: NMOS: kn = 60A/V2, VTO = 0.65V, = 0.1V1. Assume (W/L)
= 1. All calculations/steps to derive the result should be shown.

a. NMOS: VGS = 3.3V, VDS = 3.3V; PMOS: VGS = 0.5V, VDS = 1.5V.
b. NMOS: VGS = 3.3V, VDS = 2.2V; PMOS: VGS = 3.3V, VDS = 2.6V.
c. NMOS: VGS = 0.6V, VDS = 0.1V; PMOS: VGS = 3.3V, VDS = 0.5V.

Answer:
a. NMOS: Since VDS > VGS Vt (3.3 > 3.3 0.65), the device is in saturation.
Therefore,

Plugging the values, we have ID = 280.197A

PMOS:
Since |Vgs| < |Vt|, the device is turned off. Therefore, Id = 0.

2
b. NMOS: VGS = 3.3V, VDS = 2.2V; PMOS: VGS = 3.3V, VDS = 2.6V.
Since VGS > Vt and VDS < VGS Vt, the device is in linear region.
Therefore,

Plugging the values given, we have Id = 204.6A.

PMOS: Since |Vgs Vt| = 2.65, thus, |Vds| < |Vgs Vt|, the device is in linear
region of operation
Therefore,

Plugging the values given, we have Id = 210.6A.

c. NMOS: VGS = 0.6V, VDS = 0.1V; PMOS: VGS = 3.3V, VDS = 0.5V.
Since VGS < Vt, the device is in cutoff and there is no ID current: ID = 0A.
PMOS:
Since VGS > Vt and VDS < VGS Vt, the device is in linear region.
Therefore,

Plugging the values given, we have Id = 72uA.

4. Consider the circuit in Fig.2.

(a) What is the logic function implemented by this circuit?
(b) How would you implement this function with PMOS-only switches? Assume
both true and complimentary input signals are available.

Fig. 2 Circuit

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Answer:
(a) D = AB C + ABC + A BC

(b) /A, /B, /C represent A , B , C .

B /C

/B C

A D

/B /C

/A

5. Assume inputs and its complements are available. If a Boolean function is

D = A BC + AB C + AC + B C , then:

(a) Please implement the function using transmission gate and draw the
transistor level schematic diagram.
(b) Please implement this function using a compound CMOS gate and draw
the transistor level schematic diagram.

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Answer:
(a) /A, /B, /C represent A , B , C .
B C

/A

/B /C
/B C

B /C
/C

D
A

C
/C

/B

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(b) /A, /B, /C represent A , B , C .

Vdd

A /A /A B

/B B

/C /C C C

A /B /C

/A B /C

/A C

B C

Gnd