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Dr DC Hendry
March 6, 2006
The designs which we have studied so far have all considered combinational
logic, that is, logic whose outputs depend only on the inputs. The circuits we
will now study contain memory, and so their output depends on both the current
inputs, and the data stored in those memories.
Two types of memory element will be considered, the first is the latch, and the
second is the flip-flop. The latch is the more fundamental element and should
already be known to you.
1 Latches
1.1 SR Latch
S
Q
Q
R
For an SR latch the following waveform applies. No logic delays are shown in
this diagram:
S
Q
Q
R
Clk
Clk
1.3 D Latch
1. By far the most important of the clocked latches however is the clocked
D latch.
2. This latch has a single data line, D, as input.
3. The effect is that D is only copied to the output Q when the clock is
active.
D
4. Clk
The D latch waveforms show that the output Q only follows (i.e. is the same
as after a small delay) the input D when the clock signal is active, that is 1
for a positive D latch.
Clk
S Q
R Q
Clk
D Q
Clk
2 Flip-Flops
The clocked latches, in particular the D latch, allow data to flow through
then the clock signal is active. This behaviour turns out to make the design
of sequential digital systems difficult. A far more useful device is the edge
triggered flip-flop, or the master-slave flip-flop. Both of these devices have the
same behaviour, but internally are constructed with different circuitry.
Note that the term flip-flop originally referred to both latches and the devices
we now refer to as flip-flops, in todays terminology a flip-flop (usually!) does
not include latches, only the edge-triggered and master-slave designs.
Q
D D Q D Q Q
Q Q Q
Clk Clk
Clk
Note how the first of the two latches is only open (that is, its Q signal follows
the D signal) only when the clock signal is low, while the second latch is open
only when the clock signal is high, both latches are never open at the same point
in time. A typical waveform then for the above circuit is as follows:
Clk
Clk
Q0
The sampling nature of the flip-flop is denoted by a small triangle on the clock
line of the device. The presence of a negation bubble indicates a negative edge
triggered device. Symbol for a positive edge triggered flip-flop:
D Q
D Q
3 VHDL Descriptions
We now turn to VHDL descriptions of both latches and flip-flops. At the same
time additional features will be added to these devices in the form of set and
reset lines. These lines may be asynchronous or synchronous.
The following code describes a D latch. Note that both of the inputs to the
circuit, clk and D are in the sensitivity list of the process.
library ieee;
use ieee.std logic 1164.all;
entity dlatch is
port( clk : in std logic;
d : in std logic;
q : out std logic;
qbar : out std logic);
end entity dlatch;
Consider how this description behaves when either of clk or d changes value. If
the clock signal clk changes value, then since it is in the sensitivity list of the
process, the process starts to execute from the first sequential statement. If the
clock has just changed to 1, then d is copied to q (and its inverse to qbar).
This is the behaviour we would expect from the real latch, as the latch opens
the input is copied to the output. If the clock has just changed to 0, then no
copying is done. When d changes value, again the process is run. Now if the
clock is 1, d is copied to q, but if the clock is 0, no copying is done. Again,
this is the behaviour of the real circuit, and so this description does describe
the real latch.
Most importantly, given this code, a synthesis tool will infer from this code the
use of a D latch. Other code too, can infer a D latch.
library ieee;
use ieee.std logic 1164.all;
entity dff is
port(clk : in std logic;
d : in std logic;
q : out std logic;
qbar : out std logic);
end entity dff;
1. The code clkevent and clk = 1 denotes a rising edge on the clock
signal.
2. On a rising edge d is copied to q, and the inverse to qbar.
3. Note that we must use qbar <= not d;, we cannot use qbar <= not q;
as q is an output and cannot be read.
4. This code, and other similar constructs, will cause a synthesis tool to infer
a D flip-flop.
Many flips-flops (and latches) need to be placed into a specific start up state.
When powered up a flip-flop or latch takes a random state. Therefore many
flip-flops include a set line, a reset line, or both.
The VHDL code for a D flip-flop with active low synchronous set:
library ieee;
use ieee.std logic 1164.all;
entity dffs is
port(clk : in std logic;
set n : in std logic;
d : in std logic;
q : out std logic;
qbar : out std logic);
end entity dffs;
The important point about a synchronous set (or reset) is that no effect occurs
until the next active edge of the clock (that is, a rising edge for a positive edge
triggered device, the falling edge for a negative edge triggered device). This is
shown in the next waveform.
Clk
set n
The VHDL code for a D flip-flop with active low asynchronous reset:
library ieee;
use ieee.std logic 1164.all;
entity dffr is
port(clk : in std logic;
rst n : in std logic;
d : in std logic;
q : out std logic;
qbar : out std logic);
end entity dffr;
Clk
rst n