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Strong Inversion: The strong inversion condition:

Nanoelectronic Devices 2kB T



NA
 
ni
2 
qs

Pere Barber Llorens, UAB 17-18, MANN s = 2B = ln exp =1
q ni NA kB T
Its satisfied when the e concentration in the surfaces
1 Nanoelectronic FET Devices equals the h+ concentration in Si bulk. In this regime, a
small variation of s induce a great change in n(x).
1.1 MOS structure s
n2 q
 
MOS (Metal - Oxide - Semiconductor) structure: d 2kB T NA q
= + i2 e kB T
dx Si kB T NA

Charge
q per area e conc. at surface
qs
2Si kB T n2i 2k n2i kqsT
Qi = NA e BT n(0) = NA2 e B

Depletion: Following the depletion approximation


(with 1D uniform doping):
2
D x)
QD = qNA WD E = qNA WDSix = qNA (W2 Si

s
2
WD 2Si s
s = (x = 0) = qNA 2Si WD =
qNA

The maximum depletion width (when s = 2B ):


s
4Si kB T ln(NA /ni )
WDM =
q 2 NA
Some concepts:
qm = VL EF Metal work function This defines the threshold condition of a MOSFET
~
(the length channel L  2WDM ). Even increasing E,
qs = VL EF SemiConductor work function
q = VL Ec Electron affinity you cant go further this width (screening).

qB < 0 n type SC MOS Charge and Potential: The gate voltage equa-
qB = Ei EF
qB > 0 p type SC tion (assuming Vfb = 0):
Different regimes (assuming m = s ) with a ptype SC: Qs Cox = tox
ox
Vg = Vox + s = + s where
Flatband Vg = 0 No field applied. Cox ox Eox = Si Es
Accumulation Vg  0 SC bands bend upwards.
Depletion 0 < Vg < VT SC bands bend downwards. MOS Capacitances: C Cg = d(Q dVg
s)
(gate capaci-
Inversion Vg > VT e accumulated on SiO2 surface. tance). Taking derivatives with the Vg expression:
Poissons equation: is a measure of the bandgap
)
Cg = d(Q
dVg
s)
1 1 1
bending (s is the surface potential). = +
CSi = d(Q
ds
s)
C g Cox C Si
d2 dE q h i
= = p(x) n(x) + ND +
(x) NA (x) When considering the depletion and inversion regimes
dx2 dx Si | {z } | {z }
mobile carriers fixed charges we have to considerate Cd and Ci capacitances (in the
inversion regime Qs = Qi + Qd ).
q
p(x) = NA e kB T
With a ptype Si: q
C V Characteristics: Depending on the applied fre-
n2
n(x) = NAi e kB T quency, we can have three different CV representations:

d2 q

n2i  kqT  1. Low Frequency measurement (low time in com-
kqT
 
= N A e B 1 e B 1 parison to the carriers movement):
dx2 Si NA
Accumulation: Cox  CSi . Therefore C ' Cox .
Its analytical solution: Depletion: As Vg W Cd and domi-

q

n2i
 q  nates over Cox .
C e kB T + kq 1 + 2 e kB T q
1
BT NA kB T Inversion: Ci  Cd and due to saturation
p Ci  Cox . Therefore C ' Cox .
2 2kB T NA C Qs = 2Si kB T NA C
E (x) = 2. High Frequency measurement ( 100 200Hz):
Si (with = s ) Carriers dont have time to reach the surface and
to form a channel: there is no Ci capacitance. It
 
q|s |
Accumulation Qs exp 2k
BT saturates in the inversion regime in Cmin = WDMSi
.
Depletion Qs s
3. Very High Frequency measurement ( kHz): Cd
Weak inversion Qs s  capacitance doesnt have a WDM : there is no inver-
Strong inversion Qs exp 2kqBsT sion layer and we enter in the deep depletion regime
(it leads to the SC breakdown).
The depletion and weak inversion happen in s = 2B
Some effects that have an impact on the MOS: Gradual channel approximation: This approxima-
1. Effect of Gate Work function: If m 6= s , we can tion (ideal transistor) assumes that vertical field is
consider 3 cases: stronger than the lateral one (in the channel region) and
2D Poissons eq. can be solved as 1D:
m = (n+ poly).
Eg
Jn (x, y) = qn n(x, y) dVdy(y) Ids (y) = eff W dV
dy Qi (y)
m = + 2q . R xi
Eg +
where Qi (y) = q 0 n(x, y)dx (xi is the surface layer
m = + 2q (p poly). thickness). Assuming neither recombination nor genera-
Then, the threshold voltage VT = m s + 2B + Vox tion, we integrate the current:
(when m = s VT =For instance, with a n+ polySi gate
W Vds
Z
on a ptype Si Ids is independent
Ids = eff (Qi (V ))dV
  L 0 of the position
Eg kB T NA
ms = B = 0.56 ln
2q q ni Charge sheet approximation: It assumes that all the
inversion charges are located at the Si surface (like a
2. Effect of Poly-Si Gate Depletion: Due to this effect, sheet of charge) and there is no potential drop across the
there is an extra contribution to the gate capacitance: inversion layer. Having s = 2B + V (y) :
Qs 1 1 1 1
Vg = Vfb + s + p = + + Depletion charge QD = qNA WDM = 2Si qNA s
Cox C Cox CSi Cp Total charge Qs = Cox (Vg Vfb s )
This is equivalent to have a thicker oxide. Inversion charge Qi = Qs QD
p
3. Effect on Interface traps and oxide charge: This Qi = Cox (Vg Vfb 2B V ) + 2Si qNA (2B + V )
effect is added in a balance way with the four contri- Integrating Ids with all these constrains:
butions (some negative gate voltage is needed to reach  
the flatband condition): W Vds
Ids = eff Cox Vds Vg Vfb 2B
L 2
i. Qm mobile ionic charge: Due to the fabrication pro-
W 2 2Si qNA h 3/2
i
cess (contamination during the oxide growth). eff Cox (2B + Vds ) (2B )3/2
L 3Cox
ii. Qot oxide trapped charge: Due to ionazing radiation.
iii. Qf oxide fixed charge: Due to the fabrication process Lets study the region characteristics in a MOSFET:
(as an excess of Si species). 1. Linear region: VT < Vds Vd,sat . We do a pow expan-
iv. Qit oxide trapped charge: Due to the abrupt Si lat- sion with low terms with the Ids expression before:
tice termination (some levels appear within the Eg W
gap). Ids = eff Cox (Vg VT ) Vds
L
4. High-Field effects:
4Si qNA B
i. Leakage mechanism: It produces unwanted quanti- VT = Vfb + 2 B +
Cox
ties of heat.
ii. Fowler-Nordheim tunneling: e tunneling and drift 2. Saturation region: Vds > Vd,sat .
towards the gate (e from Si to the metal).
W h m 2i
iii. Direct tunneling: When reducing tox (oxide width) Ids = eff Cox (Vg VT ) Vds Vds
L 2
tunneling probability grows.
qN /4
where m = 1 + Si CoxA B = 1 + CCDM ox
= 1+ W 3tox
DM
is the
1.2 Long-channel nMOSFETs (LCT) body coefficient. It expresses the deviation from ideality
in a MOSFET device (usually m ' 1.2). It also stands
nMOSFET is a MOSFET with an ntype channel and a
for the subthreshold slope. The maximum value of Ids is
ptype substrate. It is a 2D device with 2 directions (x is V V
accomplished when Vds = Vd,sat = g m T :
the substrate width direction and y the transport direction
(i.e. the channel)). Depending on the applied Vg : W (Vg VT )2
Ids = Id,sat = eff Cox
Vg < VT No inversion layer: depletion regime. OFF. L 2m
Vg > VT Current flowing (from drain to source). ON. Pinch-off condition: When applying Vds > Vd,sat
the length channel decreases (pinch-off point is
We will assume that the source has the reference potential swifted). This happens during the linear-saturation
and Vbs = 0. Some concepts: transition.
(x, y) Band bending at any point
 (x, y). 3. Subthreshold region: Vds < VT . Considering the de-
V (y = 0) = 0 pletion/weak inversion regime (i.e. s < 2B ):
V (y) Quasi-Fermi potential
V (y = L) = Vds
 2 q(V V )  
Drain current model: There is a modification in the W kB T g T qV
k ds
Ids = eff Cox (m 1) e mkB T
1e B T

previous expressions due to the quasi-Fermi potential: L q


s
n2i V 2Si [V (y) + 2B ] Inverse subthreshold slope
n(x, y) = 2 e kB T WDM (y) =  1
d(log Ids )
 
NA qNA S= dVg = 2.3 mkqB T = 2.3 kBq T 1 + CDM
Cox

where we have used (0, y) = V (y) + 2B as the surface Vg VT


S(RT) = 60xmV/decade m(s ) ' s 2B
strong inversion condition for WDM .
Body-effect: If we apply a Vbs 6= 0, there is a modifi- Velocity-Field relation: Empirical model:
cation in Ids and VT expressions. This controls the VT
value.
eff E n = 1 for h+ vsat
v=h where and Ec =
 n i1/n n = 2 for e eff
Z Vds +Vbs p
2Si qNA (2B + Vbs 1 + EEc
Ids (Qi (V ))dV VT = Vfb +2B +
Vds Cox Analytical solution for n = 1:
eff Cox W m 2
 
This has two consequences: L (Vg VT )Vds 2 Vds
Ids =
dVT
1 + veff Vds
sat L
i. Vbs VT and dV bs
= m 1.
Vbs =0
Saturation drain current and voltage:
ii. WD gets larger.
Vg VT
Dependence of VT (T ): For a n+ poly gate: 2 m LCT
Vd,sat = q < Vd,sat
Vg VT
1+ 1+ 2eff mv sat L
Eg Eg 4Si qNA B
Vfb = B VT = +B +
q
Vg VT
2q 2q Cox 1 + 2eff mv sat L
1
Id,sat = Cox W vsat (Vg VT ) q
  Vg VT
kB T NA 1 + 2eff mv sat L
+1
As B = ln = B (T ) VT = VT (T )
q ni (T )
Channel length modulation: When Vds > Vd,sat in a
    SCT the pinch-off point P shifts from drain to source
dVT kB Nc Nv 3 m 1 dEg
= (2m 1) ln + + reducing L by L and Ids increases with Vds in the sat-
dT q NA 2 q dT
uration region.
dVT /dT ' 1mV/K. L
Ids = Id,sat
L L
MOSFET Channel Mobility: Lets study how e go
from the drain to the source. The effective mobility eff is Source-Drain series resistance: With a SCT there is
an averaged value that has to be weighted by the carriers a resistance contribution due to the metal contact with
concentration. the SC. Specially relevant in the linear region.
Z xi  
1 1
n n(x)dx Eeff = |Qd | + |Qi | 1.4 Scaling and design of MOSFETs
Si 2
eff = 0Z xi 1.4.1 MOSFET Scaling
n(x)dx n+ VT + 0.2 Vg VT
Eeff = +
0 3tox 6tox Scaling has given a path to increase the speed of transistors.
Device scaling goal is to achieve density and performance
Plotting eff vs Eeff :
gains and power reduction in VLSI (very large systems in-
Low field region: limited by impurity of Coulomb tegrated).
scattering. 1. Constant Field Scaling
Intermediate field region: limited by phonon scat-
tering eff ' 32500 E 1/3 . In this region, eff does MOSFET and Circuit Parameters >1
not depend on the doping concentration. Device dim. (tox , L, W , xi ) 1/
Scaling
High-field region: limited by surface roughness scat- Doping conc. (NA , ND )
assumptions
tering eff E 2 . Voltage (V ) 1/
Electric field (E) 1
Intrinsinc MOSFET Capacitances: Regions: Derived Carrier velocity (v) 1
scaling Depletion layer width (WD ) 1/
Subthreshold C ' W LCd behaviour Capacitance (C = A/t) 1/
Linear C = W LCox of device Inversion layer density (Qi ) 1
Saturation C = 23 W LCox parameters Current drift (I) 1/
Channel Resistance (Rch ) 1
1.3 Short-channel MOSFETs (SCT) Derived Circuit delay time ( CV /I) 1/
scaling Power dissip. circuit (P IV ) 1/2
In a short-channel MOSFET, L Ids and C and VT behaviour Power-delay prod. circuit (P ) 1/3
becomes more sensitive to L and Vds . of circuit Circuit density ( 1/A) 2
Drain-Induced Barrier Lowering (DIBL): Com- parameters Power density (P/A) 1
paring the Fermi-Dirac distribution for a LCT and a
SCT: Vdd power supply
Depletion width scaling:
bi built-in potential
LCT SCT
Vg < VT , 0 ' Ioff < Ioff . r
LCT SCT 2Si (bi + Vdd )
Vg > VT : Ids < Ids WD = WD /
SCT LCT
qNA
Vds Ioff but Ioff remains the same. r
2Si bi
WS = WS /
Velocity Saturation: Because of velocity saturation, qNA
V V
Id,sat in the SCT happens at a Vd,sat < g m T that is
r
0 4Si kB T ln(NA /ni ) 0

lower than the LCT one. WDM = < WDM /
q 2 NA
2. Generalized scaling: This scaling allows electric field to Channel profile evolution: Reducing the channel
scale up by (E E) while device dimensions scale length results in increasing the doping concentration.
down by . This has reliability and power concerns. And
NA ()NA to keep Poissons equation invariant. Quantum Effect in MOS Inversion: Channel
length reduction leads to a quantum treatment of the
3. Constant Voltage Scaling: = . With this assumption: MOS as carriers are confined in the perpendicular direc-
tion to the surface. Discrete energy levels (triangular
All depletion widths scale in the same factor 1/.
potential well):
NA 2 NA .
2/3
VT roll-off and VT remain unchanged.
 
3hqEs 3 2Ej
Ej = j+ xj =
However, its physically incorrect since E E and 4 2mx 4 3qEs
P/A 23 P/A. dIds
With quantum effects, trasconductance (gm = dVds ) gets
In practice (CMOS), its used a scaling combination of 1-3. reduced.
Non-Scaling Factors:
Eg

NA
 1.5 CMOS performances
Buil-in potential bi as bi ' 2 + ln ni .
1.5.1 CMOS Inverter
Subthreshold current Ids .
Velocity saturation, mobility at higher fields and CMOS Inverter is the simplest transistor. It consists of
oxide reliability. a complementary NMOS and PMOS. Since only one of the
Source and drain series resistance: transistors is on in the steady state, there is no power dis-
sipation.
Doping level limited by solid solubility.
Doping gradient or junction abruptness limited CMOS Inverter Transfer Curve: The sharpness of
by annealing process. the high-to-low transition of the Vout Vin curve is a
PolySi gate depletion. measure of how well the circuit performs digital opera-
tions.
1.4.2 MOSFET Design Switching Waveform for a Step Input: The way to
In order to design a good MOSFET we need to have low VT , calculate propagation delay COMPLETE
low Ioff and great Vdd VT .
Active Power Dissipation: How much power is the
n + p inverter dissipating?
Delay CV /I where =
2
2
where n is a pull-down transition and p a pull-up transition. CVdd
P = where T is a clock period
Choice of Gate Work Function: As T

Qd Propagation Delay:
VT = Vfb + 2B + Vox = Vfb + 2B +
Cox
Delay Equation: It decouples current and capac-
and 2B 1V, Vfb 1V is needed to obtain low VT .
itance: = Rsw (Cout + FO Cin + CL )
VT adjustment: To adjust VT it is necessary to employ
non-uniform channel doping in order to decouple VT and d
0 Rsw : Switching resistance dCL
WDM as they are coupled through NA .
  Cin : Input capacitance
4Si qNA B 6tox Cout : Output capacitance
VT = Vfb +2B + = Vfb + 1 + 2B
Cox WDM FO : # Fan-Outs

High-Low Doping profile: Substrate is uniformly Delay Sensitivity to n/p width ratio: Assum-
doped by NA . Therefore we increase just after the sur- ing Wp + Wn = constant:
face with more dopants (Ns ) until the xs position.
n = p Wp /Wn = 2.5
q(Ns NA )x2s
r
0 2Si n +p
Wp /Wn = 1.5
K 2B WDM = K 2
2Si qNA
Delay Sensitivity to Channel Length: There
1 p q(Ns NA )xs is a reduction of delay (i.e. the device works faster)
VT = Vfb + 2B + 2Si qNA K +
Cox Cox when reducing the channel length.
0 Delay Sensitivity to Oxide Thickness: There
WDM and VT .
0
is no propagation delay when modifying the oxide
Low-High Doping profile: VT and WDM . thickness.
s Delay Sensitivity to Vdd and VT : Its desirable
0 4Si B
WDM = + x2s to keep the ratio Vdd /VT < 0.3.
qNA

qNA 0 qNA xs
VT = Vfb + 2B + WDM
Cox Cox
1.6 More Moore nanoelectronic devices
The Moore law says that the number of transistors in a dense
integrated circuit doubles approx. every two years. The more
the gate length is reduced, the more improved are the proces-
sor chips. Thats why these trends signify a challenge for the
semiconductor industry and new materials are being investi-
gated.

1.6.1 CMOS Advanced Devices


1. Silicon-on-Insulator (SOI CMOS): SOI technology al-
lows the reduction of the source and drain junction mit-
igating the body effect.
2. Velocity overshoot: MOSFETs < 200nm, Ids > Id,sat .
Few scattering events. There is neither saturation veloc-
ity nor limitation.
3. SiGe / Strained Si MOSFETs: Enhancement of car-
rier mobility (Rsw and ).

4. Low T CMOS : Greater carrier mobility and steeper


subthreshold slope that leads to smaller Ioff .

1.6.2 Potential solutions and high-key materials


In 2008, SiO2 was changed into HfO2 (HfO2 > 5HfO2 )
due to tunneling effects (leakage current). This allowed
to keep under control the SCT effects.

Multiple gate MOSFETs (MuG): #gates


DIBL (i.e. DIBL is a measurement of the relative VT
variation). Better and more efficient control for the car-
rier mobility in the channel (a 4-gate MOSFET reduces
the subthreshold swing).
low
VT (Vdd ) VT (Vds )
DIBL = low
Vdd Vdd

Other materials: MoS2 (direct bandgap semiconductor


but with low mobility) or WSe2 .
Tunnel FETs: The tunnel transistor changes the n+ by
a p+ in the drain. This scheme enables a filter with the
e to pass through the allowed states. This device is the
best to work in the off state but has less performance
with on currents than the other MOSFETs.

1.6.3 High-performance logic requirements ITRS


ITRS explores the future of transistors. The main priority is
the high performance rather than dissipation problems. For
instance, some of the addressed issues are the delay decreas-
ing, the ballistic enhancement factor, the intrinsic switching
speed, . . .