DESIGN AND IMPLEMENTATION OF NANOSCALE DEVICES USING

NOVEL CHANNEL MATERIALS AND THEIR APPLICATIONS

A

SUMMARY
SUBMITTED TO THE

SHRI JAGDISH PRASAD JHABARMAL TIBREWALA UNIVERSITY,

FOR THE DEGREE

OF

DOCTOR OF PHILOSOPHY

IN

PHYSICS

By

K.MANJULA

Registration No:22516081

UNDER THE GUIDANCE OF

Dr. P.VENKAT REDDY

Department of Physics

SHRI JAGDISH PRASAD JHABARMAL TIBREWALA UNIVERSITY

VIDYANAGARI, JHUNJHUNU, RAJASTHAN 333001

1
 DETAILS OF RESEARCH SCHOLAR

B. Information Page

Title :- "DESIGN AND IMPLEMENTATION OF NANOSCALE DEVICES

USING NOVEL CHANNEL MATERIALS AND THEIR APPLICATIONS"

Name of the Scholar K.MANJULA

Registration No. 22516081

Subject PHYSICS

Guide Name Dr. P. VENKAT REDDY

Guide Designation PROFESSOR

SREENIDHI INSTITUTE OF SCIENCE AND

TECHNOLOGY, YAMNAMPET,
Guide Working place GHATKESAR, HYDERABAD, MEDCHAL
(DIST.), TELANGANA STATE, INDIA-501301.

Signature of student Signature and seal of guide

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 INDEX
PAGE
S NO CHAPTERS
NO

1 INTRODUCTION 4

2 PROLEM STATEMENT 8

3 SCOPE OF THE WORK 9

4 OBJECTIVES 9

5 METHODOLOGY 10

6 RESULTS 16
7 CONCLUSIONS 26

8 REFERENCES 27

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1.0 Introduction:

The driving motor for the exponential development of advanced data handling frameworks is
calling down the transistor measurements. For quite a long time, this has improved the gadget
execution, prompting denser chips with greater usefulness, a lower cost for each chip, speedier
exchanging and lower control utilization. Nonetheless, International Technology Roadmap for
Semiconductors (ITRS) has indicated basic difficulties to support the authentic scaling of silicon
innovation. Toward or past the finish of this guide period, when the present silicon-CMOS
innovation will probably end up noticeably inadequate and restrictively expensive, the beginning
of new materials will be expected to proceed with upgrades in gadget execution. Graphane and
carbon nano tube (CNT) are the two carbon allotropes, which have turned out to be unmistakable
contenders to substitute silicon in post-CMOS innovation. Graphane, one nuclear layer of carbon
sheet, may beat cutting edge silicon for some applications because of its excellent electronic
properties. The bearer transport in graphane is like the vehicle of mass less particles since 2D
electron gas in graphane gives both high transporter speed and high transporter focus, bringing
about substantial transporter versatility and, therefore, speedier exchanging capacity. In any case,
graphane is a semimetal with a zero band gap while it is fundamental necessity for advanced
coordinated circuits. The quantum repression of graphane sheet as one-dimensional strips known
as graphane nanoribbon (GNR) gives the vitality hole of a few hundred mV required for FET
operation in advanced applications.

In principle, the GNRs can be created by designing planar 2D graphane utilizing standard
manufacture strategies with substantially more controllability than their partners, carbon nano
tubes. In any case, the cutting edge designing system is a long way from accomplishing nuclear
scale exactness and GNRs with consummate smooth edges can't be created. In this manner, the
edge unpleasantness may assume a vital part in the generation of thin GNRs, with the end goal
that it abbreviates the mean free way (MFP) of electrons and thus dispenses with the appealing
electron transport properties of graphane. All things considered, the endeavors of most ebb and
flow examine are to manufacture smooth-edge GNRs to save the unrivaled electronic nature of
graphane. Yang and Murali tentatively watched the line width-subordinate versatility of electrons
in GNR, demonstrating that electron portability corrupts by diminishing the GNR width
underneath 60 nm. Edge unpleasantness is expanded by downsizing the base element estimate
because of increment in assembling variations of lithography and dry carving forms. GNR with
absolutely characterized width can be delivered by the versatile base up approach past the
accuracy furthest reaches of present day lithographic approach. In any case, both GNR-based
gadgets and interconnects can be simultaneously designed utilizing lithography strategy,
bringing about the benefits of band gap building on the whole graphane engineering.

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As the creation innovation of grapheme nano ribbon is still in a beginning time, the execution
assessment of advanced graphane based circuits requires a GNR FET demonstrate with some
parameters ascribed to the quality of edge harshness. Line-edge unpleasantness may assume a
vital part in the execution debasement of a GNR FET by upgrading the edge dissipating and
producing edge states in its opened band gap. Despite the fact that, the perfect smooth-edge GNR
FETs give an estimation of the upper bound execution, demonstrating edge harshness is
essentially vital to analyze the impact of process minor departure from the execution of
reasonable all graphane circuits. The edge unpleasantness is generally examined utilizing
numerical strategies because of its factual nature, which can't be adequately executed in circuit
test systems. The aftereffects of gadget level quantum transport reproductions of GNRFET can
be presented utilizing query table strategies for circuit reenactments. In any case, the serious
numerical reenactments should be rehashed with a solitary change in a plan parameter to remake
the model in like manner. This makes it a proper for assessing the advanced plan parameters of
GNR FET circuits.

In this work, we research the impact of edge unpleasantness on the power and defer execution of
GNRFETs by building up a diagnostic model of multi-GNR divert FET in SPICE. The
association of this paper is as per the following: In Section 2, we portray the favorable position
and test of all-graphane circuits, and additionally the structure and parameters of a GNR FET in
this structure. Segment 3 exhibits the proportional circuit model of the GNR FET by
consolidating the thermionic emanation and band-to-band-burrowing (BTBT) of bearers, and
also the impacts of line-edge harshness on the transporter transport in graphane nano ribbon. In
Sections 4, we explore the deferral, power, and vitality post pone result of GNRFETs for
different edge unpleasantness amplitudes and supply voltages. The dialog is introduced by
contrasting and 16-nm hub Si-CMOS composed by 5-arrange fanout-of-4 cushion chain.

Moreover, it has been reported that carrier mobility decreases with the increase in the carrier
density in the monolayer graphane, but in all the GFET models mentioned above, constant
carrier mobility is used. Therefore, the work presented in this paper aims to create an effective
carrier mobility, considering the mobility difference in electron and hole, including the mobility
variation against the carrier density. The concept of effective carrier mobility is introduced in
Section II. In Section II, based on the comparisons in appropriate approximations for quantum
capacitance, charge density, and saturation velocity are chosen. A full derivation of the closed-
form analytical solutions of the proposed GFET model is presented in Section III. In Section IV,
the modeled results are compared with measurement data. Section V concludes this paper.
Graphane, the latest addition to the family of two dimensional (2D) materials, is distinguished
from its cousins by its unusual band structure, rendering the quasi particles in it formally
identical to mass less choral fermions. The experimental realization of grapheme thus presents
tantalizing opportunities to study phenomena ranging from the topological phase resulting in
exotic Quantum Hall States to the famous Klein paradox the anomalous tunneling of relativistic
particles. However, despite tremendous interest and concerted experimental escorts, the presence

5
of strong impurity scattering which limits the electron mean free path to less than a micron has
been a major barrier to progress. At the same time, there is strong evidence that grapheme is a
nearly perfect crystal free of the structural defects that characterize most conductors. As a result,
it has been put forth that the scattering of charge carriers stems from extrinsic sources. Although
the exact nature of the scattering that limits the mobility of graphane devices remains unclear,
evidence has mounted that interactions with the underlying substrate are largely responsible.
Surface charge traps interfacial phonons, substrate stabilized ripples and fabrication residues on
or under the graphane sheet may all contribute. Consequently improving substrate quality or
eliminating the substrate altogether by suspending graphane over a trench seems promising
strategy towards higher quality samples. While devices suspended over the substrate were
achieved in the past, they lacked multiple electrical contacts thus precluding transport
measurements.
In this Letter we report the fabrication of electrically contacted suspended graphane and achieve
a tenfold improvement in mobility as compared to the best values reported in the literature for
traditional devices fabricated on a substrate. Besides opening new avenues for studying the
intrinsic physics of Dirac fermions, this improvement demonstrates the dominant role played by
extrinsic scattering in limiting the transport properties of unsuspended graphane samples. The
fabrication of a suspended graphane device starts with optically locating a single-layer
mechanically exfoliated graphane take on top of a silicon substrate covered with 300 nm of
SiO2. Single-layer graphane asks are identified based on their contrast, and later confirmed via
measurements of the half-integer quantum Hall etc. We avoid patterning the asks using oxygen
plasma etching, as it may introduce additional defects in the bulk and dangling bonds at the
edges of graphane. Instead, we choose natural akes of approximately rectangular shape suitable
for fabrication into Hall bars. Electron beam lithography is employed to pattern the contacts to
the ache. The contact material (3 nm Cr followed by 100 nm of Au) is deposited by thermal
evaporation followed by a lift_ in warm acetone. The large size and thickness of the electrodes
enhances the mechanical rigidity of the device. Suspension of the grapheme ache is achieved by
dipping the entire device into 1:6 bowered oxide etch (BOE) for 90 seconds, which uniformly
removes approximately 150 nm of SiO2 across the substrate, including the area below the ake
(SiO2 masked by the gold electrodes remains undetached).
Uniform etching of the substrate directly below the ache is crucial for our process as it allows the
fabrication of large-area suspended graphane, while maintaining the parallel plate capacitor
geometry for our device. To our knowledge, this unexpected etching anisotropy in the presence
of graphane was not reported before; it is, however, consistent with the rapid propagation of
BOE along the SiO2/graphane interface. Finally, the device is transferred from BOE to ethanol
and dried in a critical-point-drying step to avoid the surface-tension induced collapse of the
suspended graphane sheet.

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 FIG. 1: (a) SEM image of a typical suspended six-probe
Graphane device taken at 15 with respect to the sample plane.
(b) AFM image of the suspended device #1 before the measurements.
(c) AFM image of the device #1 after the measurements with graphane removed by a short
oxygen plasma etch (same z scale).
(d) Device schematic, side-view. Deben- irately doped silicon gate (blue), partly etched SiO2
(green), and suspended single-layer graphane (pink) and Au/Cr electrodes (orange).

The Discovery that single-layer graphane is a robust material that can be isolated, contacted, and
tested electrically has generated much excitement. Among the results obtained to date,
researchers have measured motilities as high as 250 000 cm2/V s, demonstrated field-effect
transistor action, and even done an initial characterization of transport in grapheme Nano ribbons
.Most recently, intriguing evidence has been obtained for the existence of a band gap of roughly
0.26 eV for single-layer grapheme when it is formed epitaxial on SiC by sublimation of silicon at
high temperature. All of this activity is clearly promising, but of course, whether it will
eventually lead to a practical graphane electronics technology remains to be seen. For this paper,
we take the rapid progress that has been made as sufficient motivation for framing a device-
oriented transport theory for grapheme that may one day serve as the foundation for electronic
device design and optimization tools. Theoretical work on electron transport in graphane has
generally centered on understanding ballistic or near-ballistic behaviors and on the exotic
electronic properties that grapheme can exhibit under ideal conditions, including when restricted
in dimension as in the nano ribbons. In this paper, we focus instead on the opposite limit, i.e., on
developing a device modeling approach that is apropos when the transport is dominated by

7
scattering. This interest is justified in part by the fact that except for the technologically
uninteresting case of suspended exfoliated graphane, the mobilities measured in grapheme have
so far generally been far from ideal. It seems that, at least at present, the all-surface nature of
graphane makes it particularly susceptible to nearby charges and/or localized mid gap states.
While this issue is clearly in need of attention, it does imply that a graphane transport description
that assumes strong cattering will be relevant at least for most research devices of today. The
conventional transport modeling approach with strong scattering is, of course, the diffusiondrift
(DD) description.

2.0 Problem Statement:

In spite of the fact that it has exceptional properties yet deformities may happen amid
development and creation. Be that as it may, the deviations from flawlessness can be helpful in a
few applications, especially in bio detecting. The looks into of a monolayer sheet of unblemished
and abandoned graphane have expanded as of late on account of the uncommon and possibly
valuable electronic properties of this two dimensional material . Studies did on monolayer have
as of late been stretched out into multilayer graphane which incorporates a bilayer However,
abandons in a bilayer graphane are not tended to finally in the vast majority of the audit. Along
these lines, in this examination, specific accentuation is hung on the one of a kind capacities of
fundamentally abandoned bilayer Graphane prompting every single fascinating property and
potential applications particularly in biosensing abilities.

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3.0 Scope of work:

The examination covers the reproduction of graphane differed from monolayer to bilayer
graphane field-impact transistor and the examination of the at gadget models with and without
auxiliary deformities. The extents of the investigations are as per the following.

1) Simulation work utilizing Atomistix Tool Kit Software adaptation 13.8.1 from Quantum
Wise.

2) Graphane structures utilized are in mass properties.

3) The structure of bilayer graphane is demonstrated considering the AA and AB stacking to

dissect their execution.

4) The basic deformities are constrained to SV and DV.

5) Device designs are displayed utilizing back door structure 5

6) The physical and electrical properties to be gotten are band structure, thickness of states
(DOS), warm conductance (TC), transmission range (TS) and IV attributes.

7) All works are restricted to display reproduction and no trial work will be gone ahead

4.0 Objectives:

This exploration stresses on the examination of basic imperfections on a bilayer FET utilizing
programming from Quantum Wise.

The goals of the exploration are expressed as underneath.

1) To build up the recreation model of bilayer of graphane (BLG) with and without the nearness
of single opportunity (SV) and twofold opening (DV) absconds.

2) To examine the electronic properties of AA-stacked and AB-stacked BLG.

3) To break down the electrical execution of BLG with the nearness imperfection.

4) To check the mobility of elements in the substances.

5) Analyze the application modules up to nano levels.

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5.0 Methodology:
Ge MOSFET technology

se and light opening (and) compelling masses are fundamentally dependable, separately, for the
higher electron and gap float portability. This property is the most invaluable over Si for
profoundly scaled MOSFET applications as beforehand talked about paying little respect to the
higher Si immersion speed. The more symmetric electron and opening portability in Ge would
not just diminish the land of p-MOSFETs, however would allow more CMOS rationale
entryways too. Besides, its lower liquefying point mirrors a probability to manufacture Ge
MOSFETs with much lower warm spending forms. As we would see it Ge without anyone else's
input will never be the primary material to create ICs. It should be heterogeneously incorporated
with Si. As a rule Si gadgets will be manufactured first and afterward Ge will be incorporated,
e.g., Ge PMOS on Si NMOS, in a 3D design or for combination of optical gadgets on CMOS. In
such cases warm spending plan accessible for Ge is restricted. Besides, most high-k dielectrics
and metal entryways are not for the most part good with high temperature preparing. This makes
their combination with Ge less demanding than with Si. The substandard properties of
germanium oxides when contrasted with SiO2 make this dielectric inadmissible for Ge MOSFET
door protection and field segregation, which has hence hindered vast scale reconciliation (VLSI)
acknowledgment in Ge for a considerable length of time. Moreover, for Ge to end up standard,
heterogeneous incorporation of crystalline Ge layers on Si must be accomplished. In this work
we show heterogeneous mix of crystalline Ge layers on Si, Ge surface passivation with high-k
dielectrics and creative heterostructure MOSFETs to conquer BTBT spillage.

Need for high mobility channel

The saturation of bulk Si MOSFET drive current (IDsat) upon dimension shrinkage is limiting
the prospect of future scaling. To understand this saturation phenomenon, numerous theoretical
and experimental analyses were carried out. First of all, the IDsat (and transconductance) in very
short-channel MOSFETs is believed to be limited by carrier injection from the source into the
channel. In order words, the source injection velocity (vsrc) saturates during scaling and that its
limit is set by thermal injection velocity (vinj) as depicted in figure . Also, the carrier density at
the top of the source to channel barrier is fixed by MOS electrostatics and the scattering in a
short region near the beginning of the channel limits the IDsat figure. By corroborating measured
velocity and mobility dependencies on deeply scaled MOSFETs, the carrier velocity was shown
to have a direct proportionality with the low-field effective inversion-layer mobility. Mobility is
not a well-defined quantity in a nano scale MOSFET under high drain bias where off-equilibrium
transport dominates; however in Ref it was demonstrated that the drain current of a nano scale
MOSFET is directly related to the near-equilibrium mean-free-path for backscattering, which can

10
be deduced from measurements on a corresponding long-channel MOSFET for which the is well
defined. In brief, these results suggested that mobility continues to be of crucial importance to
saturated transconductance and IDsat as channel lengths decrease below 100 nm. Moreover, the
common performance metrics, MOSFET drive current and logic gate delay, when expressed in
terms of vinj, respectively reveals a direct and indirect proportionality:
IDsat = W Qinv vinj and
CLOADVDD
IDsat
= L VDD
(VDD Vth) vinj
where W is the MOSFET channel width, Qinv is the inversion charge density, CLOAD is the
load capacitance, VDD is the supply voltage, L is the MOSFET gate length, and Vth is the
threshold voltage. Therefore, by coupling these simple relationships with the above theoretical
and experimental analyses, one can easily identify the advantage of incorporating an alternative
MOSFET channel material with higher carrier mobility (and vinj) to allow further improvements
on MOSFET ID sat versus technology scaling.
Hetero epitaxial growth of thick relaxed Ge on Si:
Hetero epitaxial development of Ge on Si is not straight forward on account of the extensive grid
jumble (4%) amongst Ge and Si, which confines the nature of the developed material. In the first
place, over the basic thickness, the layer will have numerous nonconformist disengagements
making it unusable for any reasonable applications. Second, the development of Ge on Si brings
about island morphology, or the supposed "Stranski Krastanow" (S K) development. Such
development is related with vast surface harshness, causing troubles in process reconciliation, for
example, holding for Ge-on-protector (GOI). This can prompt corruption in gadget properties.
We have built up a novel system to accomplish great hetero epitaxial Ge layers on Si. The
system includes CVD development of Ge on Si, trailed by in situ hydrogen strengthening with
consequent development and temper steps and henceforth the name various hydrogen toughening
for hetero epitaxy (MHAH). Following the primary Ge development and hydrogen temper, the
Ge surface harshness from islanding" is lessened by 90%. An extra CVD Ge layer is developed
on the low unpleasantness Ge layer took after by the last hydrogen tempering. From cross
sectional transmission electron microscopy (TEM), maverick separations are bound to the Ge/Si
interface or curve parallel to this interface, as opposed to threading to the surface of course in
this 4% grid jumbled hetero epitaxial framework

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 Cross-sectional TEM image of a heteroepitaxial-Ge layer on Si grown
by the MHAH method.
Germanium p-MOSFETs with High-k Dielectric:

Schematics of the low temperature probe station from above (a) and in cross-section (b)

Business bit of hardware, effective estimations require that it is all around kept up and introduced
accurately. This was not the situation when initial flow temperature estimations were completed
on the gadgets revealed in this section what's more, subsequently extensive time and exertion
was placed in by the creator to amend this. Basic, yet non-paltry, issues included deficient
electrical disengagement between boisterous vacuum pumps and test station bringing about
expansive clamor in electrical estimations. The arrangement was just the utilization of an
electrically protecting vacuum O-ring in the fitting put (amongst pump and test station).
Exacerbating the situation, was a brief answer for the clamor issue - executed before the creator's
association - comprising of a glass slide put amongst test and substrate throw. In spite of the fact
that this avoided electrical commotion from meddling with estimations, the glass slide was
additionally thermally protecting, implying that it was improbable that the specimen was coming
to the coveted low temperature and without doubt estimations were not repeatable with this set-
up. Once the electrical clamor had been disposed of at it's source, the glass slide was evacuated
and the administrator could make certain that the example achieved the toss temperature. In spite
of the fact that the toss was currently earthed neatly, some estimation procedures require a flag to
be connected or measured at the substrate contact. Luckily, the maker supplies a toss with a thin,
electrically protecting layer that behaviors warm and once actualized the every single electrical
estimation could be performed at low temperature.

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 The measurement procedure, developed for the reliable low temperature electrical
characterisation of Ge MOSFETs, using a Desert Cryogenics low temperature probe
station.

S.no ACTION
1 Start cryogenic flow

2 Enter temperature set point if required

3 Reduce flow so heater is on as lower power output as possible
4 Allow shield to stabilise (drift<1 C/minute)
5 Contact probe tips to unused sample area for 2030 minutes
6 Reconnect probes to sample area to be measured for 10 minutes
7 Reconnect and measure
8 Repeat measurement after 5 minutes check for connection failure or
data indicating temperature shift

9 Repeat step 8 until measurement consistent

10 Move probes one at a time to contact next structure
11 Measure and repeat (from step 8)
12 Once all measurements at the current temperature are complete, raise
probes and warm/cool to next temperature

Outline
The gadgets detailed here are germanium p-MOSFETs (with going with n-MOS capacitors)
manufactured on the Pilot Line at IMEC a huge microelectronics look into office in Leuven,
Belgium. The Pilot Line is utilized to create non-silicon gadgets on 200 mm distance across
wafers. The gadget cluster is a piece of the Ge/III-V CMOS venture with a definitive objective of
superior germanium p-MOSFET and III-V semiconductor (e.g. GaAs) n-MOSFET gadgets,
created all the while on a solitary wafer that would have isolate districts of both material sorts.
The wafers, which the gadgets revealed here are created on, are standard (100) silicon substrates
with a few micron thick completely casual germanium layer at first glance. This layer was
developed by substance vapor statement by ASM global a substantial organization gaining
practical experience in wafer preparing advances. Three specimens were given to the creator the
important point of a low- temperature electrical characterization. All specimens were cut from a
solitary wafer at IMEC two from the middle (example C and test H) and one from the edge
(test E). Test H experienced an extra 400 C strengthen after manufacture (known as a post-
metallization strengthen or PMA) in an unadulterated hydrogen gas climate. The veil set, utilized
to characterize the electrically dynamic ranges amid manufacture, contains n-MOS capacitors, p-

13
MOSFETs from 10 m down to 125 nm door lengths and MOSFETs with no entryway stack
(invalid FETS). MOSFETs are masterminded in lines (alluded to as exhibits) with the goal that
source/deplete contact cushions are shared between two neighboring gadgets keeping in mind the
end goal to spare space on the wafer surface. The MOSFET door lengths diminish down the
length of each exhibit. The germanium layer is n-doped by particle implantation to give a
substrate doping thickness of 71015 cm3. The entryway stack is framed by somewhat
oxidizing a thin silicon top (6 A) on the Ge-surface by a dunk in ozonated water. The hafnium-
oxide high-k dielectric (4 nm thick) is promptly kept by means of nuclear layer affidavit,
straightforwardly onto the silicon dioxide to keep any further oxidation. This outcomes in a last
entryway dielectric stack from the Ge-surface of: Si/SiO2/HfO2. The announced capacitive equal
thickness is 16 A. Metallization that electrically interfaces the gadgets to contact cushions, is
still in the advancement organize with the point of getting as low as resistance as could
reasonably be expected. Three diverse source/deplete geometries are accessible with various
regions of metal covering the doped source/deplete areas. No nitty gritty examination concerning
the distinctive source/deplete designs was performed; yet there was be that as it may, a setup that
had a lower source/deplete resistance than the others. For effortlessness we should allude to these
as "optimised source/deplete contacts" and the others, with a higher resistance, as "unoptimised".
The source/deplete resistance is accounted for to be 55 for the MOSFETs with improved
source/deplete contacts, with an expansive commitment from the contact cushion itself. By
changing the position of a test needle on the source/deplete contact cushion it was appeared to
differ crest trans conductance by 25% of every a 125 nm gadget. This makes solid Rsd extraction
testing as test needle arrangement unmistakably largy affects this parameter. Additionally adding
to the resistance is the gently doped deplete (LDD) expansion area, which is fused into the
MOSFET configuration to decrease short channel impacts by bringing down the doping
thickness near the channel locale. Officially distributed are the room temperature gadget
attributes. This incorporates the exhibition of a powerful portability 3 more prominent than the
silicon p-MOSFET all inclusive portability bends. This was extricated from a MOSFET on a
specimen that had experienced hydrogen strengthen as tests that had not, demonstrated huge
variety in trans conductance and limit voltage and had for the most part bring down mobilitys.
This was subjectively shown to be because of interface states with charge pumping
estimationsthe hydrogen strengthen brought about a lessening in interface state thickness and a
change in gadget execution and consistency.
STRAIN EFFECTS ON GERMANIUM P-MOSFETS
As short-channel-viewpoints (SCEs) keep the basic scaling of conventional Si MOSFETs
accomplishing authentic execution change, new material, and in addition highlight upgraded
innovation (strain innovation), pull in consideration of the specialists. Germanium is one of those
new materials because of its vast electron and gap versatility. With the stressed silicon
innovation in the business, it's a fascinating subject to find how the strain perspectives
theelectron and opening versatility in germanium MOSFETs. Germanium has been of
extraordinary enthusiasm for rapid CMOS innovation for quite a long time. The mass germanium
opening portability is bigger than that of other semiconductor materials, and its electron and gap
versatility are substantially less dissimilar than different materials. In 1989, germanium gap

14
portability of 770cm2=V sec in a pMOSFET was shown by Martin and his co{workers
utilizing SiO2 as the entryway protector. From that point forward, increasingly work has been
done on germanium or SiGe channel pMOS. With a specific end goal to diminish the surface
unpleasantness and farthest point the band{to{band burrowing issue, silicon{germanium or
Si{SiGe double divert is additionally utilized as a part of a few applications. Distinctive door
dielectric materials have been used to and the best material to restrain the surface harshness at
the interface between entryway separator and germanium channel. Because of the vulnerability
in the surface unpleasantness and the surface states, distinctive opening portability esteems have
been accounted for in those distributions. As of late, with the strain innovation connected to
silicon CMOS, strain eect is likewise researched on germanium MOSFETs.
The strain is typically accomplished by applying SiGe substrate underneath the germanium or
SiGe channel. However, a large portion of the work remains just in tests, the physical bits of
knowledge of the strain eect on germanium MOSFETs have not been examined precisely. The
main accessible hypothetical works are some Monte-Carlo recreations. The objective of this
section is to give physical experiences of strain angles on germanium using k p computation. In
this part, strain-initiated opening versatility change of Ge and Si1xGex in pMOS reversal layers
is examined. The gap portability versus electric eld and surface introduction is appeared. Strain-
upgraded opening portability is figured for various Ge fixation in Si1xGex. To comprehend the
contrast amongst Ge and Si, opening powerful mass, band and subband part, and two-
dimensional thickness of-states are computed and their consequences for gap portability is
dissected. Phonon and surface harshness dispersing is additionally assessed under strain.

15
6.0 RESULTS:
The poor quality Ge native dielectrics for gate insulator and field isolation have been one of the
classic problems that obstruct VLSI CMOS device realization in Ge. Efforts to use materials like
SiO2 on a thin Si cap, Ge3N4, GeOxNy, etc. have been only marginally successful. Inspired by
the recent successes of the high-k dielectrics on Si, we investigated the possibility of applying
these materials to Ge.Volatility of Ge surface oxides or sub-oxides makes surface cleaning easier
for high-k gate dielectric stack free of the performance limiting, lower-k, interfacial GeOx layer.
Surface passivation of Ge has been achieved with its native oxynitride (GeOxNy) and high-
permittivity (high-k) metal oxides of Al, Zr and Hf. Three different techniques were stud-
ied for surface passivation: (1) thermal growth of Ge oxynitride (2) oxidation in ozone of metals
deposited on Ge, and (3) atomic layer deposition (ALD) of high-k metal oxides. The oxynitride
in figure formation was studied by an initial rapid thermal oxidation (RTO) in dryO2 at 500600
Cfollowed by in situ RTN at 500700 C in NH3 ambient to convert the Ge oxides into
GeOxNy. Optimum process temperature for both RTO and RTN was found to be 600 C. The
degree of metrication in GeOxNy should be optimized for best results.

Cross-sectional HR-TEM the optimum dielectric stack attained by W/GeON/Ge gate stack
formed by rapid thermal nitridation

16
Cross-sectional HR-TEM the optimum dielectric stack attained by Pt/ZrO2/Ge gate stack formed
by direct UV ozone oxidation of Zr,

Cross-sectional HR-TEM the optimum dielectric stack attained by RTN of CHF Ge at 600 C
followed by HfO2 ALD.

The effect of interfacial layers between HfO2 and Ge on the physical as well as electrical
characteristics of Al/HfO2/ILs/Ge p-MOS capacitor has been discussed. We used oxidation for 3
minutes at 400C in O2 ambient and nitridation for 3 minutes at 600 C in NH3 ambient for
surface passivation. Further the effect of forming gas annealing has also been discussed.
Thickness of HfO2 Layer The thickness of the HfO2 film was found to be 9.77 nm measured
using variable angle spectroscopic ellipsometry and also by the filmetrics Reflect meter for the
confirmation of the exact value. The thickness was calculated by taking the mean of all the

17
values from both the methods. The refractive index for the deposited films was found to be in the
range 2.12 - 2.42. The equivalent oxide thickness (EOT) with GeON as IL has been found to be
3.23 nm while with GeO2 as IL, the value of EOT found was 3.67 nm. These EOT values were
determined using physical thickness of HfO2 layer and dielectric constant calculated from the
capacitance voltage (CV) measurements.
X - Ray Spectroscopy
The sample presents two Ge3d peaks at 28eV and 31eV and Ge3d XPS spectrum obtained from
GeO2 grown at 400C displays the presence of bonded oxygen in the state (sub-peak with 3.2 eV
shift in binding energy from Ge3d peak) which confirmed the growth of GeO2 as the initial
dielectric. The shifting of sub-peak towards the lower binding energy shows the presence of
nitrogen atoms due to the nitridation of GeO2 and changes in its chemical state converting it into
GeON. Figure shows the XPS depth profile of 9.77 nm thick HfO2 diectric material on Ge
substrate. In Fig 4 (d), when sample was scanned from the top, it displays two peaks at 16 eV
and 17.7 eV which correspond to Hf4f peaks. On increasing the sputter depth, Ge3d region
shows the presence of Ge-O, GeO2 and GeON peaks from the Ge substrate and confirmed the
existence of Oxygen and Nitrogen atoms in the HfO2/Ge interlayer. O1s peak was detected at
529.25 eV as shown in figure 5 (b) and two peaks of N1s at 396.25 eV and 399.5 eV were also
detected as shown in figure 5 (c) from the sample of HfO2/GeON/Ge stack.

XPS spectra of Ge3d for GeO2 and GeON

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 (a) Ge3d (b) O1s (c) N1s and Hf4f XPS depth profile of 9.77 nm HfO2 dielectric on Ge
substrate.

Key properties of different gate stack for Al/HfO2/Ge p-MOS Capacitor.

Dielectric Controlled sample RTO GeO2/HfO2 RTN GeON/HfO2

properties
Dit (eV-1 cm-2) 1.928 1014 2.531013 6.31011

Thermal stability Stable Un Stable Stable

Dielectric constant 11.6 11.4 13

Qeff (cm-2) 1.151012 1.751013 1.691013

EOT (nm) 3.27 3.67 3.23

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 Caparison of C-V characterstics for RTN GeON and RTO GeO2 ILs with controlled sample
measured on Al/HfO2/Ge p-MOS capacitor at 100 KHz frequency.

Mobility Analysis:
It has been quantitatively demonstrated that interface states are responsible for the threshold
voltage shift and range of sub threshold slopes observed in this device batch. However, we also
observe a large decrease in peak transconductance with more negative threshold voltages. It is a
reasonable assumption that the decrease in peak transconductance is caused by the presence of
interface states as it correlates strongly with threshold voltage, sub threshold slope and increasing
interface state shoulder in the gate-channel split C-V branch. Tran conductance is directly related
to the field effect mobility as described in section 3.1.6. Remember that only peak field effect
mobility can be trusted as a reasonable measure of the effective mobility in the channel. We
therefore begin with a simple analysis of peak field effect mobility before moving on to a more
detailed analysis of the effective mobility as a function of vertical effective field. Peak Field
Effect Mobility we have assumed that the interface states in the bottom half of the band-gap are
donor-like and gain a positive charge as the device tends towards strong inversion. Given their
close proximity to the channel (as indicated by the interface state shoulder in the gate-channel
split C-V branch), these will then act as scattering sites for the holes that make up the inversion
charge and increase the Coulomb scattering rate. The scattering rate will be proportional to the
areal density of charged impurities nim. Using Mathiessens rule we see that the reciprocal of the
total measured mobility should be proportional to the Coulomb scattering limited mobility. It is
now assumed that the main source of scattering sites is the charged interface states in inversion.
Alternative sources could be other types of trapped oxide charge near the interface or impurities
such as dopants in the channel. There is no evidence that these vary greatly or at all between
devices and as we are performing a comparative study here, these constant factors are ignored.

20
The MOSFETs with the higher peak mobility have optimized source/drain contacts and as
expected have a lower Rsd than the other, unoptimised ones, lying on the lower peak mobility
trend. All measurements are corrected for Rsd but only a single value that extracted for the
optimised devices is used. It is expected that if the source/drain resistance was accurately
measured for the unoptimised devices and used to correct the data, all devices would fit on the
same trend. To the authors knowledge, this linear trend of reciprocal peak field effect mobility
against threshold voltage has not been observed before and therefore warrants some discussion.
demonstrates a decrease in peak effective mobility at low fields due to Coulomb scattering by
interface traps, but with five data points compared to the one hundred or so here. A threshold
voltage shift due to interface traps is well documented and therefore the relationship between
mobility and interface traps demonstrated here is expected. A lack of previous publications could
be for several reasons, the most obvious of which, is that it is rare to have such a variation in
interface state density across a processed wafer. Normally when fabricating MOSFETs.

Reciprocal field effect mobility against threshold voltage extracted for many 10 m10 m p-
MOSFETs with Vd = 0.05 V at 77 K and 300 K includes hydrogen-annealed devices

Reciprocal field effect mobility against threshold voltage extracted for many 10 m10 m p
MOSFETs with Vd = 0.05 V at 77 K and 300 K. omits them to better demonstrate a linear
relationship between the two parameters for those devices that did not undergo anneal.
21
Germanium Hole Mobility
Unstrained Ge hole mobility vs vertical electric field and device surface orientation is shown in
figure. Experimental works give a lot of different mobility values ranging from 70cm2=V sec
to over 1000cm2=V sec, depending on what the gate dielectric materials are used and if Si
buffer is applied between the Ge or Si Ge) and the gate oxide. With Si buffer, the device acts as a
buried-Ge channel transistor and normally shows large hole mobility due to the lack of continent
and surface roughness scattering. Due to the bad scalability of buried-channel devices, only
surface channel Ge-p MOS is discussed here. Calculated Ge whole mobility matches the
measured data and the mobility is much larger mobility than silicon. oriented device shows
higher mobility than (001)-oriented device, which is consistent with the results of Si. We shall
show that the larger whole mobility of germanium mainly comes from the smaller effective mass
of the holes. The relative smaller inter-sub band phonon scattering rate due to the larger sub band
splitting (and smaller optical phonon energy) also improves the germanium mobility.
Biaxial Tensile Stress
In silicon MOSFETs, biaxial tensile strain is obtained via applying Si1xGex substrate the Si
channel. Biaxial tension is not a popular stress type for germanium devices due to the large
lattice constant of germanium. For comparison purpose,

Germanium hole mobility vs effective electric field.

22
 Germanium and silicon hole mobility under biaxial tensile stress where the
Inversion hole concentration is 1 1013=cm2.

Germanium and silicon hole mobility on (001)-oriented device under uni axial compressive
stress where the inversion hole concentration is 1 1013=cm2.

Germanium and silicon hole mobility on (110)-oriented device under uniaxial compressive stress
where the inversion hole concentration is 1 1013=cm2.

23
 E{k diagrams for Ge under (a) no stress; (b) 1 GPa biaxial tensile stress; (c) GPa biaxial
compressive stress; and (d) 1 GPa uniaxial compressive stress.

Energy Contours:
The energy contours of the valence band provide a straightforward picture of the conductivity
effective mass and density-of-states of each band. The conductivity and density-of-states
effective mass change with strain can also be seen from the shape change of the contours. The 25
meV contours of the unstressed Ge are shown in figure. Contours (25 meV) under biaxial
compressive and tensile stress are shown in figure and Figure shows the contours under uniaxial
compressive stress. The energy contours are similar to those of silicon, but the shape of the
contours changes more than Si contours when the same amount of strain is present. Another
difference is that under uniaxial compressive stress, the 2D DOS of Ge looks much smaller than
Si. From the analysis of Si, lower point DOS leads to smaller strain induced mobility
improvement due to fewer holes are affected by strain. This may explain why the mobility
enhancement factor for Ge is not larger than Si, although the effective mass change is much
larger at point.

25meV energy contours for unstressed Ge: (a) Heavy-hole; (b) Light-hole.

24
 25meV energy contours for biaxial compressive stressed Ge: (a) Top band; (b) Bottom band.

25meV energy contours for biaxial tensile stressed Ge: (a) Top band; (b)Bottom band.

25meV energy contours for uniaxially compressive stressed Ge: (a) Top band; (b) Bottom band.

25
7.0 Conclusions:

Inventive gadget structures and new materials must be considered to proceed with the
memorable advance in data. As a promising MOSFET channel material competitor, Ge offers
various points of interest over Si. In this work, we have tended to the exemplary issues of Ge
surface passivation and its joining on Si, and showed different propelled Ge MOSFETs proper
for Nano scale innovations.
An underlying 55 nm SiGe layer with 5 nm Si-top on 100 nm SOI substrate was oxidized for
different circumstances and temperatures to get a progression of tests with different SGOI layer
thicknesses and Ge-creations. 1700 minutes of oxidation brought about a last 10 nm thick SGOI
layer with a Ge-creation of 58% and this is the most slender, most astounding Ge- creation layer
at any point got, from thick (t i=160 nm) introductory Si/SiGe layers of low Ge-organization
(x=4%). Moreover, this layer could be more slender and, hence, have a higher Ge-organization
than answered here because of precise blunders happening in both XTEM and SIMS estimations.
Thin film of hafnia with thickness of 9.77 nm was effectively stored on n-sort Ge substrate by
ALD strategy. Physical and electrical portrayal of the HfO2 thin film MOS capacitor with FGA
at 420 C temperature has been contemplated. Thickness of hafnia is controlled by ellipsometer
and profilometer. This investigation proposed that before testimony of HfO2 on Ge, surface must
be compulsory which help us in change of general nano gadget execution.

26
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