Toshiba Satellite C850 C855 - INVENTEC DAKAR10F DAKAR10FG PDF

8 7 6 5 4 3 2 1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.
F HSF Property:ROHS or Halogen-Free(5L3?) F
E E
DAKAR10F/FG D
2011.09.02
C C
B B
A A
EE DATE POWER DATE

DRAWER
DESIGN
INVENTEC
CHECK TITLE MODEL,PROJECT,FUNCTION
RESPONSIBLE Everest Main Board
21-OCT-2002 SIZE= VER: SIZE CODE DOC.NUMBER REV

FILE NAME: C CS X01
DATE CHANGE NO. REV P/N 1310xxxxx-0-0 SHEET 1 of 68
XXX
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE OF CONTENTS
D
D
PAGE PAGE PAGE
1. COVER PAGE 26. CARDREADER 51. PCH 5 USB

2. INDEX 52. PCH 6 MISC
27. MINI1 WLAN/DEBUG CARD 53. PCH 7 POWER
3. BLOCK DIAGRAM 28. MINI2 3G/LTE 54. PCH 8 POWER
4. POWER MAP 29. SATA HDD/ODD CONN 55. PCH 9 GND
5. POWER CHARGER 30. USB 2.0 CONN 56. VGA 1
6. POWER +V3LA/+V3A/+5A 31. USB 3.0 CONTROLLER 57. VGA 2
7. POWER +V1.5/+V0.75 32. USB 3.0 CONN W/ S&C 58. VGA 3
C
8. POWER +V1.8S 33. USB 3.0 CONN 59. VGA 4
C
9. POWER VCCIO 34. LCM CONN 60. VGA 5

10. POWER VCCSA 35. CRT CONN 61. VGA 6
11. POWER VCORE 36. HDMI CONN 62. VRAM 1
12. POWER VGFX 37. HDMI CEC 63. VRAM 2
13. POWER VCORE_DGPU 38. DDR3 DIMM0 64. VRAM 3
39. DDR3 DIMM1 65. VRAM 4
14. ENABLE PIN
15. LOAD SWITCH-1 40. FAN & THERMAL SENSOR 66. POWER BUTTON BOARD
16. LOAD SWITCH-2 41. CPU 1 67. EMI
17. PCB SCREW 42. CPU 2
B 18. HALL SENSOR 43. CPU 3 DRAM B
19. LED 44. CPU 4 POWER

20. K/B & TP/B CONN 45. CPU 5 POWER
21. EC 46. CPU 6 GND
22. LAN 47. PCH 1
23. RJ45 & TRANSFORMER 48. PCH 2
24. AUDIO CODEC 49. PCH 3
25. SPEAKER/HP JACK/MIC JACK 50. PCH 4 AXG
A A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS
CHANGE by DATE SHEET 2 of 68

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR3@1.5/0.75V
AMD PEG IVY BRIDGE DDR3 INTERFACE (1333/1600 MHZ)
W/ POWER EXPRESS DC 35W 204-PIN SODIMM0
SOCKET-RPGA989
THAMES
37.5 X 37.5 X 5 mm DDR3 INTERFACE
29X 29 MM
DDR3@1.5/0.75V
D (1333/1600 MHZ)
D
204-PIN SODIMM1
FDI DMI 2.0
INTERNAL MIC IN
AUDIO CODEC
EXT MIC IN
HDA REA_ALC269Q_VB6
C HDMI C
HEADPHONE
PCH
USB2.0 USB_0: USB CONN
CRT PANTHER POINT
USB_2: USB CONN
USB_8: CARD READER
25 X 25 X 2.3 mm
LVDS
USB_9: MINICARD WLAN
LCM
USB_10:WEBCAM
SLEEP & CHARGE
B B
PCIE_1:LAN USB3.0 USB_1: USB3.0 CONN
RJ45 PCIE
ATHEROS_AR8161/8162
PCIE USB2.0
USB_8: CARD READER
PCIE_2:WLAN REA_RTS5129
PCIE
PCIE_3:USB3.0 SATA
SATA0:ESATA
SPI SATA1: HDD
SATA6: ODD
A A
ENE-P2809A EC WINDBOND SPI SPI FLASH 8MB
THERMAL SENSOR NPCE885LA0DX
MXIC_MX25L3206EM2I
BATTERY CHARGER &

DC/DC & IMVP 7
KEYBOARD TOUCH PAD INVENTEC
LI-ION BATTERY TITLE
6-Cell Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADAPTOR +VBAT +V5A_+-5% +V5S
BQ24725RGRR
FUSE TPS51123 AO6402L
CHARGER
EC_SMB2 POWER BUDGET 12.139 A POWER BUDGET 4.711AINRUSH 0.9A

65W-75W 8A 6036A0003401
CHG_EN F 300K PEAK2.592A 100.82UF_0.842M[
90W 10A 6036A0002901 BATT_IN OCP 10.4A R=120K +V0.85S_+-0.5%
ACPRES PEAK 7.283A AVG 2.363A
120W 12A 6036A0006001
D
220UF_25M[ // 53.92UF_1.529M[ TSP51461
D
POWER BUDGET 6A
F 340K
OCP 6A
BATTERY PACK
PEAK 6A AVG 1.262A
+V3LA_+-5%
+VCORE_+-0.5% +V3A +V3_LAN
+VCORE1_+-0.5% TPS51123 AO6402L AM2321P

TI_TPS61640
POWER BUDGET 9.429 A INRUSH 0.9A
POWER BUDGET 4.711A POWER BUDGET 4.711A INRUSH 0.9A
POWER BUDGET 53A
F 375K 100.82UF_0.842M[
PEAK2.592A PEAK2.592A 100.82UF_0.842M[
F 280K OCP 10.7A R=130K +V3S +V1.8S
OCP 53A PEAK 5.695A AVG1.048 A
C C
PEAK 53A AVG 28.822A 220UF_25M[ //10.6UF_5.924M[ AO6402L GMT_AT1530F11U
1880UF_1.1M[ // 2276UF_0.203M[
VDD_CORE POWER BUDGET 4.711A INRUSH 0.9A POWER BUDGET 4.711A INRUSH 0.9A
PEAK2.592A 100.82UF_0.842M[ PEAK2.592A 100.82UF_0.842M[
TPS51217
POWER BUDGET 20.070A V1.5_+-5% +V0.75S

F 340K
OCP 29.1A R=75K
PEAK 20.070A AVG 11.531A
TPS51216 TPS51216
560UF_25M[ // 80UF_0.93M[
POWER BUDGET 13.7 A

+V1.5S
F 340K
OCP 10.1A R=115K
PEAK 17.107A AVG4.835 A
B
560UF_25M[ // 1274.8UF_0.214M[
AON7410 B
+V1.5_CPU
AON7410
+VTT_+-5%
TPS51216
POWER BUDGET 13.7 A
CHANGING POINTS~~ F 340K
A TPS51218 SAME AS 2009 PROJECT OCP 10.1A R=115K A
TPS51217 SAME AS 2010 PROJECT PEAK 17.107A AVG4.835 A
+V1.8S IS NEW IC GMT_AT1530F11U
560UF_25M[ // 1274.8UF_0.214M[
CHARGE IS NEW IC BQ24725
VCC CORE IS NEW IC TPS51640
VTT IS NEW IC TPS51219
V0.85 IS NEW IC TPS 51641
V3_V5 IS NEW IC TPS51123
POWER BUDGET ~~IC SPEC (MAX CURRENT ) INVENTEC
PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION TITLE
AVG CURRENT ~~TEST RESULT(MAX CURRENT) MODEL,PROJECT,FUNCTION

Block Diagram
INRUSH ~~L/S TURN NO
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FUSE6000
65W-75W 8A(6036A0003401)
90W 10A(6036A0002901) PVPACK
PVADPTR PVBAT FUSE6050
120W 12A(6036A0006001)
P3V3AL 1 2
L7600
1
CN6000
FUSE6000 NFE31PT222Z1E9L
2
C6050 LITTLEFUSE_R451015_15A_65V
1 1 1 2 1 2
R6054 R6053
1
2 2 R6800 1 2 1 2 1000PF_50V_2
G1 5 3 3 8A_125V C7602 RSC_0603_DY
G2 4 1M_5%_2 220K_1%_2
2
6 4 CN6050
C7601 1
1
10PF_50V_2 BATT+
ACES_50315_0047N_002_4P 1000PF_50V_2 2 BATT+
HW_V_ADC 1 R6802 2 3
2
ID
OUT R6052 1K_5%_2
33K_5%_2_DY 21E8 21E6 1 2 4 B-I
OUT
BATT_IN
2
TP6003 TP6004 TP6005 5 TS
1 1 1 R6050 33_5%_2
21D2
21D3 1 2 6 SMD G G1
D BI
TP30 TP30 TP30 21D2
21D3 EC_SMB1_DATA 1 2 7 SMC G G2
R6801 BI D
EC_SMB1_CLK
2
C6800 R6051 33_5%_2 8 GND G G3
RSC_0603_DY 9 G4
0.1UF_16V_2_DY GND G
1
R6015 NEAR EC
1 2 D6701 D6702 D6703 SYN_200045GR009G18TZR_9P
PVADPTR EZJZ0V500AA_DY EZJZ0V500AA_DY EZJZ0V500AA_DY
4.7K_5%_3
1
1 R6014 2
RSC_0603_DY PVBAT
PVPACK
Q6010 Q6011
R6000 Q6012 C6033
8 D S 1 1 S D 8 1 2 8 D S 1 1 2
7 2 2 7 3 4 7 2
6 3 3 6 0.01_1%_6 6 3 0.1UF_25V_3
5 G 4 4 G 5 5 G 4
1
CSC0805_DY
NMOS_4D3S NMOS_4D3S NMOS_4D3S

C6020
C6014
1
AM4410NC AM4410NC 1 2 TPCA8065_H
C6030 C6031
1 2 1 2 0.1UF_16V_2
1
PAD6000
2
PVADPTR POWERPAD_2_0610
1
2200PF_50V_2 0.1UF_25V_3
2
C C
R6006
1
1
RSC_1206_DY
RSC_1206_DY
1
1 2 3
2
D6000
RSC_0603_DY
R6018
R6019
D6002
2
DIODES_BAV99 1 A1 A2 2
P3V3AL
R6002 C6021 C6022
C
2
R6004 R6005 0.1UF_25V_3
2
20.5K_1%_2
2
4.3K_5%_2 4.3K_5%_2 0.1UF_25V_3 BAT54C_30V_0.2A
2
3
1
5
6
7
8
2
R6013
1
10K_5%_3 Q6000
R6012
D
AON7410
10_5%_5 C6001 C6002 C6003 C6004
NMOS_4D3S
1
470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

21E6 OUT
ACPRES
5
4
3
2
1
1
C6026
2
U6000 1UF_25V_3
ACOK
ACDRV
CMSRC
ACP
ACN
1 2
S
TI_BQ24725RGRR_QFN_20P
21
4
3
2
1
TML
VRCHARGER_HG
6 ACDET
VCC 20 L6000 R6001
21E8 21E6 HW_I_ADC 7 IOUT
OUT PHASE 19 VRCHARGER_PH 1 2 1 2
B 8 SDA B
HIDRV 18 C6027 3 4
9 SCL ETQP3W4R7WFN
1
BTST 17 1 2
10 ILIM
REGN 16 0.01_1%_6
C6036
BATDRV
5
6
7
8
1
0.047UF_16V_2
LODRV
CSC0805_DY
C6037 100PF_50V_2
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
SRN
SRP
GND
C6010
C6011
C6012
C6013
Q6001
100PF_50V_2 P3V3AL R7600
D
C
1
AON7410
NEAR IC RSC_0603_DY
NMOS_4D3S
SBR3U40P1_DY
2
1
1 2
2
NEAR EC A1 A2 C6023
1
C6034 1 2
11
12
13
14
15
D6700
R6003
2
C6029 CSC0402_DY
3.32K_1%_3
CSC0603_DY C6028 D6001 0.1UF_16V_2
2
1
G
S
C6035 1UF_10V_2 BAT54C_30V_0.2A
1
1
2
CSC0402_DY
0.1UF_25V_3
0.1UF_25V_3
C7600
2
4
3
2
1
C6024
C6025
R6007
CSC0402_DY
110K_5%_2
1
2
R6016
EC_SMB2_DATA 1 2 VRCHARGER_LG
2
37C3
56C8
21D3 21D2
BI
SHORT_0402
R6017
56D8
21D3
37C6 21D2 EC_SMB2_CLK 1 2
BI
SHORT_0402
R6011
A 1 2 A
2
C6032 SHORT_0402
0.1UF_16V_2
R6008 R6010
30K_5%_2 2 1
6.98_1%_2
1
1 R6009 2
4.3K_5%_2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
14D7 EN_5V
IN
120K_1%_2
R6160
D
D
2
PVBAT
2VREF VRP5V0A_PH 6D3
14C7 EN_3V OUT OUT
IN
1
PAD6110 5V_PG
OUT
1
R6110
130K_1%_2
POWERPAD_2_0610
2
VBATP
2
6C3 14C8
OUT
14C8 6C6 VBATP
IN
1
8
7
6
5
5
6
7
8
1
C6123
1
1
Q6100 Q6150
6
5
4
3
2
1
25
0.22UF_6.3V_2
D
D
AON7410
C6160 C6161
C C6111 C
NMOS_4D3S
AON7410
C6110
NMOS_4D3S
TML
TRIP2
VFB2
TONSEL
VREF
VFB1
TRIP1
2
4.7UF_25V_5 4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
2
2
2
R6114 7 VO2 VO1 24
S
S
C6115 2.2_5%_3 8 VREG3 PGOOD 23 R6155 C6155
2.2_5%_3
1 21 2 9 VBST2 VBST1 22
1 1
2 2
1
2
3
4
4
3
2
1
L6100 VRP3V3A_HG10 DRVH2 U6100 DRVH1 21 VRP5V0A_HG 0.1UF_16V_2 L6150
14D6
14D6 VRP3V3A 1 2 0.1UF_16V_2 VRP3V3A_PH11 LL2 LL1 20 VRP5V0A_PH 1 2 VRP5V0A 14C8
OUT OUT
VRP3V3A_LG12 DRVL2 DRVL1 19 VRP5V0A_LG 14D4
ETQP3W3R3WFN ETQP3W3R3WFN
1
1
SKIPSEL
8
7
6
5
5
6
7
8
1
1
VREG5
Q6101 R6150
Q6151
EN0
GND
VIN
ENC
R7610 14C6 R7615
AON7702A
D
D
14C8
R6100 RSC_0603_DY RSC_0603_DY
AON7702A
VRP3V3A_LDO
21
OUT TI_TPS51123RGER_QFN_24P
1
2
15.4K_1%_2
13
14
15
16
17
18
1
2
6.8K_1%_2
2
C7615
+
C6100 14C7 SKIP_3V_5V C6150
C7610 IN CSC0402_DY
+
EN_3V_5V
G
1
G
S
330UF_6.3V
S
CSC0402_DY IN
1
330UF_6.3V VRP5V0A_VIN VRP5V0A_LDO

2
1
2
3
4
4
3
2
1
2
14C7 14D6
IN OUT R6151
2
R6101 10K_1%_2
1
1UF_25V_3
2
B 10K_1%_2 B
C6122
C6121 C6120
2
1UF_6.3V_2 R6113
10UF_6.3V_3
RSC_0402_DY
2
2
VO=(( R6150/R6151)+1)*2
VOUT=((R6100/R6101)+1)*2 VRP5V0A_LG 6B3 14D5

OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVBAT
POWERPAD_2_0610
2
P5V0A
PAD6210
2
D
1
D
P0V75S
1
1
2.2UF_6.3V_3
C6216
5
6
7
8
1
Q6200
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
FDMC8884
C6210
C6211
C6212
NMOS_4D3S
2
2
U6200
S
R6215 C6215
12 V5IN VBST 15 1 2 1 2
4
3
2
1
DRVH 14 VRP1V5_HG 2.2_5%_3 0.1UF_16V_2
L6200
14D1 EN_0V75 17 S3 SW 13 VRP1V5_PH 1 2 VRP1V5 14C2
IN OUT
3 4
RSC_0603_DY
EN_1V5
2
14D1 16 S5 PCMC104T_1R0MN
IN
POWERPAD1X1M
2
5
6
7
8
C C
R7620
11 VRP1V5_LG
FDMS0310AS
DRVL
Q6201
D
PAD6220
1
R6200
DDR3L_SEL
560UF_2.5V
1 2 6 VREF PGND 10
IN
+
CSC0402_DY
1
11
C6200
10K_1%_2 20
PGOOD
C7620
1
9
2
S
VDDQSNS
8 2
4
3
2
1
REFIN VLDOIN
2
VTT 3
VTTSNS 1
7 GND
P0V75M_VREF
2
1
0.01UF_50V_2
0.1UF_16V_2
52.3K_1%_2
19 4
R6201
C6217
C6218
MODE VTTGND
18 TRIP VTTREF 5
1
21
1
100K_5%_2
TML
1
R6203
75K_1%_2
10UF_6.3V_3
0.22UF_6.3V_2
B 1V5_PG B
1 R6202
C6220
C6221
OUT 14C2
TI_TPS51216RUKR_QFN_20P
2
2
VOUT=REFIN=1.8*(R6201/(R6200+R6201))
MODE=100KOHM:TRACKING DISCHARGE
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
P5V0A P3V3S
C C
1
1
GMT_AT1530F11U_SOP8_8P
10UF_6.3V_3
U6970 VOUT=((13K+10K)+1)*0.8
R6970
C6971
10_5%_2
TML 9 OCP=4.5AMP
L6970 VRP1V8S
8 VIN LX 7 VRP1V8S_PH 1 2 14A2
OUT
2
2
PAN_ELL5PR2R2N
1
CSC0402_DY
13K_1%_2
R6973
22UF_6.3V_5
C6974
C6970
1 VCC FB 4
2
EN_1V8
2
14B1 5 EN REF 2
IN
1
1
PGND
0.1UF_16V_2
0.1UF_16V_2
10K_1%_2
GND
C6972
C6973
R6972
2
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
14B7 EN_VCCP PVBAT

IN
POWERPAD_2_0610
2
PAD6310
1
2
100K_5%_2
R6303
1
2
1
14B6 14A8 VCCP_PG
OUT
5
6
7
8
C R6315 C6315 C
1
1 2 1 2
Q6300
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
FDMC8884
D
17
16
15
14
13
C6310
C6311
C6312
2.2_5%_3
NMOS_4D3S
P3V3A 0.1UF_16V_2
U6300
R6306
PWPD
MODE
PGOOD
EN
1 2
BST
2
G
S
10K_5%_2 1 12 VRP1VO_VCCP_PH
VREF SW
R6307
4
3
2
1
46B4 VCCIO_SEL 1 2 2 REFIN DH 11 VRP1VO_VCCP_HG
IN
1
2.2UF_6.3V_3
VSS_SENSE_VCCIO 0_5%_2_DY 3 10 VRP1V0_VCCP_LG L6300

C6318
44A3 GSNS DL
IN
1 1 2 2 VRP1V05S 14A8
P5V0A OUT
44A3 VCC_SENSE_VCCIO 4 VSNS V5 9 3 3 4 4
IN
RSC_0603_DY
5
6
7
8
2
COMP
PGND
CYN_PCMB063T_R68MS_4P
2
TRIP
GND
FDMS0310AS
R7630
Q6301
D
1
1
TI_TPS51219RTER_QFN_16P
22UF_6.3V_5
560UF_2.5V
2.2UF_6.3V_3
C6316
+
1 1
C6300
C6301
C6319
CSC0402_DY
5
2 6
8
2 1
86.6K_1%_2
C7630
0.01UF_50V_2
2
R6302
2
B B
4
3
2
1
2
1
VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
1
C6522
0.01UF_50V_2
C6520 R6520
1 2 1 2
2
3300PF_50V_2 5.11K_1%_2
1
VCCSA_SENSE 45A2
IN
C6521
P5V0A R6521
0.22UF_6.3V_2 1 2
2
RSC_0402_DY
1
2
3
4
5
6
C C
COMP
MODE
GND
SLEW
VOUT
VREF
TI_TPS51461RGER_QFN_24P
25 TML L6500
24 VIN SW 7 VRPVSA_PH 1 1 2 2 VRPVCCSA 14A6
OUT
23 VIN SW 8 3 3 4 4
22 VIN U6500 SW 9
1
21 PGND SW 10 CYN_PCMB063T_R33MS_4P
C6510 C6511 20 PGND SW 11 C6515
1
0.1UF_16V_2 19 PGND BST 12 1 2
22UF_6.3V_5
PGOOD
C6500 C6501 C6502 C6503
V5DRV
V5FILT
1
VID1
VID0
0.1UF_16V_2
2
EN
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY
R7650
2
RSC_0603_DY
18
17
16
15
14
13
EN_SA
1 2
IN 14B5
R6524
1 2 VCCSA_VID0 C7650
IN 45A2
CSC0402_DY
SHORT_0402
R6525
2
1 2 VCCSA_VID1 45A2
IN
1
B SHORT_0402 B
1UF_6.3V_2
1UF_6.3V_2
C6523
C6524
2
SA_PG 14A6 21B6

OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PVBAT PAD6610
VREF_CPU 1 R6620 2 1 R6622 2
11D7 11D4 11C8 11B7 11A7 11A4 IN POWERPAD_2_0610
43K_1%_2 PVBAT_CPU
39K_1%_2 1 2 11B3 11D3
1 2 OUT
1
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
C6611
C6612
C6613
C6614
C6615
C6616
C6617
R6623
1 R6621 2 1 2 C6000
C6610
68UF_25V
90.9K_1%_2 24K_1%_2
2
2+1 2+0 C6632
11B7 11A7 11A4 VREF_CPU 1 2
IN
R6626 3.3K DNP 11D6 11D4 11C8
1
1
100PF_50V_2 CPU_CSN1
C6631 11D5 OUT
R6627 56K DNP
44B3
44B3
P3V3A R6618
0.1UF_16V_2_DY
R6625 100K_5%_NTC
R6711 200K DNP 1 2
D
2
11C3
11C3
11D3
11D3
2
C6623 D
R6712 30K DNP 8.45K_1%_2 R6619 CPU_CSP1 1 2
2 VREF_CPU OUT
1
1 11A4 11A7 11B7 11C8 11D6 11D7
IN
R6714 DNP 0
R6626 15.4K_1%_2 0.033UF_16V_2
IN
IN
IN
IN
IN
IN
P5V0A
R6716 DNP 0 3.3K_1%_2 PVBAT_CPU 11B3 11D1 R6605
IN
R6617 1 2
V5_CPU
11 VCCSENSE
12 VSSSENSE
8
5
6
7
1 2
6 CPU_CSN2
7 CPU_CSP2
4 CPU_CSP1
11C4
CPU_CSN1
R6719 DNP 0 OUT
2
10_5%_3 162K_1%_2
Q6610
FDMS7692
D
R6723 DNP 0 C6629 C6630 R6602 R6603 R6604
NMOS_4D3S
PVCORE
1
1 2 1 2 1 2
10
2.2UF_10V_3 4.7UF_10V_3
1
R6627 17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
56K_1%_2
S
CCOMP
CGFB
CVFB
CCSN3
CCSP3
CCSP2
CCSN2
CCSN1
CCSP1
CF-IMAX
COCP-R
CTHERM
PAN_ETQP4LR36ZFC_4P
3 4
2
4
3
2
1
GND 49 1 2
1
5
6
7
8
L6610
P3V3A 13 48 V5_CPU
FDMS0306AS
GOCP-R V5
IN 11D5
11D6 11D7
Q6611
R7661
D
11C8 11D4
1
VREF_CPU RSC_0603_DY C6600 C6601
1
11B7 14 VREF CDH1 47
VREF_CPU 11A4 OUT 470UF_2V
IN
21
11A7 R6601 C6622 470UF_2V
+
15 V3R3 CBST1 46 1 2 1 2
1
C7661
C C
C6634 VR_ON 16 45 2.2_5%_3 0.1UF_16V_2 CSC0402_DY
S
11A7 IN VR_ON CSW1
3
2.2UF_6.3V_3
3
PVCORE_PG 17 44 CPU_CSN2
4
3
2
1
2
49B7 40B4 11A4 OUT CPGOOD U6600 CDL1 11D5 OUT
C6633
1
2.2UF_6.3V_3 VR_SVID_CLK 18 43
44C2 11A3 IN VCLK V5DRV P5V0A
R6628
R6711 VR_SVID_ALERT#19 42
44C2 OUT ALERT# PGND C6625
200K_1%_2 0_5%_2_DY CPU_CSP2 1 2
11D5 OUT
VR_SVID_DATA 20 41
2
44C2 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2
0.033UF_16V_2
41D6 21C3 CPU_PROCHOT# 21 VR_HOT# CSW2 40 R6610
OUT PVBAT_CPU 11D1 11D3
R6606 C6624 IN 1 2
5
6
7
8
22 SLEW CBST2 39 1 2 1 2
162K_1%_2
2.2_5%_3 0.1UF_16V_2
Q6620
FDMS7692
D
11A4 PVAXG_PG 23 GPGOOD CDH2 38 R6607 R6608 R6609
OUT
NMOS_4D3S
R6616 1 2 1 2 1 2 PVCORE
24 GF_IMAX VBAT 37 1 2
GTHERM
GSKIP#
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
GCOMP
GCSN1
GCSP1
GCSP2
GCSN2
GPWM1
GPWM2
CPWM3
GGFB
GVFB
10K_5%_3
1
S
R6629
PAN_ETQP4LR36ZFC_4P
20K_1%_2 3 4
4
3
2
1
B 45C3 GFX_VSS_SENSE 1 2 1 2 B
IN PVBAT
1
25
26
27
28
29
30
31
32
33
GPWM134
GPWM235
CPWM336
R6712 R6713 0_5%_2 L6620
5
6
7
8
30K_1%_2 45C3 GFX_VCC_SENSE 1 2
IN
2
FDMS0306AS
R7662
0_5%_2
Q6621
R6715
D
RSC_0603_DY
1
1
11D7
P3V3A
21
11D6 C6602 C6603
11C8 C6726
VREF_CPU 470UF_2V 470UF_2V
+
11A4 1 2 1 2 C7662
IN
OUT
OUT
OUT
11A7
1
R6719 0_5%_2_DY
11D4 CSC0402_DY
S
100PF_50V_2
3
2
3
R6714 R6716 1 2
2
R6718
4
3
2
1
0_5%_2_DY 0_5%_2_DY 1 2
12B8
R6723 0_5%_2_DY
4.12K_1%_2
2
P3V3A
21D3 EN_PVCORE R6731

IN
0_5%_2
0_5%_2
1 2 VREF_CPU 11A7 11B7 11C8 11D4 11D6 11D7

IN
1
RSC_0402_DY
1
R6724
R6720
GSKIP# 12C8
R6630 OUT
2
20K_5%_2
1
GPU_CSN1
GPU_CSP1
2
A R6730 P3V3A P1V05S A

VR_ON 11C7 100K_5%_2
OUT
1
R6631
IN
IN
1
1
8.66K_1%_2
0.1UF_16V_2
130_1%_2
2K_5%_2
54.9_1%_2
R6732
R6632
R6633
C6635
2K_5%_2
R6634
R6728
2
11D7 11D6 11D4 11C8 11B7 11A4 VREF_CPU 1 2

IN
1
15.4K_1%_2
INVENTEC
12C5
12C5
2
R6729 C6727 2
49B7 40B4 11C7 PVCORE_PG 11C7 VR_SVID_CLK
100K_5%_NTC 0.1UF_16V_2_DY OUT IN
44C2
TITLE
2
2
PVAXG_PG VR_SVID_DATA MODEL,PROJECT,FUNCTION

11B7 OUT 44C2 11C7 BI Block Diagram
DOC.NUMBER REV
CODE
R6638 SIZE 1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
11A6 GPU_CSN1
OUT
C6722
11A6 GPU_CSP1 1 2
OUT
0.033UF_16V_2
PVBAT_AXG R6705
12B1
IN 1 2
C C
5
6
7
8
162K_1%_2
Q6710
R6701 C6720 PVBAT
FDMS7692
D
1 2 1 2 R6702 R6703 R6704
NMOS_4D3S
1 2 1 2 1 2 PVAXG
1
2.2_5%_3 0.1UF_16V_2
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
U6710
1
9 PAD6710
S
PAD
PAN_ETQP4LR36WFC_4P
1 8 POWERPAD_2_0610
2
BST DRVH 3 4
4
3
2
1
11A4 GSKIP# 2 SKIP# SW 7
IN 1 2
1
11B5 GPWM1 3 PWM VDD 6 L6710
IN PVBAT_AXG
5
6
7
8
2
12C5
4 GND DRVL 5 OUT
FDMS0306AS
R7671
Q6711
D
1
P5V0A RSC_0603_DY
TI_TPS51601DRBR_SON_8P
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
C6710
C6711
C6712
C6713
C6700
21
C6701 C6702
+
+
+
1
470UF_2V 560UF_2.5V_DY
470UF_2V_DY
1UF_6.3V_2
C6721
C7671
CSC0402_DY
G
2
S
2
4
3
2
1
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R7016
16A1 13B2 DGPU_PWR_EN
1 2 EN_DGPU 13C8
IN OUT
16A8
16C4
10K_5%_2
PVBAT
45D3 21D6 R7020
14A6 13A2 SLP_S3#_3R1 2
IN
1
14D2 14B8
0.1UF_16V_2
1
49A1
C7010
0_5%_2_DY
POWERPAD_2_0610
PAD6760
2
D
2
D
1
1
P5V0A R6755
5
6
7
8
1 2
C6761
C6762
C6760
PVCORE_DGPU
4.7UF_25V_5
4.7UF_25V_5
4.7UF_25V_5
Q6750
FDMS7692
D
240K_5%_2
NMOS_4D3S
R6752 C6753
U6750 PAD6750
2
2.2_5%_3 0.1UF_16V_2 VRPVCORE_DGPU1 2
2
16 13 1 2 1 2 13C3 IN 1 2
1 R6756 2 TON BOOT
1
POWERPAD_2_0610
9
S
10_5%_2 VDDP
1UF_6.3V_2
1UF_6.3V_2
PAD6751
C6754
C6757
1 2
12 VRPVCORE_DGPU_HG
4
3
2
1
1 2
UGATE
L6750
VRPVCORE_DGPU
1
PAN_ETQP4LR36WFC_4P POWERPAD_2_0610
2 VDD PHASE 11 VRPVCORE_DGPU_PH 1 2 13C2
OUT
2
3 4 C6751
+
5
6
7
8
1
8 VRPVCORE_DGPU_LG
RSC_0603_DY
LGATE
2K_1%_2
FDMS0308AS
470UF_2V
Q6751
R7675
R6750
D
52C6 13B2 DGPU_PWRGD 4 PGOOD
OUT
3
470UF_2V
C 10 7 PWRCNTL_1 C6752 C
2
CS G0
IN 56C5 56F7
+
2
2 C6750
1
470UF_2V
CSC0402_DY
1
3
C7675
FB
1
G
S
R6758
16.2K_1%_2
56F7
3
9.53K_1%_2 14 PWRCNTL_0
R6751
G1
IN 56D5
4
3
2
1
EN_DGPU
15 5 1 2
2
2
13D1 IN EN_DEM D1
R6753 8.66K_1%_2 P3V3S_DGPU
2
17 GND D0 6 1 2
R6754 21K_1%_2
1
VOUT 1
10K_5%_2
REA_RT8208BGQW_WQFN_16P
R7017
2
DGPU_PWRGD
52C6 13C8
IN OUT
P.S. R6750(R1) R6751(R2) R6753(R3) R6754(R4)

B B
P1V5S_DGPU
P1V5S_DGPU
1
R7018
100K_5%_2_DY
22UF_6.3V_5
C6955 2
P5V0A
16A1 13D2 1 R7019
DGPU_PWR_EN 2 EN_VPCIE 13A6
IN OUT
16C4 16A8 1K_5%_2
2
VRPVPCIE
1
13A2 49A1
OUT 21D6
1UF_6.3V_2
C7011
14B8 R7030
13D2 SLP_S3#_3R1 2
IN
14A6
1
U6950
14D2
68PF_50V_2
2.7K_1%_2
0_5%_2_DY
C6952
45D3
R6950
2
5 VIN VO_2 4
1
6 3
2
VPP VO_1
22UF_6.3V_5
1UF_10V_5
C6950
C6951
7 2
POK ADJ PVPCIE
13B1 EN_VPCIE 8
IN
1
VEN
A 9 1 PAD6950
A
10K_1%_2
TML GND
1
2
R6951 13A3 VRPVPCIE 1 2
1UF_10V_5
IN 1 2
C6954
GMT_G9731AF11U_SOP_8P
POWERPAD_2_0610
2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR_P1V5
3V & 5V 21D6
R7010
14A6
13A2 SLP_S3#_3R 1 2 EN_0V75 7C7
IN OUT
EN_5V 6D6 13D2 47K_5%_2
OUT VRP5V0A
1
P5V0A 14D6 14C8 6C1 14B8
IN 49A1
45D3
1
Q7000 PAD6150
0.047UF_16V_2
VRP5V0A C7005
2
1 2
C7000
14D4 14C8 6C1 IN 1 2
15D4
21C3 EC_PW_ON# 1 G 0.1UF_16V_2
IN
POWERPAD_2_0610
2
S
2 13
2
SSM3K7002BFU
C7001 D7001
2
0.1UF_16V_2
P3V3AL DIODES_BAV99
SLP_S5#_3R 1 R7012 2 EN_1V5
1
21D3 IN OUT 7C7
49B3
1
D PAD6100 0_5%_2
6C8 VRP3V3A 1 2 D
IN
1
1
1 2
C7006
POWERPAD_2_0610
2
CSC0402_DY
A1
C7002 C7003
0.1UF_16V_2
2
0.1UF_16V_2
6B3 VRP5V0A_LG 2 13
IN P3V3S
2
21F6 D7000
14C8 P5VAUXON 3
IN C P5V0AL
15D6 D7002 P15V0A
2
DIODES_BAV99
1
BAT54C_30V_0.2A_DY VRP5V0A_LDO1 2
6B4 IN R7013
1
1 2
A2
RSC_0402_DY
PAD6120 C7004
7B3 1V5_PG 1V5_PG
EN_3V POWERPAD1X1M IN OUT
1
OUT 6D6 1UF_25V_3 14C2
2
VRP3V3A_LDO 1 R7000 2
2
14C6 6B6 IN P3V3_LDO
RSC_0402_DY P1V5
R7001 PAD6200
14D4 6C1 VRP5V0A 1 2 SKIP_3V_5V 6B5 14C8 6B6 VRP3V3A_LDO
1 2
IN OUT IN 1 2 1 2
14D6 10K_5%_2 1 2
PAD6121
R7002 POWERPAD_2_0610
6C6 6C3 VBATP 1 2 VRP5V0A_VIN 6B5 POWERPAD1X1M PAD6201
IN OUT
C 0_5%_3 7C1 VRP1V5 1 2 C
IN 1 2
21F6 R7003
14D8 P5VAUXON 1 2 EN_3V_5V 6B4 POWERPAD_2_0610
IN OUT
15D6 0_5%_2
VCCIO VCCSA DGPU P1V8S
R7040
21D6 VCCP_PG 1 2 EN_SA
14A6 R7021 14A8 9C6 IN OUT 10B4
13A2 SLP_S3#_3R 1 2 EN_VCCP 9D6
IN OUT
1
13D2 0_5%_2
14D2 P3V3S
49A1
45D3 47K_5%_2 C7040
1
0.1UF_16V_2
CSC0402_DY
C7020
R7050
1 2 EN_1V8 8B6
OUT
2
10K_5%_2
B B
2
1
C7050
0.01UF_50V_2
P3V3S
2
1
P3V3S
R7041
10K_5%_2
2
10K_5%_2
R7022
21B6 14A6 10A5 SA_PG SA_PG

IN OUT
2
1
14B6
14A8 D7040
9C6 VCCP_PG VCCP_PG
IN OUT P1V8S
NC
14B8 13D2 13A2 SLP_S3#_3R 3 1

IN
49A1
45D3 21D6 14D2
PAD6900
DIODE-BAT54-TAP-PHP VRP1V8S 1 2
8C2 IN 1 2
A A
POWERPAD_2_0610
P1V05S
PAD6300 PVSA
1 2
1 2
POWERPAD_2_0610 PAD6500
10C1 VRPVCCSA 1 2
IN 1 2
PAD6301
9B1 IN
VRP1V05S 1
POWERPAD_2_0610
1 2
2 POWERPAD_2_0610
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P15V0A P3V3AL
P3V3A
P3V3AL
Q7102 PAD7100
1
1 D S 4 1 2
1 2
1
2
R7105 5 POWERPAD_2_0610
R7104 100K_5%_2 6 3
G
PVBAT P3V3_LDO NMOS_4D1S
2
100K_5%_2_DY
1
AO6402AL
3
R7106
1
Q7101 200_5%_2
1
4
D
R7491
U7490
510K_1%_2 21C3
14D8 EC_PW_ON# 1 G C7100
IN
2
VDD
2
D 2200PF_50V_2
S
2
D7490 D
1
SSM3K7002BFU
NC
2
21F6
2
THRM_SHUTDWN#3 P5VAUXON
3
40B1
40A8
56D6 1 5 SENSE RESET# 3 14C8
OUT OUT R7100
14D8 Q7103
D
10K_5%_2
DIODE-BAT54-TAP-PHP 1
R7492 G
2
GND
GND
S
120K_1%_2 TI_TPS3801_01_SC70_5P
2 SSM3K7002BFU
2
P3V3AL
P15V0A P3V3S
C PAD7101 C
POWERPAD_2_0610
Q7105
1 D S 4 2 1
1
2 1
2
470K_5%_2
1
R7107
1
5
200_5%_2
R7109
22UF_6.3V_5
6 3
C7103
G
NMOS_4D1S
AO6402AL
2
R7108
1 2
32
2
1
3
680PF_50V_2
Q7106
0_5%_2
C7102
1
D
Q7104
2200PF_50V_2
15B8
SLP_S3_3R 1
D
C7101
15A4 G
49B1
16A7 IN
15A4 SLP_S3_3R 1 G 15B4
IN 49B1
16A7
S
15B4
2
S
SSM3K7002BFU
2
2
SSM3K7002BFU
2
P5V0S
P5V0A
PAD7102
POWERPAD_2_0610
Q7107 2 1
B 1 D S 4 B
2 1
1
2
5
200_5%_2
R7111
1
6 3
22UF_6.3V_5
G
C7105
NMOS_4D1S
AO6402AL
R7110
3
2
1 2
Q7108
1
2
CSC0402_DY
D
0_5%_2 15B8
C7104
15A4 SLP_S3_3R 1 G
IN
15B4
49B1
16A7
S
SSM3K7002BFU
2
2
P1V5S
P1V5
PAD7103
POWERPAD_2_0610
Q7109
8 D S 1 1 2
1 2
1
7 2
200_5%_2
R7113
6 3
1
5 G 4
A A
22UF_6.3V_5
NMOS_4D3S
C7107
23
AON7410 P0V75S
Q7112 Q7110
8 1
D
D S
1
15B4
7 2 SLP_S3_3R 1
2
G
49B1
16A7 IN
200_5%_2
R7114
6 3 15B8
S
5 G 4
NMOS_4D3S
SSM3K7002BFU
2
R7112 AON7410
3
2
1 2
Q7111
INVENTEC
1
D
CSC0402_DY
0_5%_2 1
C7106
TITLE
S
SSM3K7002BFU Block Diagram
2
2
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V5 P1V5S_DGPU
Q7113
8 D S 1
7 2
6 3 POWER EXPRESS
5 G 4
NMOS_4D3S
AON7410
Q7114
8 D S 1 DURING RESET AFTER RESET
7 2
D 6 3
5 G 4 D
HIGH HIGH 0 : DGPU POWER SWITCH TURNED ON
NMOS_4D3S
DGPU_PWR_EN#
AON7410
1 : POWER SWITCH TURNED OFF
1
R7116
16B7 16A5 DGPU_PWR_EN_15R 1 2 R7115
IN
0 : DGPU POWER IS NOT STABLE
1
200_5%_2
220K_5%_2 DGPU_PWRGD
C7108 1 : DGPU POWER IS STABLE
2
680PF_50V_2
0 : KEEP DGPU IN RESET
2
LOW LOW
DGPU_HOLD_RST#
3
1 : RESET IS RELEASED
Q7115
D
16B7 16A6 DGPU_PWR_EN_3R 1 G SSM3K7002FU
IN
S
P3V3S P3V3S_DGPU
0_5%_2_DY
2
R7042
1 2
P3V3S DIODES_DMP2305U_SOT23_3P
Q7003
C S D C
1
S D
P1V8S P1V8S_DGPU
CSC0402_DY
CSC0402_DY
10K_5%_2
R7031
C7023
C7024
G
R7038
1 0_5%_6_DY
2
G
Q7118
3
2
2
1 4 Q7002
D S
2 SSM3K7002BFU
D
5 R7039
16A8 16A1 13D2 13B2 DGPU_PWR_EN1 2 1 G
6 G 3 IN
NMOS_4D1S 0_5%_2
S
1
AO6402AL
CSC0402_DY
1
C7021
2
R7120 R7119
16D7 16A5 DGPU_PWR_EN_15R 1 2
IN 200_5%_2
1
2
220K_5%_2
2
C7110
680PF_50V_2
3
2
B B
Q7119
D
16C7 16A6 DGPU_PWR_EN_3R 1 G SSM3K7002FU

IN
S
P3V3S
2
1
R7121
10K_5%_2
DGPU_PWR_EN
2
OUT 13B2 13D2 16A8 16C4
3
P15V0A
Q7120
1M_5%_2
1
D
DGPU_PWR_EN#1 SSM3K7002BFU
R7034
51C7 51B6 IN G
P3V3_LDO
S
1
10K_5%_2
DGPU_PWR_EN_15R
R7033
OUT 16B7
16D7
3
2
2
16B7 IN Q7019
16C7 SSM3K7002BFU
D
DGPU_PWR_EN_3R 1 G
3
2
A Q7018 A
SSM3K7002BFU
S
D
R7047
13D2 13B2 DGPU_PWR_EN 1R7035 2 1 G SLP_S3_3R
1 2
IN IN
2
16C4 16A1 0_5%_2

1
0_5%_2_DY
C7022
CSC0402_DY
2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 0~49(PCB SCREW)
D
D
BOUNDARY SCAN TEST POINT

FIX1 FIX5
1 1
PVCORE PVBAT
FIX_MASK FIX_MASK
TP1
1 TP3 TP4 TP5
FIX2 FIX6 1 1 1
1 1
TP30
TP30 TP30 TP30
FIX_MASK FIX_MASK
PVCORE_DGPU
PVAXG
FIX3 FIX7
1 1 TP2
1
TP6 TP7
FIX_MASK FIX_MASK 1 1
TP30
FIX4 FIX8 TP30 TP30
1 1 PVADPTR
FIX_MASK FIX_MASK
TP8 TP9 TP10
1 1 1
TP30 TP30 TP30
C C
PCB CPU GPU WLAN

S1 S10 S14 STD16
1 1 1 1
SCREW300_1000_1P
SCREW330_600_1P SCREW330_600_1P
STDPAD_1.15_6-TOP
1.6MM
S2 S11 S15
1 1 1
SCREW300_1000_1P
SCREW330_600_1P SCREW330_600_1P
S23
1
S3
1
S12 1 3G
SCREW300_1000_1P SCREW330_600_1P 1 STD17
SCREW330_600_1P
S13 S24 STDPAD_1.15_6-TOP
S5 1 1.6MM
1 1
SCREW300_1000_1P SCREW330_600_1P 1 STD18
B SCREW330_600_1P B
STDPAD_1.15_6-TOP
S6 1.6MM
1
SCREW300_1000_1P
S7
1
SCREW300_1000_1P
S8
1
SCREW300_1000_1P
FAN
S21
S18 1
1 SCREW120_0_600_1P
SCREW220_700_1P
S20
1
SCREW540_1000_NP_1P
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 50-99(HALL SENSOR)
D
D
C P3V3AL C
1
R50
U50 100K_5%_2
VDD 1
2
3 GND
OUT 2 LID_SW#_3 21D3

OUT
1
1
MAG_MH248BESO_SOT23_3P D50
C50
VARISTOR_DY
1000PF_50V_2
2
2
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 100~199(LED)
D
SUSPEND LED P3V3A
D
D154
R160
TP100
21B6 PWR_OLED# 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
P5V0S
POWER ON LED
C D159 C
R150
TP101
21D6 PWR_WLED# 1 1 2 1 2
IN
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
P3V3S
WIFI/WIMAX/3G/LTE LED
D156
R155
TP104
21D6 WL_OLED# 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
DC IN / BATTERY CHARGE LED

B D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED B
D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

BLINK:LOW BATTERY
P5V0A
D152
R152
TP102
21B6 DCIN_WLED# 1 1 2 1 2
IN
TP30
220_5%_2
19_217_T1D_CP1Q2QY_3T
P3V3AL
D155
A BAT_OLED# TP103
R154 A
21B6 1 1 2 1 2
IN
TP30
150_5%_2
HT_191UY
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 200~249(POWER CONN)

R253
REFERENCE 250~299(KB/TP CONN) 1 2
0_5%_2_DY
P3V3S CN250
SCAN_OUT<17..0>
21B3 34 34
OUT
16 SCAN_OUT<16> 33 33
32 32
17 SCAN_OUT<17> 31 31 G2 G2
30 30 G1 G1
D 29 29
4 SCAN_OUT<4> 28 D
28
2 SCAN_OUT<2> 27 27
13 SCAN_OUT<13> 26 26
15 SCAN_OUT<15> 25 25
1 SCAN_OUT<1> 24 24
0 SCAN_OUT<0> 23 23
SCAN_IN<7..0>
11 SCAN_OUT<11> 22 22 21B3 20C6
IN 0 SCAN_IN<0> D250 1 2 VARISTOR_DY
9 SCAN_OUT<9> 21 21
5 SCAN_OUT<5> 20 20 1 SCAN_IN<1> D251 1 2 VARISTOR_DY
6 SCAN_OUT<6> 19 19
2 SCAN_IN<2> D252 1 2 VARISTOR_DY

14 SCAN_OUT<14> 17 17
8 SCAN_OUT<8> 16 16

7 SCAN_OUT<7> 14 14
21B3 20D3 SCAN_IN<7..0>
IN 7 SCAN_IN<7> 12 12
2 SCAN_IN<2> 11 11
C C
3 SCAN_IN<3> 10 10
4 SCAN_IN<4> 9 9
0 SCAN_IN<0> 8 8
5 SCAN_IN<5> 7 7
6 SCAN_IN<6> 6 6
1 SCAN_IN<1> 5 5
4 4
21B6 CAPS_LED#_3 R250 1 2 200_5%_2 3 3

IN
21D6 SCROLL_LED#_3 R251 1 2 200_5%_2 2 2

IN
21D6 NUM_LED#_3 R252 1 2 200_5%_2 1 1
IN
PTWO_AFF340_A2G1V_P _34P
KEYBOARD CONN
2
D258 D259 D260
VARISTOR_DY VARISTOR_DY VARISTOR_DY
1
B B
P5V0S
CN200
CN280
1 1 21D3 PWR_SWIN#_3 1 1 G 3
OUT
21D2
21D3 IM_CLK_5 2 2 2 2 G 4
BI
21D2
21D3 IM_DAT_5 3 3 G G1
BI
2
4 4 G G2
ACES_50224_0020N_001_2P
ACES_50503_0044N_001_4P D200
VARISTOR_DY
2
A A
D280
PHP_PESD5V2S2UT_SOT23_3P_DY
3
POWER CONN
TOUCHPAD CONN
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 300~389(KBC)
P3V3AL P3V3AL_R P3V3S

F P3V3AL F
CLOSE PIN4
R318
1 2
1
1
1
10UF_6.3V_5_DY
2.2_5%_3
R320
4.7UF_6.3V_3
2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
C313
C300
C301
C302
C303
C304
C312
C306
100K_5%_2
FOR ESD PROTECT D300
NC
2
15D6 14D8 14C8 P5VAUXON 3 1 VCC_POR# 21B6
IN OUT
2
2
DIODE-BAT54-TAP-PHP
R301 0_5%_1
56D6 VGA_LCM_BKLTEN 1 2 LCM_BKLTEN 21E6
IN OUT
R302 0_5%_1 P3V3AL_R P3V3AL_EC

PCH_LCM_BKLTEN 1 2
P3V3AL 50D7
P3V3AL_EC IN P3V3S P3V3AL_EC
P3V3S
1
GM: 100K
115
102
R344 R345
19
46
76
88
L300
PM: 10K
4
1 2
100K_5%_2 10K_5%_2_DY R332 R323 U301
FBM_11_160808_121T
10K_5%_2 4.7K_5%_2 P3V3S
VDD
1
AVCC
10UF_6.3V_5_DY
VCC1
VCC2
VCC3
VCC4
VCC5
2
2
0.1UF_16V_2
2
C314
C305
2
E P3V3AL_EC_VREF104 VREF LRESET#/GPIOF7 7 BUF_PLT_RST# 27C3 27C7 28C3 51A8 57A6 E
IN
LCLK/GPIOF5 2 CLK_KBPCI 51A7
BI
1
HW_I_ADC 97 3 LPC_3S_FRAME#
2
21E8 5B7 IN GPIO90/AD0 LFRAME#/GPIOF6

BI 27C3 47C3
10K_5%_2
TP310 1 98 GPIO91/AD1 LAD3/GPIOF4 1 LPC_3S_AD<3> 27C3 47C3
BI
10K_5%_2
R312
R326
21E8 5D3 BATT_IN TP30 99 GPIO92/AD2 LAD2/GPIOF3 128 LPC_3S_AD<2> 27C3 47C3
IN BI
TP311 1 100 GPIO93/AD3 LAD1/GPIOF2 127 LPC_3S_AD<1> 27C3 47C3
BI
34B5 EC_BKLTEN TP30 108 GPIO05/AD4 LAD0/GPIOF1 126 LPC_3S_AD<0> 27C3 47C3
OUT BI
AGND_KBC LCM_BKLTEN 96 125 PCI_3S_SERIRQ
2
21E6 IN GPIO04/AD5 SERIRQ/GPIOF0
BI 27B7 47C2
5B8 ACPRES 95 GPIO03/AD6 GPIO11/CLKRUN# 8 PCI_3S_CLKRUN# 49A5 49B3
IN OUT
R303 1 2 94 GPIO07/AD7 GPIO65/SMI# 91 TP324TP30
21E6 5B7 HW_I_ADC 10K_5%_2 ECSCI#/GPIO54 29 RUNSCI0#_3 51C7 52D6
IN OUT
TP313 1 101 GPIO94/DA0 GPIO10/LPCPD# 124 TP30 1
TP325
21E6 5D3 BATT_IN TP314 1
TP30 105 GPIO95/DA1 GPIO85/GA20 121 EC_3S_A20GATE 52C2
OUT OUT
45D3
49A1 14D2 14B8 14A6 13D2 13A2 SLP_S3#_3R TP30 106 GPIO96/DA2 KBRST#/GPIO86 122 KBRST# 52C2
IN P3V3AL OUT
1
36B2 37B1 HDMI_HPD_EC 107 GPIO97/DA3

OUT R300
2 1
0.1UF_16V_2
0.1UF_16V_2
C317
C315
10K_5%_2
TP315 1 79 GPIO02 GPIO52/PSDAT3/RDY# 27 PWR_SWIN#_3 20A4
OUT
20B7 SCROLL_LED#_3 TP30 114 25 TP30 TP306 1 RSMRST# 21D1 49B7 49C2
P3V3AL OUT GPIO16 GPIO50/PSCLK3/TDO
OUT P5V0S
1 6 11 EN_PVCORE
2
TP316 GPIO24 GPIO27/PSDAT2 11A8

OUT
20B7 NUM_LED#_3 TP30 109 GPIO30/F_WP# GPIO26/PSCLK2 10 USB_OC#_2 30A3
R346 OUT IN 21D3 20A8 IM_DAT_5 R308 2 1 47K_5%_2
49A6 49A5 ACPRESENT 14 GPIO34/CIRRXL GPIO35/PSDAT1 71 IM_DAT_5 20A8 21D2 BI
2 1 IN BI 21D3 20A8 IM_CLK_5 R311
2 1 47K_5%_2
49B8 EC_PWRSW# TP307 1 15 GPIO36 GPIO37/PSCLK1 72 IM_CLK_5 20A8 21D2 BI
IN BI
100K_5%_2 49A8 LOW_BAT#_3 TP30 80 GPIO41/F_WP#
OUT P3V3AL
19B4 WL_OLED# 26 GPIO51/N2TCK
OUT
32A6
32C1
33C6 USB_OC#_1 123 GPIO67/N2TMS GPIO17/SCL1/N2TCK 70 EC_SMB1_CLK 5D3 21D2
OUT BI 21D3 5D3 EC_SMB1_CLK R322
2 1 3.3K_5%_2
24A2 EC_MUTE# 73 GPIO70 GPIO22/SDA1/N2TMS 69 EC_SMB1_DATA 5D3 21D2 BI
OUT BI 21D3 5D3 EC_SMB1_DATA R321 2 1 3.3K_5%_2
D 22D7 WOL_AUX_ON# 74 GPIO71 GPIO73/SCL2 67 EC_SMB2_CLK 56D8 BI D
OUT BI 37C6 56D8 21D3 5A7 EC_SMB2_CLK R317
2 1 1.8K_5%_2
TP317 1 75 GPIO72 GPIO74/SDA2 68 EC_SMB2_DATA 56C8 BI
EC_SMB1 EC_SMB2 EC_SMB3 BI 27C2 37C3 56C8 21D3 5A7 EC_SMB2_DATA R316
2 1 1.8K_5%_2
TP30 GPIO23/SCL3A 119 AOAC_ON# 21D2 BI
BI 21D3 27C2 AOAC_ON# 2
R334
1
1.8K_5%_2
GPIO31/SDA3A 120 WLON# 21D2 27B2 BI
1.BATTERY 1.CHARGE BI 21D3 27B2 WLON# 2
R335
1
1.8K_5%_2
31D4 31A5 USB30_PWR_EN 117 GPIO20/TA2/IOX_DIN_DIO GPIO47/SCL4A 24 FLASH_OVERRIDE 47B7
47B8 BI
OUT OUT
32A8 EC_ILIM_SEL 112 GP(I)O84/IOX_SCLK/XORTR# GPIO53/SDA4A 28 LID_SW#_3 18C4
2.GPU THERMAL OUT IN
32A8 EC_CTL2 110 GPO82/IOX_LDSH/TEST# GPIO42/SCL3B/TCK 17 TP30 TP326 1
OUT
19C7 PWR_WLED# 93 GPIO06/IOX_DOUT GPIO43/SDA3B/TMS 20 TP30 TP303 1 SLP_S5#_3R 14D2 49B3
3.CEC OUT IN
GPIO44/SCL4B/TDI 21 TP30 TP304 1 H_PROCHOT_EC 21B1
OUT
GPIO46/SDA4B/CIRRXM/TRST# 23 TP30 TP305 1 SB_USB_2 30B6
OUT
TP318 1 91 GPIO81/F_WP#
47A6 21C8 EC_SPI_CS0# TP30 90 F_CS0# RSMRST# 21D3 49B7 49C2

OUT 33_5%_2 OUT
47A6 21C7 EC_SPI_CLK R342 1 2 EC_SPI_CLK_R 92 F_SCK
OUT
1
GPIO75/SPI_SCK 82 EC_PW_ON# 15D4
14D8
33_5%_2 OUT
47A6 21C7 EC_SPI_SI R341 1 2 EC_SPI_SI_R 86 F_SDI_F_SDIO1 GPIO77/SPI_DI 84 SB_USB_1 32C3
32A8
33D8 R333
OUT OUT
47A6 21C8 EC_SPI_SO R340 1 2 EC_SPI_SO_R 87 F_SDIO_F_SDIO0 GPIO76/SPI_DO 83 EC_CTL1 32A8 10K_5%_2
IN OUT
33_5%_2
1
44
P3V3AL VCORF
2
P3V3AL R336
R313
AGND
10K_5%_2
GND1
GND2
GND3
GND4
GND5
GND6
1 2 1 10K_5%_2_DY
U300 C310
47A6 21D6 EC_SPI_CS0# 1 CS# VCC 8 WINB_NPCE885LA0DX_LQFP_128P
IN
1
2
EC_SPI_SO 2 7 1 R314 23.3K_5%_2 1UF_6.3V_2
5
18
45
78
89
47A6
21C8 21C6 SO_SIO1 HOLD#
OUT
116
103
0.1UF_16V_2
3 6 EC_SPI_CLK
C309
WP#_ACC SCLK 21C7 47A6

21D6
IN
4 5 EC_SPI_SI
2
GND SI_SIO0 21C6 47A6

21C7
IN PAD319
2 1
2 1
2
C POWERPAD1X1M C
MXIC_MX25L3206EM2I_12G_SOP_8P
P3V3AL
R315 P3V3AL
10K_5%_2_DY
1 2
U302 AGND_KBC
47A6 EC_SPI_CS1# 1 CS# VCC 8
IN
1
EC_SPI_SO 2 7
1 R319 3.3K_5%_2_DY
2
0.1UF_16V_2_DY
47A6
21C8 21C6 SO_SIO1 HOLD#
OUT
3 6 EC_SPI_CLK
C318
WP#_ACC SCLK 21C7 21D6

47A6
IN
4 GND SI_SIO0 5 EC_SPI_SI 21C6 21C7
47A6
IN
2
41D6 11B7 CPU_PROCHOT#

MXIC_MX25L3206EM2I_12G_SOP_8P_DY OUT
3
U301 Q300
SCAN_OUT<17..0>
D
OUT 20D6
TP319 1 31 GPIO56/TA1 KBSOUT0/GPOB0/JENK# 53 SCAN_OUT<0> 0 G 1 H_PROCHOT_EC 21D3
IN
FAN_TACH1 21B6 40C8 40C8 21B6 FAN_TACH1 TP30 63 GPIO14/TB1 KBSOUT1/GPIOB1/TCK 52 SCAN_OUT<1> 1
IN IN
1
S
SCAN_OUT<2>
1
14A6 10A5 SA_PG 64 GPIO01/TB2 KBSOUT2/GPIOB2/TMS 51 2

IN
C311 KBSOUT3/GPIOB3/TDI 50 SCAN_OUT<3> 3 SSM3K7002BFU R324
1 32 49 SCAN_OUT<4>
2
TP320 GPIO15/A_PWM KBSOUT4/GPOB4/JEN0# 4 100K_5%_2
680PF_50V_2 PCH_PWROK TP30 118 48 SCAN_OUT<5> 5
49B7 49A6 OUT GPIO21/B_PWM KBSOUT5/GPIOB5/TDO
19A7 BAT_OLED# 62 GPIO13/C_PWM KBSOUT6/GPIOB6/RDY# 47 SCAN_OUT<6> 6

OUT
2
DCIN_WLED# 65 43 SCAN_OUT<7>
2
19A7 GPIO32/D_PWM KBSOUT7/GPIOB7 7

OUT
TP321 1 22 GPIO45/E_PWM KBSOUT8/GPIOC0 42 SCAN_OUT<8> 8
40C6 FAN1_PWM TP30 81 GPIO66/G_PWM KBSOUT9/GPOC1/SDP_VIS# 41 SCAN_OUT<9> 9
OUT
B 20C7 CAPS_LED#_3 66 GPIO33/H_PWM KBSOUT10_P80_CLK/GPIOC2 40 SCAN_OUT<10> 10 B
OUT
19D7 PWR_OLED# 16 GPIO40/F_PWM KBSOUT11_P80_DAT/GPIOC3 39 SCAN_OUT<11> 11
OUT
KBSOUT12/GPIO64 38 SCAN_OUT<12> 12
KBSOUT13/GPIO63 37 SCAN_OUT<13> 13
TP322 1 111 GP(I)O83/SOUT_CR/TRIST# KBSOUT14/GPIO62 36 SCAN_OUT<14> 14
TP323 1
TP30 113 GPIO87/CIRRXM/SIN_CR KBSOUT15/GPIO61/XOR_OUT 35 SCAN_OUT<15> 15
TP30 GPIO60/KBSOUT16 34 SCAN_OUT<16> 16
GPIO57/KBSOUT17 33 SCAN_OUT<17> 17
49B3 EC_32KHZ 77 GPIO00/EXTCLK
IN
22B5 LAN_RST# 30 GPIO55/CLKOUT/IOX_DIN_DIO KBSIN0/GPIOA0/N2TCK 54 SCAN_IN<0> 0 SCAN_IN<7..0> 20C6 20D3
OUT IN
KBSIN1/GPIOA1/N2TMS 55 SCAN_IN<1> 1
KBSIN2/GPIOA2 56 SCAN_IN<2> 2
21F4 VCC_POR# 85 VCC_POR# KBSIN3/GPIOA3 57 SCAN_IN<3> 3
IN
KBSIN4/GPIOA4 58 SCAN_IN<4> 4
R339 KBSIN5/GPIOA5 59 SCAN_IN<5> 5
52C2 41D5 H_PECI 1 2 EC_PECI 13 PECI KBSIN6/GPIOA6 60 SCAN_IN<6> 6
BI
43_5%_2 12 VTT KBSIN7/GPIOA7 61 SCAN_IN<7> 7
P1V05S WINB_NPCE885LA0DX_LQFP_128P
A A
INVENTEC
TITLE
Block Diagram
SIZE CODE DOC.NUMBER REV

C CS 1310xxxxx-0-0 X01
CHANGE by XXX DATE 21-OCT-2002 SHEET 21 of 68
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
D
P3V3A Q400 P3V3A_LAN
PAD400 PAVDDVCO_LAN D
DIODES_DMP2305U_SOT23_3P
S D 1 2
S D 1 2
1
1
10UF_6.3V_5_DY
0.1UF_16V_2
CSC0402_DY
POWERPAD_2_0610
1UF_6.3V_2
4.7UF_6.3V_3
1
C403
C405
G
0.047UF_16V_2
C400
C401
C402
C404
1UF_10V_2_DY
C424
0.1UF_16V_2
C425
G
2
2
1
2
2
WOL_AUX_ON# 1 R400 2
21D6 IN
100K_5%_2 R402
0_5%_3
PDVDDL_LAN PAVDDL_LAN
2
1
1
1UF_6.3V_2
C427
0.1UF_16V_2
C426
PVLX_LAN C423
0.1UF_16V_2
2
C FOR LDO MODE C
2 R403 1
10K_5%_2 PCIE_LAN_TX_DN
IN 48D8
48D8 2 R404 1 PCIE_LAN_TX_DP
IN 48D8
48D7 10K_5%_2_DY CLK_PCIE_LAN_DP 48C7
CLKREQ_LAN# IN
48C7 OUT CLK_PCIE_LAN_DN 48C7
IN
41
40
39
38
37
36
35
34
33
32
31
P3V3A_LAN
U400
P3V3S
GND
LX
RX_N
RX_P
AVDDL
AVDDL
DVDDL_REG
LED_1
LED_0
REFCLK_N
REFCLK_P
2
1 VDD33
49B3 30 PCIE_LAN_RX_C_DP C421 1 2 0.1UF_16V_2 PCIE_LAN_RX_DP 48D8
21B6 R401 LAN_RST# 2 PERSTN
TX_P OUT
49A5 IN 29 PCIE_LAN_RX_C_DN C422 1 2 0.1UF_16V_2 PCIE_LAN_RX_DN 48D8
PAVDDL_LAN 30K_5%_2 27C7 PCIE_WAKE# 3 WAKEN
TX_N OUT
PVLX_LAN PDVDDL_LAN OUT 28
31C6 4 CLKREQN
NC
27
L400 R406 5 TESTMODE
ISOLATN
26 PAVDDH_LAN
1
1 2 1 2 6 AVDDL_REG
SMDATA
1
1
25
22A5 PAVDDH_LAN LAN_X1 7 XTLO
SMCLK
IN
1UF_6.3V_2
1
24
10UF_6.3V_5_DY
0.1UF_16V_2_DY
LQM21PN2R2MC0D_DY
1000PF_50V_2_DY
LAN_X2 8 PPS
C412
C413
RSC_0603_DY 22A5 IN XTLI
23
9 LED_2
C406
C407
AVDDH_REG
22
C408
R405
1
0.1UF_16V_2 1 2 10 RBIAS
AVDDH
21
1UF_6.3V_2
1
TRXN3
2.37K_1%_2 C420
AVDD33
2
B B
C414
0.1UF_16V_2
AVDDL
AVDDL
TRXN0
TRXN1
TRXN2
TRXP0
TRXP1
TRXP2
TRXP3
C415
2
0.1UF_16V_2
2
FOR SW MODE
2
2
LAN_TRD0_DP ATHEROS_AR8161_AL3A_R_QFN_40P
11
12
13
14
15
16
17
18
19
20
23B7 BI
23B7 23C6 LAN_TRD0_DN
BI
23C6 23B7 LAN_TRD1_DP
BI
23B7 23C6 LAN_TRD1_DN
BI
23C6 23B7 LAN_TRD2_DP
BI P3V3A_LAN
23B7 LAN_TRD2_DN
BI
23B7 LAN_TRD3_DP
BI
23B7 LAN_TRD3_DN
BI
1
PAVDDL_LAN
C418 C419
1
1UF_10V_2_DY 0.1UF_16V_2
LAN_X1 22B5
OUT C416
LAN_X2
2
OUT 22B5 C417
X400 0.1UF_16V_2 0.1UF_16V_2

1 2
2
1
25MHZ
33PF_50V_2
33PF_50V_2
C409
C410
A A
C417:8161 STUFF 8162 OPEN
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 400~499(LAN)
JACK470
23C3 23B3 LAN_TD_DP 1 TX+
IN
23C3 23B3 LAN_TD_DN 2 TX-
IN
23C3 23B3 LAN_RD_DP 3 RX+ G G1
IN
23C2 23B3 LAN_C_DP 4 P4 G G2
IN
23C2 23B3 LAN_C_DN 5 P5
IN
23C3 23B3 LAN_RD_DN 6 RX-
IN
23C2 23B3 LAN_D_DP 7 P7
IN
23C2 23B3 LAN_D_DN 8 P8
D IN
SANTA_13045_8P D
U471
2 TCT TCT 15
23B7 22B5 LAN_TRD0_DN 3 TD- TX- 14 LAN_TD_DN 23B3 23D5
IN OUT
23B7 22B5 LAN_TRD0_DP 1 TD+ TX+ 16 LAN_TD_DP 23B3 23D5
IN OUT
7 RCT RCT 10
23B7 22B5 LAN_TRD1_DN 8 RD- RX- 9 LAN_RD_DN 23B3 23D5
IN OUT
23B7 22B5 LAN_TRD1_DP 6 RD+ RX+ 11 LAN_RD_DP 23B3 23D5
IN OUT
1
C C
1
4 NC NC 12
R476
75_5%_3
75_5%_3
5 NC NC 13 2 1 LAN_C_DN 23B3 23D5
OUT
R474
R475
0.1UF_16V_2
0.1UF_16V_2
C478
C479
RSC_0603_DY
BOTH_TS21C_HF_SOP_16P R478
2 1 LAN_C_DP 23B3 23D5
OUT
2
RSC_0402_DY
2
2 R477 1 LAN_D_DN
OUT 23B3 23D5
RSC_0603_DY
PAVDDL_LAN R479
2 1 LAN_D_DP 23B3 23D5
OUT
RSC_0402_DY
U470
1 TCT1 MCT1 24
23C6 22B5 LAN_TRD0_DN 3 TD1- MX1- 22 LAN_TD_DN 23C3 23D5
IN OUT
23C6 22B5 LAN_TRD0_DP 2 TD1+ MX1+ 23 LAN_TD_DP 23C3 23D5
IN OUT
4 TCT2 MCT2 21
23C6 22B5 LAN_TRD1_DN 6 TD2- MX2- 19 LAN_RD_DN 23C3 23D5
IN OUT
23C6 22B5 LAN_TRD1_DP 5 TD2+ MX2+ 20 LAN_RD_DP 23C3 23D5
IN OUT
7 TCT3 MCT3 18
22B5 LAN_TRD2_DN 9 TD3- MX3- 16 LAN_C_DN 23C2 23D5
IN OUT
22B5 LAN_TRD2_DP 8 TD3+ MX3+ 17 LAN_C_DP 23C2 23D5
IN OUT
10 TCT4 MCT4 15
22B5 LAN_TRD3_DN 12 TD4- MX4- 13 LAN_D_DN 23C2 23D5
IN OUT
B 22B5 LAN_TRD3_DP 11 TD4+ MX4+ 14 LAN_D_DP 23C2 23D5 B
IN OUT
1
75_5%_3
75_5%_3
75_5%_3
75_5%_3
BOTH_GST5009_RA_SOP_24P
R470
R471
R472
R473
1
1
CSC0402_DY
CSC0402_DY
CSC0402_DY
CSC0402_DY
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
2
C480
C481
C482
C483
C470
C471
C472
C473
C474
1
2
2
C475
1000PF_2000V_6
2
1
CSC0402_DY
100PF_50V_2
C476
C477
2
2
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 500~549(AUDIO CODEC)

CLOSE TO PIN27
P5V0S P5V0S_AUDIO_AVDD
1
C519 C513
1
R515
C512 1 2
C503
2.2UF_6.3V_3 0.1UF_16V_2 0_5%_3
2.2UF_6.3V_3
AGND_AUDIO 10UF_6.3V_3
2
BLM18PG121SN1(6014B0041601_0603)
2
AGND_AUDIO
D P5V0S_AUDIO_AVDD
HP_R
1
OUT 25B3
D
C502 HP_L 25A3
P5V0S OUT
BLM18PG121SN1(6014B0041601_0603) 2.2UF_6.3V_3 MIC_REF_L
OUT 25D3 P5V0S_AUDIO_AVDD
R516 MIC_REF_R 25D3
P5V0S_PVDD OUT
2
1 2
1
4.7UF_6.3V_3
0.1UF_16V_2
C536
C500
0_5%_3
36
35
34
33
32
31
30
29
28
27
26
25
1
1
10UF_6.3V_3_DY
1
1
0.1UF_16V_2_DY
4.7UF_6.3V_3
4.7UF_6.3V_3
0.1UF_16V_2
0.1UF_16V_2
C505
C507
C504
C532
C506
C501
2
2
U500
CBN
CBP
VREF
CPVEE
AVDD1
AVSS1
LDO-CAP
HP-OUT-R
HP-OUT-L
MIC2-VREFO
MIC1-VREFO-R
2
2
MIC1-VREFO-L
2
2
37 AVSS2 LINE1-R 24
AGND_AUDIO
38 AVDD2 ANALOG LINE1-L 23
39 PVDD1 MIC1-R 22 MIC_R 25C2 AGND_AUDIO

BI
25B8 SPK_OUT_L_P R512 1 2 0_5%_3 40 SPK-L+

DIGITAL MIC1-L 21 MIC_L 25C2
C OUT BI C
SPK_OUT_L_N R511 1 2 0_5%_3 41 20
25B8 OUT SPK-L- MONO-OUT
R514
42 PVSS1 JDREF 19 1 2
RESERVE FOR EMI (THERMAL PAD 4X4 VIAS)
43 PVSS2 Sense-B 18 20K_1%_2
25B8 SPK_OUT_R_N R510 1 2 0_5%_3 44 SPK-R- MIC2-R 17

OUT
AGND_AUDIO
25B8 SPK_OUT_R_P R509 1 2 0_5%_3 45 SPK-R+ MIC2-L 16
OUT
46 PVDD2 LINE2-R 15
47 14 CLOSE TO PIN13
EAPD LINE2-L
1
1
4.7UF_6.3V_3
R500
0.1UF_16V_2
48 13 1 2 MICS
GPIO0/DMIC-DATA
SPDIFO Sense A
IN 25C5
GPIO1/DMIC-CLK
C529
C531
20K_1%_2
SDATA-OUT
GND 49
SDATA-IN
R501
BIT-CLK
HPS
DVDD-IO
PCBEEP
1 2
RESET#
IN 25B2
DVDD1
DVSS2
SYNC
2
39.2K_1%_2
PD#
REA_ALC269Q_VB6_CGT_QFN_48P
B C520
B
P3V3S R507
1 2 1 2 PCSPKR_PCH_3 47C8
IN
10
11
12
C514
2 1 47K_1%_2 C521
0.1UF_16V_2 2 1
1000PF_50V_2
100PF_50V_2
1
R506
0.1UF_16V_2
1UF_6.3V_2
C515 1 2
C508
C509
2 1 4.7K_1%_2
1000PF_50V_2 HDA_3S_RST#
IN 47C7
2
C516 HDA_3S_SYNC
IN 47C7
2 1
HDA_R_SDIN0 1 R502 2 HDA_3S_SDIN0 47B7
1000PF_50V_2 IN
22_5%_2
C517 HDA_R_BITCLK 1 R503 2 HDA_3S_BITCLK
2 1 IN 47C7
0_5%_2 HDA_3S_SDOUT
IN 47B7
1000PF_50V_2
TIED UNDER OR NEAR CODEC
34B3 MIC_IN_DATA EC_MUTE# 21D6
BI IN
R505
PAD500 34B3 MIC_IN_CLK 1 2 MIC_IN_CLK_R P3V3A
BI
AGND_AUDIO 1
1 2
2
100_5%_2
POWERPAD1X1M
A A
1
1
22PF_50V_2_DY
0.1UF_16V_2
1UF_6.3V_2
C518
C510
C522
AGND_AUDIO
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERCE 600~649(JACK/MIC/SPEAKER)
AUDIO JACKS
D MIC_REF_L 24D3
IN D
MIC_REF_R 24D3
IN
MICPHONE
2
R605 R604
TP30 2.2K_5%_2 2.2K_5%_2

JACK600 5 TP607 R606
1
14 MICS 0_5%_3 C606 2.2UF_6.3V_3
OUT 24B2 R602
3 1 1 2 1 21K_5%_2 1 2 MIC_R 24C2
BI
6 TP605
TP30
2 1 1 2 1 2 1 2 MIC_L 24C2
BI
11 1K_5%_2 C607 2.2UF_6.3V_3
TP30 TP604 R607 R603
G1
TP30 0_5%_3
G2 TP606
SINGA_2SJ_T351_019_6P
RESERVE FOR EMI
1
C600 C601
CSC0402_DY CSC0402_DY
C AGND_AUDIO C
2
RESERVE FOR EMI
AGND_AUDIO
D600
2
3
B 1 B
PHP_PESD5V2S2UT_SOT23_3P_DY
INTERNAL SPEAKERS AGND_AUDIO

HEADPHONE
NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH
CN600 JACK601
24C7 SPK_OUT_L_P 4 G2 R601 R609 TP603 5
IN 4 G2
HPS
24C7 SPK_OUT_L_N 3 G1 75_5%_2 0_5%_3 24B2 1TP30 4
IN 3 G1 OUT
24C7 SPK_OUT_R_N 2 24D3 HP_R 1 2 1 2 TP601 1 3
IN 2 IN
24C7 SPK_OUT_R_P 1 TP30 6
IN 1
24D3 HP_L 1 2 1 2 TP600 1 2
IN
ACES_50224_0040N_001_4P TP30 1TP30 1
R600 R608 G1
TP602
75_5%_2 0_5%_3
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
470PF_50V_2_DY
1
G2
470PF_50V_2_DY
1
470PF_50V_2_DY
1
C602
C603
C604
C605
SINGA_2SJ_T351_019_6P
C609
C608
470PF_50V_2_DY
470PF_50V_2_DY
1
1
2
C611
C610
2
2
AGND_AUDIO
2
A A
RESERVE FOR EMI
RESERVE FOR EMI

AGND_AUDIO
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERNCE 900~999(CARDREADER)
D
D
SD_CMD 26B3
BI
SD_R_CLK 1 R901 2 SD_CLK

BI 26B3
0_5%_2
RESERVE FOR EMI
SD_CD#
BI 26B3
18
17
16
15
14
13
C P3V3S_CR C
U900
SP9
SP8
SP7
SP6
SP10
GPIO0
1
C905 C906
19 SP11 SP5 12
2.2UF_6.3V_3 0.1UF_16V_2
26B3 SD_D320 SP12 SP4 11 SD_D0 26B3
BI BI
2
26B3 SD_D221 SP13 SP3 10 SD_D1 26B3
BI BI CN900
22 SP14 SP2 9 26C7 SD_D3 1 CD-DAT3
BI
26D5 SD_CMD 2 CMD
BI
23 XD_D7 SP1 8 SD_WP 26B3 3 VSS1
BI
4 VDD
24 V18 XD_CD# 7 26C5 SD_CLK 5 CLK
BI
1
6
CARD_3V3
VSS2
26C5 SD_D0 7
SDREG
DAT0
BI
3V3_IN
C901
RREF
25 TML 26C5 SD_D1 8 DAT1

BI
DM
DP
1UF_6.3V_2 26C7 SD_D2 9 DAT2

BI
REA_RTS5129_QFN_24P 26C5 SD_CD# 10 CARD_DETECT
BI
SD_WP 11 G1
2
26B5 WRIT_PROTECT G1
BI
1
G2
1
B G2 B
C904 TAI_PSDAT0_09GLBS1ZZ4H1_11P
1UF_6.3V_2
R900
1 2 CARD_REF
2
6.2K_1%_2
P3V3S_CR
51B2 USB_CR_DN
BI
1
51B2 USB_CR_DP
BI
C902
0.1UF_16V_2
2
P3V3S
PAD900
1
1 2
2 P3V3S_CARD
A POWERPAD_2_0610 A
1
C900
C903
4.7UF_6.3V_3
0.1UF_16V_2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1300~1349(WLAN)
D
D
SUPPORT AOAC:OPEN SUPPORT AOAC:STUFF
P3V3S
P3V3S
1
P3V3A
P1V5S
R1304
Q1300
0_5%_5
1
1 D S 4
2
2
C1302 C1304 5
1
0.1UF_16V_2 6 3
10UF_6.3V_3 G
PMOS_4D1S
C1307
2
AM3423P_DY
1
CSC0402_DY
C1305 C1301
2
C1306
0.1UF_16V_2 10UF_6.3V_3 CSC0402_DY
2
AOAC_ON# 21D2
21D3
IN
R1300 CN1300
C PCIE_WAKE# 1 2 0_5%_2 1 2 C
49B3 49A5 31C6 22B5 BI WAKE# 3.3V
3 CH_DATA GND 4
52B6 27B7 BTIFON# 1 R1301 2 0_5%_2 5 CH_CLK 1.5V 6
BI
48D8 48D7 48B7 CLKREQ_WLAN# 7 CLKREQ# LPC_FRAME# 8 LPC_3S_FRAME# 21E3 47C3
IN IN
9 GND LPC_AD3 10 LPC_3S_AD<3> 21E3 47C3
IN
48B7 CLK_PCIE_WLAN_DN 11 REFCLK- LPC_AD2 12 LPC_3S_AD<2> 21E3 47C3
IN IN
48B7 CLK_PCIE_WLAN_DP 13 REFCLK+ LPC_AD1 14 LPC_3S_AD<1> 21E3 47C3
IN IN
15 GND LPC_AD0 16 LPC_3S_AD<0> 21E3 47C3
IN
57A6 51A8 28C3 27C3 21E3 BUF_PLT_RST# 17 LPC_DEBUG_RST# GND 18
IN
51A7 CLK_PCI_DEBUG 19 LPC_PCI_CLK W_DISABLE# 20
IN
21 GND PERST# 22 BUF_PLT_RST# 21E3 27C7
IN
3
48D8 PCIE_WLAN_RX_DN 23 PERN0 +3.3VAUX 24 28C3 51A8
OUT 57A6 Q1301
48D8 PCIE_WLAN_RX_DP 25 PERP0 GND 26
OUT
D
27 GND 1.5V 28
G 1 WLON# 21D2
21D3
29 GND SMB_CLK 30 PCH_3A_ALERT_CLK 48D2 IN
BI
48D8 PCIE_WLAN_TX_DN 31 32 PCH_3A_ALERT_DAT 48D3 48D2
S
PETN0 SMB_DATA
IN BI
48D8 PCIE_WLAN_TX_DP 33 PETP0 GND 34 48D3
IN SSM3K7002BFU
35 GND USB_D- 36 USB_WLAN_DN 51B2
BI
2
37 Reserved USB_D+ 38 USB_WLAN_DP 51B2
BI
39 Reserved GND 40
41 Reserved LED_WWAN# 42
43 Reserved LED_WLAN# 44
B 45 +V3AL LED_WPAN# 46 B
BTIFON# 1 R1302 2 0_5%_2 47 48
52B6 27C7 BI PWR_LED# 1.5V
49 NUM_LED# GND 50
PCI_3S_SERIRQ 1 R1303 2 51 52
47C2 21E3 IN 0_5%_2_DY CAPS_LED# 3.3V
G1 G G G2
BELLW_80003_4021_52P
A A
MINI CARD 1(WLAN)

INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1400~1499(3G) P1V5S
1
C1410
C1411
C1412
0.1UF_16V_2
0.1UF_16V_2
22UF_6.3V_5
2
2
P3V3S
D
D
1
C1402 C1401 C1400
CN1400
1 WAKE# 3.3V 2 0.1UF_16V_2 0.1UF_16V_2
3 4 22UF_6.3V_5
CH_DATA GND
2
5 CH_CLK 1.5V 6
7 CLKREQ# LPC_FRAME# 8 UIM_PWR 28A4 28B6
OUT
9 GND LPC_AD3 10 UIM_DATA 28A6
BI
11 REFCLK- LPC_AD2 12 UIM_CLK 28A4
BI
13 REFCLK+ LPC_AD1 14 UIM_RST 28A4
OUT
15 GND LPC_AD0 16
17 LPC_DEBUG_RST# GND 18
CLOSE TO CONN SIDE 19 LPC_PCI_CLK W_DISABLE# 20 3G_OFF#
21 GND PERST# 22 BUF_PLT_RST# 21E3 27C3
C1405 0.01UF_50V_2 IN
47B3 SATA_MINICARD_RX_DP 1 2 SATA_MINICARD_C_RX_DP 23 PERN0 +3.3VAUX 24 27C7 51A8
BI C1406 57A6
47B3 SATA_MINICARD_RX_DN 1 2
0.01UF_50V_2 SATA_MINICARD_C_RX_DN 25 PERP0 GND 26
BI
27 GND 1.5V 28
3
29 GND SMB_CLK 30 TP24 1
TP1400 Q1400
47B3 SATA_MINICARD_TX_DN C1407 1 2 0.01UF_50V_2 SATA_MINICARD_C_TX_DN 31 PETN0 SMB_DATA 32 TP24 1
BI
D
C1408 1 0.01UF_50V_2 TP1401
47B3 SATA_MINICARD_TX_DP 2 SATA_MINICARD_C_TX_DP 33 PETP0 GND 34
BI G 1 3G_ON# 52D6
C 35 GND USB_D- 36 USB_3G_DN 51B2 IN C
BI
37 38 USB_3G_DP 51B2
S
Reserved USB_D+
BI
39 Reserved GND 40
41 42 SSM3K7002BFU
Reserved LED_WWAN#
2
43 Reserved LED_WLAN# 44
45 +V3AL LED_WPAN# 46
47 PWR_LED# 1.5V 48
1 TP24 49 NUM_LED# GND 50
TP1402
51 CAPS_LED# 3.3V 52
G1 G G G2
BELLW_80003_4021_52P
B P3V3S B
U1400
28D3 28A4 UIM_PWR 1 VIO VIO 6

IN
2 GND VBUS 5
3 VIO VIO 4
NXP_IP4223CZ6_SOT457_6P_DY
CN1401
P5 GND VCC P1 UIM_PWR 28B6 28D3
IN
P6 VPP RST P2 UIM_RST 28C3
IN
28D3 UIM_DATA P7 I_O CLK P3 UIM_CLK 28C3
BI BI
G2 G G G1
TAI_PMPAT5_06GLBS7NI4H1_6P
1
A A
4.7UF_6.3V_3
C1404
0.1UF_16V_2
C1403
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 1700~1749(HDD)
REFERENCE 1750~1799(ODD)
SATA HDD
D CN1700
1 GND
SATA_HDD_TX_DP C1704 1 2 0.01UF_50V_2 SATA_HDD_TX_C_DP 2 D
47C3 IN A+
47C3 SATA_HDD_TX_DN 1 2 0.01UF_50V_2 SATA_HDD_TX_C_DN 3

IN C1705 A-
4 GND
47C3 SATA_HDD_RX_DN C1700 1 2 0.01UF_50V_2 SATA_HDD_RX_C_DN 5 B-

OUT
47C3 SATA_HDD_RX_DP 1 2 0.01UF_50V_2 SATA_HDD_RX_C_DP 6 B+
OUT C1701
7 GND
8 V3.3
PLACE CLOSE TO CONNECTOR(<100MILS) 9 V3.3
10 V3.3
11
P5V0S GND
12 GND
40MIL 13 GND
14 V5
15 V5
1
16
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
V5
C1706
C1703
C1702
17 GND
18 RESERVED
19 GND
20 V12
2
21 V12 G1 G1
22 V12 G2 G2
SANTA_194911_1_22P
C C
P5V0S
1
1
P3V3S
R1752 C1754
4
CSC0402_DY
1M_5%_2_DY
1
S
G
1
R1751
1 2
2
PMOS_4D1S
R1750 R1754
10K_5%_2_DY
100K_5%_2_DY 0_5%_6
Q1751
2
2
TPC6111_DY
Q1750
6
5
2
1
D
B 52D2 SATA_ODD_PWREN 1 G B
IN
C1758
S
2 1
SSM3K7002BFU_DY
2
1
CSC0402_DY
22UF_6.3V_5
22UF_6.3V_5
0.1UF_16V_2
C1757
C1756
C1755
2
CN1750
P6 GND
P5 GND
51C7 51B6 SATA_ODD_DA# P4 MD

OUT
P3 +5V
P2 +5V
52D7 52B6 SATA_ODD_PRSNT# P1 DP

OUT
SATA ODD
A S7 GND A
47B3 SATA_ODD_RX_DP C1750
1 2
0.01UF_50V_2 SATA_ODD_RX_C_DP S6 B+
OUT C1751
47B3 SATA_ODD_RX_DN 1 2
0.01UF_50V_2 SATA_ODD_RX_C_DN S5 B-
OUT
S4 GND
47B3 SATA_ODD_TX_DN C1753 1 2

0.01UF_50V_2 SATA_ODD_TX_C_DN S3 A-
IN
47B3 SATA_ODD_TX_DP C1752 1 2
0.01UF_50V_2 SATA_ODD_TX_C_DP S2 A+ G G1
IN
S1 GND G G2
SYN_127382FR013G212ZR_13P
PLACE CLOSE TO CONNECTOR(<100MILS)
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2000~2099(USB)
D
D
P5V0A_USB3
CN2002
1 1
66C6
51C2 USB_P2_DN 2 2
BI
66C6
51C2 USB_P2_DP 3 3 G1 G1
BI
4 4 G2 G2
ACES_50224_0040N_001_4P
C C
P5V0A
PAD2000
P5V0A_USB_PW1
1 2
1 2
1
POWERPAD_2_0610
C2000 C2001
22UF_6.3V_5_DY 1UF_6.3V_2
2
B P5V0A_USB3 B
U2000
1 GND VOUT 8
1
2 VIN VOUT 7
3 VIN VOUT 6 R2000
SB_USB_2 C2002 C2003
21D3 4 EN_EN# FLG# 5
IN
22UF_6.3V_5
RICH_RT9711APF_MSOP_8P 0.1UF_16V_2
1
RSC_0402_DY
2
C2004
CSC0402_DY
P3V3AL
2
1
R2001
10K_5%_2
USB_OC#_2
2
OUT 21D3
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0) P3V3A

P3V3_USB3
Q2403
S D
P1V05_USB3
1
S D
1
CSC0402_DY
CSC0402_DY
10UF_6.3V_3
0.1UF_16V_2
0.1UF_16V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
C2472
C2473
C2400
C2401
C2402
C2403
C2404
C2405
C2470
C2471
R2424
G
10K_5%_2
G
1
2
0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
0.01UF_50V_2
C2417
C2421
C2423
C2424
C2425
1 R2427 2
C2418
C2419
C2420
C2422
220K_5%_2
3
2
D
31A5 21D6 USB30_PWR_EN 1 G Q2402
IN
D SSM3K7002BFU
S
D
P3V3_USB3 P1V05_USB3 P3V3_USB30_AVDD
2
12
22
34
43
21
30
33
39
42
25
6
3
U2400
P3V3_USB3 P3V3_USB30_AVDD
VDD33
VDD33
VDD33
VDD33
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
VDD10
AVDD33
AVDD33
1 L2400 2
48B7 CLK_PCIE_USB3_DP 1 PECLKP
IN BLM21PG600SN1D_3A
CLK_PCIE_USB3_DN 2 PECLKN U3TXDP2 37 USB3_IC_TX2_DP
48B7 IN BI 33B5
1
C2409 0.1UF_16V_2
0.1UF_16V_2
0.1UF_16V_2
PCIE_USB3_RX_DP 1 2 PCIE_USB3_RX_C_DP 4 38 USB3_IC_TX2_DN
0.01UF_50V_2
0.01UF_50V_2
C2406
C2408
C2414
C2415
C2416
48D8 PETXP U3TXDN2 33B5
OUT BI
10UF_6.3V_3
48D8 PCIE_USB3_RX_DN 1 2 PCIE_USB3_RX_C_DN 5 PETXN U2DM2 45 USB2_IC_TX2_DN
OUT BI 33C5
C2410 0.1UF_16V_2
48D8 PCIE_USB3_TX_DP 7 44 USB2_IC_TX2_DP
P3V3_USB3 IN PERXP U2DP2
BI 33C5
PCIE_USB3_TX_DN 8 40 USB3_IC_RX2_DP
2
PERXN U3RXDP2
48D8 IN BI 33B5
U3RXDN2 41 USB3_IC_RX2_DN
BI 33B5
C C
51A7 36B2 41C7 PLT_RST# 47
2 R4754 1 CLKREQ_USB3# 31B8 48B7 IN PERSTB P3V3_USB3
IN 49B3 49A5 27C7 22B5 PCIE_WAKE# 48 PEWAKEB
10K_5%_2 OUT
CLKREQ_IC_USB3# 10 PECREQB OCI2B 17 R2415 1 2 10K_5%_2
31B6 IN
R4955 OCI1B 19 R2416 1 2 10K_5%_2
1 2 USB3_SMI# 31C6 51B6
IN
PPON2 18
10K_5%_2 31C7 USB3_SMI# 46 SMIB PPON1 20
P3V3_USB3 OUT
51B6
R2406
1 2 11 PONRSTB
10K_5%_2 U3TXDP1 28 USB3_IC_TX1_DP 32D7

BI
2
USB3_SCLK 15 SPISCK U3TXDN1 29 USB3_IC_TX1_DN

31A6 OUT BI 32D7
USB3_CS# USB2_IC_TX1_DN
NC
14 SPICSB U2DM1 36
31A8 OUT BI 32B8
3 1 USB3_SI 16 SPISI
31A6 OUT
USB3_SO 13 SPISO U2DP1 35 USB2_IC_TX1_DP 32B8
32A8
31A8 IN BI
USB3_IC_RX1_DP
1
D2400 U3RXDP1 31
BI 32D7
DIODE-BAT54-TAP-PHP
C2411 U3RXDN1 32 USB3_IC_RX1_DN
BI 32D7
1UF_6.3V_2 USB3_XT1 24 XT1
X2400 USB3_XT2 23 XT2
1 2
2
R2400
B B
1
1.6K_1%_2
24MHZ 27 IC(L) RREF 26 1 2
C2413 C2412
12PF_50V_2 12PF_50V_2
GND
2
RENESAS_UPD720202K8_BAA_A_QFN_48P
49
CLKREQ_USB3# 1 R2405 2 CLKREQ_IC_USB3#
31C7 OUT IN 31C6
48B7 0_5%_2
P1V5 P5V0A
U2403 P1V05_USB3
9 1
P3V3_USB3 VIN GND
P3V3_USB3 31D4 21D6 USB30_PWR_EN 8 EN

IN
7 POK FB 2
PAD2400
TRACE WIDTH>20MILS1
1
R2480 R2481 6 VCNTL VOUT 3 2

1 2
1
10K_5%_2 47K_5%_2
A POWERPAD1X1M A
1
5 VIN VOUT 4
C2480
1 R2422 2
U2480 0.1UF_16V_2 ANPEC_APL5930KAI_TRG_SOP_8P
1
10K_1%_2
2
1 2 C2434
2
C2435
USB3_CS# 1 8 C2438
2
31B6 IN CS# VCC
1
22UF_6.3V_5 1UF_6.3V_2 22UF_6.3V_5
C2433
31B6 USB3_SO 2 SO NC 7 150PF_50V_2
OUT
2
2 R2423
3 WP# SCLK 6 USB3_SCLK 31B6 31.6K_1%_2
IN
INVENTEC
2
4 GND SI 5 USB3_SI 31B6
IN
MAC_MX25L5121EMC_20G_SOP_8P TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0)
31B2 USB3_IC_RX1_DN R2430 1 2 0_5%_2 USB3_SSRX1_DN 32C7
USB3.0 FROM CONTROLLLER BI BI
31B2 USB3_IC_RX1_DP R2431 1 2 0_5%_2 USB3_SSRX1_DP 32C7
BI BI
USB3.0 FROM PCH 51C6 USB3_PCH_RX1_DN R2432 1 2 0_5%_2

BI
51C6 USB3_PCH_RX1_DP R2433 1 2 0_5%_2
BI
31B2 USB3_IC_TX1_DN C2447 1 2 0.1UF_16V_2 USB3_SSTX1_DN 32B7

BI BI
USB3.0 FROM CONTROLLLER 31B2 USB3_IC_TX1_DP C2448 1 2 0.1UF_16V_2 USB3_SSTX1_DP 32B7
BI BI
D
D
51C6 USB3_PCH_TX1_DN C2440 1 2 0.1UF_16V_2

BI
USB3.0 FROM PCH 51C6 USB3_PCH_TX1_DP C2441 1 2 0.1UF_16V_2
BI
P5V0A_USB1
P5V0A_USB1
USB3.0
1
P5V0A
C2429
+
CURRENT LIMIT 2.5A 100UF_6.3V
2
U2402 P3V3AL
1 GND OUT 8
2 IN OUT 7
3 IN OUT 6
1
R2446 33D8
32A8
21C3 SB_USB_1 4 EN OC# 5
32A8 USB_IC_DP 1 2 0_5%_2 IN
BI
1
USB_IC_DN R2408
1
C 32A8 1 2 0_5%_2 GMT_G547E1P81U_MSOP_8P C
BI C2427
R2447 C2432 10K_5%_2
C2428
C2426
47UF_6.3V_5
2
0.1UF_16V_2 1000PF_50V_2
22UF_6.3V_5
2
L2404
2
CN2401
R2455 0_5%_2 WCM_2012_900T 1 VBUS USB_OC#_1 33C6
21D6
32A6
OUT
51C2
32B8 USB_P0_DN 1 2 USB_P0_R_DN 1 2 USB_P0_L_DN 2 D-
BI
32B8
51C2 USB_P0_DP 1 2 USB_P0_R_DP 4 3 USB_P0_L_DP 3 D+
BI
4 PGND
R2454 0_5%_2 USB3_SSRX1_DN 5
32D5 BI SSRX-
32D5 USB3_SSRX1_DP 6 SSRX+ G G1

BI
USB 3.0 CONNECTOR

7 GND G G2
USB2_IC_TX1_DN1 R2503 2 0_5%_2 USB3_SSTX1_DN 8 G3
32B8 31B2 BI 32D5 BI SSTX- G
32A8 31B2 USB2_IC_TX1_DP1 2 0_5%_2 32D5 USB3_SSTX1_DP 9 SSTX+ G G4

BI BI
R2504
LOTES_AUSB0026_P001_9P
B B
USB_P0_DN 1 R2456 2 0_5%_2

51C2 32C8 BI
51C2 32C8 USB_P0_DP 1 2 0_5%_2
P5V0A
BI
R2457
32B8
31B2 USB2_IC_TX1_DN
BI
1
32B8
31B2 USB2_IC_TX1_DP
BI
21D6 EC_ILIM_SEL C2442
IN
0.1UF_16V_2
4
3
2
1
U2401
ILIM_SEL
DP_OUT
DM_OUT
IN
PWPD 17
21C3
33D8
32C3 SB_USB_1 5 EN ILIM0 16
IN
21C3 EC_CTL1 6 CTL1 ILIM1 15
IN
21D6 EC_CTL2 7 CTL2 GND 14
IN
EC_CTL3 USB_OC#_1
1
8 13
DP_IN
DM_IN
IN CTL3 FAULT#
OUT 33C6
21D6
32C1
OUT
NC
A R2435 R2436 A
P3V3AL
P5V0A TI_TPS2540A_QFN_16P
20K_5%_2 0_5%_2_DY
9
10
11
12
R2458 P5V0A_USB1
2
1 2 1 R2434 2
10K_5%_2
100K_5%_2_DY
32C8 USB_IC_DP
BI
32C8 USB_IC_DN
BI
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 2400~2499(USB3.0)
P5V0A_USB2
1
D
P5V0A D
USB 3.0 CONNECTOR

C2449
+
CURRENT LIMIT 2.5A 100UF_6.3V
2
U2404 P3V3AL
1 GND OUT 8
2 IN OUT 7
3 IN OUT 6 P5V0A_USB2
1
21C3
32C3
32A8 SB_USB_1 4 EN OC# 5
IN
1 R2410
GMT_G547E1P81U_MSOP_8P
10K_5%_2
C2454
1
1
47UF_6.3V_5
2
C2452
2
USB_OC#_1 C2453
OUT 21D6
32A6
32C1 C2451
0.1UF_16V_2 1000PF_50V_2
22UF_6.3V_5_DY
2
2
31C2 USB2_IC_TX2_DN R2453 1 2 0_5%_2
BI
USB2.0 FROM PCONTROLLER USB2_IC_TX2_DP R2452 1 2 0_5%_2
BI
CN2402
C L2405 1 VBUS C
USB2.0 FROM PCH USB_P1_DN R2450 1 2 0_5%_2 USB_P1_R_DN 1 2 USB_P1_L_DN 2 D-
BI
51C2 USB_P1_DP R2451 1 2 0_5%_2 USB_P1_R_DP 4 3 USB_P1_L_DP 3 D+
BI
4 PGND
WCM_2012_900T
33B3 USB3_SSRX2_DN 5 SSRX-
BI
33B3 USB3_SSRX2_DP 6 SSRX+ G G1
BI
7 GND G G2
33B2 USB3_SSTX2_DN 8 SSTX- G G3
BI
33B2 USB3_SSTX2_DP 9 SSTX+ G G4
BI
LOTES_AUSB0026_P001_9P
USB3_IC_RX2_DN R2437 1 2 0_5%_2 USB3_SSRX2_DN 33C3

USB3.0 FROM CONTROLLLER BI BI
USB3_IC_RX2_DP R2438 1 2 0_5%_2 USB3_SSRX2_DP 33C3
BI BI
USB3.0 FROM PCH 51C6 USB3_PCH_RX2_DN R2439 1 2 0_5%_2

BI
51C6 USB3_PCH_RX2_DP R2440 1 2 0_5%_2
BI
B B
USB3_IC_TX2_DN C2443 1 2 0.1UF_16V_2 USB3_SSTX2_DN 33C3

BI BI
USB3.0 FROM CONTROLLLER USB3_IC_TX2_DP C2444 1 2 0.1UF_16V_2 USB3_SSTX2_DP 33C3
BI BI
51C6 USB3_PCH_TX2_DN C2445 1 2 0.1UF_16V_2

USB3.0 FROM PCH BI
51C6 USB3_PCH_TX2_DP C2446 1 2 0.1UF_16V_2
BI
USB3.0
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFFERENCE 3000~3049(LCM)
P3V3S
Q3000
PAD3003
P3V3S_MOS_LCM P3V3S_LCM
S D 1 2
S D 1 2
POWERPAD_2_0610
1
G
1
0.01UF_50V_2
0.1UF_16V_2
10UF_6.3V_3
1
C3000
C3001
C3003
C3002
47K_5%_2
R3000
G
2 1
680PF_50V_2
2
2
2
D
2
2
D
R3001 R3004
R3011 1 2 PCH_LCM_VDDEN#
VGA_LCM_VDDEN 1 0_5%_1 100_5%_2
3
57B6 2
IN
Q3001 470K_5%_2
3
1
D
R3012
PCH_LCM_VDDEN 1 0_5%_1
2 LCM_VDDEN 1 Q3002
50D7 G
IN
D
P3V3S
1 G
S
GM:2.2K P3V3S
SSM3K7002BFU
S
PM:4.7K
2
SSM3K7002BFU
(60130B4720ZT)
1
2
1
2.2K_5%_2
2.2K_5%_2
0.1UF_16V_2
C3004
R3002
R3005
2
2
2
56D6 VGA_LVDS_DDCCLK 1
R3015 2
0_5%_1
BI
56D6 VGA_LVDS_DDCDATA 1
R3016 2
0_5%_1 CN3000
BI 1 1
2 2
3 3
50D7 PCH_LVDS_DDCCLK 1
R3017 2
0_5%_1 LVDS_DDCCLK 4 4
C BI C
50C7 PCH_LVDS_DDCDATA 1
R3018 2
0_5%_1 LVDS_DDCDATA 5 5
BI
6 6
34A6 LVDS_TXDL0_DN 7 7
IN
34A6 LVDS_TXDL0_DP 8 8
IN
9 9
IN
IN
12 12
IN
IN
15 15
34A6 LVDS_TXCL_DN 16 16
IN
34A6 LVDS_TXCL_DP 17 17
IN
18 18
R3009 19
VGA_INV_PWM_3 1R3013 0_5%_1
2 19
57B6 IN 100_5%_2 20 20
PCH_INV_PWM_3 1R3014 0_5%_1
2 1 2 INV_PWM_3_R 21
50D7 IN 21
21E6 EC_BKLTEN 1 2 EC_BKLTEN_R 22 22

IN
1
1
R3003 23 23
100_5%_2 24 24
1
C3007
1
R3006 25 25
GM:OPEN R3035 C3006 100K_5%_2 CSC0402_DY 51B2 USB_CAM_DN 26 26

BI
B 50C6 PCH_LVDS_TXDL0_DN 1
R3019 2
0_5%_1 51B2 USB_CAM_DP 27 27 G G1 B
IN PM: 10K BI
2
PCH_LVDS_TXDL0_DP 1 2 10K_5%_2 1000PF_50V_2 28 G2
2
50C6
IN R3020 0_5%_1 28 G
24A6 MIC_IN_CLK 29 29
BI
2
PCH_LVDS_TXDL1_DN 1 2 MIC_IN_DATA 1 2 MIC_IN_DATA_R30
2
50C6 IN R3021 0_5%_1 24A6 BI 30
50C6 PCH_LVDS_TXDL1_DP 1
R3022 2
0_5%_1 R3010
IN ACES_50203_03001_001_30P
100_5%_2
50C6 PCH_LVDS_TXDL2_DN 1
R3023 2
0_5%_1
IN
50C6 PCH_LVDS_TXDL2_DP 1
R3024 2
0_5%_1
IN
50C6 PCH_LVDS_TXCL_DN 1
R3025 2
0_5%_1
IN
50C6 PCH_LVDS_TXCL_DP 1
R3026 2
0_5%_1
IN
P3V3S
PVBAT PVBAT_LCD
57A6 VGA_LVDS_TXDL0_DN 1
R3027 2
0_5%_1 LVDS_TXDL0_DN 34C3
IN OUT
VGA_LVDS_TXDL0_DP LVDS_TXDL0_DP
1
57A6 1
R3028 2
0_5%_1 34C3
IN OUT PAD3001
0.1UF_16V_2
C3011
1 2
57A6 VGA_LVDS_TXDL1_DN 1
R3029 2
0_5%_1 LVDS_TXDL1_DN 34C3
1 2
IN OUT
57A6 VGA_LVDS_TXDL1_DP 1
R3030 2
0_5%_1 LVDS_TXDL1_DP 34C3
IN OUT POWERPAD_2_0610
0.1UF_25V_3
4.7UF_25V_5
VGA_LVDS_TXDL2_DN 1 2 LVDS_TXDL2_DN
2
0_5%_1
C3009
C3010
57A6 IN R3031 OUT 34C3
57A6 VGA_LVDS_TXDL2_DP 1
R3032 2
0_5%_1 LVDS_TXDL2_DP 34C3
IN OUT
A 57A6 VGA_LVDS_TXCL_DN 1
R3033 2
0_5%_1 LVDS_TXCL_DN 34B3 A
IN OUT
VGA_LVDS_TXCL_DP 1 2 LVDS_TXCL_DP
2
57A6 IN R3034 0_5%_1 OUT 34B3
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3050~3099(CRT)
P5V0S
2
D3050
SBR3U40P1
VGA_CRTR R3064
1 0_5%_1
2
56E2 56D3
IN
1
PCH_CRTR R3065
1 0_5%_1
2 CRTR L3052 1 2 120NH,5% CRTR_L
50B7 35A7 35C3
IN OUT
R3066 0_5%_1 P5V0S_CRT1
56E2 56D3 VGA_CRTG 1 2
IN L3051
PCH_CRTG R3067
1 2 CRTG 1 2 CRTG_L
50B7
IN 0_5%_1 120NH,5% OUT 35A7 35C3
D
2
VGA_CRTB R3068
1 0_5%_1
2 D
56E2 56D3
IN L3050 FUSE3050
0_5%_1 CRTB_L
50B7 PCH_CRTB R3069
1 2 CRTB 1 2 120NH,5% 35A7 35C3
IN OUT
SMD1812P110TF
1
1
1
1
15PF_50V_2
15PF_50V_2
C3050
C3051
15PF_50V_2
150_1%_2
150_1%_2
150_1%_2
C3052
P5V0S_CRT2
R3054
R3055
R3056
CN3051
2
P5V0S_CRTVDD CRTR_L 1
2
35D4 35A7 1
IN
35D4 35A7 CRTG_L 2 2
IN
35D4 35A7 CRTB_L 3 3
IN
1 TP24 4 4
TP3050
5 5
GM:2.2K
1
6 6
PM:2K 7
R3050 R3051 7
(60130B2020ZT) 8 8
2.2K_5%_2 9
2.2K_5%_2 9
10 10
2
1TP24 11 11
R3053 TP3051
35A3 CRT_DDCDATA_OUT 1 2 CRT_DDCDATA_R_OUT 12 12 G1 G1
C BI C
35A3 CRT_HSYNC_R_OUT 13 13 G2 G2
100_5%_2 IN
35A3 CRT_VSYNC_R_OUT 14 14
R3052 IN
35A3 CRT_DDCCLK_OUT 1 2 CRT_DDCCLK_R_OUT 15 15
BI
100_5%_2 SUYIN_070546HR015M25KZR_15P
1
C3053 C3054
0.1UF_16V_2_DY 0.1UF_16V_2_DY
2
RESERVE CAP FOR EMI
B R3070
1 0_5%_1
2 VGA_CRT_VSYNC B
56D3
56F7
IN
CRT_VSYNC R3071
1 0_5%_1
2 PCH_CRT_VSYNC
35A4 50A6
OUT IN
R3072
1 0_5%_1
2 VGA_CRT_HSYNC 56D3
56F7
IN
CRT_HSYNC R3073
1 2 PCH_CRT_HSYNC
35A4
OUT 0_5%_1 IN 50A6
P5V0S P3V3S R3074

1 0_5%_1
2 VGA_CRT_DDCDATA 56A3
IN
CRT_DDCDATA R3075 0_5%_1 PCH_CRT_DDCDATA
1
35A4 1 2 50A6
OUT IN
GM:2.2K
1
1
C3056
PM:10K R3076
1 0_5%_1
2 VGA_CRT_DDCCLK 56A3
(60130B1030ZT) R3060 R3061 IN
0.22UF_6.3V_2
CRT_DDCCLK R3077
1 0_5%_1
2 PCH_CRT_DDCCLK
2.2K_5%_2 2.2K_5%_2 35A4
OUT IN 50A6
2
P3V3S
U3050 R3062
1 VCC-SYNC SYNC_OUT2 16 CRT_VSYNC_OUT 1 2 30_5%_2 CRT_VSYNC_R_OUT 35C3
OUT
2 VCC-VIDEO SYNC_IN2 15 CRT_VSYNC 35B4
IN R3063
A 35D4 35C3 CRTR_L 3 VIDEO_1 SYNC_OUT1 14 CRT_HSYNC_OUT 1 2 30_5%_2 CRT_HSYNC_R_OUT 35C3 A
IN OUT
1
35D4 35C3 CRTG_L 4 VIDEO_2 SYNC_IN1 13 CRT_HSYNC 35B4

IN IN
C3055 35C3 CRTB_L 5 VIDEO_3 DCC_OUT2 12 CRT_DDCDATA_OUT 35C5
P5V0S_CRTVDD IN OUT
35D4 6 GND DDC_IN2 11 CRT_DDCDATA 35A4
IN
0.22UF_6.3V_2 7 VCC-DCC DDC_IN1 10 CRT_DDCCLK 35A4
IN
8 BYP DDC_OUT1 9 CRT_DDCCLK_OUT 35C5
OUT
2
TI_TPD7S019_15DBQR_SSOP_16P
C3057
0.22UF_6.3V_2
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 3150~3199(HDMI)
PLACE CLOSE TO CONNECTOR
HDMI_TX2_C_DP 1 R3166 2 HDMI_TX2_R_DP

PCH_HDMI_DDCDATA 1 2 0_5%_1 36A7 36A2 IN
50B3 BI R3174
0_5%_2
50B3 PCH_HDMI_DDCCLK 1
R3175 2 0_5%_1
P5V0AL
BI
HDMI_TX2_C_DN 1 R3167 2 HDMI_TX2_R_DN
1
36A7 36A2 IN
0_5%_2
56B3 VGA_HDMI_DDCDATA 1
R3176 2 0_5%_1 HDMI_DDCDATA 36C8
BI BI 2 NC D3150
VGA_HDMI_DDCCLK 1 2 0_5%_1 HDMI_DDCCLK HDMI_TX1_C_DP 1 R3168 2 HDMI_TX1_R_DP

56B3 BI R3177 BI 36C8 36A7 36A2 IN DIODE-BAT54-TAP-PHP
D 0_5%_2
3
D
36A7 36A2 IN
1
R3152 GM: 2.2K
0_5%_2 R3153
PM:10K
2.2K_5%_2
2.2K_5%_2
(60130B1030ZT)
2
2
HDMI_TX0_C_DP 1 R3170 2 HDMI_TX0_R_DP
36A7 36A2 IN
0_5%_2

36B7 36A2 IN CN3150
P3V3S 1 TMDS Data2+
0_5%_2 2 TMDS Data2 Shield
3
P3V3S TMDS Data2-
GM: 2.2K
1
R3172 4 TMDS Data1+

36B7 36A2 HDMI_TXC_C_DP 1 2 HDMI_TXC_R_DP
PM:10K IN 5 TMDS Data1 Shield
R3178 R3179
(60130B1030ZT) 0_5%_2 6 TMDS Data1-
7 TMDS Data0+
2.2K_5%_2 2.2K_5%_2
G
R3173 8 TMDS Data0 Shield

Q3151 36B7 36A2 HDMI_TXC_C_DN1 2 HDMI_TXC_R_DN
IN 9
2
TMDS Data0-
G
SSM3K17FU 0_5%_2 10 TMDS Clock+

11 TMDS Clock Shield
36D6 HDMI_DDCDATA S S D D HDMI_CN_DDCDATA 36C3 37C3 12 TMDS Clock-

C BI BI C
37D6 HDMI_CEC 13 CEC G1 G1
BI
TP24 1 14 G2
G
Reserved G2
P5V0AL TP3151
37D3 36C6 HDMI_CN_DDCCLK 15 DDC Clock G3 G3
Q3150 BI
D3155 37C3 36C6 HDMI_CN_DDCDATA 16 DDC Data G4 G4
BI
G
SSM3K17FU FUSE3150 17 DDC/CEC GND

40MIL 2 1 P5V0AL_HDMI_VDD1 1 2 P5V0AL_HDMI_VDD2 18 +5V Power
36D6 HDMI_DDCCLK S S D D HDMI_CN_DDCCLK 36C3 37D3
BI BI 19 Hot Plug Detect
SMD1812P110TF
R3154 SYN_100042GR019M26DZL_19P
SBR3U40P1 37C1 HPDET_IC 1 2
OUT
1
P3V3S 1K_5%_2
C3150 R3150
C3151
100PF_50V_2
22PF_50V_2_DY
470K_5%_2
2
1
2
CLOSE TO CONNECTOR
GM:680_5% R3165
PM:499_5% 100K_5%_2
(6013A0076801)
1
Q3152 P3V3S
G
B B
HDMI_TXC_C_DP 1 R3164 2 3 2
36C5 36A2 IN D S R3180
5
50B3 PCH_HPDET 1 2 0_5%_1
680_5%_2 OUT U3150
SSM3K7002BFU HDMI_HPD_EC
+
R3181 1 21D6 37B1
R3163 IN
HDMI_TXC_C_DN 56C5 VGA_HPDET 1 2 0_5%_1 HPDET 4
36C5 36A2 1 2 OUT
IN 2 PLT_RST# 31C6 41C7 51A7
IN
680_5%_2
-
TC7SZ08FU
R3162
3
36D5 36A2 HDMI_TX0_C_DN 1 2
IN
680_5%_2
R3161
36D5 36A2 HDMI_TX0_C_DP 1 2
IN
680_5%_2
R3160
36D5 36A2 HDMI_TX1_C_DN 1 2
IN
C3152
680_5%_2 VGA_HDMI_TX2_DN 1 2
56F3 IN 0.1UF_6.3V_1 C3153
R3159 56F3 VGA_HDMI_TX2_DP C3154 1 2
0.1UF_6.3V_1
IN
36D5 36A2 HDMI_TX1_C_DP 1 2 56F3 VGA_HDMI_TX1_DN 1 2
0.1UF_6.3V_1 C3155
IN IN
56F3 VGA_HDMI_TX1_DP C3156 1 2
0.1UF_6.3V_1
680_5%_2 IN
56F3 VGA_HDMI_TX0_DN 1 2
0.1UF_6.3V_1 C3157
IN
A R3158 56F3 VGA_HDMI_TX0_DP C3158 1 2
0.1UF_6.3V_1 A
IN
36D5 36A2 HDMI_TX2_C_DN 1 2 56F3 VGA_HDMI_TXC_DN 1 2
0.1UF_6.3V_1 C3159
IN IN
56F3 VGA_HDMI_TXC_DP 1 2
0.1UF_6.3V_1
680_5%_2 IN
R3157
36D5 36A2 HDMI_TX2_C_DP 1 2
IN
C3160
680_5%_2 PCH_HDMI_TX2_DN 1 2 HDMI_TX2_C_DN
50B3 IN 0.1UF_6.3V_1 C3161 OUT 36A7 36D5
50B3 PCH_HDMI_TX2_DP C3162 1 2
0.1UF_6.3V_1 HDMI_TX2_C_DP 36A7 36D5
IN OUT
50B3 PCH_HDMI_TX1_DN 1 2
0.1UF_6.3V_1 C3163 HDMI_TX1_C_DN 36A7 36D5
IN OUT
PCH_HDMI_TX1_DP HDMI_TX1_C_DP
50B3
50B3
50B3
IN
IN
PCH_HDMI_TX0_DN
PCH_HDMI_TX0_DP
C3164
1
C3166
2
0.1UF_6.3V_1
1
C3165
1
2
0.1UF_6.3V_1
2
0.1UF_6.3V_1
HDMI_TX0_C_DN
HDMI_TX0_C_DP
OUT
OUT
36A7 36D5
36B7 36D5
36A7 36D5
INVENTEC
IN OUT
50B3 PCH_HDMI_TXC_DN 1 2
0.1UF_6.3V_1 C3167 HDMI_TXC_C_DN 36B7 36C5
IN OUT TITLE
50B3 PCH_HDMI_TXC_DP 1 2
0.1UF_6.3V_1 HDMI_TXC_C_DP 36B7 36C5
IN OUT MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3AL
P3V3AL
1
D3200
2 R3201 Q3201
G
NC
DIODE-BAT54-TAP-PHP
4.02K_1%_2 SSM3K17FU
G
2
D
3
37B3 HDMI_DDCCLK_CEC S S D DHDMI_CN_DDCCLK 36C3 36C6 D
BI BI
P3V3AL
1
P3V3AL
R3204
27K_5%_2
5
1
NC
2
U3203
+
R3214 HDMI_CEC
1
37B6 CEC_IN1 24 2 36C3
IN BI
R3200
G
- Q3200
68_5%_2 4.02K_1%_2
3
SSM3K17FU
G
74LVC1G14GV Q3203
3
2
D
R3206
G 1 1 2 CEC_OUT 37B6 37B3 HDMI_DDCDATA_CEC S S D DHDMI_CN_DDCDATA 36C3 36C6
OUT BI BI
1
S
22K_5%_2 P3V3AL
SSM3K7002BFU
2
R3205
1
100K_5%_2 P3V3AL
0.1UF_16V_2
C3200
2
C P3V3AL C
1
2
1
1
4.7K_5%_2
4.7K_5%_2
R3209
R3208
R3213
R3210
4.7K_5%_2
4.7K_5%_2
5
1
NC
U3202
2
U3200
2
2
EC_SMB2_CLK EC_SMB2_DATA
+
5A7 1 P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1 20 5A7 R3227
BI BI
21D3
56D8
21D2 2 P3_7-CNTR0#-SSO-TXD1 P3_3-TCIN-INT3#-SSI00-CMP1_0 19 21D3
56C8
21D2 1 2 4 2 HPDET_IC 36C4
IN
3 RESET# P1_0-KI0#-AN8-CMP0_0 18 HDMI_DDCDATA_CEC 37C5
BI
37A8 CEC_XOUT 4 XOUT-P4_7 P1_1-KI1#-AN9-CMP0_1 17 HDMI_DDCCLK_CEC 37D5 33_5%_2 -
OUT BI
5 VSS-AVSS P4_2-VREF 16
CEC_XIN 6 15 PHP_74LVC1G17_SOT753_5P
3
37A6 XIN-P4_6 P1_2-KI2#-AN10-CMP0_2
IN
7 VCC-AVCC P1_3-KI3#-AN11-TZOUT 14
8 MODE P1_4-TXD0 13
37D8 CEC_IN 9 P4_5-INT0#-RXD1 P1_5-RXD0-CNTR01-INT11# 12
IN
37C6 CEC_OUT 10 P1_7-CNTR00-INT10# P1_6-CLK0-SSI01 11
OUT
HDMI_HPD_EC 36B2
21D6
RENESAS_R5F211B4D61SP_LSSOP_20P OUT
RSC_0402_DY
B P3V3AL B
R3202
1
1
0.1UF_16V_2
1UF_6.3V_2
C3202
C3205
2
2
2
P3V3AL
1
1
47K_5%_2
47K_5%_2
R3211
R3212
2
37B6 CEC_XOUT CEC_XIN 37B6

OUT IN
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4100~4299(DDR)
43A4 BI
M_A_A<15..0>
CHA
M_A_DQ<63..0>
43D8
CN4100 BI
0 M_A_A<0> 98 A0 DQ0 5 M_A_DQ<0> 0
1 M_A_A<1> 97 A1 DQ1 7 M_A_DQ<1> 1
2 M_A_A<2> 96 A2 DQ2 15 M_A_DQ<2> 2
3 M_A_A<3> 95 A3 DQ3 17 M_A_DQ<3> 3
4 M_A_A<4> 92 A4 DQ4 4 M_A_DQ<4> 4
5 M_A_A<5> 91 A5 DQ5 6 M_A_DQ<5> 5
6 M_A_A<6> 90 A6 DQ6 16 M_A_DQ<6> 6
7 M_A_A<7> 86 A7 DQ7 18 M_A_DQ<7> 7
8 M_A_A<8> 89 A8 DQ8 21 M_A_DQ<8> 8
D 9 M_A_A<9> 85 A9 DQ9 23 M_A_DQ<9> 9 P1V5
CN4100
10 M_A_A<10> 107 A10/AP DQ10 33 M_A_DQ<10> 10 D
LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 75 VDD1 VSS16 44
11 M_A_A<11> 84 A11 DQ11 35 M_A_DQ<11> 11
76 VDD2 VSS17 48
12 M_A_A<12> 83 A12/BC# DQ12 22 M_A_DQ<12> 12
1
1
81 VDD3 VSS18 49
13 M_A_A<13> 119 A13 DQ13 24 M_A_DQ<13> 13
C4101 C4102 C4103 C4104 C4105 C4106 C4107 82 VDD4 VSS19 54
14 M_A_A<14> 80 A14 DQ14 34 M_A_DQ<14> 14 C4100
+
87 VDD5 VSS20 55
15 M_A_A<15> 78 A15 DQ15 36 M_A_DQ<15> 15
88 VDD6 VSS21 60
39 M_A_DQ<16> 16 330UF_2.5V_DY 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
DQ16 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 VDD7 VSS22 61
43A8 M_A_BS0 109 BA0 DQ17 41 M_A_DQ<17> 17
IN 94 65
2
2
VDD8 VSS23
43A8 M_A_BS1 108 BA1 DQ18 51 M_A_DQ<18> 18
IN 99 VDD9 VSS24 66
43A8 M_A_BS2 79 BA2 DQ19 53 M_A_DQ<19> 19
IN NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S 100 VDD10 VSS25 71
M_CS#0 40 M_A_DQ<20>
1
43C5 114 S0# DQ20 20
IN 105 VDD11 VSS26 72
43C5 M_CS#1 121 S1# DQ21 42 M_A_DQ<21> 21 C4110 C4109 C4108
IN P3V3S 106 VDD12 VSS27 127
43D4 M_CLK_DDR0_DP 101 CK0 DQ22 50 M_A_DQ<22> 22
IN 111 VDD13 VSS28 128
43D4 M_CLK_DDR0_DN 103 CK0# DQ23 52 M_A_DQ<23> 23
IN 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3
112 VDD14 VSS29 133
43D4 M_CLK_DDR1_DP 102 CK1 DQ24 57 M_A_DQ<24> 24
IN 117 VDD15 VSS30 134
M_CLK_DDR1_DN 104 59 M_A_DQ<25>
2
43D4 CK1# DQ25 25
IN 118 VDD16 VSS31 138
43D4 M_CKE0 73 CKE0 DQ26 67 M_A_DQ<26> 26
IN
1
123 VDD17 VSS32 139
43D4 M_CKE1 74 CKE1 DQ27 69 M_A_DQ<27> 27
IN 124 VDD18 VSS33 144
43A8 M_A_CAS# 115 CAS# DQ28 56 M_A_DQ<28> 28 C4114 C4115
IN VSS34 145
43A8 M_A_RAS# 110 RAS# DQ29 58 M_A_DQ<29> 29
IN 199 VDDSPD VSS35 150
43A8 M_A_WE# 113 WE# DQ30 68 M_A_DQ<30> 30 2.2UF_6.3V_3 0.1UF_16V_2
IN VSS36 151
38A6 SA0_DIM0 197 SA0 DQ31 70 M_A_DQ<31> 31
OUT 77 155
2
NC1 VSS37
38A6 SA1_DIM0 201 SA1 DQ32 129M_A_DQ<32> 32
C OUT 122 NC2 VSS38 156 C
48A8 39C8 PCH_3S_SMCLK 202 SCL DQ33 131M_A_DQ<33> 33
IN 125 NCTEST VSS39 161
48A8 39C8 PCH_3S_SMDATA 200 SDA DQ34 141M_A_DQ<34> 34
IN VSS40 162
DQ35 143M_A_DQ<35> 35
VSS41 167
43C5 M_ODT0 116 ODT0 DQ36 130M_A_DQ<36> 36
IN 39C3 38B5 PM_EXTTS#1_R 198 EVENT# VSS42 168
43C5 M_ODT1 120 ODT1 DQ37 132M_A_DQ<37> 37
P0V75M_VREF OUT
IN 41A5 39C3 DDR3_DRAMRST# 30 RESET# VSS43 172
DQ38 140M_A_DQ<38> 38 OUT
VSS44 173
11 DM0 DQ39 142M_A_DQ<39> 39
VSS45 178
28 DM1 DQ40 147M_A_DQ<40> 40 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 1 VREF_DQ VSS46 179
46 DM2 DQ41 149M_A_DQ<41> 41
126 VREF_CA VSS47 184
157M_A_DQ<42>
1
63 DM3 DQ42 42
VSS48 185
136 DM4 DQ43 159M_A_DQ<43> 43
C4150 C4116 189
153 DM5 DQ44 146M_A_DQ<44> 44
VSS49 P0V75S
2 VSS1 VSS50 190
170 148M_A_DQ<45> 45
DM6 DQ45
0.1UF_16V_2 P0V75M_VREF 3 195
187 DM7 DQ46 158M_A_DQ<46> 46 2.2UF_6.3V_3 VSS2 VSS51
8 VSS3 VSS52 196
160M_A_DQ<47>
2
DQ47 47
9 VSS4
43B5 M_A_DQS0_DP 12 DQS0 DQ48 163M_A_DQ<48> 48
IN 13 VSS5
IN 14 VSS6
IN 19 VSS7
M_A_DQS3_DP 177M_A_DQ<51>
1
43B5 64 DQS3 DQ51 51
IN 20
43B5 IN
M_A_DQS4_DP 137 DQS4 DQ52 164M_A_DQ<52> 52
C4117 C4118 25
VSS8
VSS9 VTT1 203 1.5A

IN 26 VSS10 VTT2 204
IN 2.2UF_6.3V_3 0.1UF_16V_2 31 VSS11
B 43B5 M_A_DQS7_DP 188 176M_A_DQ<55> 55 B
IN DQS7 DQ55 P3V3S 32 VSS12 G1 G1
M_A_DQS0_DN 10 181M_A_DQ<56>
2
43B5 DQS0# DQ56 56
IN 37 VSS13 G2 G2
43B5 M_A_DQS1_DN 27 DQS1# DQ57 183M_A_DQ<57> 57
IN 38 VSS14
IN
1
43 VSS15
IN
IN R4104 BELLW_80001_1021_204P
IN 10K_5%_2
IN
IN
2
PM_EXTTS#1_R
39C3 38C3
BELLW_80001_1021_204P IN
PLACE THESE CAPS CLOSE TO VTT1 AND VTT2
1
P3V3S C4119 C4120 C4121 C4122
1
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
NOTE:
R4100 R4101
10K_5%_2_DY 10K_5%_2_DY
IF SA0_DIM0=1 , SA1_DIM0=0
A A
SO-DIMMA SPD ADDRESS IS 0XA2
2
SA0_DIM0 38C8
SO-DIMMA TS ADDRESS IS 0X32 IN
SA1_DIM0 38C8
IN
1
IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0 R4102 R4103
10K_5%_2 10K_5%_2
SO-DIMMA TS ADDRESS IS 0X30
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4100~4299(DDR)
43A1 BI
M_B_A<15..0>
CHB
M_B_DQ<63..0>
BI 43D4
CN4101
0 M_B_A<0> 98 A0 DQ0 5 M_B_DQ<0> 0
1 M_B_A<1> 97 A1 DQ1 7 M_B_DQ<1> 1
2 M_B_A<2> 96 A2 DQ2 15 M_B_DQ<2> 2
3 M_B_A<3> 95 A3 DQ3 17 M_B_DQ<3> 3
4 M_B_A<4> 92 A4 DQ4 4 M_B_DQ<4> 4
5 M_B_A<5> 91 A5 DQ5 6 M_B_DQ<5> 5
6 M_B_A<6> 90 A6 DQ6 16 M_B_DQ<6> 6
D 7 M_B_A<7> 86 A7 DQ7 18 M_B_DQ<7> 7
8 M_B_A<8> 89 A8 DQ8 21 M_B_DQ<8> 8 D
9 M_B_A<9> 85 23 M_B_DQ<9> 9
A9 DQ9 P1V5
10 M_B_A<10> 107 A10_AP DQ10 33 M_B_DQ<10> 10 CN4101
LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN 75 VDD1 VSS16 44
11 M_B_A<11> 84 A11 DQ11 35 M_B_DQ<11> 11
76 VDD2 VSS17 48
12 M_B_A<12> 83 A12 DQ12 22 M_B_DQ<12> 12
1
81 VDD3 VSS18 49
13 M_B_A<13> 119 A13 DQ13 24 M_B_DQ<13> 13
C4124 C4125 C4126 C4127 C4128 C4129 C4130 82 VDD4 VSS19 54
14 M_B_A<14> 80 A14 DQ14 34 M_B_DQ<14> 14
87 VDD5 VSS20 55
15 M_B_A<15> 78 A15 DQ15 36 M_B_DQ<15> 15
88 VDD6 VSS21 60
39 M_B_DQ<16> 16 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
DQ16 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 93 VDD7 VSS22 61
43A4 M_B_BS0 109 BA0 DQ17 41 M_B_DQ<17> 17
IN 94 65
2
VDD8 VSS23
43A4 M_B_BS1 108 BA1 DQ18 51 M_B_DQ<18> 18
IN 99 VDD9 VSS24 66
43A4 M_B_BS2 79 BA2 DQ19 53 M_B_DQ<19> 19
IN 100 VDD10 VSS25 71
M_CS#2 40 M_B_DQ<20>
1
43C1 114 S0# DQ20 20
IN 105 VDD11 VSS26 72
43C1 M_CS#3 121 S1# DQ21 42 M_B_DQ<21> 21 C4133 C4132 C4131
IN P3V3S 106 VDD12 VSS27 127
43D1 M_CLK_DDR2_DP 101 CK0 DQ22 50 M_B_DQ<22> 22
IN 111 VDD13 VSS28 128
43D1 M_CLK_DDR2_DN 103 CK0# DQ23 52 M_B_DQ<23> 23
IN 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3
112 VDD14 VSS29 133
43D1 M_CLK_DDR3_DP 102 CK1 DQ24 57 M_B_DQ<24> 24
IN 117 VDD15 VSS30 134
M_CLK_DDR3_DN 104 59 M_B_DQ<25>
2
43D1 CK1# DQ25 25
IN 118 VDD16 VSS31 138
43D1 M_CKE2 73 CKE0 DQ26 67 M_B_DQ<26> 26
IN
1
123 VDD17 VSS32 139
43D1 M_CKE3 74 CKE1 DQ27 69 M_B_DQ<27> 27
IN 124 VDD18 VSS33 144
43A4 M_B_CAS# 115 CAS# DQ28 56 M_B_DQ<28> 28 C4138 C4137
IN VSS34 145
43A4 M_B_RAS# 110 RAS# DQ29 58 M_B_DQ<29> 29
IN 199 VDDSPD VSS35 150
43A4 M_B_WE# 113 WE# DQ30 68 M_B_DQ<30> 30
2.2UF_6.3V_3 0.1UF_16V_2
C IN VSS36 151 C
39A7 SA0_DIM1 197 SA0 DQ31 70 M_B_DQ<31> 31
OUT 77 155
2
NC1 VSS37
39A6 SA1_DIM1 201 SA1 DQ32 129M_B_DQ<32> 32
OUT 122 NC2 VSS38 156
48A8 38C8 PCH_3S_SMCLK 202 SCL DQ33 131M_B_DQ<33> 33
IN 125 NCTEST VSS39 161
48A8 38C8 PCH_3S_SMDATA 200 SDA DQ34 141M_B_DQ<34> 34
IN VSS40 162
DQ35 143M_B_DQ<35> 35
38C3 38B5 PM_EXTTS#1_R 198 EVENT# VSS41 167
43C1 M_ODT2 116 ODT0 DQ36 130M_B_DQ<36> 36
P0V75M_VREF OUT
IN 41A5 38C3 DDR3_DRAMRST# 30 RESET# VSS42 168
43C1 M_ODT3 120 ODT1 DQ37 132M_B_DQ<37> 37 OUT
IN VSS43 172
DQ38 140M_B_DQ<38> 38
VSS44 173
11 DM0 DQ39 142M_B_DQ<39> 39 ALL VREF TRACES SHOULD HAVE 10 MIL TRACE WIDTH 1 VREF_DQ VSS45 178
28 DM1 DQ40 147M_B_DQ<40> 40
126 VREF_CA VSS46 179
46 DM2 DQ41 149M_B_DQ<41> 41
VSS47 184
157M_B_DQ<42>
1
63 DM3 DQ42 42
VSS48 185
136 DM4 DQ43 159M_B_DQ<43> 43
C4151 C4139 2 189
153 DM5 DQ44 146M_B_DQ<44> 44
VSS1 VSS49 P0V75S
3 VSS2 VSS50 190
170 148M_B_DQ<45> 45
DM6 DQ45
0.1UF_16V_2 P0V75M_VREF 8 195
187 DQ46 158M_B_DQ<46> 46 2.2UF_6.3V_3 VSS3 VSS51
DM7
9 VSS4 VSS52 196
160M_B_DQ<47>
2
DQ47 47
13 VSS5
43B1 M_B_DQS0_DP 12 DQS0 DQ48 163M_B_DQ<48> 48
IN 14 VSS6
IN 19 VSS7
IN 20 VSS8
M_B_DQS3_DP 177M_B_DQ<51>
1
43B1 64 DQS3 DQ51 51
IN 25
43B1 IN
M_B_DQS4_DP 137 DQS4 DQ52 164M_B_DQ<52> 52
C4140 C4141 26
VSS9
VSS10 VTT1 203 1.5A

B 43B1 M_B_DQS5_DP 154 DQS5 DQ53 166M_B_DQ<53> 53 B
IN 31 VSS11 VTT2 204
IN 2.2UF_6.3V_3 0.1UF_16V_2 32 VSS12
IN 37 VSS13 G1 G1
M_B_DQS0_DN 10 181M_B_DQ<56>
2
43B1 DQS#0 DQ56 56
IN 38 VSS14 G2 G2
43B1 M_B_DQS1_DN 27 DQS#1 DQ57 183M_B_DQ<57> 57
IN 43 VSS15
IN
43B1 M_B_DQS3_DN 62 DQS#3 DQ59 193M_B_DQ<59> 59 BELLW_80001_5021_204P
IN
IN
IN
IN
IN
BELLW_80001_5021_204P
PLACE THESE CAPS CLOSE TO VTT1 AND VTT2
1
NOTE: P3V3S C4142 C4143 C4144 C4145
SO-DIMMB SPD ADDRESS IS 0XA4
SO-DIMMB TS ADDRESS IS 0X34
1
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2
2
R4105 R4106
A A
10K_5%_2_DY 10K_5%_2
2
39C8 SA0_DIM1 SA1_DIM1 39C8

IN IN
1
R4107 R4108
10K_5%_2 10K_5%_2_DY
INVENTEC
2
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL ) P5V0S
PAD4300
P5V0S_FAN
1 2
1 2
POWERPAD_2_0610
L4300
1 2
1
22UF_6.3V_5_DY
1
4.7UF_6.3V_3
KC_FBM_11_160808_101_T_2P_DY
0.1UF_16V_2
C4301
C4302
C4307
2
2
D
P3V3S D
10K_5%_2
2 R4300
CN4300
1 1
2 2
FAN_TACH1 1
TP4300
3 G1
21B6 3 G
IN
4 4 G G2
TP30
ACES_50273_0047N_001_4P
1
P3V3S
CSC0402_DY
220pF_50V_2
C4300
C4305
2
1
C C
10K_5%_2
R4306
FAN CN
2
FAN1_PWM TP4301
21B6 1
IN
TP30
CSC0402_DY
C4306
2
B B
P5V0AL
49B7 11C7 11A4 PVCORE_PG
IN
1
100K_1%_NTC 26.7K_1%_2
R4442
THRM_SHUTDWN# 15D8 56D6

40A8
P5V0AL OUT
1
1
R4414
0.1UF_16V_2
1
3
1
C4441
2M_5%_2
R4445 Q4411
R4444
D
2
100K_5%_2 P5V0AL 1 G
2
S
C
2
26.7K_1%_2
U4441
2
R4446
Q4412
1
1 VCC TMSNS1 8 R4413 SSM3K7002BFU
PM_THRMTRIP#
C
1 2 B
2
52C1 41D5
IN B C4412
2 71 R4443 2
E
GND RHYST1 330_5%_2
MMBT4401
13.3K_1%_2
2
CSC0402_DY
E
56D6
40B1 15D8 THRM_SHUTDWN# 3 OT1 TMSNS2 6
OUT
2
4 5 1 R4441 2
OT2 RHYST2
1
100K_1%_NTC
13.3K_1%_2
R4447
ENE_P2809A2_SOT23_8P
A A
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU) CN4500
P1V8S
BCLK A28 CLK_DMI_PCH_DP 48B3
IN
CLOCKS
MISC
41D8 H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_DMI_PCH_DN 48B3
OUT IN
P1V05S
2
TP4500
1 AN34 SKTOCC#
R4500 R4502 DPLL_REF_CLK A16 R4510 1 2 1K_5%_2

TP24
2.2K_5%_2 2.2K_5%_2_DY DPLL_REF_CLK# A15 R4511 1 2 1K_5%_2
1
P1V05S TP4501
1 AL33 CATERR#
H_SNB_IVB# 1 R4501 2 NV_CLE TP24

41D5 52B2
OUT OUT
THERMAL
D 1K_5%_2
DDR3
PLACE CLOSE TO CPT AND NVRAM CONNECTOR H_PECI AN33 R8 CPU_DRAMRST# D
52C2 21A6 OUT PECI SM_DRAMRST#
OUT 41A5
MISC
R4503
62_5%_2
CPU_PROCHOT# 1 R4504 2 CPU_PROCHOT#_R AL32 AK1SM_RCOMP0 R4512 1 2
2
21C3 11B7 PROCHOT# SM_RCOMP[0] 140_1%_2
PROCESS STRAP SETTING OUT
SM_RCOMP[1] A5 SM_RCOMP1 R4513 1 2 25.5_1%_2
1
56_5%_2
SM_RCOMP[2] A4 SM_RCOMP2 R4514 1 2 200_1%_2
C4500
SANDY BRIDGE ONLY STUFF R4502 PM_THRMTRIP# AN32
CSC0402_DY 40A4 OUT THERMTRIP#
52C1
STUFF R4500/R4501
2
SANDY BRIDGE/IVY BRIDGE
PRDY# AP29 TP30 1 TP4502 H_PRDY#

OUT
PREQ# AP27 TP30 1 TP4503 H_PREQ# 41B2
IN
P1V5S TCK AR26 TP30 1 TP4504 H_TCK 41B2
LOW IN C6/C7 IN
DMI&FDI TERMINATIONVOLTAGE AR27 TP30 1 TP4505 H_TMS
PWR MANAGEMENT
TMS 41B2
IN
H_PM_SYNC TP30 H_TRST#
1
AM34 AP30 1
JTAG & BPM

49A3 PM_SYNC TRST# TP4506 41B2
BI IN
NV_CLE SET TOVSS WHEN LOW(DEFAULT) R4505 TDI AR28 TP30 1 TP4507 H_TDI 41B2
IN
200_5%_2 TDO AP26 1 TP4508 H_TDO
TP30 OUT
C SET TOVCC WHEN HIGH 52C2 H_CPUPWRGD AP33 UNCOREPWRGOOD C
IN
2
R4506 DBR# AL35 TP30 1 TP4509 SYS_RESET# 49B8
OUT
49B7 PM_DRAM_PWRGD 1 2 PM_DRAM_PWRGD_R V8 SM_DRAMPWROK
IN
130_1%_2 AT28
BPM#[0]
BPM#[1] AR29 CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT
R4507 BPM#[2] AR30 - MAX LENGTH = 500 MILS
51A7
36B2 31C6 PLT_RST# 1 2 AR33 RESET# BPM#[3] AT30 - TRACE WIDTH = 15MILS AND
IN
BPM#[4] AP32 - MB TRACE IMPEDANCE < 68 MOHMS
1.5K_5%_2 BPM#[5] AR31 (WORST CASE RESISTANCE)
1
BPM#[6] AT31
BPM#[7] AR32
R4509
R4508
10K_5%_2
750_1%_2 P1V05S
2
LOTES_ACA_ZIF_069_P01_989P 41C1 H_TMS R4516 1 2 51_5%_2
IN
41C1 H_TDI R4517 1 2 51_5%_2
IN
41C1 H_PREQ# R1418 1 2 51_5%_2_DY
IN
B B
41C1 H_TCK R4519 1 2 51_5%_2

S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3 IN
41C1 H_TRST# R4520 1 2 51_5%_2
IN
P3V3A P1V5
1
R4602
R4601
1K_5%_2 1K_5%_2
2
R4603 DDR3_DRAMRST#
1 2 38C3 39C3
DRAMRST_CNTRL OUT
45D6
OUT 1K_5%_2
45D8
3
Q4600
D
DRAMRST_CNTRL_PCH R4600
48D3 1 2 1 G
IN
S
0_5%_2
A CPU_DRAMRST# A
SSM3K7002BFU
IN 41D2
1 2
1
C4620 R4604
0.047UF_16V_2
4.99K_1%_2
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S
REFERENCE 4500~4699(CPU) CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS
SHOULD BE SHORTED AND ROUTED WITH
1
- MAX LENGTH = 500 MILS
R4522
- TYPICAL IMPEDANCE = 43 MOHMS
24.9_1%_2
CN4500
J22 P1V0S_VCCP_PEG_ICOMPI
2
PEG_ICOMPI
J21 PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH
PEG_ICOMPO
49D6 DMI_TX0_DN B27 DMI_RX#[0] PEG_RCOMPO H22 - MAX LENGTH = 500 MILS
OUT
49D6 DMI_TX1_DN B25 DMI_RX#[1]
OUT - TYPICAL IMPEDANCE = 14.5 MOHMS
49D6 DMI_TX2_DN A25 DMI_RX#[2]
OUT
49C6 DMI_TX3_DN B24 DMI_RX#[3] PEG_RX#[0] K33 PEG_C_RX15_DN 57B1
OUT IN
PEG_RX#[1] M35 PEG_C_RX14_DN 57B1
IN
D 49C6 DMI_TX0_DP B28 DMI_RX[0] PEG_RX#[2] L34 PEG_C_RX13_DN 57B1
OUT IN
49C6 DMI_TX1_DP B26 DMI_RX[1] PEG_RX#[3] J35 PEG_C_RX12_DN 57B1 D
OUT IN
DMI
49C6 DMI_TX2_DP A24 DMI_RX[2] PEG_RX#[4] J32 PEG_C_RX11_DN 57B1
OUT IN
49C6 DMI_TX3_DP B23 DMI_RX[3] PEG_RX#[5] H34 PEG_C_RX10_DN 57C1
OUT IN
PEG_RX#[6] H31 PEG_C_RX9_DN
IN 57C1 CLOSE TO CPU
49D6 DMI_RX0_DN G21 DMI_TX#[0] PEG_RX#[7] G33 PEG_C_RX8_DN 57C1
OUT IN
49D6 DMI_RX1_DN E22 DMI_TX#[1] PEG_RX#[8] G30 PEG_C_RX7_DN 57C1
OUT IN
49D6 DMI_RX2_DN F21 DMI_TX#[2] PEG_RX#[9] F35 PEG_C_RX6_DN 57C1 42B4 PEG_TX0_DN C4580 1 2 0.22UF_6.3V_1 PEG_C_TX0_DN 57D6
OUT IN IN OUT
49D6 DMI_RX3_DN D21 DMI_TX#[3] PEG_RX#[10] E34 PEG_C_RX5_DN 57C1
OUT IN
PEG_RX#[11] E32 PEG_C_RX4_DN 57D1 42B4 PEG_TX1_DN C4581 1 2 0.22UF_6.3V_1 PEG_C_TX1_DN 57D6
IN IN OUT
49D6 DMI_RX0_DP G22 DMI_TX[0] PEG_RX#[12] D33 PEG_C_RX3_DN 57D1
OUT IN
49D6 DMI_RX1_DP D22 DMI_TX[1] PEG_RX#[13] D31 PEG_C_RX2_DN 57D1 42B4 PEG_TX2_DN C4582 1 2 0.22UF_6.3V_1 PEG_C_TX2_DN 57D6
OUT IN IN OUT
49D6 DMI_RX2_DP F20 DMI_TX[2] PEG_RX#[14] B33 PEG_C_RX1_DN 57D1
OUT IN
49D6 DMI_RX3_DP C21 DMI_TX[3] PEG_RX#[15] C32 PEG_C_RX0_DN 57D1 42B4 PEG_TX3_DN C4583 1 2 0.22UF_6.3V_1 PEG_C_TX3_DN 57D6
OUT IN IN OUT
PEG_RX[0] J33 PEG_C_RX15_DP 57B1 42B4 PEG_TX4_DN C4584 1 2 0.22UF_6.3V_1 PEG_C_TX4_DN 57D6
IN IN OUT
PEG_RX[1] L35 PEG_C_RX14_DP 57B1
IN
PCI EXPRESS* - GRAPHICS

PEG_RX[2] K34 PEG_C_RX13_DP 57B1 42B4 PEG_TX5_DN C4585 1 2 0.22UF_6.3V_1 PEG_C_TX5_DN 57C6
IN IN OUT
49D3 FDI_TX0_DN A21 FDI0_TX#[0] PEG_RX[3] H35 PEG_C_RX12_DP 57B1
OUT IN
49D3 FDI_TX1_DN H19 FDI0_TX#[1] PEG_RX[4] H32 PEG_C_RX11_DP 57B1 42B4 PEG_TX6_DN C4586 1 2 0.22UF_6.3V_1 PEG_C_TX6_DN 57C6
OUT IN IN OUT
49D3 FDI_TX2_DN E19 FDI0_TX#[2] PEG_RX[5] G34 PEG_C_RX10_DP 57C1
OUT IN
49D3 FDI_TX3_DN F18 FDI0_TX#[3] PEG_RX[6] G31 PEG_C_RX9_DP 57C1 42B4 PEG_TX7_DN C4587 1 2 0.22UF_6.3V_1 PEG_C_TX7_DN 57C6
OUT IN IN OUT
49D3 FDI_TX4_DN B21 FDI1_TX#[0] PEG_RX[7] F33 PEG_C_RX8_DP 57C1
OUT IN
49D3 FDI_TX5_DN C20 FDI1_TX#[1] PEG_RX[8] F30 PEG_C_RX7_DP 57C1 42B4 PEG_TX8_DN C4588 1 2 0.22UF_6.3V_1 PEG_C_TX8_DN 57C6
C OUT IN IN OUT C
FDI_TX6_DN D18 E35 PEG_C_RX6_DP
Intel(R) FDI
49D3 OUT FDI1_TX#[2] PEG_RX[9]
IN 57C1
49D3 FDI_TX7_DN E17 FDI1_TX#[3] PEG_RX[10] E33 PEG_C_RX5_DP 57D1 42B4 PEG_TX9_DN C4589 1 2 0.22UF_6.3V_1 PEG_C_TX9_DN 57C6
OUT IN IN OUT
PEG_RX[11] F32 PEG_C_RX4_DP 57D1
IN
PEG_RX[12] D34 PEG_C_RX3_DP 57D1 42B4 PEG_TX10_DN C4590 1 2 0.22UF_6.3V_1 PEG_C_TX10_DN 57C6
IN IN OUT
49D3 FDI_TX0_DP A22 FDI0_TX[0] PEG_RX[13] E31 PEG_C_RX2_DP 57D1
OUT IN
49D3 FDI_TX1_DP G19 FDI0_TX[1] PEG_RX[14] C33 PEG_C_RX1_DP 57D1 42B4 PEG_TX11_DN C4591 1 2 0.22UF_6.3V_1 PEG_C_TX11_DN 57B6
OUT IN IN OUT
49D3 FDI_TX2_DP E20 FDI0_TX[2] PEG_RX[15] B32 PEG_C_RX0_DP 57D1
OUT IN
49D3 FDI_TX3_DP G18 FDI0_TX[3] 42B4 PEG_TX12_DN C4592 1 2 0.22UF_6.3V_1 PEG_C_TX12_DN 57B6
OUT IN OUT
49C3 FDI_TX4_DP B20 FDI1_TX[0] PEG_TX#[0] M29 PEG_TX15_DN 42B3
OUT OUT
49C3 FDI_TX5_DP C19 FDI1_TX[1] PEG_TX#[1] M32 PEG_TX14_DN 42B3 42C4 PEG_TX13_DN C4593 1 2 0.22UF_6.3V_1 PEG_C_TX13_DN 57B6
OUT OUT IN OUT
49C3 FDI_TX6_DP D19 FDI1_TX[2] PEG_TX#[2] M31 PEG_TX13_DN 42C3
OUT OUT
49C3 FDI_TX7_DP F17 FDI1_TX[3] PEG_TX#[3] L32 PEG_TX12_DN 42C3 42C4 PEG_TX14_DN C4594 1 2 0.22UF_6.3V_1 PEG_C_TX14_DN 57B6
OUT OUT IN OUT
PEG_TX#[4] L29 PEG_TX11_DN 42C3
OUT
49C3 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 PEG_TX10_DN 42C3 42C4 PEG_TX15_DN C4595 1 2 0.22UF_6.3V_1 PEG_C_TX15_DN 57B6
IN OUT IN OUT
49C3 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 PEG_TX9_DN 42C3
IN OUT
PEG_TX#[7] J30 PEG_TX8_DN 42C3 42A4 PEG_TX0_DP C4596 1 2 0.22UF_6.3V_1 PEG_C_TX0_DP 57D6
P1V05S OUT IN OUT
49C3 FDI_INT H20 FDI_INT PEG_TX#[8] J28 PEG_TX7_DN 42C3
IN OUT
PEG_TX#[9] H29 PEG_TX6_DN 42C3 42A4 PEG_TX1_DP C4597 1 2 0.22UF_6.3V_1 PEG_C_TX1_DP 57D6
OUT IN OUT
PEG_TX5_DN
1
49C3 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 42C3

IN OUT
49C3 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 PEG_TX4_DN 42C3 42A4 PEG_TX2_DP C4598 1 2 0.22UF_6.3V_1 PEG_C_TX2_DP 57D6
IN OUT IN OUT
R4521 PEG_TX#[12] F27 PEG_TX3_DN 42C3
OUT
24.9_1%_2 PEG_TX#[13] D28 PEG_TX2_DN 42D3 42A4 PEG_TX3_DP C4599 1 2 0.22UF_6.3V_1 PEG_C_TX3_DP 57D6
OUT IN OUT
B PEG_TX#[14] F26 PEG_TX1_DN 42D3 B
OUT
E25 PEG_TX0_DN PEG_TX4_DP 1 2 PEG_C_TX4_DP
2
PEG_TX#[15]
OUT 42D3 42A4 IN C4600 0.22UF_6.3V_1
OUT 57D6
P1V0S_VCCP_EDP_COMPIO A18 eDP_COMPIO
A17 eDP_ICOMPO PEG_TX[0] M28 PEG_TX15_DP 42A3 42A4 PEG_TX5_DP C4601 1 2 0.22UF_6.3V_1 PEG_C_TX5_DP 57D6
OUT IN OUT
CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS B16 eDP_HPD PEG_TX[1] M33 PEG_TX14_DP 42A3
OUT
PEG_TX[2] M30 PEG_TX13_DP 42A3 42A4 PEG_TX6_DP C4602 1 2 0.22UF_6.3V_1 PEG_C_TX6_DP 57C6
SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH OUT IN OUT
PEG_TX[3] L31 PEG_TX12_DP 42A3
OUT
- TYPICAL IMPEDANCE < 25 MOHMS C15 eDP_AUX PEG_TX[4] L28 PEG_TX11_DP 42A3 42B4 PEG_TX7_DP C4603 1 2 0.22UF_6.3V_1 PEG_C_TX7_DP 57C6
OUT IN OUT
D15 K30 PEG_TX10_DP 42A3
eDP
eDP_AUX# PEG_TX[5]
OUT
PEG_TX[6] K27 PEG_TX9_DP 42B3 42B4 PEG_TX8_DP C4604 1 2 0.22UF_6.3V_1 PEG_C_TX8_DP 57C6
OUT IN OUT
PEG_TX[7] J29 PEG_TX8_DP 42B3
OUT
C17 eDP_TX[0] PEG_TX[8] J27 PEG_TX7_DP 42B3 42B4 PEG_TX9_DP C4605 1 2 0.22UF_6.3V_1 PEG_C_TX9_DP 57C6
OUT IN OUT
F16 eDP_TX[1] PEG_TX[9] H28 PEG_TX6_DP 42B3
OUT
C16 eDP_TX[2] PEG_TX[10] G28 PEG_TX5_DP 42B3 42B4 PEG_TX10_DP C4606 1 2 0.22UF_6.3V_1 PEG_C_TX10_DP 57C6
OUT IN OUT
G15 eDP_TX[3] PEG_TX[11] E28 PEG_TX4_DP 42B3
OUT
PEG_TX[12] F28 PEG_TX3_DP 42B3 42B4 PEG_TX11_DP C4607 1 2 0.22UF_6.3V_1 PEG_C_TX11_DP 57B6
OUT IN OUT
C18 eDP_TX#[0] PEG_TX[13] D27 PEG_TX2_DP 42B3
OUT
E16 eDP_TX#[1] PEG_TX[14] E26 PEG_TX1_DP 42B3 42B4 PEG_TX12_DP C4608 1 2 0.22UF_6.3V_1 PEG_C_TX12_DP 57B6
OUT IN OUT
D16 eDP_TX#[2] PEG_TX[15] D25 PEG_TX0_DP 42B3
OUT
F15 eDP_TX#[3] 42B4 PEG_TX13_DP C4609 1 2 0.22UF_6.3V_1 PEG_C_TX13_DP 57B6
IN OUT
42B4 PEG_TX14_DP C4610 1 2 0.22UF_6.3V_1 PEG_C_TX14_DP 57B6

LOTES_ACA_ZIF_069_P01_989P
IN OUT
42B4 PEG_TX15_DP C4611 1 2 0.22UF_6.3V_1 PEG_C_TX15_DP 57B6

IN OUT
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4500~4699(CPU)
SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR
CN4500
CN4500
39D5 M_B_DQ<63..0>
38D5 M_A_DQ<63..0> BI
BI SB_CLK[0] AE2 M_CLK_DDR2_DP 39C8
OUT
SB_CLK#[0] AD2 M_CLK_DDR2_DN 39C8
SA_CLK[0] AB6 M_CLK_DDR0_DP 38C8 OUT
OUT 0 M_B_DQ<0> C9 SB_DQ[0] SB_CKE[0] R9 M_CKE2 39C8
SA_CLK#[0] AA6 M_CLK_DDR0_DN 38C8 OUT
OUT 1 M_B_DQ<1> A7 SB_DQ[1]
0 M_A_DQ<0> C5 SA_DQ[0] SA_CKE[0] V9 M_CKE0 38C8
D OUT 2 M_B_DQ<2> D10 SB_DQ[2]
1 M_A_DQ<1> D5 SA_DQ[1]
3 M_B_DQ<3> C8 SB_DQ[3] D
2 M_A_DQ<2> D3 SA_DQ[2]
4 M_B_DQ<4> A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3_DP 39C8
3 M_A_DQ<3> D2 SA_DQ[3] OUT
5 M_B_DQ<5> A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR3_DN 39C8
4 M_A_DQ<4> D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1_DP 38C8 OUT
OUT 6 M_B_DQ<6> D9 SB_DQ[6] SB_CKE[1] R10 M_CKE3 39C8
5 M_A_DQ<5> C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR1_DN 38C8 OUT
OUT 7 M_B_DQ<7> D8 SB_DQ[7]
6 M_A_DQ<6> C2 SA_DQ[6] SA_CKE[1] V10 M_CKE1 38C8
OUT 8 M_B_DQ<8> G4 SB_DQ[8]
7 M_A_DQ<7> C3 SA_DQ[7]
9 M_B_DQ<9> F4 SB_DQ[9]
8 M_A_DQ<8> F10 SA_DQ[8]
10 M_B_DQ<10> F1 SB_DQ[10] RSVD_TP[11] AB2
9 M_A_DQ<9> F8 SA_DQ[9]
11 M_B_DQ<11> G1 SB_DQ[11] RSVD_TP[12] AA2
10 M_A_DQ<10> G10 SA_DQ[10] RSVD_TP[1] AB4
12 M_B_DQ<12> G5 SB_DQ[12] RSVD_TP[13] T9
11 M_A_DQ<11> G9 SA_DQ[11] RSVD_TP[2] AA4
13 M_B_DQ<13> F5 SB_DQ[13]
12 M_A_DQ<12> F9 SA_DQ[12] RSVD_TP[3] W9
14 M_B_DQ<14> F2 SB_DQ[14]
13 M_A_DQ<13> F7 SA_DQ[13]
15 M_B_DQ<15> G2 SB_DQ[15]
14 M_A_DQ<14> G8 SA_DQ[14]
16 M_B_DQ<16> J7 SB_DQ[16] RSVD_TP[14] AA1
15 M_A_DQ<15> G7 SA_DQ[15]
17 M_B_DQ<17> J8 SB_DQ[17] RSVD_TP[15] AB1
16 M_A_DQ<16> K4 SA_DQ[16] RSVD_TP[4] AB3
18 M_B_DQ<18> K10 SB_DQ[18] RSVD_TP[16] T10
17 M_A_DQ<17> K5 SA_DQ[17] RSVD_TP[5] AA3
19 M_B_DQ<19> K9 SB_DQ[19]
18 M_A_DQ<18> K1 SA_DQ[18] RSVD_TP[6] W10
20 M_B_DQ<20> J9 SB_DQ[20]
19 M_A_DQ<19> J1 SA_DQ[19]
21 M_B_DQ<21> J10 SB_DQ[21]
20 M_A_DQ<20> J5 SA_DQ[20]
22 M_B_DQ<22> K8 SB_DQ[22] SB_CS#[0] AD3 M_CS#2 39C8
21 M_A_DQ<21> J4 SA_DQ[21] OUT
23 M_B_DQ<23> K7 SB_DQ[23] SB_CS#[1] AE3 M_CS#3 39C8
22 M_A_DQ<22> J2 SA_DQ[22] SA_CS#[0] AK3 M_CS#0 38D8 OUT
OUT 24 M_B_DQ<24> M5 SB_DQ[24] RSVD_TP[17] AD6
23 M_A_DQ<23> K2 SA_DQ[23] SA_CS#[1] AL3 M_CS#1 38C8
OUT 25 M_B_DQ<25> N4 SB_DQ[25] RSVD_TP[18] AE6
C 24 M_A_DQ<24> M8 SA_DQ[24] RSVD_TP[7] AG1 C
26 M_B_DQ<26> N2 SB_DQ[26]
25 M_A_DQ<25> N10 SA_DQ[25] RSVD_TP[8] AH1
27 M_B_DQ<27> N1 SB_DQ[27]
26 M_A_DQ<26> N8 SA_DQ[26]
28 M_B_DQ<28> M4 SB_DQ[28]
27 M_A_DQ<27> N7 SA_DQ[27]
29 M_B_DQ<29> N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 39C8
28 M_A_DQ<28> M10 SA_DQ[28] OUT
30 M_B_DQ<30> M2 SB_DQ[30] SB_ODT[1] AD4 M_ODT3 39C8
29 M_A_DQ<29> M9 SA_DQ[29] SA_ODT[0] AH3 M_ODT0 38C8 OUT
OUT 31 M_B_DQ<31> M1 SB_DQ[31] RSVD_TP[19] AD5
30 M_A_DQ<30> N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 38C8
OUT 32 M_B_DQ<32> AM5 SB_DQ[32] RSVD_TP[20] AE5
M_A_DQ<31>
DDR SYSTEM MEMORY B

31 M7 SA_DQ[31] RSVD_TP[9] AG2
33 M_B_DQ<33> AM6 SB_DQ[33]
32 M_A_DQ<32> AG6 SA_DQ[32] RSVD_TP[10] AH2
34 M_B_DQ<34> AR3 SB_DQ[34]
M_A_DQ<33>
DDR SYSTEM MEMORY A
33 AG5 SA_DQ[33]
35 M_B_DQ<35> AP3 SB_DQ[35]
34 M_A_DQ<34> AK6 SA_DQ[34]
36 M_B_DQ<36> AN3 SB_DQ[36]
35 M_A_DQ<35> AK5 SA_DQ[35]
37 M_B_DQ<37> AN2 SB_DQ[37] SB_DQS#[0] D7 M_B_DQS0_DN 39B8
36 M_A_DQ<36> AH5 SA_DQ[36] OUT
38 M_B_DQ<38> AN1 SB_DQ[38] SB_DQS#[1] F3 M_B_DQS1_DN 39B8
37 M_A_DQ<37> AH6 SA_DQ[37] SA_DQS#[0] C4 M_A_DQS0_DN 38B8 OUT
OUT 39 M_B_DQ<39> AP2 SB_DQ[39] SB_DQS#[2] K6 M_B_DQS2_DN 39B8
38 M_A_DQ<38> AJ5 SA_DQ[38] SA_DQS#[1] G6 M_A_DQS1_DN 38B8 OUT
OUT 40 M_B_DQ<40> AP5 SB_DQ[40] SB_DQS#[3] N3 M_B_DQS3_DN 39B8
39 M_A_DQ<39> AJ6 SA_DQ[39] SA_DQS#[2] J3 M_A_DQS2_DN 38B8 OUT
OUT 41 M_B_DQ<41> AN9 SB_DQ[41] SB_DQS#[4] AN5 M_B_DQS4_DN 39B8
40 M_A_DQ<40> AJ8 SA_DQ[40] SA_DQS#[3] M6 M_A_DQS3_DN 38B8 OUT
OUT 42 M_B_DQ<42> AT5 SB_DQ[42] SB_DQS#[5] AP9 M_B_DQS5_DN 39B8
41 M_A_DQ<41> AK8 SA_DQ[41] SA_DQS#[4] AL6 M_A_DQS4_DN 38B8 OUT
OUT 43 M_B_DQ<43> AT6 SB_DQ[43] SB_DQS#[6] AK12 M_B_DQS6_DN 39B8
42 M_A_DQ<42> AJ9 SA_DQ[42] SA_DQS#[5] AM8 M_A_DQS5_DN 38B8 OUT
OUT 44 M_B_DQ<44> AP6 SB_DQ[44] SB_DQS#[7] AP15 M_B_DQS7_DN 39B8
43 M_A_DQ<43> AK9 SA_DQ[43] SA_DQS#[6] AR12M_A_DQS6_DN 38B8 OUT
OUT 45 M_B_DQ<45> AN8 SB_DQ[45]
44 M_A_DQ<44> AH8 SA_DQ[44] SA_DQS#[7] AM15M_A_DQS7_DN 38B8
OUT 46 M_B_DQ<46> AR6 SB_DQ[46]
45 M_A_DQ<45> AH9 SA_DQ[45]
47 M_B_DQ<47> AR5 SB_DQ[47]
46 M_A_DQ<46> AL9 SA_DQ[46]
B 48 M_B_DQ<48> AR9 SB_DQ[48] B
47 M_A_DQ<47> AL8 SA_DQ[47]
49 M_B_DQ<49>AJ11 SB_DQ[49] SB_DQS[0] C7 M_B_DQS0_DP 39B8
48 M_A_DQ<48> AP11 SA_DQ[48] OUT
50 M_B_DQ<50> AT8 SB_DQ[50] SB_DQS[1] G3 M_B_DQS1_DP 39B8
49 M_A_DQ<49> AN11 SA_DQ[49] SA_DQS[0] D4 M_A_DQS0_DP 38B8 OUT
OUT 51 M_B_DQ<51> AT9 SB_DQ[51] SB_DQS[2] J6 M_B_DQS2_DP 39B8
50 M_A_DQ<50> AL12 SA_DQ[50] SA_DQS[1] F6 M_A_DQS1_DP 38B8 OUT
OUT 52 M_B_DQ<52>AH11 SB_DQ[52] SB_DQS[3] M3 M_B_DQS3_DP 39B8
51 M_A_DQ<51> AM12 SA_DQ[51] SA_DQS[2] K3 M_A_DQS2_DP 38B8 OUT
OUT 53 M_B_DQ<53> AR8 SB_DQ[53] SB_DQS[4] AN6 M_B_DQS4_DP 39B8
52 M_A_DQ<52> AM11 SA_DQ[52] SA_DQS[3] N6 M_A_DQS3_DP 38B8 OUT
OUT 54 M_B_DQ<54>AJ12 SB_DQ[54] SB_DQS[5] AP8 M_B_DQS5_DP 39B8
53 M_A_DQ<53> AL11 SA_DQ[53] SA_DQS[4] AL5 M_A_DQS4_DP 38B8 OUT
OUT 55 M_B_DQ<55>AH12 SB_DQ[55] SB_DQS[6] AK11 M_B_DQS6_DP 39B8
54 M_A_DQ<54> AP12 SA_DQ[54] SA_DQS[5] AM9 M_A_DQS5_DP 38B8 OUT
OUT 56 M_B_DQ<56>AT11 SB_DQ[56] SB_DQS[7] AP14 M_B_DQS7_DP 39B8
55 M_A_DQ<55> AN12 SA_DQ[55] SA_DQS[6] AR11M_A_DQS6_DP 38B8 OUT
OUT 57 M_B_DQ<57>AN14 SB_DQ[57]
56 M_A_DQ<56> AJ14 SA_DQ[56] SA_DQS[7] AM14M_A_DQS7_DP 38B8
OUT 58 M_B_DQ<58>AR14 SB_DQ[58]
57 M_A_DQ<57> AH14 SA_DQ[57]
59 M_B_DQ<59>AT14 SB_DQ[59]
58 M_A_DQ<58> AL15 SA_DQ[58]
60 M_B_DQ<60>AT12 SB_DQ[60] M_B_A<15..0>
59 M_A_DQ<59> AK15 SA_DQ[59] OUT
M_A_A<15..0> 38D8 61 M_B_DQ<61>AN15 SB_DQ[61] SB_MA[0] AA8 M_B_A<0> 0
60 M_A_DQ<60> AL14 SA_DQ[60] OUT
62 M_B_DQ<62>AR15 SB_DQ[62] SB_MA[1] T7 M_B_A<1> 1
61 M_A_DQ<61> AK14 SA_DQ[61] SA_MA[0] AD10 M_A_A<0> 0
63 M_B_DQ<63>AT15 SB_DQ[63] SB_MA[2] R7 M_B_A<2> 2
62 M_A_DQ<62> AJ15 SA_DQ[62] SA_MA[1] W1 M_A_A<1> 1
SB_MA[3] T6 M_B_A<3> 3
63 M_A_DQ<63> AH15 SA_DQ[63] SA_MA[2] W2 M_A_A<2> 2
SB_MA[4] T2 M_B_A<4> 4
SA_MA[3] W7 M_A_A<3> 3
SB_MA[5] T4 M_B_A<5> 5
SA_MA[4] V3 M_A_A<4> 4
SB_MA[6] T3 M_B_A<6> 6
SA_MA[5] V2 M_A_A<5> 5
39D8 M_B_BS0 AA9 SB_BS[0] SB_MA[7] R2 M_B_A<7> 7
SA_MA[6] W3 M_A_A<6> 6 OUT
39D8 M_B_BS1 AA7 SB_BS[1] SB_MA[8] T5 M_B_A<8> 8
38D8 M_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 M_A_A<7> 7 OUT
OUT 39C8 M_B_BS2 R6 SB_BS[2] SB_MA[9] R3 M_B_A<9> 9
38D8 M_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 M_A_A<8> 8 OUT
OUT SB_MA[10] AB7 M_B_A<10> 10
38D8 M_A_BS2 V6 SA_BS[2] SA_MA[9] W5 M_A_A<9> 9
A OUT SB_MA[11] R1 M_B_A<11> 11 A
SA_MA[10] AD8 M_A_A<10> 10
SB_MA[12] T1 M_B_A<12> 12
SA_MA[11] V4 M_A_A<11> 11
39C8 M_B_CAS# AA10 SB_CAS# SB_MA[13] AB10 M_B_A<13> 13
SA_MA[12] W4 M_A_A<12> 12 OUT
39C8 M_B_RAS# AB8 SB_RAS# SB_MA[14] R5 M_B_A<14> 14
38C8 M_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 M_A_A<13> 13 OUT
OUT 39C8 M_B_WE# AB9 SB_WE# SB_MA[15] R4 M_B_A<15> 15
38C8 M_A_RAS# AD9 SA_RAS# SA_MA[14] V5 M_A_A<14> 14 OUT
OUT
38C8 M_A_WE# AF9 SA_WE# SA_MA[15] V7 M_A_A<15> 15
OUT
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
POWER
CN4500
REFERENCE 4500~4699(CPU)
E PVCORE E
P1V05S
AG35 VCC1
AG34 VCC2 VCCIO1 AH13
1
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
1
C4510 C4511 C4512 C4513 AG31 VCC5 VCCIO4 AC10
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AG30 Y10
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
C4531
C4533
C4534
C4535
C4536
C4537
VCC6 VCCIO5
C4542
C4541
C4540
C4532
AG29 VCC7 VCCIO6 U10
AG28 P10
2
VCC8 VCCIO7
AG27 VCC9 VCCIO8 L10
2
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF32 VCC14 VCCIO13 H14
1
1
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
C4514 C4515 C4516 C4517 AF27 G12
VCC19 VCCIO18
PEG AND DDR

22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AF26 F14
VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
2
2
AD32 VCC24 VCCIO23 E14
D AD30 VCC26 D
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
1
1
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
C4518 C4519 C4520 C4521 AC32 C12
VCC34 VCCIO32
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AC31 C11
VCC35 VCCIO33
AC30 VCC36 VCCIO34 B14
2
2
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
1
AA30 VCC46
P1V05S
AA29 VCC47
C4522 C4523 C4524 C4525
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5
AA28 VCC48 PLACE CLOSE TO CPU
AA27 VCC49
AA26 VCC50
1
2
Y35 VCC51
CORE SUPPLY
Y34 VCC52
Y33 R4528 R4527
C VCC53 C
Y32
130_1%_2 75_5%_2
VCC54
Y31 VCC55
2
Y30 VCC56
Y29 VCC57
Y28 VCC58
Y27
Y26
VCC59
VCC60
SVID SIGNAL TO VR
V35 VCC61
SVID
V34 VCC62 VIDALERT# AJ29 H_CPU_SVIDALRT# R4529 1 243_5%_2 VR_SVID_ALERT# 11C7
OUT
V33 VCC63 VIDSCLK AJ30 H_CPU_SVIDCLK R4530 1 2 0_5%_2 VR_SVID_CLK 11A3 11C7
OUT
V32 VCC64 VIDSOUT AJ28 H_CPU_SVIDDAT R4531 1 2 0_5%_2 VR_SVID_DATA 11A3 11C7
OUT
V31 VCC65
V30 VCC66
V29 VCC67 PVCORE
V28 VCC68
V27 VCC69
1
V26 VCC70
U35 VCC71
U34 R4532
VCC72
U33
100_1%_2
VCC73
U32 VCC74
VCCSENSE
2
11D6
U31 VCC75 OUT
VSSSENSE 11D6
U30 VCC76 OUT
1
U29 VCC77
U28 VCC78
U27 R4533
VCC79
U26
100_1%_2
B VCC80 B
R35 VCC81
2
R34 VCC82
R33 VCC83
R32 VCC84
R31 VCC85
R30 VCC86
P1V05S
R29 VCC87
R28 VCC88
1
SENSE LINES
R27 VCC89 VCC_SENSE AJ35

R26 VCC90 VSS_SENSE AJ34
P35 R4534
VCC91
P34
10_1%_2
VCC92
P33 VCC93 2
P32 VCC94 VCCIO_SENSE B10 VCC_SENSE_VCCIO 9B7
OUT
P31 VCC95 VSSIO_SENSE A10 VSS_SENSE_VCCIO 9B7
OUT
1
P30 VCC96
P29 VCC97
P28 R4535
VCC98
P27
10_1%_2
VCC99
P26 VCC100
2
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:
ROUTE WITH MIN. TRACE WIDTH OF 10 MILS

P0V75M_VREF P0V75M_VREF_H
P0V75M_VREF
P0V75M_VREF
46C4 CPUDDR_WR_VREF2 2 3
46C4 CPUDDR_WR_VREF1 2 3 IN S D 3 2
IN S D D S
Q4502
Q4501
1
AM2302N
G
AM2302N
Q4500
1
1
1
DRAMRST_CNTRL AM2302N R4541
45D8 41A8
IN 100K_5%_2
D 45D6 41A8 DRAMRST_CNTRL
IN
2
D
R4538
49A1
21D6 14D2 14B8 14A6 0_5%_2
13A2 SLP_S3#_3R 1 2
PVAXG IN
13D2
POWER
1
1
PVAXG R4539
CN4500
10_1%_2
C4578
2
AT24 AK35 GFX_VCC_SENSE 470PF_50V_2
2
VAXG1 VAXG_SENSE 11B8
OUT
SENSE
AT23 AK34 GFX_VSS_SENSE 11B8
LINES
VAXG2 VSSAXG_SENSE
OUT
AT21 VAXG3
1
1
AT20 VAXG4
AT18 VAXG5
AT17 R4540
VAXG6
C4651 C4545 C4546 C4547 C4548 C4549 C4550 AR24 VAXG7 10_1%_2
22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 AR23 VAXG8
AR21
2
2
VAXG9
AR20 VAXG10
P0V75M_VREF_H
VREF
AR18 VAXG11
AR17 VAXG12
C AP24 AL1 C
VAXG13 SM_VREF
AP23 VAXG14
AP21 VAXG15
AP20 VAXG16
AP18 VAXG17
AP17 VAXG18
AN24 VAXG19
AN23 VAXG20 NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE
AN21 VAXG21
AN20 VAXG22
P1V5S
AN18 VAXG23
AN17 VAXG24
5A
GRAPHICS
AM24 VAXG25 VDDQ1 AF7
DDR3 -1.5V RAILS

1
AM20 VAXG28 VDDQ4 AC7
+
AL24 Y7 C4567 C4568 C4569 C4570 C4571 C4572 C4573
VAXG31 VDDQ7
AL23 Y4 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3 220UF_2.5V
2
VAXG32 VDDQ8
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
B AL18 VAXG35 VDDQ11 U4 B
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20 VAXG46
AJ18 VAXG47
AJ17 VAXG48
AH24 VAXG49
PVSA
AH23 VAXG50
AH21 VAXG51 VCCSA1 M27
SA RAIL
1
AH20 VAXG52 VCCSA2 M26
1
AH18 VAXG53 VCCSA3 L26
AH17 J26
+
VAXG54 VCCSA4
J25 C4577
VCCSA5 C4574 C4575 C4576
J24 100UF_6.3V
VCCSA6 PVSA 10UF_6.3V_3 10UF_6.3V_3 10UF_6.3V_3
H26
2
VCCSA7
2
VCCSA8 H25
1
A A
R4544
P1V8S
1.8V RAIL
100_5%_2
L4500
1.2A
2
1 2 P1V8S_VCCPLL B6 VCCPLL1 VCCSA_SENSE H23 VCCSA_SENSE 10C4
OUT
MISC
A6 VCCPLL2
MPZ1608S221AT
1
A2 VCCPLL3
FC_C22 C22 VCCSA_VID0 10B4

OUT
VCCSA_VID1
C4562 C4563 C4564
C4565
22UF_6.3V_5
VCCSA_VID1 C24
OUT 10B4
INVENTEC
1
1
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2
2
R4556 R4547
R4547 TITLE
LOTES_ACA_ZIF_069_P01_989P MODEL,PROJECT,FUNCTION
1K_5%_2 1K_5%_2 SNB:0 OHM Block Diagram
2
2
IVB:1K OHM DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CN4500 CN4500
CN4500
RSVD28 L7
AT35 VSS1 VSS81 AJ22 T35 VSS161 VSS234 F22 RSVD29 AG7
AT32 VSS2 VSS82 AJ19 T34 VSS162 VSS235 F19 CFG<0> AK28 CFG[0] RSVD30 AE7
OUT
AT29 VSS3 VSS83 AJ16 T33 VSS163 VSS236 E30 CFG<1> AK29 CFG[1] RSVD31 AK2
OUT
AT27 VSS4 VSS84 AJ13 T32 VSS164 VSS237 E27 46A6 CFG<2> AL26 CFG[2] RSVD32 W8
OUT
AT25 VSS5 VSS85 AJ10 T31 VSS165 VSS238 E24 CFG<3> AL27 CFG[3]
OUT
AT22 VSS6 VSS86 AJ7 T30 VSS166 VSS239 E21 46A6 CFG<4> AK26 CFG[4]
OUT
AT19 VSS7 VSS87 AJ4 T29 VSS167 VSS240 E18 46A6 CFG<5> AL29 CFG[5] RSVD33 AT26
OUT
AT16 VSS8 VSS88 AJ3 T28 VSS168 VSS241 E15 46A6 CFG<6> AL30 CFG[6] RSVD34 AM33
OUT
AT13 VSS9 VSS89 AJ2 T27 VSS169 VSS242 E13 46A6 CFG<7> AM31 CFG[7] RSVD35 AJ27
OUT
AT10 VSS10 VSS90 AJ1 T26 VSS170 VSS243 E10 CFG<8> AM32 CFG[8]
OUT
AT7 VSS11 VSS91 AH35 P9 VSS171 VSS244 E9 CFG<9> AM30 CFG[9]
OUT
OUT
OUT
AR25 VSS14 VSS94 AH30 P5 VSS174 VSS247 E6 CFG<12> AN28 CFG[12]
D OUT
AR22 VSS15 VSS95 AH29 P3 VSS175 VSS248 E5 CFG<13> AN31 CFG[13] RSVD37 T8
OUT D
AR19 VSS16 VSS96 AH28 P2 VSS176 VSS249 E4 CFG<14> AN26 CFG[14] RSVD38 J16
OUT
AR16 VSS17 VSS97 AH26 N35 VSS177 VSS250 E3 CFG<15> AM27 CFG[15] RSVD39 H16
OUT
AR13 VSS18 VSS98 AH25 N34 VSS178 VSS251 E2 CFG<16> AK31 CFG[16] RSVD40 G16
OUT
AR10 VSS19 VSS99 AH22 N33 VSS179 VSS252 E1 CFG<17> AN29 CFG[17]
OUT
AR7 VSS20 VSS100 AH19 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N29 VSS183 VSS256 D26 RSVD41 AR35
AP31 VSS24 VSS104 AG9 N28 VSS184 VSS257 D20 AJ31 VAXG_VAL_SENSE RSVD42 AT34
AP28 VSS25 VSS105 AG8 N27 VSS185 VSS258 D17 AH31 VSSAXG_VAL_SENSE RSVD43 AT33
AP25 VSS26 VSS106 AG4 N26 VSS186 VSS259 C34 AJ33 VCC_VAL_SENSE RSVD44 AP35
AP22 VSS27 VSS107 AF6 M34 VSS187 VSS260 C31 AH33 VSS_VAL_SENSE RSVD45 AR34
AP19 VSS28 VSS108 AF5 L33 VSS188 VSS261 C28
AP16 VSS29 VSS109 AF3 L30 VSS189 VSS262 C27
AP13 VSS30 VSS110 AF2 L27 VSS190 VSS263 C25 AJ26 RSVD5
AP10 AE35 L9 C23
RESERVED
VSS31 VSS111 VSS191 VSS264
AP7 VSS32 VSS112 AE34 L8 VSS192 VSS265 C10
AP4 VSS33 VSS113 AE33 L6 VSS193 VSS266 C1 RSVD46 B34
AP1 VSS34 VSS114 AE32 L5 VSS194 VSS267 B22 45D8 CPUDDR_WR_VREF1 B4 RSVD6 RSVD47 A33
IN
AN30
AN27
VSS35
VSS36
VSS115
VSS116
AE31
AE30
L4
L3
VSS195
VSS196
VSS_1 VSS268
VSS269
B19
B17
45D6 IN
CPUDDR_WR_VREF2 D1 RSVD7 RSVD48
RSVD49
A34
B35
AN25
AN22
VSS37 VSS VSS117 AE29
AE28
L2
L1
VSS197 VSS270 B15
B13
RSVD50 C35
C VSS38 VSS118 VSS198 VSS271 C
AN19 VSS39 VSS119 AE27 K35 VSS199 VSS272 B11 F25 RSVD8
AN10 VSS42 VSS122 AD7 K26 VSS202 VSS275 B7 D24 RSVD11 RSVD51 AJ32
AN7 VSS43 VSS123 AC9 J34 VSS203 VSS276 B5 G25 RSVD12 RSVD52 AK32
AN4 VSS44 VSS124 AC8 J31 VSS204 VSS277 B3 G24 RSVD13
AM29 VSS45 VSS125 AC6 H33 VSS205 VSS278 B2 E23 RSVD14
AM25 VSS46 VSS126 AC5 H30 VSS206 VSS279 A35 D23 RSVD15
AM22 VSS47 VSS127 AC3 H27 VSS207 VSS280 A32 C30 RSVD16 VCC_DIE_SENSE AH27
AM19 VSS48 VSS128 AC2 H24 VSS208 VSS281 A29 A31 RSVD17
AM16 VSS49 VSS129 AB35 H21 VSS209 VSS282 A26 B30 RSVD18
AM13 AB34 H18 A23 B29 REMOVE
VSS50 VSS130 VSS210 VSS283 RSVD19
AM10 VSS51 VSS131 AB33 H15 VSS211 VSS284 A20 D30 RSVD20 RSVD54 AN35 CLK_XDP_CLKGEN_DP
AM7 VSS52 VSS132 AB32 H13 VSS212 VSS285 A3 B31 RSVD21 RSVD55 AM35
AM4 AB31 H10 A30 CLK_XDP_CLKGEN_DN
VSS53 VSS133 VSS213 RSVD22
AM3 VSS54 VSS134 AB30 H9 VSS214 C29 RSVD23
AM2 VSS55 VSS135 AB29 H8 VSS215
AM1 VSS56 VSS136 AB28 H7 VSS216
AL34 VSS57 VSS137 AB27 H6 VSS217 J20 RSVD24
AL31 VSS58 VSS138 AB26 H5 VSS218 B18 RSVD25 RSVD56 AT2
AL28 VSS59 VSS139 Y9 H4 VSS219 9C7 VCCIO_SEL A19 VCCIO_SEL RSVD57 AT1
OUT
AL25 VSS60 VSS140 Y8 H3 VSS220 RSVD58 AR1
B B
2
AL22 Y6 H2
10K_5%_2_DY
VSS61 VSS141 VSS221
AL19 Y5 H1 J15
R4555
VSS62 VSS142 VSS222 RSVD27
AL16 VSS63 VSS143 Y3 G35 VSS223
AL13 VSS64 VSS144 Y2 G32 VSS224
AL10 VSS65 VSS145 W35 G29 VSS225 KEY B1
AL7 W34 G26
1
VSS66 VSS146 VSS226
AL4 VSS67 VSS147 W33 G23 VSS227
AL2 VSS68 VSS148 W32 G20 VSS228
AK33 VSS69 VSS149 W31 G17 VSS229
AK30 VSS70 VSS150 W30 G11 VSS230
AK27 VSS71 VSS151 W29 F34 VSS231
AK25 VSS72 VSS152 W28 F31 VSS232 LOTES_ACA_ZIF_069_P01_989P
AK22 VSS73 VSS153 W27 F29 VSS233
AK19 VSS74 VSS154 W26
AK16 VSS75 VSS155 U9
AK7 U5 PEG STATIC LANE REVERSAL
VSS78 VSS158
AK4 VSS79 VSS159 U3
AJ25 U2 CFG(2) 1 : (DEFAULT) NORMAL OPERATION
VSS80 VSS160
0 : LANE REVERSED
LOTES_ACA_ZIF_069_P01_989P LOW EDP ENABLE

A A
LOTES_ACA_ZIF_069_P01_989P 1 : (DEFAULT) EDP DISABLED
R4550 CFG(4) 0 : EDP ENABLED
CFG<2> 1 2
PEG STATIC LAN REVERSAL IN
1K_1%_2
PEG DEFER TRAINING
CFG<4> 1 R4551 2
46D4 IN
LOW EDP ENABLE 1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION
1K_1%_2_DY
CFG(7) 0 : PEG WAIT FOR BIOS FOR TRAINING
CFG<5> 1 R4552 2
46D4 IN
1K_1%_2_DY PCIE PORT BIFURCATION STRAPS
PCIE PORT BIFURCATION IN

CFG<6> 1 R4553 2 11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED INVENTEC
1K_1%_2_DY
10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED TITLE
CFG<7> R4554
CFG[6:5] 01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED)
PEG DEFER TRAINING 46D4 1 2 MODEL,PROJECT,FUNCTION
IN Block Diagram
1K_1%_2_DY
00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS
STRAP PIN
XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH)
P3V3AL P3V3A
1 R4736 2
0_5%_2_DY
2A2 P1V05S
1 R4737 2
P3V3_RTC
RSC_0402_DY
C4703
RTCX2
1
1 2
3
C P3V3_RTC
D4700 18PF_50V_2
R4703
3
4
BAT54C_30V_0.2A
1
20K_1%_2 R4738 R4740 R4742
D 1 2 R4708 RSC_0402_DY RSC_0402_DY RSC_0402_DY
PCH_TDI
2
X4700
A1
47A6 OUT
1
10M_5%_2 PCH_TMS D
32.768KHZ 47B6 OUT
1 1
C4701 PCH_TDO
47A6 OUT
1
R4704
1
2
1
1UF_6.3V_2
2
20K_1%_2
R4700 1 2 C4704
RTCX1 1 2
2
1K_5%_2 R4739 R4741 R4743
TP4705
1
1 18PF_50V_2 RSC_0402_DY RSC_0402_DY RSC_0402_DY
2
2
TP30
1UF_6.3V_2
C4702
1
1M_5%_2
1UF_6.3V_2
C4700
R4705
+
CN4700
U4700
2
-
P3V3_RTC A20 RTCX1 FWH0/LAD0 C38 LPC_3S_AD<0> 21E3 27C3

LOTES_AAA_BAT_063_P02_A_2P BI
FWH1/LAD1 A38 LPC_3S_AD<1> 21E3 27C3
BI
2
2
LPC_3S_AD<2> P3V3S
1
C20 RTCX2 FWH2/LAD2 B37 21E3 27C3

BI
FWH3/LAD3 C37 LPC_3S_AD<3> 21E3 27C3
R4707 BI
1
D20
RTC
RTCRST#
LPC
330K_5%_3 FWH4/LFRAME# D36 LPC_3S_FRAME# 21E3 27C3
OUT
G22 SRTCRST#
E36 R4744
2
R4706 LDRQ0#
K22 K36 10K_5%_2
0_5%_2_DY INTRUDER# LDRQ1#/GPIO23
1 2
2
C17 INTVRMEN SERIRQ V5 PCI_3S_SERIRQ 21E3 27B7
C BI C
INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE STRAPPING
1:ENABLE INTERNAL VRS AM3
SATA0RXN
0:ENABLE EXTERNAL VRS HDA_3S_BITCLK 1 R4709 2 HDA_3S_BITCLK_R N34 AM1
24A2 HDA_BCLK SATA0RXP
BI
33_5%_2 SATA0TXN AP7
SATA 6G
HDA_3S_SYNC 1 R4711 2 HDA_3S_SYNC_R L34 AP5
24B2 BI HDA_SYNC SATA0TXP
33_5%_2
STRAPPING
24B1 PCSPKR_PCH_3 T10 SPKR SATA1RXN AM10 SATA_HDD_RX_DN 29D5
OUT IN
SATA1RXP AM8 SATA_HDD_RX_DP 29D5
R4712 IN
PCSPKR_PCH_3(NO REBOOT) 24B2 HDA_3S_RST# 1 2 HDA_3S_RST#_R K34 HDA_RST# SATA1TXN AP11 SATA_HDD_TX_DN 29D5
OUT OUT
1 : NO REBOOT ENABLED 33_5%_2 SATA1TXP AP10 SATA_HDD_TX_DP 29D5
OUT
0 : (DEFAULT) NO REBOOT DISABLED
24A2 HDA_3S_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7 SATA_MINICARD_RX_DN 28C7
IN IN
IHDA
SATA2RXP AD5 SATA_MINICARD_RX_DP 28C7
IN
G34 HDA_SDIN1 SATA2TXN AH5 SATA_MINICARD_TX_DN 28C7
OUT
SATA2TXP AH4 SATA_MINICARD_TX_DP 28C7
STRAP OUT
C34 HDA_SDIN2
FLASH OVERRIDE SATA3RXN AB8

47B8 FLASH_OVERRIDE 1 R4715 2 A34 AB10
FLASH DESCRIPTOR SECURITY OVERIDE IN HDA_SDIN3 SATA3RXP
21D3 AF3
1K_5%_2 SATA3TXN
1:ENABLE AF1
SATA3TXP
0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)P3V3A HDA_3S_SDOUT 1 R4716 2 A36
24A2 OUT HDA_SDO
SATA
B SATA4RXN Y7 B
33_5%_2 STRAPPING Y5
21D3 FLASH_OVERRIDE 1 R4720 2 SATA4RXP
OUT C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
47B7
10K_5%_2_DY SATA4TXP AD1
EC_SMI N32 HDA_DOCK_RST#/GPIO13
IN
SATA5RXN Y3 SATA_ODD_RX_DN 29A7
R4718 IN
SATA5RXP Y1 SATA_ODD_RX_DP 29A7
R4714 1 2 IN
HDA_3S_SYNC_R 1 2 SATA5TXN AB3 SATA_ODD_TX_DN 29A7
OUT TP4720 OUT
RSC_0402_DY 1 PCH_TCK J3 JTAG_TCK SATA5TXP AB1 SATA_ODD_TX_DP 29A7
OUT OUT
JTAG
1K_5%_2 TP30
47D3 1 TP4721 PCH_TMS H7 Y11
HDA_3S_SYNC_R(PLL ODVR VOLTAGE) OUT JTAG_TMS SATAICOMPO P1V05S
TP30 R4747
1 : VCC VRM = 1.6V 47D3 1 TP4722 PCH_TDI K5 JTAG_TDI SATAICOMPI Y10 P1V05S_SATARCOMPO 1 2
OUT
0 : VCC VRM = 1.8V(DEFAULT) TP30 37.4_1%_2
47D3 1 TP4723 PCH_TDO H1 JTAG_TDO
OUT
TP30 SATA3RCOMPO AB12
P1V05S P3V3S
AB13 P1V05S_SATA3RCOMPO 1 R4748 2
SATA3COMPI
49.9_1%_2
1
EC_SPI_CLK T3 AH1
1 R4749 2
21D6 21C7 OUT SPI_CLK SATA3RBIAS
R4751 R4750 R4752
EC_SPI_CS0# 750_1%_2
SPI
21D6 21C8 Y14 SPI_CS0# 10K_5%_2 10K_5%_2 10K_5%_2

OUT
EC_SPI_CS1# T1
2
A 21C8 OUT SPI_CS1# A
SATALED# P3
21C7 21C6 EC_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14

OUT
21C8 21C6 EC_SPI_SO U3 SPI_MISO SATA1GP/GPIO19 P1

OUT STRAPPING
2
ITL_PANTHERPOINT_FCBGA_989P
R4734
RSC_0402_DY
INVENTEC
1
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) SMB_ALERT# 48B2

OUT
U4700 P3V3A P3V3A

22B1 PCIE_LAN_RX_DN BG34 PERN1
IN R4795 2
22B1 PCIE_LAN_RX_DP C4724 BJ34 PERP1 SMBALERT#/GPIO11 E12 1
IN
22C2 PCIE_LAN_TX_DN 1 2 C4725 PCIE_LAN_TX_C_DN AV32 PETN1 10K_5%_2 R4796
OUT 48D3 SML1ALERT# 1 2
22C2 PCIE_LAN_TX_DP 1 2 PCIE_LAN_TX_C_DP AU32 H14 PCH_3A_SMCLK 48A8 IN
SMBUS
PETP1 SMBCLK
OUT BI 10K_5%_2
0.1UF_16V_2
PCIE_WLAN_RX_DN 0.1UF_16V_2 BE34 C9 PCH_3A_SMDATA 1 R4797 2
27B7 PERN2 SMBDATA 48A8
IN BI
27B7 PCIE_WLAN_RX_DP C4726 BF34 PERP2
IN 2.2K_5%_2
27B7 PCIE_WLAN_TX_DN 1 2 C4727 PCIE_WLAN_TX_C_DN BB32 PETN2
OUT R4798
27B7 PCIE_WLAN_TX_DP 1 2 PCIE_WLAN_TX_C_DP AY32 PETP2 1 2
OUT
0.1UF_16V_2 SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH 41A8
0.1UF_16V_2 OUT 2.2K_5%_2
31C7 PCIE_USB3_RX_DN BG36 PERN3
IN 48D3 R4799
31C7 PCIE_USB3_RX_DP C4793 BJ36 PERP3 SML0CLK C8 PCH_3A_ALERT_CLK 27B3 48D2 27B3 PCH_3A_ALERT_CLK 1 2
IN OUT IN
31C7 PCIE_USB3_TX_DN 1 2 C4794 PCIE_USB3_TX_C_DN AV34 PETN3
D OUT 2.2K_5%_2
31C7 PCIE_USB3_TX_DP 1 2 PCIE_USB3_TX_C_DP AU34 PETP3 SML0DATA G12 PCH_3A_ALERT_DAT 27B3 48D2
OUT OUT 48D3 R4800 D
0.1UF_16V_2 27B3 PCH_3A_ALERT_DAT 1 2
0.1UF_16V_2 IN
BF36 PERN4
PCI-E*
2.2K_5%_2
BE36 PERP4
AY34 PETN4 SML1ALERT#/PCHHOT#/GPIO74 C13 SML1ALERT# 48D2
P3V3A IN P3V3A
2
48D7 R4775 BB34 PETP4 48D3 SML1_CLK
22C5 CLKREQ_LAN# 1 2 48D8 R4773 BI
OUT 22C5 CLKREQ_LAN# 1 2 SML1CLK/GPIO58 E14 SML1_CLK 48D2
48C7 10K_5%_2_DY OUT OUT Q4702
48C7 BG37
S
PERN5
48D7 10K_5%_2 BH37 M16 SML1_DATA
CLKREQ_WLAN# 1 R4776 2 P3V3S PERP5 SML1DATA/GPIO75
OUT 48C2 G
27C7 1
OUT AY36 PETN5
48B7 10K_5%_2_DY 48D8 R4772
D
27C7 CLKREQ_WLAN# 1 2 BB36 PETP5
OUT SSM3K7002FU_DY
48B7 10K_5%_2 EC_SMB3_CLK
BI
3
BJ38 PERN6
BG38 PERP6
AU36 PETN6 CL_CLK1 M7
CLOCK TERMINATION FOR FICM AV36 PETP6
2
48D3 SML1_DATA
STUFF FOR INTEGRATED CLK BI
BG40 T11 Q4703
Controller
PERN7 CL_DATA1
BJ40
Link
S
PERP7
R4777 AY40 PETN7
48B3 CLKIN_DMI_PCH_DN 1 2 G 1
IN BB40 PETP7 CL_RST1# P10
P3V3A
10K_5%_2 R4753
D
48C3 CLKREQ_GPU# 1 2 SSM3K7002FU_DY
BE38 PERN8 OUT EC_SMB3_DATA
R4778 BI
3
C BC38 PERP8 10K_5%_2 C
48B3 CLKIN_DMI_PCH_DP 1 2
IN AW38 PETN8
10K_5%_2 AY38 PETP8
R4779 M10 CLKREQ_GPU#

PEG_A_CLKRQ#/GPIO47 48C3
48B3 CLKIN_BUF_DOT96_DN 1 2 OUT
IN 22C2 CLK_PCIE_LAN_DN Y40 CLKOUT_PCIE0N
10K_5%_2 OUT
22C2 CLK_PCIE_LAN_DP Y39 CLKOUT_PCIE0P
OUT
CLKOUT_PEG_A_N AB37 CLK_PEG_REF_DN 57B6
R4780 48D8 OUT
22C5 CLKREQ_LAN# J2 PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P AB38 CLK_PEG_REF_DP 57B6
48B3 CLKIN_BUF_DOT96_DP 1 2 IN OUT
IN 48D7 XTAL25_OUT 48A3
10K_5%_2 OUT
1
27C7 CLK_PCIE_WLAN_DN AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLK_DMI_PCH_DN 41D2
R4781 OUT OUT
27C7 CLK_PCIE_WLAN_DP AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_DMI_PCH_DP 41D2
48A3 CLKIN_PCH14 1 2 OUT OUT R4801
IN
10K_5%_2 48D8 1M_5%_2
27C7 CLKREQ_WLAN# M1 PCIECLKRQ1#/GPIO18
IN
48D7 CLKOUT_DP_N AM12
X4701
2
R4782 AM13
CLKOUT_DP_P
48B3 CLKIN_SATA1_DP 1 2 1 2 XTAL25_IN 48A3
IN 31C7 CLK_PCIE_USB3_DN AA48 CLKOUT_PCIE2N OUT
10K_5%_2 OUT
31C7 CLK_PCIE_USB3_DP AA47 CLKOUT_PCIE2P
OUT 25MHZ
CLOCKS
BF18 CLKIN_DMI_PCH_DN
1
CLKIN_DMI_N 48C8
IN
1
R4783 CLKREQ_USB3# V10 BE18 CLKIN_DMI_PCH_DP
31B8 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P 48C8
48B3 CLKIN_SATA1_DN 1 2 IN IN C4729
IN 31C7
C4728 18PF_50V_2
10K_5%_2 R4837
B TP24 1 Y37 BJ30 1 2 18PF_50V_2 B
CLKOUT_PCIE3N CLKIN_GND1_N
P3V3A TP4703
TP24 1 Y36 BG30
2
CLKOUT_PCIE3P CLKIN_GND1_P
2
TP4704
R4789 10K_5%_2
1 2 A8 PCIECLKRQ3#/GPIO25
10K_5%_2_DY CLKIN_DOT_96N G24 CLKIN_BUF_DOT96_DN 48C8

IN
CLKIN_DOT_96P E24 CLKIN_BUF_DOT96_DP 48C8
IN
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
R4790 CLKIN_SATA_N AK7 CLKIN_SATA1_DN 48B8

IN
1 2 L12 PCIECLKRQ4#/GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA1_DP 48B8
P3V3S P3V3A IN B500
10K_5%_2_DY 48D3 SMB_ALERT# 1 2
P5V0S IN
V45 K45 CLKIN_PCH14 PASSWORD_0805
CLKOUT_PCIE5N REFCLK14IN 48B8
IN
V46 CLKOUT_PCIE5P
1
2.2K_5%_2 R4791
R4784 R4785 1 2 L14 PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK H45 CLKIN_PCI_FB 51A7
R4787 IN
2.2K_5%_2 10K_5%_2_DY
2.2K_5%_2
R4786
2.2K_5%_2 AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25_IN 48B1
OUT
2
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 XTAL25_OUT 48C1

OUT
PCH_3S_SMCLK R4792
3
38C8 P1V05S
BI 1 2 E6 PEG_B_CLKRQ#/GPIO56
39C8 Q4700
10K_5%_2_DY R4802
D
XCLK_RCOMP Y47 1 2
A G 1 A
V40 CLKOUT_PCIE6N 90.9_1%_2
V42
S
CLKOUT_PCIE6P
PCH_3A_SMCLK R4793 CLOSE TO PCH
48D3
BI SSM3K7002BFU 1 2 T13 PCIECLKRQ6#/GPIO45
2
10K_5%_2_DY TP24
V38 CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 K43 1
PCH_3A_SMDATA
3
TP4700
FLEX CLOCKS
48D3
BI V37 CLKOUT_PCIE7P
Q4701 TP24
R4794 CLKOUTFLEX1/GPIO65 F47 1
D
TP4701
1 2 K12 PCIECLKRQ7#/GPIO46
G 1 TP24
10K_5%_2_DY CLKOUTFLEX2/GPIO66 H47 1
AK14
TP4702
INVENTEC
S
CLKOUT_ITPXDP_N
AK13 CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49
38C8 PCH_3S_SMDATA SSM3K7002BFU
BI
39C8
2
TITLE
ITL_PANTHERPOINT_FCBGA_989P MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE

U4700
HIGH-ENABLED(DEFAULT)
42D7 DMI_RX0_DN BC24 DMI0RXN FDI_RXN0 BJ14 FDI_TX0_DN 42C7 LOW-DISABLED
IN IN
D 42D7 DMI_RX1_DN BE20 DMI1RXN FDI_RXN1 AY14 FDI_TX1_DN 42C7
IN IN
42D7 DMI_RX2_DN BG18 DMI2RXN FDI_RXN2 BE14 FDI_TX2_DN 42C7 D
IN IN
42D7 DMI_RX3_DN BG20 DMI3RXN FDI_RXN3 BH13 FDI_TX3_DN 42C7
IN IN
FDI_RXN4 BC12 FDI_TX4_DN 42C7 P3V3_RTC
IN
42D7 DMI_RX0_DP BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TX5_DN 42C7
IN IN
42D7 DMI_RX1_DP BC20 DMI1RXP FDI_RXN6 BG10 FDI_TX6_DN 42C7
IN IN
42C7 DMI_RX2_DP BJ18 DMI2RXP FDI_RXN7 BG9 FDI_TX7_DN 42C7
IN IN
DMI_RX3_DP
1
42C7 BJ20 DMI3RXP
IN
FDI_RXP0 BG14 FDI_TX0_DP 42C7
IN
42D7 DMI_TX0_DN AW24 DMI0TXN FDI_RXP1 BB14 FDI_TX1_DP 42C7 STRAPPING R4829
OUT IN
DMI
DMI_TX1_DN FDI_TX2_DP
FDI
42D7 AW20 DMI1TXN FDI_RXP2 BF14 42C7 330K_5%_2
OUT IN
42D7 DMI_TX2_DN BB18 DMI2TXN FDI_RXP3 BG13 FDI_TX3_DP 42C7
P1V05S OUT IN
DMI_TX3_DN AV18 BE12 FDI_TX4_DP
2
42D7 DMI3TXN FDI_RXP4 42C7
OUT IN
FDI_RXP5 BG12 FDI_TX5_DP 42C7
IN
42D7 DMI_TX0_DP AY24 DMI0TXP FDI_RXP6 BJ10 FDI_TX6_DP 42C7
OUT IN
DMI_TX1_DP FDI_TX7_DP
1
42D7 AY20 DMI1TXP FDI_RXP7 BH9 42B7
OUT IN
1
42D7 DMI_TX2_DP AY18 DMI2TXP
R4812 OUT
42D7 DMI_TX3_DP AU18 DMI3TXP
OUT R4830
49.9_1%_2 FDI_INT AW16 FDI_INT 42B7
OUT 330K_5%_2_DY
BJ24 AV12 FDI_FSYNC0
2
DMI_ZCOMP FDI_FSYNC0 42B7

OUT
2
BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 42B7
OUT
R4814
C 1 2 BH21 AV14 FDI_LSYNC0 C
DMI2RBIAS FDI_LSYNC0 42B7
OUT
750_1%_2 FDI_LSYNC1 BB10 FDI_LSYNC1 42B7

P3V3S OUT
P3V3A
1
DSWVRMEN A18
1
R4832
R4815 STRAPPING
R4816
10K_5%_2 SUSACK# 1 2 C12 E22 1 R4831 2 RSMRST# 1K_5%_2_DY
IN SUSACK# DPWROK
IN 21D1 21D3 49B7
0_5%_2
2
0_5%_2_DY
2
41C1 SYS_RESET# K3 SYS_RESET# WAKE# B9 PCIE_WAKE# 22B5 27C7 31C6 49A5

IN IN
40B4 P3V3_LDO
11A4 PVCORE_PG P12 SYS_PWROK CLKRUN#/GPIO32 N3 PCI_3S_CLKRUN# 21E3 49A5
System Power Management

IN IN
11C7
1
PCH_PWROK
21B6 L22 PWROK SUS_STAT#/GPIO61 G8
49A6 IN R4883
10K_5%_2_DY
L10 APWROK SUSCLK/GPIO62 N14 EC_32KHZ 21B6
P3V3_LDO
OUT
2
B SLP_S5_3R B
P3V3A OUT
PM_DRAM_PWRGD SLP_S5#_3R
3
41C7 B13 DRAMPWROK SLP_S5#/GPIO63 D10 14D2 21D3
OUT OUT
Q4713
1
1
D
49C2
21D1 RSMRST# C21 RSMRST# SLP_S4# H4 1 G R4834
IN
21D3
R4820 10K_5%_2
S
10K_5%_2_DY SUS_PWR_ACK
SLP_S3#_IC_3R
2
49A5 K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 SSM3K7002FU_DY

OUT SLP_S3_3R
2
2
2
D4706 OUT 15A4
NC
3
15B8
16A7
21D6 EC_PWRSW# 3 1 E20 PWRBTN# INT. PU 20K SLP_A# G10 Q4714 15B4
IN
D
1 G
ACPRESENT SLP_SUS#
2
BAT54_30V_0.2A 21D6 H20 ACPRESENT/GPIO31 INT. PD 20K SLP_SUS# G16

IN OUT
S
D4707 49A5
NC
SSM3K7002BFU
LOW_BAT#_3 3 1 E10 AP14 H_PM_SYNC
2
21D6 BATLOW#/GPIO72 INT. PU 20K PMSYNCH 41C5
IN BI
P3V3A
BAT54_30V_0.2A 49A5 PM_RI# A10 RI# SLP_LAN#/GPIO29 K14
IN
P3V3A
5
U4704
R4822 P3V3A
+
A 1 A
1 2
4 SLP_S3#_3R 13A2 13D2 14A6
OUT
ACPRESENT 14B8 14D2 21D6
45D3
2
49A6 21D6 R4824 1 2 10K_5%_2 2
8.2K_5%_2 IN
-
PCH_PWROK SUS_PWR_ACK 1 2 R4710
21B6 49B7 R4825 10K_5%_2 TC7SZ08FU
IN IN
3
49B7
1
PM_RI# 1 2 100K_5%_2
49A6
IN R4826 10K_5%_2
1
R4823
31C6 22B5 PCIE_WAKE# R4827 1 2 10K_5%_2
10K_5%_2 IN
49B3 27C7
INVENTEC
2
P3V3S
TITLE
PCI_3S_CLKRUN# 1 2 8.2K_5%_2 Block Diagram
49B3 21E3
IN R4828
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S
1
D R4855
D
100K_5%_2
2
U4700
1
21E7 PCH_LCM_BKLTEN J47 L_BKLTEN SDVO_TVCLKINN AP43

OUT
R4856 R4857 34D7 PCH_LCM_VDDEN M45 L_VDD_EN SDVO_TVCLKINP AP45
OUT
2.2K_5%_2 2.2K_5%_2
34B5 PCH_INV_PWM_3 P45 L_BKLTCTL SDVO_STALLN AM42
OUT
SDVO_STALLP AM40
2
34C5 PCH_LVDS_DDCCLK T40 L_DDC_CLK

OUT
34C5 PCH_LVDS_DDCDATA K47 L_DDC_DATA SDVO_INTN AP39
OUT
SDVO_INTP AP40
T45 L_CTRL_CLK
P39 L_CTRL_DATA
WHEN 1- LVDS IS DETECTED

R4858
PCH_LVDS_DDCDATA - LVDS DETECT 1 2 AF37 LVD_IBG SDVO_CTRLCLK P38
AF36 LVD_VBG SDVO_CTRLDATA M39
2.37K_1%_2
HIGH-LVDS ENABLED AE48 LVD_VREFH
LVDS
AE47 LVD_VREFL DDPB_AUXN AT49
LOW-LVDS DISABLED (DEFAULT) AT47
DDPB_AUXP
DDPB_HPD AT40
C PCH_LVDS_TXCL_DN AK39 C
34B8 OUT LVDSA_CLK#
34B8 PCH_LVDS_TXCL_DP AK40 LVDSA_CLK DDPB_0N AV42

OUT
DDPB_0P AV40
34B8 PCH_LVDS_TXDL0_DN AN48 LVDSA_DATA#0 DDPB_1N AV45
OUT
34B8 PCH_LVDS_TXDL1_DN AM47 LVDSA_DATA#1 DDPB_1P AV46
OUT
34B8 PCH_LVDS_TXDL2_DN AK47 LVDSA_DATA#2 DDPB_2N AU48
OUT
AJ48 LVDSA_DATA#3 DDPB_2P AU47
DDPB_3N AV47
Digital Display Interface

34B8 PCH_LVDS_TXDL0_DP AN47 LVDSA_DATA0 DDPB_3P AV49
OUT
34B8 PCH_LVDS_TXDL1_DP AM49 LVDSA_DATA1
OUT
34B8 PCH_LVDS_TXDL2_DP AK49 LVDSA_DATA2
OUT
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 PCH_HDMI_DDCCLK 36D8
BI
DDPC_CTRLDATA P42 PCH_HDMI_DDCDATA 36D8
BI
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38 PCH_HPDET 36B5
IN
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47 PCH_HDMI_TX2_DN 36A5
OUT
AF45 LVDSB_DATA#3 DDPC_0P AY49 PCH_HDMI_TX2_DP 36A5
OUT
DDPC_1N AY43 PCH_HDMI_TX1_DN 36A5
OUT
B AH43 LVDSB_DATA0 DDPC_1P AY45 PCH_HDMI_TX1_DP 36A5 B
OUT
AH49 LVDSB_DATA1 DDPC_2N BA47 PCH_HDMI_TX0_DN 36A5
OUT
AF47 LVDSB_DATA2 DDPC_2P BA48 PCH_HDMI_TX0_DP 36A5
OUT
AF43 LVDSB_DATA3 DDPC_3N BB47 PCH_HDMI_TXC_DN 36A5
OUT
DDPC_3P BB49 PCH_HDMI_TXC_DP 36A5
OUT
35D8 PCH_CRTB N48 CRT_BLUE DDPD_CTRLCLK M43

OUT
PCH_CRTG P49 M36
CRT
35D8 OUT CRT_GREEN DDPD_CTRLDATA
35D8 PCH_CRTR T49 CRT_RED

OUT
R4859 AT45
DDPD_AUXN
1 2
35A2 PCH_CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
OUT
35A2 PCH_CRT_DDCDATA M40 CRT_DDC_DATA DDPD_HPD BH41
150_1%_2 OUT
R4860 BB43
DDPD_0N
1 2
35B2 PCH_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
OUT
35B2 PCH_CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
150_1%_2 OUT
DDPD_1P BE44
R4861 DDPD_2N BF42
1 2 T43 DAC_IREF DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
150_1%_2 DDPD_3P BG42
1
A R4862 ITL_PANTHERPOINT_FCBGA_989P A
1K_1%_2
2
CLOSE TO PCH
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U4700
RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25 TP3
BJ16 TP4 RSVD5 AT10
BG16 TP5 RSVD6 BC8
GPIO19 AH38
GPIO51 BOOT BIOS
TP6
AH37 TP7 RSVD7 AU2
BBS_BIT1 BBS_BIT0
DESTINATION AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3
0 1 RESERVED(NAND) C18 AT1
TP10 RSVD10
N30 TP11 RSVD11 AY3
1 0 ------ H3 AT5
TP12 RSVD12
AH12 TP13 RSVD13 AV3
1 1 SPI (DEFAULT) AM4 AV1
D
NVRAM
TP14 RSVD14
AM5 TP15 RSVD15 BB1 D
0 0 LPC Y13 BA3
RSVD
TP16 RSVD16
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8
RSVD21 BD4
P3V3S RSVD22 BF6
B21 TP21 RSVD23 AV5

R4874 1 2 8.2K_5%_2 PCI_3S_INTA# 51B6 M20 TP22
BI
AY16 TP23
1 2 PCI_3S_INTB# ROUTE WITH 90 OHMS IMPEDANCE BG46 AV10
R4875 8.2K_5%_2 BI 51B6 TP24 RSVD24
TOTAL LENGTH NO LONGER THAN 11 INCHES

R4876 1 2 8.2K_5%_2 PCI_3S_INTC# 51B6 RSVD25 AT8
BI
R4877 1 2 8.2K_5%_2 PCI_3S_INTD# 51B6 32D7 USB3_PCH_RX1_DN BE28 USB3RN1 RSVD26 AY5
BI BI
33B5 USB3_PCH_RX2_DN BC30 USB3RN2 RSVD27 BA2
BI
R4878 1 2 8.2K_5%_2 RUNSCI0#_3 21E3 BE32 USB3RN3
IN 52D6
BJ32 USB3RN4 RSVD28 AT12 NOTE:
32D7 USB3_PCH_RX1_DP BC28 USB3RP1 RSVD29 BF3
BI USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2
33B5 USB3_PCH_RX2_DP BE30 USB3RP2
BI
R4880 1 2 10K_5%_2 DGPU_HOLD_RST# 51B6
57A6 BF32 USB3RP3
C IN C
BG32 USB3RP4 USBP0N C24 USB_P0_DN 32C8 32B8
BI P0.P1 RESERVER FOR USB3.0
R4881 1 2 10K_5%_2 PCI_3S_REQ2# 51B6 32D7 USB3_PCH_TX1_DN AV26 USB3TN1 DEBUG PORT USBP0P A24 USB_P0_DP 32C8 32B8
IN BI BI
33B5 USB3_PCH_TX2_DN BB26 USB3TN2 USBP1N C25 USB_P1_DN 33C5
BI BI
R4882 1 2 10K_5%_2 DGPU_PWR_EN# 16A3
51B6 AU28 USB3TN3 USBP1P B25 USB_P1_DP 33C5
IN BI
AY30 USB3TN4 USBP2N C26 USB_P2_DN 30C5
66C6
BI
32D7 USB3_PCH_TX1_DP AU26 USB3TP1 USBP2P A26 USB_P2_DP 66C6
30C5
BI BI
33B5 USB3_PCH_TX2_DP AY26 USB3TP2 USBP3N K28
BI
R4838 1 2 10K_5%_2 SATA_ODD_DA# 29A5 51B6 AV28 USB3TP3 USBP3P H28
IN
AW30 USB3TP4 USBP4N E28
R4956 1 2 10K_5%_2 PCI_3S_PIRQG# 51B6 USBP4P D28
IN
USBP5N C28
R4879 1 2 10K_5%_2 PCI_3S_PIRQH# 51B6 USBP5P A28
IN
USBP6N C29
BBS STRAPING USBP6P B29
51D7 PCI_3S_INTA# K40 PIRQA# USBP7N N28
BI
51C7 PCI_3S_INTB# K38 PIRQB# USBP7P M28
BBS_BIT1 BI
51C7 PCI_3S_INTC# H38 PIRQC# USBP8N L30 USB_CR_DN 26A8
BI BI CARD READER
PCI
51C7 PCI_3S_INTD# G38 PIRQD# USBP8P K30 USB_CR_DP 26A8
BI BI
STP_A16OVR G30 USB_WLAN_DN
USB
USBP9N 27B3
BI WLAN
2
51C7
57A6 DGPU_HOLD_RST# C46 REQ1#/GPIO50 USBP9P E30 USB_WLAN_DP 27B3
OUT BI
51C7 PCI_3S_REQ2# C44 REQ2#/GPIO52 USBP10N C30 USB_CAM_DN 34B3
R4885 R4886 OUT BI WEBCAM
51C7
16A3 DGPU_PWR_EN# E40 REQ3#/GPIO54 USBP10P A30 USB_CAM_DP 34B3
OUT BI
B 1K_5%_2_DY 1K_5%_2_DY USBP11N L32 B
D47 GNT1#/GPIO51 USBP11P K32
1
E42 GNT2#/GPIO53 USBP12N G32

F46 GNT3#/GPIO55 USBP12P E32
USED AS GPIO ONLY. USBP13N C32 USB_3G_DN 28C3
INT. PU 20K BI 3G
LOW=A16 SWAP OVERRIDE USBP13P A32 USB_3G_DP 28C3
31C7 BI
31C6 USB3_SMI# G42 PIRQE#/GPIO2
STP_A16OVR BI
29A5 SATA_ODD_DA# G40 PIRQF#/GPIO3 R4835
BI
TOP-BLOCK SWAP OVERRIDE 51C7 PCI_3S_PIRQG# C42 PIRQG#/GPIO4 USBRBIAS# C33 1 2
51C7 BI
PCI_3S_PIRQH# D44 PIRQH#/GPIO5
HIGH=DEFAULT 51B7 BI
P3V3A 22.6_1%_3
USBRBIAS B33
1 R4887 2 P3V3A_PME# K10 CLOSE TO PCH
PME# INT. PU 20K
PLT_RST# 10K_5%_2_DY C6 A14 MACHINE_ID0

41C7 31C6 PLTRST# OC0#/GPIO59 51A4 51A5
36B2 BI IN
OC1#/GPIO40 K20 MACHINE_ID1 51A4 51A5
IN
OC2#/GPIO41 B17 MACHINE_ID2 51A4 51A5
IN
P3V3A 21E3 CLK_KBPCI R4889 1 2 22_5%_2 CLK_KBPCI_R H49 CLKOUT_PCI0 OC3#/GPIO42 C16 MACHINE_ID3 51A4 51A5
OUT IN
48A3 CLKIN_PCI_FB R4890 1 2 22_5%_2 CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 MACHINE_ID4 51A4 51A5
OUT IN
J48 CLKOUT_PCI2 OC5#/GPIO9 A16 MACHINE_ID5 51A4 51A5
TP24 IN
MACHINE_ID6
5
1 K42 CLKOUT_PCI3 OC6#/GPIO10 D14 51A4 51A5

TP4717 IN
U4705 27C7 CLK_PCI_DEBUGR4891 1 2 22_5%_2 H40 CLKOUT_PCI4 OC7#/GPIO14 C14 MACHINE_ID1_DB 51A4 51A5
OUT IN
CLK_PCI_DEBUG_R
+
1
28C3 27C3 21E3 BUF_PLT_RST# 4 ITL_PANTHERPOINT_FCBGA_989P
BI TO BE USED AS GPIO
57A6
2
A 27C7 2 A
-
R4888 TC7SZ08FU
3
100K_5%_2 P3V3A
51A5
1
51A2 MACHINE_ID0 R4900 1 2 10K_5%_2_DY

51A4 51A2 MACHINE_ID0 R4892 1 2 10K_5%_2_DY OUT
OUT MACHINE_ID1 R4901 1 2 10K_5%_2_DY
51A4 51A2 MACHINE_ID1 R4893 1 2 10K_5%_2_DY 51A5 OUT
OUT 51A2 MACHINE_ID2 R4902 1 2 10K_5%_2_DY
MACHINE_ID4 OUT
51A4
51A4
51A4
51A2
51A2
51A2
OUT
OUT
MACHINE_ID5
MACHINE_ID6
R4896
R4897
R4898
1
1
1
2 10K_5%_2_DY
2 10K_5%_2_DY
2 10K_5%_2_DY
51A5
51A2
OUT
OUT
MACHINE_ID5
MACHINE_ID6
R4905
R4906
1
1
2 10K_5%_2_DY
2 10K_5%_2_DY INVENTEC
OUT 51A2 MACHINE_ID1_DB R4907 1 2 10K_5%_2_DY
51A4 51A2 MACHINE_ID1_DB R4899 1 2 10K_5%_2_DY OUT
OUT 51A5 TITLE
Block Diagram
NOTE:10K_5%(60130B1030ZT)
NOTE:10K_5%(60130B1030ZT)
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3A
R4927 1 2 10K_5%_2_DY PCH_GPIO6 52D6

OUT
R4908 1 2 1K_5%_2_DY PCH_GPIO15 52C6
OUT
R4909 1 2 10K_5%_2 PCH_GPIO8 52D6
P3V3S
OUT
R4910 1 2 10K_5%_2_DY PCH_GPIO12 52C6
OUT
1 R4721 2
D
33K_5%_2_DY
D
P3V3S U4700 P3V3S
SATA_ODD_PWREN
MSATA_DET T7 BMBUSY#/GPIO0 TACH4/GPIO68 C40 29B8
IN OUT
R4916 1 2 10K_5%_2_DY PCH_GPIO22 52C6 52C7 28C2 3G_ON# A42 TACH1/GPIO1 TACH5/GPIO69 B41 R4724 1 2 10K_5%_2_DY
OUT IN
R4917 1 2 10K_5%_2_DY PCH_GPIO38 52B6
OUT 52D7 PCH_GPIO6 H36 TACH2/GPIO6 TACH6/GPIO70 C41 R4725 1 2 10K_5%_2_DY
IN
51C7 21E3 RUNSCI0#_3 E38 TACH3/GPIO7 TACH7/GPIO71 A40 R4726 1 2 10K_5%_2_DY

R4915 1 2 10K_5%_2_DY PCH_GPIO16 52C6 IN
OUT
INT. PU 20K
R4919 1 2 10K_5%_2 SATA_ODD_PRSNT# 29A5 52B6 52D7 PCH_GPIO8 C10 GPIO8 INT. PU 20K
OUT OUT
52D7 PCH_GPIO12 C4 LAN_PHY_PWR_CTRL/GPIO12

OUT
INT. PD 20K
52D7 PCH_GPIO15 G2 GPIO15 A20GATE P4 EC_3S_A20GATE 21E2
OUT STRAPPING IN
AU16 PCH_PECI 1 R4940 2 H_PECI
PECI
OUT 21A6 41D5
52D7 PCH_GPIO16 U2 SATA4GP/GPIO16 0_5%_2_DY
OUT
R4727 1 2 10K_5%_2_DY PCH_GPIO22 52C6 52D7 RCIN# P5 KBRST# 21D2
OUT IN
GPIO
INT. PU 20K
CPU/MISC
13C8 13B2 DGPU_PWRGD D40 TACH0/GPIO17 PROCPWRGD AY11 H_CPUPWRGD 41C5
IN OUT
52D7 52C7 PCH_GPIO22 T5 SCLOCK/GPIO22 THRMTRIP# AY10 THRMTRIP#_R

C OUT C
P1V05S P1V05S
KBLED_ID E8 GPIO24 INIT3_3V# T14
OUT
1
R4928 1 2 10K_5%_2_DY E16 GPIO27 INT.PD 20K
1
STRAPPING
DF_TVS AY1
P3V3S 52A7 PLL_ODVR_EN STRAPPING
P8 GPIO28 INT. PU 20K R4942 R4944
OUT
TS_VSS1 AH8 56_5%_2 56_5%_2
R4929 1 2 10K_5%_2_DY K1 STP_PCI#/GPIO34
GFX_CRB_DET(GPIO39) AK11
2
TS_VSS2 R4941 R4943
2
R4930 1 2 10K_5%_2_DY K4 GPIO35 1 2 1 2 PM_THRMTRIP# 40A4
IN
INTERNAL GFX :100K PD TS_VSS3 AH10 41D5
1 2 10K_5%_2_DY V8 0_5%_2_DY
EXTERNAL GFX :10K PU R4932 SATA2GP/GPIO36 390_5%_2
INT. PD 20K TS_VSS4 AK10
PCH_GPIO37STRAPPING M5 BOTH THESE SHOULD BE CLOSE TO PCH
P3V3S 52B7 SATA3GP/GPIO37
OUT
NC_1 P37
52D7 PCH_GPIO38 N2 SLOAD/GPIO38
R4920 1 210K_5%_2_DY PCH_GPIO39 52B6 OUT NV_CLE 41D6
OUT OUT
PCH_GPIO39STRAPPING M3 FOLLOW EDS1.0
R4926 1 2100K_5%_2 52B7 OUT SDATAOUT0/GPIO39
STRAPPING
1 TP24 V13 SDATAOUT1/GPIO48 VSS_NCTF_15 BG2
TP4907
52D7 29A5 SATA_ODD_PRSNT# V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 BG48

OUT
B B
27C7 27B7 BTIFON# D6 GPIO57 VSS_NCTF_17 BH3
OUT
FDI_OVRVLTG(GPIO37) VSS_NCTF_18 BH47
LOW- TX,RXTERMINATED TO SAME VOLTAGE A4 VSS_NCTF_1 VSS_NCTF_19 BJ4
(DC COUPLING MODE) DEFAULT

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44
P3V3S A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
R4934 1 2
1K_5%_2_DY PCH_GPIO37 52B6 A46 VSS_NCTF_4 VSS_NCTF_22 BJ46
OUT
NCTF
R4935 1 2100K_5%_2
B3 VSS_NCTF_7 VSS_NCTF_25 C2
B47 VSS_NCTF_8 VSS_NCTF_26 C48
BD1 VSS_NCTF_9 VSS_NCTF_27 D1

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
A HIGH-ENABLED (DEFAULT) A
LOW-DISABLED BE1 VSS_NCTF_11 VSS_NCTF_29 E1
BE49 E49
P3V3A VSS_NCTF_12 VSS_NCTF_30
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
1 R4950 2 PLL_ODVR_EN
IN 52C6 BF49 VSS_NCTF_14 VSS_NCTF_32 F49
10K_5%_2
R4936 ITL_PANTHERPOINT_FCBGA_989P
1
10K_5%_2_DY
2
INVENTEC
TITLE
STRAP
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P3V3S
1.3A U4700 L4700
AA23 U48 15MIL P3V3S_VCCADAC 1 2
VCCCORE[1]
POWER VCCADAC
1
1
1
AC23 VCCCORE[2] FBM_11_160808_121T
AD21 C4784
VCCCORE[3] C4782 C4783
CRT
1
1
AD23 VCCCORE[4] VSSADAC U47
C4772 C4773 C4774 C4775 AF21 0.1UF_16V_2
VCC CORE
VCCCORE[5]
AF23 10UF_6.3V_3 0.01UF_50V_2
VCCCORE[6] P3V3S
2
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 AG21
2
D VCCCORE[7]
AG23 VCCCORE[8] D
2
AG24 VCCCORE[9] VCCALVDS AK36 15MIL
AG26 VCCCORE[10]
AG27 AK37
VCCCORE[11] VSSALVDS P1V8S
AG29 VCCCORE[12]
AJ23 VCCCORE[13] L4701
15MIL
LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 P1V8S_VCCTX_LVDS 1 2
1
AJ27 VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 C4785 C4786 C4787 FBM_11_160808_121T
AJ31 VCCCORE[17]
AP36
P1V05S VCCTX_LVDS[3]
0.01UF_50V_2 0.01UF_50V_2 22UF_6.3V_5
AP37
2
VCCTX_LVDS[4]
20MIL AN19
P1V05S VCCIO[28]
R4945
1 2 P1V05S_VCCAPLLEXP BJ22 P3V3S
P1V05S VCCAPLLEXP
15MIL
HVCMOS
0_5%_2_DY VCC3_3[6] V33
3A AN16 VCCIO[15]
C4788
1 2
AN17 VCCIO[16]
VCC3_3[7] V34
1
1
C 0.1UF_16V_2 C
C4777 C4778 C4779 C4780
C4776
AN21 VCCIO[17]
10UF_6.3V_3 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 P1V5S_VCCAFDI_VRM
AN26 VCCIO[18]
2
2
VCCVRM[3] AT16 15MIL
AN27 VCCIO[19]
P1V05S
VCCIO
AP21 VCCIO[20]
DMI
VCCDMI[1] AT20 15MIL
AP23 C4789
VCCIO[21] P1V05S
1 2
AP24 VCCIO[22]
VCCCLKDMI AB36 15MIL 1UF_6.3V_2

P3V3S AP26 VCCIO[23]
C4790
1 2
AT24 VCCIO[24]
1UF_6.3V_2_DY P1V8S
1
AN33 VCCIO[25]
VCCDFTERM[1] AG16 15MIL

C4781 AN34 VCCIO[26]
1
B B
0.1UF_16V_2 15MIL BH29 AG17
VCC3_3[3] VCCDFTERM[2] C4791
2
P1V5S_VCCAFDI_VRM
AJ16 0.1UF_16V_2
VCCDFTERM[3] P3V3AL P3V3A
NAND / SPI
2
15MIL AP16 VCCVRM[2]
P1V05S VCCDFTERM[4] AJ17
2
R4946
1 2 P1V05S_VCCAFDIPLL BG6 R4947
VccAFDIPLL R4948
P1V05S
FDI
0_5%_2_DY 0_5%_2
0_5%_2_DY
P1V05S 20MIL AP17 VCCIO[27]
1
VCCSPI V1 15MIL
1
15MIL AU20 VCCDMI[2]
C4792
1UF_6.3V_2
2
A A
P1V5S_VCCAFDI_VRM P1V5S
R4949
1 2
40MIL
0_5%_3
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P1V05S P1V05S
P3V3A R4865
U4700
3A REFERENCE 4700~4949(PCH)
1 2 P1V05S_VCCACLKAD49 N26
P3V3S 15MIL
VCCACLK
POWER VCCIO[29]
1
0_5%_2_DY
C4803 VCCIO[30] P26
2 1 1 R4866 2T16 C4829
VCCDSW3_3
0_5%_2 VCCIO[31] P28 1UF_6.3V_2
1
0.1UF_16V_2
C4804
2 1 V12 T27
2
C4801 C4802 DCPSUSBYP VCCIO[32]
P3V3A
2
0.1UF_16V_2 10UF_6.3V_3 0.1UF_16V_2_DY
T29
VCCIO[33] P3V3A
20MIL T38 VCC3_3[5] D4708
NC
2
2
P1V05S BAT54_30V_0.2A
T23 10MIL 3 1
VCCSUS3_3[7]
P1V05S 1 R4867 2 P1V05S_VCCAPLLDMI2 BH23 VCCAPLLDMI2
T24 C4830 P5V0A
USB
0_5%_2_DY VCCSUS3_3[8]
1 2
20MIL AL29 VCCIO[14]
VCCSUS3_3[9] V23 0.1UF_16V_2

D R4869 1 210_5%_5
C4805
1 2 AL24 V24 P3V3A D
DCPSUS[3] VCCSUS3_3[10]
P1V05S 1UF_6.3V_2_DY
P24 10MIL
VCCSUS3_3[6]
C4833 1 20.1UF_16V_2
C4831
1.1A AA19 VCCASW[1]
1 2 P1V05S
Clock and Miscellaneous

AA21 T26 20MIL
VCCASW[2] VCCIO[34] 0.1UF_16V_2
2
AA24 M26 V5REF_SUS 10MIL P3V3S
C4806 C4807 VCCASW[3] V5REF_SUS
NC
22UF_6.3V_5 22UF_6.3V_5
AA26 D4709 3 1BAT54_30V_0.2A
VCCASW[4] C4832
DCPSUS[4] AN23 2 1 P3V3A
2
AA27 VCCASW[5]
P5V0S
P1V05S 1UF_6.3V_2_DY
VCCSUS3_3[1] AN24 10MIL
AA29 VCCASW[6] R4870 1 2 10_5%_5
AA31 VCCASW[7]
C4834
10MIL
1
1
AC26 VCCASW[8] V5REF P34 V5REF 1 2
C4808 C4809 C4810
AC27 1UF_6.3V_2
VCCASW[9] P3V3A
1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 VCCSUS3_3[2] N20
AC29
PCI/GPIO/LPC
C VCCASW[10] C
10MIL
2
2
VCCSUS3_3[3] N22
AC31 VCCASW[11] C4835
VCCSUS3_3[4] P20 1 2
AD29 VCCASW[12]
P22 1UF_6.3V_2
P1V05S VCCSUS3_3[5]
AD31 VCCASW[13] P3V3S
L4706
1 2 P1V05S_VCCADPLLA W21 AA16 20MIL
VCCASW[14] VCC3_3[1]
1
FBM_11_160808_121T
W23 W16 C4836 1 2 0.1UF_16V_2 P3V3S
VCCASW[15] VCC3_3[8]
C4812 C4813 C4814

W24 VCCASW[16] VCC3_3[4] T34
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3 C4837 1 2 0.1UF_16V_2
W26 VCCASW[17]
1
2
C4811 W29 VCCASW[18] P3V3S

0.1UF_16V_2
W31 VCCASW[19]
VCC3_3[2] AJ2 20MIL

2
L4707 W33 VCCASW[20]

1 2 P1V05S_VCCADPLLB C4838 1 2 0.1UF_16V_2
VCCIO[5] AF13
1
B FBM_11_160808_121T
P1V05S B
N16
C4815 C4816 C4817 P1V5S_VCCAFDI_VRM DCPRTC
VCCIO[12] AH13 20MIL

C4839
22UF_6.3V_5_DY 1UF_6.3V_2 10UF_6.3V_3
15MIL Y49 VCCVRM[4] VCCIO[13] AH14 1 2
SATA
2
1UF_6.3V_2
AF14
VCCIO[6] P1V05S
15MIL BD47 VCCADPLLA L4708
AK1 P1V05S_VCCAPLLSATA 1 2
VCCAPLLSATA P1V5S_VCCAFDI_VRM
15MIL BF47 VCCADPLLB
P1V05S 0603_DY
VCCVRM[1] AF11 10MIL

20MIL AF17 VCCIO[7]
C4818 1UF_6.3V_2 AF33 VCCDIFFCLKN[1]
P1V05S
2 1 15MIL AF34 VCCDIFFCLKN[2] VCCIO[2] AC16
AG34 VCCDIFFCLKN[3]
C4819 1UF_6.3V_2
2 1 VCCIO[3] AC17 20MIL
C4840
15MIL AG33 VCCSSC VCCIO[4] AD17 1 2
C4820 1UF_6.3V_2
1UF_6.3V_2
2 1
C4821 0.1UF_16V_2 V16 DCPSST
2 1
A A
MISC
C4822 T17 T21

DCPSUS[1] VCCASW[22] P1V05S
1 2 V19
P1V05S DCPSUS[2]
1UF_6.3V_2_DY
VCCASW[23] V21 20MIL
CPU
10MIL BJ8 V_PROC_IO

1
VCCASW[21] T19
P3V3A
C4823 C4824 C4825 P3V3_RTC
RTC
HDA
INVENTEC
4.7UF_6.3V_3
0.1UF_16V_2 0.1UF_16V_2
A22 VCCRTC VCCSUSHDA P32 10MIL
1
1
2
C4841
C4826 C4827 C4828 ITL_PANTHERPOINT_FCBGA_989P
TITLE
0.1UF_16V_2 1UF_6.3V_2 0.1UF_16V_2 0.1UF_16V_2 MODEL,PROJECT,FUNCTION

Block Diagram
2
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 4700~4949(PCH) U4700

AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
U4700 AY46 K26
VSS[161] VSS[261]
H5 VSS[0]
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
AA17 VSS[1] VSS[80] AK38
B15 VSS[164] VSS[264] K7
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
AB11 VSS[6] VSS[85] AL16
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
F45 VSS[172] VSS[272] M12
BB12 VSS[173] VSS[273] P16
D AB5 VSS[11] VSS[90] AL23
BB16 VSS[174] VSS[274] M18
AB7 VSS[12] VSS[91] AL26 D
BB20 VSS[175] VSS[275] M22
AC19 VSS[13] VSS[92] AL27
BB22 VSS[176] VSS[276] M24
BB24 VSS[177] VSS[277] M30
BB28 VSS[178] VSS[278] M32
BB30 VSS[179] VSS[279] M34
BB38 VSS[180] VSS[280] M38
AC34 VSS[18] VSS[97] AM11
BB4 VSS[181] VSS[281] M4
AC48 VSS[19] VSS[98] AM14
BB46 VSS[182] VSS[282] M42
AD10 VSS[20] VSS[99] AM36
BC14 VSS[183] VSS[283] M46
AD11 VSS[21] VSS[100] AM39
BC18 VSS[184] VSS[284] M8
AD12 VSS[22] VSS[101] AM43
BC2 VSS[185] VSS[285] N18
AD13 VSS[23] VSS[102] AM45
BC22 VSS[186] VSS[286] P30
AD19 VSS[24] VSS[103] AM46
BC26 VSS[187] VSS[287] N47
AD24 VSS[25] VSS[104] AM7
BC32 VSS[188] VSS[288] P11
AD26 VSS[26] VSS[105] AN2
BC34 VSS[189] VSS[289] P18
AD27 VSS[27] VSS[106] AN29
BC36 VSS[190] VSS[290] T33
AD33 VSS[28] VSS[107] AN3
BC40 VSS[191] VSS[291] P40
AD34 VSS[29] VSS[108] AN31
BC42 VSS[192] VSS[292] P43
AD36 VSS[30] VSS[109] AP12
BC48 VSS[193] VSS[293] P47
AD37 VSS[31] VSS[110] AP19
BD46 VSS[194] VSS[294] P7
AD38 VSS[32] VSS[111] AP28
BD5 VSS[195] VSS[295] R2
AD39 VSS[33] VSS[112] AP30
BE22 VSS[196] VSS[296] R48
AD4 VSS[34] VSS[113] AP32
C BE26 VSS[197] VSS[297] T12 C
AD40 VSS[35] VSS[114] AP38
BE40 VSS[198] VSS[298] T31
BF10 VSS[199] VSS[299] T37
AD43 VSS[37] VSS[116] AP42
BF12 VSS[200] VSS[300] T4
AD45 VSS[38] VSS[117] AP46
BF16 VSS[201] VSS[301] W34
BF20 VSS[202] VSS[302] T46
AD8 VSS[40] VSS[119] AR2
BF22 VSS[203] VSS[303] T47
AE2 VSS[41] VSS[120] AR48
BF24 VSS[204] VSS[304] T8
AE3 VSS[42] VSS[121] AT11
BF26 VSS[205] VSS[305] V11
AF10 VSS[43] VSS[122] AT13
BF28 VSS[206] VSS[306] V17
AF12 VSS[44] VSS[123] AT18
BD3 VSS[207] VSS[307] V26
AD14 VSS[45] VSS[124] AT22
BF30 VSS[208] VSS[308] V27
AD16 VSS[46] VSS[125] AT26
BF38 VSS[209] VSS[309] V29
AF16 VSS[47] VSS[126] AT28
BF40 VSS[210] VSS[310] V31
AF19 VSS[48] VSS[127] AT30
BF8 VSS[211] VSS[311] V36
AF24 VSS[49] VSS[128] AT32
BG17 VSS[212] VSS[312] V39
AF26 VSS[50] VSS[129] AT34
BG21 VSS[213] VSS[313] V43
AF27 VSS[51] VSS[130] AT39
BG33 VSS[214] VSS[314] V7
AF29 VSS[52] VSS[131] AT42
BG44 VSS[215] VSS[315] W17
AF31 VSS[53] VSS[132] AT46
BG8 VSS[216] VSS[316] W19
AF38 VSS[54] VSS[133] AT7
BH11 VSS[217] VSS[317] W2
AF4 VSS[55] VSS[134] AU24
BH15 VSS[218] VSS[318] W27
AF42 VSS[56] VSS[135] AU30
BH17 VSS[219] VSS[319] W48
B AF46 VSS[57] VSS[136] AV16 B
BH19 VSS[220] VSS[320] Y12
AF5 VSS[58] VSS[137] AV20
H10 VSS[221] VSS[321] Y38
BH27 VSS[222] VSS[322] Y4
BH31 VSS[223] VSS[323] Y42
AG19 VSS[61] VSS[140] AV38
BH33 VSS[224] VSS[324] Y46
AG2 VSS[62] VSS[141] AV4
BH35 VSS[225] VSS[325] Y8
AG31 VSS[63] VSS[142] AV43
BH39 VSS[226] VSS[328] BG29
AG48 VSS[64] VSS[143] AV8
BH43 VSS[227] VSS[329] N24
AH11 VSS[65] VSS[144] AW14
BH7 VSS[228] VSS[330] AJ3
AH3 VSS[66] VSS[145] AW18
D3 VSS[229] VSS[331] AD47
D12 VSS[230] VSS[333] B43
AH39 VSS[68] VSS[147] AW22
D16 VSS[231] VSS[334] BE10
AH40 VSS[69] VSS[148] AW26
D18 VSS[232] VSS[335] BG41
AH42 VSS[70] VSS[149] AW28
D22 VSS[233] VSS[337] G14
AH46 VSS[71] VSS[150] AW32
D24 VSS[234] VSS[338] H16
D26 VSS[235] VSS[340] T36
AJ19 VSS[73] VSS[152] AW36
D30 VSS[236] VSS[342] BG22
AJ21 VSS[74] VSS[153] AW40
D32 VSS[237] VSS[343] BG24
AJ24 VSS[75] VSS[154] AW48
D34 VSS[238] VSS[344] C22
AJ33 VSS[76] VSS[155] AV11
D38 VSS[239] VSS[345] AP13
AJ34 VSS[77] VSS[156] AY12
D42 VSS[240] VSS[346] M14
AK12 VSS[78] VSS[157] AY22
D8 VSS[241] VSS[347] AP3
AK3 VSS[79] VSS[158] AY28
E18 VSS[242] VSS[348] AP1
E26 VSS[243] VSS[349] BE16
A ITL_PANTHERPOINT_FCBGA_989P G18 BC16 A
VSS[244] VSS[350]
G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26
H30
VSS[254]
VSS[255]
INVENTEC
H32 VSS[256]
H34 VSS[257]
TITLE
F3 VSS[258] MODEL,PROJECT,FUNCTION
Block Diagram
ITL_PANTHERPOINT_FCBGA_989P DOC.NUMBER REV

SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
P3V3S_DGPU
R5016 1 2 10K_5%_2 GPIO0 56D5

OUT
R5010 1 2 10K_5%_2 GPIO1 56D5
OUT
10K_5%_2
R5011 1
1
2
2 RSC_0402_DY
GPIO2
GPIO5
OUT 56D5
MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0
U5001 THAMES (6019B0917601)
R5028 OUT 56D5
1 2 RSC_0402_DY GPIO9 0 0 0 0 HYNIX

R5037 OUT 56D5
1 2 10K_5%_2 GPIO11 0 1 0 0 SAMSUNG AU24 VGA_HDMI_TXC_DP

R5014 56D5 GPIO11:MEMORY APERTURE SIZE 256M TXCAP_DPA3P 36A5
OUT OUT
F AV23 VGA_HDMI_TXC_DN F
R5030 1 210K_5%_2 VGA_CRT_HSYNC 35B2
56D3
TXCAM_DPA3N
OUT 36A5
OUT
R5031 1 210K_5%_2 VGA_CRT_VSYNC 35B2
56D3 TX0P_DPA2P AT25 VGA_HDMI_TX0_DP 36A5
OUT P1V8S_DGPU MUTI GFX OUT
10K_5%_2_DY TX0M_DPA2N AR24 VGA_HDMI_TX0_DN 36A5
R5027 2 1 GPIO22 56C5 DPA OUT
OUT
R5056 1 210K_5%_2 PWRCNTL_0 13C6 56D5 TX1P_DPA1P AU26 VGA_HDMI_TX1_DP 36A5
OUT OUT
AV25 VGA_HDMI_TX1_DN
R5017 1 210K_5%_2 PWRCNTL_1 13C6 56C5
TX1M_DPA1N
OUT 36A5
OUT
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
10K_5%_2_DY
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 VGA_HDMI_TX2_DP 36A5
OUT
2
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 VGA_HDMI_TX2_DN 36A5
OUT
R5006
R5007
R5008
R5009
AP8 DVPCNTL_0
AW8 DVPCNTL_1 TXCBP_DPB3P AR30
AR3 DVPCNTL_2 TXCBM_DPB3N AT29
PIN BASE STRAPS AR1 DVPCLK
1
MEM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31
MEM_ID1 AU3 DVPDATA_1 TX3M_DPB2N AU30
GPIO_0 TRANSMITTER POWER SAVING ENABLE 0 : 50% TX OUTPUT SWING (DEFAULT) MEM_ID2 AW3 DPB
DVPDATA_2
1 : FULL TX OUTPUT SWING MEM_ID3 AP6 AR32
DVPDATA_3 TX4P_DPB1P
AW5 DVPDATA_4 TX4M_DPB1N AT31
AU5 DVPDATA_5
GPIO_1 PCIE TRANSMITTER DE-EMPHASIS 0 : DE-EMPHASIS DISABLED (DEFAULT) AR6 AT33
DVPDATA_6 TX5P_DPB0P
1 : DE-EMPHASIS ENABLED AW6 DVPDATA_7 TX5M_DPB0N AU32
AU6 DVPDATA_8
GPIO_2 GEN1/GEN2 ENABLE 0 : GEN1 (DEFAULT) AT7 DVPDATA_9 TXCCP_DPC3P AU14

1 : GEN2 AV7 DVPDATA_10 TXCCM_DPC3N AV13
AN7 DVPDATA_11
GPIO_8 AV9 AT15

MUST BE LOW DURING RESET LEFT UNCONNECTED DVPDATA_12 TX0P_DPC2P
AT9 AR14
GPIO_21 AR10
DVPDATA_13 TX0M_DPC2N
DVPDATA_14
DPC
E AW10 DVPDATA_15 TX1P_DPC1P AU16 E
GPIO_9 0 : ENABLE (DEFAULT) AU10 DVPDATA_16 TX1M_DPC1N AV15
VGA DISABLE AP10
1 : DISABLE DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20
GPIO_[11:13] MEMORY APERTURE SIZE GPIO_13 GPIO_12 GPIO_11 MEMORY APERTURE SIZE AW12 DVPDATA_21 TXCDP_DPD3P AU20 PLACE CLOSE TO ASIC
AU12 DVPDATA_22 TXCDM_DPD3N AT19
0 0 0 128M AP12 DVPDATA_23
R5072
150_1%_2
56D3 35D8 VGA_CRTR 1 2
AT21 IN
0 0 1 TX3P_DPD2P
R5073
256M AJ21 SWAPLOCKA TX3M_DPD2N AR20
VGA_CRTG 1 150_1%_2
2
56D3 35D8
1 0 AK21 IN
0 64M SWAPLOCKB
DPD R5074
TX4P_DPD1P AU22 150_1%_2
1 1 VGA_CRTB 1 2
0 32M TX4M_DPD1N AV21 56D3 35D8
IN
I2C
TX5P_DPD0P AT23
GPIO_22 ENABLE EXTERNAL BIOS ROM DEVICE 0 : DISABLE (DEFAULT) TX5M_DPD0N AR22
1 : ENABLE 34C5 VGA_LVDS_DDCCLK AK26 SCL
BI
34C5 VGA_LVDS_DDCDATA AJ26 SDA
BI
HSYNC[1] 00 : NO AUDIO FUNCTION
AUDIO[1:0] R AD39 VGA_CRTR
OUT 35D8 56E2
VSYNC[0] 01 : AUDIO FOR DP ONLY 56F7
GENERAL PURPOSE I/O
RB AD37
GPIO0 AH20 GPIO_0
IN
10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED 56F7 GPIO1 AH18 GPIO_1 G AE36 VGA_CRTG 35D8 56E2
IN OUT
56F7 GPIO2 AN16 GPIO_2 GB AD35
11 : AUDIO FOR BOTH DP AND HDMI IN
GPU_SID AH23
56C7 GPIO_3_SMBDATA
BI
56D7 GPU_SIC AJ23 GPIO_4_SMBCLK B AF37 VGA_CRTB 35D8 56E2
BI OUT
D 56F7 GPIO5 AH17 AE38 D
IN GPIO_5_AC_BATT
DAC1
BB P1V8S_DGPU
AJ17 GPIO_6
21E7 VGA_LCM_BKLTEN AK17 GPIO_7_BLON HSYNC AC36 VGA_CRT_HSYNC 56F7

35B2
OUT OUT L5000
AJ13 GPIO_8_ROMSO VSYNC AC38 VGA_CRT_VSYNC 35B2
56F7 I=70MA TRACE WIDTH>=15MIL
P3V3S_DGPU OUT P1V8S_AVDD 2 1
56F7 GPIO9 AH15 GPIO_9_ROMSI
40B1 40A8 15D8 THRM_SHUTDWN# IN
OUT
1
AJ16 GPIO_10_ROMSCK R5000
GPIO11 AK16 AB34 1 2 FBM_11_160808_121T
56F7 GPIO_11 RSET
IN
3
1
AL16 GPIO_12 499_1%_2 C5001 C5000 C5005

10K_5%_2
AM16 AD34 0.1UF_16V_2 1UF_6.3V_2

P3V3S_DGPU GPIO_13 AVDD 10UF_6.3V_3
1
D
R5094
Q5000 AM14 GPIO_14_HPD2 AVSSQ AE34

G 1
PWRCNTL_0 AM13
2
SSM3K7002BFU OUT GPIO_15_PWRCNTL_0
G
AK14 AC33
S
GPIO_16 VDD1DI
AG30 AC34
2
GPIO_17_THERMAL_INT VSS1DI
21D3
37C6 21D2 5A7 EC_SMB2_CLK 3 2 GPU_SIC 56D5
BI D S
BI AN14 GPIO_18_HPD3
2
P1V8S_DGPU
10K_5%_2
10K_5%_2
10K_5%_2
Q5001 AM17 GPIO_19_CTF

R5061
R5063
R5015
SSM3K7002BFU 13C6 PWRCNTL_1 AL13 GPIO_20_PWRCNTL_1 R2/NC AC30

OUT I=100MA TRACE WIDTH>=15MIL
56F7 AJ14 GPIO_21_BB_EN R2B/NC AC31 L5001
P3V3S_DGPU 56F7 GPIO22 AK13 GPIO_22_ROMCSB P1V8S_VDD1DI 2 1
IN
AN13 GPIO_23_CLKREQB G2/NC AD30 FBM_11_160808_121T
1
1
1 TP14 AM23 JTAG_TRSTB G2B/NC AD31

TP30
1
1 TP15 AN23 JTAG_TDI

TP30 C5003 C5002 C5004
10K_5%_2
1 TP11 AK23 JTAG_TCK B2/NC AF30

1
0.1UF_16V_2 1UF_6.3V_2
R5095
1 TP16 TP30 AL24 JTAG_TMS B2B/NC AF31 10UF_6.3V_3

TP30 1
1
TP12 AM24 JTAG_TDO

G
2
TP30 AJ19 GENERICA
AK19 AC32
2
EC_SMB2_DATA 3 2 GPU_SID R5060 GENERICB C/NC

21D3
37C3 21D2 5A7
BI D S
BI 56D5 R5005 AJ20 AD32
10K_5%_2 GENERICC Y/NC
10K_5%_2_DY AK20 AF32
C Q5002 GENERICD COMP/NC C
AJ24
2
SSM3K7002BFU GENERICE_HPD4
1
DAC2
AH26 GENERICF_HPD5
AH24 GENERICG_HPD6 H2SYNC/GENLK_CLK AD29
P1V8S_DGPU V2SYNC/GENLK_VSYNC AC29
2
36B5 VGA_HPDET AK24 HPD1

P1V8S_DGPU IN
VDD2DI/NC AG31
R5004 AG32
L5004 VSS2DI/NC
1 2 P1V8S_DPLL_PVDD I=75MA TRACE WIDTH>=15MIL
499_1%_2
P0V6S_VREFG
1
21
FBM_11_160808_121T AG33
0.1UF_16V_2
A2VDD/NC
1UF_6.3V_2
C5011
C5012
0.1UF_16V_2
C5010
R5003 AD33
C5013 A2VDDQ/NC
249_1%_2 AH13 VREFG

10UF_6.3V_3 A2VSSQ/TSVSSQ AF33
2
R2SET/NC AA29
PVPCIE AM32 DPLL_PVDD
L5005 AN32 DPLL_PVSS

1 2 PVPCIE_DPLL_VDDC I=125MA TRACE WIDTH>=15MIL
1
DDC/AUX
DDC1CLK AM26 VGA_HDMI_DDCCLK 36D8
PLL/CLOCK BI
FBM_11_160808_121T AN31 DPLL_VDDC DDC1DATA AN26 VGA_HDMI_DDCDATA 36D8
C5014 C5015 BI
C5016
0.1UF_16V_2 AM27
1UF_6.3V_2 AUX1P
10UF_6.3V_3 AV33 XTALIN AUX1N AL27
2
B R4 AU34 XTALOUT B
1 2
DDC2CLK AM19
1M_5%_2 AL19
DDC2DATA
X5000
AW34 XO_IN
1 2
AUX2P AN20
1
AW35 AM20
12PF_50V_2
XO_IN2 AUX2N
27MHZ
C5211
C5212
12PF_50V_2
DDCCLK_AUX3P AL30
DDCDATA_AUX3N AM30
2
DDCCLK_AUX4P AL29
AF29 DPLUS DDCDATA_AUX4N AM29
THERMAL
AG29 DMINUS
DDCCLK_AUX5P AN21
DDCDATA_AUX5N AM21
TP5000
1 AK32 TS_FDO
DDC6CLK AJ30 VGA_CRT_DDCCLK 35A2

TP30 BI
AL31 TS_A/NC DDC6DATA AJ31 VGA_CRT_DDCDATA 35B2
P1V8S_DGPU BI
L5006 DDCCLK_AUX7P AK30

1 2 P1V8S_TSVDD I=20MA TRACE WIDTH>=15MIL AJ32 AK29
TSVDD DDCDATA_AUX7N
AJ33 TSVSS
1
FBM_11_160808_121T
C5017 C5018
C5019 AMD_216_0833002_FCBGA_962P
1UF_6.3V_2 0.1UF_16V_2
10UF_6.3V_3
2
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001
42B1 PEG_C_TX0_DP AA38 PCIE_RX0P PCIE_TX0P Y33 PEG_RX0_DP C5022 1 2 0.1UF_6.3V_1 PEG_C_RX0_DP 42C4
BI BI
42D1 PEG_C_TX0_DN Y37 PCIE_RX0N PCIE_TX0N Y32 PEG_RX0_DN C5023 1 2 0.1UF_6.3V_1 PEG_C_RX0_DN 42C4
BI BI
42B1 PEG_C_TX1_DP Y35 PCIE_RX1P PCIE_TX1P W33 PEG_RX1_DP C5024 1 2 0.1UF_6.3V_1 PEG_C_RX1_DP 42C4
BI BI
42D1 PEG_C_TX1_DN W36 PCIE_RX1N PCIE_TX1N W32 PEG_RX1_DN C5025 1 2 0.1UF_6.3V_1 PEG_C_RX1_DN 42C4
BI BI
42B1 PEG_C_TX2_DP W38 PCIE_RX2P PCIE_TX2P U33 PEG_RX2_DP C5026 1 2 0.1UF_6.3V_1 PEG_C_RX2_DP 42C4
BI BI
42D1 PEG_C_TX2_DN V37 PCIE_RX2N PCIE_TX2N U32 PEG_RX2_DN C5027 1 2 0.1UF_6.3V_1 PEG_C_RX2_DN 42D4
D BI BI
D
42B1 PEG_C_TX3_DP V35 PCIE_RX3P PCIE_TX3P U30 PEG_RX3_DP C5028 1 2 0.1UF_6.3V_1 PEG_C_RX3_DP 42C4
BI BI
42C1 PEG_C_TX3_DN U36 PCIE_RX3N PCIE_TX3N U29 PEG_RX3_DN C5029 1 2 0.1UF_6.3V_1 PEG_C_RX3_DN 42D4
BI BI
42B1 PEG_C_TX4_DP U38 PCIE_RX4P PCIE_TX4P T33 PEG_RX4_DP C5030 1 2 0.1UF_6.3V_1 PEG_C_RX4_DP 42C4
BI BI
42C1 PEG_C_TX4_DN T37 PCIE_RX4N PCIE_TX4N T32 PEG_RX4_DN C5031 1 2 0.1UF_6.3V_1 PEG_C_RX4_DN 42D4
BI BI
42B1 PEG_C_TX5_DP T35 PCIE_RX5P PCIE_TX5P T30 PEG_RX5_DP C5032 1 2 0.1UF_6.3V_1 PEG_C_RX5_DP 42C4
BI BI
42C1 PEG_C_TX5_DN R36 PCIE_RX5N PCIE_TX5N T29 PEG_RX5_DN C5033 1 2 0.1UF_6.3V_1 PEG_C_RX5_DN 42D4
BI BI
42B1 PEG_C_TX6_DP R38 PCIE_RX6P PCIE_TX6P P33 PEG_RX6_DP C5034 1 2 0.1UF_6.3V_1 PEG_C_RX6_DP 42C4
BI BI
42C1 PEG_C_TX6_DN P37 PCIE_RX6N PCIE_TX6N P32 PEG_RX6_DN C5035 1 2 0.1UF_6.3V_1 PEG_C_RX6_DN 42D4
BI BI
42B1 PEG_C_TX7_DP P35 PCIE_RX7P PCIE_TX7P P30 PEG_RX7_DP C5036 1 2 0.1UF_6.3V_1 PEG_C_RX7_DP 42C4
BI BI
42C1 PEG_C_TX7_DN N36 PCIE_RX7N PCIE_TX7N P29 PEG_RX7_DN C5037 1 2 0.1UF_6.3V_1 PEG_C_RX7_DN 42D4
BI BI
42B1 PEG_C_TX8_DP N38 PCIE_RX8P PCIE_TX8P N33 PEG_RX8_DP C5038 1 2 0.1UF_6.3V_1 PEG_C_RX8_DP 42C4
BI BI
C 42C1 PEG_C_TX8_DN M37 PCIE_RX8N PCIE_TX8N N32 PEG_RX8_DN C5039 1 2 0.1UF_6.3V_1 PEG_C_RX8_DN 42D4 C
BI BI
PCI EXPRESS INTERFACE

42B1 PEG_C_TX9_DP M35 PCIE_RX9P PCIE_TX9P N30 PEG_RX9_DP C5040 1 2 0.1UF_6.3V_1 PEG_C_RX9_DP 42C4
BI BI
42C1 PEG_C_TX9_DN L36 PCIE_RX9N PCIE_TX9N N29 PEG_RX9_DN C5041 1 2 0.1UF_6.3V_1 PEG_C_RX9_DN 42D4
BI BI
42A1 PEG_C_TX10_DP L38 PCIE_RX10P PCIE_TX10P L33 PEG_RX10_DP C5042 1 2 0.1UF_6.3V_1 PEG_C_RX10_DP 42C4
BI BI
42C1 PEG_C_TX10_DN K37 PCIE_RX10N PCIE_TX10N L32 PEG_RX10_DN C5043 1 2 0.1UF_6.3V_1 PEG_C_RX10_DN 42D4
BI BI
42A1 PEG_C_TX11_DP K35 PCIE_RX11P PCIE_TX11P L30 PEG_RX11_DP C5044 1 2 0.1UF_6.3V_1 PEG_C_RX11_DP 42C4
BI BI
42C1 PEG_C_TX11_DN J36 PCIE_RX11N PCIE_TX11N L29 PEG_RX11_DN C5045 1 2 0.1UF_6.3V_1 PEG_C_RX11_DN 42D4
BI BI
42A1 PEG_C_TX12_DP J38 PCIE_RX12P PCIE_TX12P K33 PEG_RX12_DP C5046 1 2 0.1UF_6.3V_1 PEG_C_RX12_DP 42C4
BI BI
42C1 PEG_C_TX12_DN H37 PCIE_RX12N PCIE_TX12N K32 PEG_RX12_DN C5047 1 2 0.1UF_6.3V_1 PEG_C_RX12_DN 42D4
U5001 BI BI
42A1 PEG_C_TX13_DP H35 PCIE_RX13P PCIE_TX13P J33 PEG_RX13_DP C5048 1 2 0.1UF_6.3V_1 PEG_C_RX13_DP 42C4
BI BI
LVDS CONTROL 42C1 PEG_C_TX13_DN G36 PCIE_RX13N PCIE_TX13N J32 PEG_RX13_DN C5049 1 2 0.1UF_6.3V_1 PEG_C_RX13_DN 42D4
VARY_BL AK27 VGA_INV_PWM_3 34B5 BI BI
OUT
DIGON AJ27 VGA_LCM_VDDEN 34D7
OUT
B PEG_C_TX14_DP G38 K30 PEG_RX14_DP 1 2 0.1UF_6.3V_1 PEG_C_RX14_DP B
42A1 BI PCIE_RX14P PCIE_TX14P C5050 BI 42C4
2
R5070 R5071 42B1 PEG_C_TX14_DN F37 PCIE_RX14N PCIE_TX14N K29 PEG_RX14_DN C5051 1 2 0.1UF_6.3V_1 PEG_C_RX14_DN 42D4
BI BI
TXCLK_UP_DPF3P AK35
42A1 PEG_C_TX15_DP F35 PCIE_RX15P PCIE_TX15P H33 PEG_RX15_DP C5052 1 2 0.1UF_6.3V_1 PEG_C_RX15_DP 42C4
TXCLK_UN_DPF3N AL36 BI BI
10K_5%_2 10K_5%_2 42B1 PEG_C_TX15_DN E37 PCIE_RX15N PCIE_TX15N H32 PEG_RX15_DN C5053 1 2 0.1UF_6.3V_1 PEG_C_RX15_DN 42D4
BI BI
1
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
CLOCK
TXOUT_U1P_DPF1P AH35
48C3 CLK_PEG_REF_DP AB35 PCIE_REFCLKP
TXOUT_U1N_DPF1N AJ36 BI
48C3 CLK_PEG_REF_DN AA36 PCIE_REFCLKN
BI PVPCIE
TXOUT_U2P_DPF0P AG38
TXOUT_U2N_DPF0N AH37 CALIBRATION
PCIE_CALRP Y30 GPU_PCIE_CALRP R5035 1 2 1.27K_1%_2

TXOUT_U3P AF35
AG36
TXOUT_U3N
1 R5039 2 AH16 PWRGOOD PCIE_CALRN Y29 GPU_PCIE_CALRN R5034 1 2 2K_1%_2
1K_5%_2
LVTMDP
R5013 0_5%_2_DY AA30 PERSTB
1 2
TXCLK_LP_DPE3P AP34 VGA_LVDS_TXCL_DP 34A8
BI
TXCLK_LN_DPE3N AR34 VGA_LVDS_TXCL_DN 34A8
BI
A P3V3S_DGPU AMD_216_0833002_FCBGA_962P A
TXOUT_L0P_DPE2P AW37 VGA_LVDS_TXDL0_DP 34A8
BI
TXOUT_L0N_DPE2N AU35 VGA_LVDS_TXDL0_DN 34A8
BI
5
TXOUT_L1P_DPE1P AR37 VGA_LVDS_TXDL1_DP 34A8

U5005
BI
VGA_LVDS_TXDL1_DN BUF_PLT_RST#
+
TXOUT_L1N_DPE1N AU39 34A8 27C3 21E3 1

BI IN
27C7
51A8
28C3 4 DGPU_PERST
TXOUT_L2P_DPE0P AP35 VGA_LVDS_TXDL2_DP 34A8 51B6
51C7 DGPU_HOLD_RST#2
BI IN
AR35 VGA_LVDS_TXDL2_DN 34A8
-
TXOUT_L2N_DPE0N
BI
TC7SZ08FU
AN36
INVENTEC
3
TXOUT_L3P
TXOUT_L3N AP37
TITLE
Block Diagram
AMD_216_0833002_FCBGA_962P
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001 U5001
DDR2 DDR2 DDR2 DDR2

GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 DDR3 DDR3
65D4
62D5 62D1 DQA<63..0> 0 DQA<0> C37 DQA0_0/DQA_0 MAA0_0/MAA_0 G24 MAA<0> 0 MAA<12..0> DQB<63..0> 0 DQB<0> C5 DQB0_0/DQB_0 MAB0_0/MAB_0 P8 MAB<0> 0 MAB<12..0> 64D4
BI OUT BI OUT
63D5 63D1 1 DQA<1> C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 MAA<1> 1 1 DQB<1> C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9 MAB<1> 1 64D7
65D8
2 DQA<2> A35 DQA0_2/DQA_2 MAA0_2/MAA_2 H24 MAA<2> 2 2 DQB<2> E3 DQB0_2/DQB_2 MAB0_2/MAB_2 P9 MAB<2> 2
3 DQA<3> E34 DQA0_3/DQA_3 MAA0_3/MAA_3 J24 MAA<3> 3 3 DQB<3> E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7 MAB<3> 3
4 DQA<4> G32 DQA0_4/DQA_4 MAA0_4/MAA_4 H26 MAA<4> 4 4 DQB<4> F1 DQB0_4/DQB_4 MAB0_4/MAB_4 N8 MAB<4> 4
5 DQA<5> D33 J26 MAA<5> 5 5 DQB<5> F3 N9 MAB<5> 5
MEMORY INTERFACE A
DQA0_5/DQA_5 MAA0_5/MAA_5 DQB0_5/DQB_5 MAB0_5/MAB_5
6 DQA<6> F32 H21 MAA<6> 6 6 DQB<6> F5 U9 MAB<6> 6
MEMORY INTERFACE B
DQA0_6/DQA_6 MAA0_6/MAA_6 DQB0_6/DQB_6 MAB0_6/MAB_6
7 DQA<7> E32 DQA0_7/DQA_7 MAA0_7/MAA_7 G21 MAA<7> 7 7 DQB<7> G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8 MAB<7> 7
8 DQA<8> D31 DQA0_8/DQA_8 MAA1_0/MAA_8 H19 MAA<8> 8 8 DQB<8> H5 DQB0_8/DQB_8 MAB1_0/MAB_8 Y9 MAB<8> 8
9 DQA<9> F30 DQA0_9/DQA_9 MAA1_1/MAA_9 H20 MAA<9> 9 9 DQB<9> H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9 MAB<9> 9
D 10 DQA<10> C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 MAA<10> 10 10 DQB<10> J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8 MAB<10> 10
11 DQA<11> A30 DQA0_11/DQA_11 MAA1_3/MAA_11 G16 MAA<11> 11 11 DQB<11> K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9 MAB<11> 11 D
12 DQA<12> F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 MAA<12> 12 12 DQB<12> K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7 MAB<12> 12
13 DQA<13> C28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 H16 MAA_BA<2> 62D4 62D7 63D4 63D8 13 DQB<13> L4 DQB0_13/DQB_13 MAB1_5/BA2 AA8 MAB_BA<2> 64D4 64D7 65D4
OUT OUT
14 DQA<14> A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 MAA_BA<0> 62D4 62D7 63D4 63D8 14 DQB<14> M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8 MAB_BA<0> 65D8 64D4 64D7
OUT OUT
15 DQA<15> E28 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 H17 MAA_BA<1> 62D4 62D7 63D4 63D8 15 DQB<15> M1 DQB0_15/DQB_15 MAB1_7/BA1 AA9 MAB_BA<1> 64D4 65D4 65D8
OUT OUT
16 DQA<16> D27 DQA0_16/DQA_16 16 DQB<16> M3 DQB0_16/DQB_16
64D7 65D4 65D8
17 DQA<17> F26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 A32 DQMA<0> 62C7 17 DQB<17> M5 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H3 DQMB<0> 64C7
BI BI
18 DQA<18> C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 DQMA<1> 62C7 18 DQB<18> N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1 DQMB<1> 64C4
BI BI
19 DQA<19> A26 DQA0_19/DQA_19 WCKA0_1/DQMA_2 D23 DQMA<2> 62C4 19 DQB<19> P6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T3 DQMB<2> 64C4
BI BI
20 DQA<20> F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 DQMA<3> 62C4 20 DQB<20> P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5 DQMB<3> 64C7
BI BI
21 DQA<21> C24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 C14 DQMA<4> 63C4 21 DQB<21> R4 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AE4 DQMB<4> 65C4
BI BI
22 DQA<22> A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 DQMA<5> 63C4 22 DQB<22> T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5 DQMB<5> 65C4
BI BI
23 DQA<23> E24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 E10 DQMA<6> 63C8 23 DQB<23> T1 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK6 DQMB<6> 65C8
BI BI
24 DQA<24> C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 DQMA<7> 63C8 24 DQB<24> U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5 DQMB<7> 65C8
BI BI
25 DQA<25> A22 DQA0_25/DQA_25 25 DQB<25> V6 DQB0_25/DQB_25
GDDR5/DDR2/GDDR3 GDDR5/DDR2/GDDR3
26 DQA<26> F22 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 C34 DQSA0_DP 62C7 26 DQB<26> V1 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 F6 DQSB0_DP 64C7
BI BI
27 DQA<27> D21 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D29 DQSA1_DP 62C7 27 DQB<27> V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3 DQSB1_DP 64C4
BI BI
28 DQA<28> A20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 D25 DQSA2_DP 62C4 28 DQB<28> Y6 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 P3 DQSB2_DP 64C4
BI BI
29 DQA<29> F20 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 E20 DQSA3_DP 62C4 29 DQB<29> Y1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 V5 DQSB3_DP 64C7
BI BI
30 DQA<30> D19 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E16 DQSA4_DP 63C4 30 DQB<30> Y3 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AB5 DQSB4_DP 65C4
BI BI
31 DQA<31> E18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 E12 DQSA5_DP 63C4 31 DQB<31> Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1 DQSB5_DP 65C4
BI BI
32 DQA<32> C18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 J10 DQSA6_DP 63C8 32 DQB<32> AA4 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AJ9 DQSB6_DP 65C8
BI BI
33 DQA<33> A18 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 D7 DQSA7_DP 63C8 33 DQB<33> AB6 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 AM5 DQSB7_DP 65C8
C BI BI C
34 DQA<34> F18 DQA1_2/DQA_34 34 DQB<34> AB1 DQB1_2/DQB_34
35 DQA<35> D17 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 A34 DQSA0_DN 62C7 35 DQB<35> AB3 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 G7 DQSB0_DN 64C7
BI BI
36 DQA<36> A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 DQSA1_DN 62C7 36 DQB<36> AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1 DQSB1_DN 64C4
BI BI
37 DQA<37> F16 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 E26 DQSA2_DN 62C4 37 DQB<37> AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 P1 DQSB2_DN 64C4
BI BI
38 DQA<38> D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 DQSA3_DN 62C4 38 DQB<38> AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4 DQSB3_DN 64C7
BI BI
39 DQA<39> E14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C16 DQSA4_DN 63C4 39 DQB<39> AD5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AC4 DQSB4_DN 65C4
BI BI
40 DQA<40> F14 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 C12 DQSA5_DN 63C4 40 DQB<40> AF1 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AH3 DQSB5_DN 65C4
BI BI
41 DQA<41> D13 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 J11 DQSA6_DN 63C8 41 DQB<41> AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8 DQSB6_DN 65C8
BI BI
42 DQA<42> F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 DQSA7_DN 63C8 42 DQB<42> AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AM3 DQSB7_DN 65C8
BI BI
43 DQA<43> A12 DQA1_11/DQA_43 43 DQB<43> AG4 DQB1_11/DQB_43
44 DQA<44> D11 J21 ODTA0 62C4 62C7 44 DQB<44> AH5 T7 ODTB0 64C4 64C7
P1V5S_DGPU DQA1_12/DQA_44 ADBIA0/ODTA0
BI DQB1_12/DQB_44 ADBIB0/ODTB0
BI
45 DQA<45> F10 DQA1_13/DQA_45 ADBIA1/ODTA1 G19 ODTA1 63C4 63C8 45 DQB<45> AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7 ODTB1 65C4 65C8
BI BI
46 DQA<46> A10 DQA1_14/DQA_46 46 DQB<46> AJ4 DQB1_14/DQB_46
47 DQA<47> C10 DQA1_15/DQA_47 CLKA0 H27 CLKA0_DP 62B3 62D4 62D7 47 DQB<47> AK3 DQB1_15/DQB_47 CLKB0 L9 CLKB0_DP 64B3 64D4 64D7
OUT OUT
DQA<48> CLKA0_DN DQB<48> CLKB0_DN
1
48 G13 G27 62B5 62C4 48 AF8 L8 64B5 64C4 64C7

DQA1_16/DQA_48 CLKA0B
OUT P1V5S_DGPU DQB1_16/DQB_48 CLKB0B
OUT
49 DQA<49> H13 DQA1_17/DQA_49
62C7 49 DQB<49> AF9 DQB1_17/DQB_49
40.2_1%_2
DQA<50> CLKA1_DP DQB<50> CLKB1_DP
1
50 J13 DQA1_18/DQA_50 CLKA1 J14 63B4 63D4 63D8 50 AG8 DQB1_18/DQB_50 CLKB1 AD8 65B4 65D4 65D8
R5052
OUT OUT
51 DQA<51> H11 H14 CLKA1_DN 51 DQB<51> AG7 AD7 CLKB1_DN
40.2_1%_2
DQA1_19/DQA_51 CLKA1B
OUT 63B5 63C8 63D4 DQB1_19/DQB_51 CLKB1B
OUT 65B5 65C8 65D4
52 DQA<52> G10 DQA1_20/DQA_52 52 DQB<52> AK9 DQB1_20/DQB_52
R5001
DQA<53> G8 K23 RASA0# DQB<53> AL7 T10 RASB0#
2
53 DQA1_21/DQA_53 RASA0B 62C4 62C7 53 DQB1_21/DQB_53 RASB0B 64C4 64C7

OUT OUT
54 DQA<54> K9 DQA1_22/DQA_54 RASA1B K19 RASA1# 63C4 63C8 54 DQB<54> AM8 DQB1_22/DQB_54 RASB1B Y10 RASB1# 65C4 65C8
OUT OUT
DQA<55> DQB<55>
1
K10 AM7
1 2
55 DQA1_23/DQA_55 55 DQB1_23/DQB_55
P1V5S_DGPU
0.1UF_16V_2
DQA<56> CASA0# DQB<56> CASB0#
1
B 56 G9 K20 56 AK1 W10 B
C5204
DQA1_24/DQA_56 CASA0B
OUT 62C4 62C7 DQB1_24/DQB_56 CASB0B
OUT 64C4 64C7
100_1%_2
0.1UF_16V_2
DQA<57> A8 K17 CASA1# DQB<57> AL4 AA10 CASB1#
100_1%_2
57 57
C5201
DQA1_25/DQA_57 CASA1B 63C4 63C8 DQB1_25/DQB_57 CASB1B 65C4 65C8
R5045
OUT OUT
58 DQA<58> C8 DQA1_26/DQA_58 58 DQB<58> AM6 DQB1_26/DQB_58
R5002
59 DQA<59> E8 DQA1_27/DQA_59 CSA0B_0 K24 CSA0#_0 62C4 62C7 59 DQB<59> AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 64C4 64C7
OUT OUT
1
DQA<60> A6 K27 DQB<60> AN4 L10

2
60 60
DQA1_28/DQA_60 CSA0B_1 P1V5S_DGPU DQB1_28/DQB_60 CSB0B_1
40.2_1%_2
DQA<61> C6 DQB<61> AP3
2
61 DQA1_29/DQA_61 61 DQB1_29/DQB_61
R5053
DQA<62> CSA1#_0 DQB<62> CSB1#_0
1
62 E6 DQA1_30/DQA_62 CSA1B_0 M13 63C4 63C8 62 AP1 DQB1_30/DQB_62 CSB1B_0 AD10 65C4 65C8
OUT OUT
63 DQA<63> A5 K16 63 DQB<63> AP5 AC10
40.2_1%_2
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
R5020
2
P1V05_REFDA_GPU L18 MVREFDA CKEA0 K21 CKEA0 62C4 62C7 CKEB0 U10 CKEB0 64C4 64C7
OUT OUT
P1V05_REFSA_GPU L20 MVREFSA CKEA1 J20 CKEA1 63C4 63C8 P1V05_REFDB_GPU Y12 MVREFDB CKEB1 AA11 CKEB1 65C4 65C8
P1V5S_DGPU OUT OUT
P1V05_REFSB_GPU AA12
1 2
MVREFSB
WEA0# WEB0#
1
1
R5033 1 2240_1%_2 L27 MEM_CALRN0 WEA0B K26
OUT 62C4 62C7 WEB0B N10
OUT 64C4 64C7
0.1UF_16V_2
0.1UF_16V_2
WEA1# WEB1#
1
R5022 1 2 N12 L15 AB11
100_1%_2
RSC_0402_DY
C5205
C5202
MEM_CALRN1 WEA1B
OUT 63C4 63C8 P3V3S_DGPU WEB1B
OUT 65C4 65C8
R5058 1 2240_1%_2 AG12
100_1%_2
MEM_CALRN2
R5021
R5012
R5023
GDDR5
GDDR5
TP13
R5048 1 2
RSC_0402_DY M12 MEM_CALRP1 MAA0_8 H23 MAA<13> 62D4 62D8 1 2 1 AD28 TESTEN MAB0_8 T8 MAB<13> 64D4 64D7 65D4 65D8
OUT OUT
R5047 1 2240_1%_2 M27 J19 63D4 63D8 W8
2
2
MEM_CALRP0 MAA1_8 5.11K_1%_2_DY TP30 MAB1_8
R5050 1 2240_1%_2 AH12 AK10

2
MEM_CALRP2 CLKTESTA
1
AL10 CLKTESTB DRAM_RST AH11 1R5029 2 1R5032 2 VM_RESET
OUT
2 R5024
THAMES
1K_5%_2
10_5%_2 51_5%_2
120PF_50V_2
R5022 OPEN
C5200
5.1K_1%_2
2 R5025
R5048 OPEN
A A
SEYMOUR
AMD_216_0833002_FCBGA_962P
2
R5022 STUFF AMD_216_0833002_FCBGA_962P
R5048 STUFF
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
U5001
P1V5S_DGPU MEM I/O
PCIE P1V8S_DGPU
1.8V_504MA L5013
AC7 VDDR1#1 PCIE_VDDR#1 AA31 P1V8S_PCIE_VDDR 1 2
AD11 VDDR1#2 PCIE_VDDR#2 AA32
10UF_6.3V_3
AF7 AA33
0.01UF_50V_2
BLM18PG221SN1D
0.1UF_16V_2
VDDR1#3 PCIE_VDDR#3
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1
1
1
C5110
C5111
C5112
C5113
C5114
C5115
AG10 VDDR1#4 PCIE_VDDR#4 AA34
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5077
C5078
C5079
C5080
C5081
C5082
C5083
C5084
C5085
C5086
AJ7 VDDR1#5 PCIE_VDDR#5 V28
AK8 VDDR1#6 PCIE_VDDR#6 W29
AL9 VDDR1#7 PCIE_VDDR#7 W30
2
G11 VDDR1#8 PCIE_VDDR#8 Y31
2
2
2
G14 AB37
VDDR1#9 PCIE_VDDR/PCIE_PVDD PVPCIE
G17 VDDR1#10
G20 VDDR1#11 PCIE_VDDC#1 G30
G23 VDDR1#12 PCIE_VDDC#2 G31
10UF_6.3V_3
G26 H29
0.1UF_16V_2
0.1UF_16V_2
VDDR1#13 PCIE_VDDC#3
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5119
C5120
C5121
C5122
C5123
C5124
C5125
C5126
E G29 VDDR1#14 PCIE_VDDC#4 H30 E
H10 VDDR1#15 PCIE_VDDC#5 J29
1
1
1
J7 VDDR1#16 PCIE_VDDC#6 J30
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
J9 L28
C5087
C5088
C5089
C5090
C5091
C5092
VDDR1#17 PCIE_VDDC#7
2
K11 VDDR1#18 PCIE_VDDC#8 M28
K13 VDDR1#19 PCIE_VDDC#9 N28
K8 VDDR1#20 PCIE_VDDC#10 R28
L12 T28
2
2
2 VDDR1#21 PCIE_VDDC#11
L16 VDDR1#22 PCIE_VDDC#12 U28
L21 VDDR1#23
PVCORE_DGPU
L23 VDDR1#24
L26 VDDR1#25 VDDC#1 AA15
L7 CORE AA17
VDDR1#26 VDDC#2
1
M11 VDDR1#27 VDDC#3 AA20
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
N11 AA22
C5129
C5130
C5132
C5133
C5134
C5135
C5136
VDDR1#28 VDDC#4
P7 AA24
P1V8S_DGPU VDDR1#29 VDDC#5
1.8V_110MA R11 VDDR1#30 VDDC#6 AA27

L5009 U11 AB16
VDDR1#31 VDDC#7
1 2 P1V8S_VDDCT
U7 AB18
2
VDDR1#32 VDDC#8
1
1
1
10UF_6.3V_3
Y11 AB21
0.1UF_16V_2
VDDR1#33 VDDC#9
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
FBM_11_160808_121T
C5093
C5094
C5095
C5096
C5097
Y7 VDDR1#34 VDDC#10 AB23
VDDC#11 AB26
VDDC#12 AB28
VDDC#13 AC17
2
2
2
VDDC#14 AC20
1
LEVEL VDDC#15 AC22
TRANSLATION
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
AC24
C5143
C5144
C5145
C5146
VDDC#16
D AF26 VDD_CT#1 VDDC#17 AC27 D

AF27 AD18
P3V3S_DGPU VDD_CT#2 VDDC#18
AG26 VDD_CT#3 VDDC#19 AD21
AG27 AD23
2
VDD_CT#4 VDDC#20
POWER
1
VDDC#21 AD26
10UF_6.3V_3
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
AF17
C5098
C5099
C5100
C5101
VDDC#22
I/O AF20
VDDC#23
AF23 VDDR3#1 VDDC#24 AF22
AF24 VDDR3#2 VDDC#25 AG16
AG23 AG18
2
VDDR3#3 VDDC#26
AG24 AG21
P1V8S_DGPU VDDR3#4 VDDC#27
1
VDDC#28 AH22
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5147
C5148
C5150
C5151
C5152
C5153
C5154
L5010 VDDC#29 AH27
1 2 P1V8S_VDDR4 AF13 VDDR4#4 VDDC#30 AH28
AF15 M26
VDDR4#5 VDDC#31 PVDDCORE_DGPU
FBM_11_160808_121T AG13 VDDR4#7 VDDC#32 N24
1
2
AG15 N27
0.1UF_16V_2
0.1UF_16V_2
VDDR4#8 VDDC/BIF_VDDC#33
1UF_6.3V_2
1UF_6.3V_2
C5106
C5102
C5103
C5108
VDDC#34 R18
VDDC#35 R21
AD12 VDDR4#1 VDDC#36 R23
AF11 VDDR4#2 VDDC#37 R26
2
AF12 VDDR4#3 VDDC#38 T17

AG11 VDDR4#6 VDDC#39 T20
1
P1V8S_DGPU
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
VDDC#40 T22
C5159
C5160
C5161
C5163
C5164
C5165
L5014 T24
VDDC#41
1 2 P1V8S_MPV
VDDC/BIF_VDDC#42 T27
U16
FBM_11_160808_121T P1V8S_DGPU VDDC#43
1
C M20 NC_VDDRHA VDDC#44 U18 C
2
0.1UF_16V_2
10UF_6.3V_3
1UF_6.3V_2
M21 U21
C5104
C5105
C5107
NC_VSSRHA VDDC#45
L5015 P1V8S_SPV18 U23
VDDC#46
1 2
VDDC#47 U26
V12 NC_VDDRHB VDDC#48 V17
FBM_11_160808_121T U12 V20
2
NC_VSSRHB VDDC#49
VDDC#50 V22
1
1
1
10UF_6.3V_3
V24
0.1UF_16V_2
VDDC#51
1UF_6.3V_2
C5206
C5207
C5208
VDDC#52 V27
1
VDDC#53 Y16
10UF_6.3V_3
PLL
1UF_6.3V_2
1UF_6.3V_2
Y18
C5265
C5266
C5166
VDDC#54
VDDC#55 Y21
2
2
VDDC#56 Y23
H7 MPV18#1 VDDC#57 Y26
H8 Y28
2
MPV18#2 VDDC#58
PVCORE_DGPU
PVPCIE
AM10 SPV18
L5016 VDDCI#1 AA13

PVPCIE_SPV10
1 2 AN9 SPV10 VDDCI#2 AB13
1
VDDCI#3 AC12
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
FBM_11_160808_121T AN10 AC15
C5188
C5189
C5190
C5191
C5192
C5193
C5195
C5197
SPVSS VDDCI#4
VDDCI#5 AD13
1
1
10UF_6.3V_3
AD16
0.1UF_16V_2
VDDCI#6
1UF_6.3V_2
C5209
C5210
C5213
VDDCI#7 M15
M16
2
VDDCI#8
VOLTAGE VDDCI#9 M18

B SENESE VDDCI#10 M23 B
2
VDDCI#11 N13
AF28 FB_VDDC VDDCI#12 N15
VDDCI#13 N17
1
10UF_6.3V_3
10UF_6.3V_3
10UF_6.3V_3
VDDCI#14 N20
C5167
C5168
C5169
AG28 FB_VDDCI VDDCI#15 N22
ISOLATED VDDCI#16 R12

CORE I/O VDDCI#17 R13
AH29 FB_GND VDDCI#18 R16
2
VDDCI#19 T12
VDDCI#20 T15
VDDCI#21 V15
VDDCI#22 Y13
AMD_216_0833002_FCBGA_962P
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5001
P1V8S_DGPU DP C/D POWER DP A/B POWER
P1V8S_DGPU
L5019 L5017
1 2 DPCD_VDD18 AP20 DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1 AN24 DPAB_VDD18 1 2
FBM_11_160808_121T AP21 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2 AP24 FBM_11_160808_121T
10UF_6.3V_3
1
0.1UF_16V_2
10UF_6.3V_3
1UF_6.3V_2
C5220
C5221
C5222
0.1UF_16V_2
1UF_6.3V_2
C5226
C5227
C5228
D AP13 AP31
DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1
AT13 AP32 D
DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2
2
2
2
AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
60C6 60B3 DPCD_VDD18 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25 DPAB_VDD18 60C3 60B3
IN IN
AP23 AP26
DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2 PVPCIE
PVPCIE
L5020 L5018
1 2 DPCD_VDD10 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33 DPAB_VDD10 1 2
FBM_11_160808_121T AP15 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 AP33 FBM_11_160808_121T
1
10UF_6.3V_3
10UF_6.3V_3
0.1UF_16V_2
0.1UF_16V_2
1UF_6.3V_2
1UF_6.3V_2
C5229
C5230
C5231
C5223
C5224
C5225
AN19 DP/DPD_VSSR#1 DP/DPB_VSSR#1 AN29
C AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29 C
2
AP19 DP/DPD_VSSR#3 DP/DPB_VSSR#3 AP30
AW20 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30
AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
R5041 R5040
1 2 AW18 DPCD_CALR DPAB_CALR AW28 1 2
P1V8S_DGPU 150_1%_2 150_1%_2
L5021 DP E/F POWER DP PLL POWER

1 2 DPEF_VDD18 AH34 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD AU28 DPAB_VDD18 60C3
IN
FBM_11_160808_121T AJ34 DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS AV27
1
1
10UF_6.3V_3
0.1UF_16V_2
1UF_6.3V_2
C5232
C5233
C5234
AL33 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD AV29

AM33 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS AR28
2
AN34 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD AU18 DPCD_VDD18 60C6

IN
AP39 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS AV17
B AR39 B
DP/DPE_VSSR#3
AU37 DP/DPE_VSSR#4
DPCD_VDD18/DPD_PVDD AV19
DP_VSSR/DPD_PVSS AR18
60B3 60B6 DPEF_VDD18 AF34 DPEF/DPF_VDD18#1

IN
AG34 DPEF/DPF_VDD18#2
PVPCIE DPEF_VDD18/DPE_PVDD AM37 DPEF_VDD18 60B6

IN
DP_VSSR/DPE_PVSS AN38
L5022
1 2 DPEF_VDD10 AK33 DPEF/DPF_VDD10#1
FBM_11_160808_121T AK34 DPEF/DPF_VDD10#2

1
1
10UF_6.3V_3
AL38
0.1UF_16V_2
DPEF_VDD18/DPF_PVDD
1UF_6.3V_2
C5235
C5236
C5237
DP_VSSR/DPF_PVSS AM35
AF39 DP/DPF_VSSR#1
AH39 DP/DPF_VSSR#2
2
AK39 DP/DPF_VSSR#3
AL34 DP/DPF_VSSR#4
AM34 DP/DPF_VSSR#5
R5042
A 1 2 AM39 A
DPEF_CALR
150_1%_2
AMD_216_0833002_FCBGA_962P
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
F F
U5001
AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
J31 PCIE_VSS#10 GND#10 AA6
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
E M34 AB27 E
PCIE_VSS#17 GND#17
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 PCIE_VSS#30 GND#30 AD20
V39 PCIE_VSS#31 GND#31 AD22
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9
Y39 PCIE_VSS#35 GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18
GND GND#40
GND#41
AF21
AG17
F15 GND#100 GND#42 AG2
F17 GND#101 GND#43 AG20
D F19 AG22 D
GND#102 GND#44
F25 GND#105 GND#47 AH21
F27 GND#106 GND#48 AJ10
F29 GND#107 GND#49 AJ11
F31 GND#108 GND#50 AJ2
F33 GND#109 GND#51 AJ28
F7 GND#110 GND#52 AJ6
F9 GND#111 GND#53 AK11
G2 GND#112 GND#54 AK31
G6 GND#113 GND#55 AK7
H9 GND#114 GND#56 AL11
J2 GND#115 GND#57 AL14
J27 GND#116 GND#58 AL17
K14 GND#119 GND/PX_EN#61 AL21 PX_EN
IN
K7 GND#120 GND#62 AL23
L11 GND#121 GND#63 AL26
L17 GND#122 GND#64 AL32
L2 GND#123 GND#65 AL6
L22 GND#124 GND#66 AL8
L24 GND#125 GND#67 AM11
L6 GND#126 GND#68 AM31
M17 GND#127 GND#69 AM9
M22 GND#128 GND#70 AN11
C M24 AN2 C
GND#129 GND#71
N16 GND#130 GND#72 AN30
N18 GND#131 GND#73 AN6
N2 GND#132 GND#74 AN8
N21 GND#133 GND#75 AP11
N23 GND#134 GND#76 AP7
N26 GND#135 GND#77 AP9
N6 GND#136 GND#78 AR5
R15 GND#137 GND#79 B11
R17 GND#138 GND#80 B13
R2 GND#139 GND#81 B15
R20 GND#140 GND#82 B17
R22 GND#141 GND#83 B19
R24 GND#142 GND#84 B21
R27 GND#143 GND#85 B23
R6 GND#144 GND#86 B25
T11 GND#145 GND#87 B27
T13 GND#146 GND#88 B29
T16 GND#147 GND#89 B31
T18 GND#148 GND#90 B33
T21 GND#149 GND#91 B7
T23 GND#150 GND#92 B9
T26 GND#151 GND#93 C1
U15 GND#153 GND#94 C39
U17 GND#154 GND#95 E35
U2 GND#155 GND#96 E5
U20 GND#156 GND#97 F11
B U22 F13 B
GND#157 GND#98
U24 GND#158
U27 GND#159
U6 GND#160
V11 GND#161
V16 GND#163
V18 GND#164
V21 GND#165
V23 GND#166
V26 GND#167
W2 GND#168
W6 GND#169
Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39
Y24 GND#174 VSS_MECH#2 AW1
Y27 GND#175 VSS_MECH#3 AW39
U13 GND#152
V13 GND#162
AMD_216_0833002_FCBGA_962P
A A
INVENTEC
TITLE
Block Diagram

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5500 U5501
62A8 VRAM_VREFC_A<0> M9 VREFCA DQL0 E4 DQA<3> 58D8 62B4 VRAM_VREFC_A<2> M9 VREFCA DQL0 E4 DQA<26> 58D8
IN BI IN BI
62A7 VRAM_VREFD_A<3> H2 VREFDQ DQL1 F8 DQA<0> 58D8 62B2 VRAM_VREFD_A<1> H2 VREFDQ DQL1 F8 DQA<31> 58D8
IN BI IN BI
DQL2 F3 DQA<4> 58D8 DQL2 F3 DQA<29> 58D8
BI BI
63D8 63D4 62D4 58D4 58A5 MAA<13..0> 0 MAA<0> N4 A0 DQL3 F9 DQA<2> 58D8 63D8 63D4 62D8 58D4 58A5 MAA<13..0> 0 MAA<0> N4 A0 DQL3 F9 DQA<25> 58D8
BI BI BI BI
1 MAA<1> P8 A1 DQL4 H4 DQA<6> 58D8 1 MAA<1> P8 A1 DQL4 H4 DQA<24> 58D8
BI BI
BI BI
3 MAA<3> N3 A3 DQL6 G3 DQA<5> 58D8 3 MAA<3> N3 A3 DQL6 G3 DQA<27> 58D8
BI BI
BI BI
5 MAA<5> P3 A5 5 MAA<5> P3 A5
6 MAA<6> R9 A6 6 MAA<6> R9 A6
7 MAA<7> R3 A7 DQU0 D8 DQA<12> 58D8 7 MAA<7> R3 A7 DQU0 D8 DQA<19> 58D8
BI BI
8 MAA<8> T9 A8 DQU1 C4 DQA<13> 58D8 8 MAA<8> T9 A8 DQU1 C4 DQA<18> 58D8
BI BI
9 MAA<9> R4 A9 DQU2 C9 DQA<9> 58D8 9 MAA<9> R4 A9 DQU2 C9 DQA<21> 58D8
BI BI
10 MAA<10> L8 A10_AP DQU3 C3 DQA<15> 58D8 10 MAA<10> L8 A10_AP DQU3 C3 DQA<16> 58D8
BI BI
11 MAA<11> R8 A11 DQU4 A8 DQA<8> 58D8 11 MAA<11> R8 A11 DQU4 A8 DQA<23> 58D8
BI BI
12 MAA<12> N8 A12 DQU5 A3 DQA<14> 58D8 12 MAA<12> N8 A12 DQU5 A3 DQA<17> 58D8
D BI BI
13 MAA<13> T4 A13 DQU6 B9 DQA<10> 58D8 13 MAA<13> T4 A13 DQU6 B9 DQA<22> 58D8
BI BI D
T8 A14 DQU7 A4 DQA<11> 58D8 T8 A14 DQU7 A4 DQA<20> 58D8
BI P1V5S_DGPU BI P1V5S_DGPU
M8 A15_BA3 M8 A15_BA3
63D8 63D4 62D4 58D5 MAA_BA<0> M3 BA0 VDD#B3 B3 63D8 63D4 62D7 58D5 MAA_BA<0> M3 BA0 VDD#B3 B3
BI BI
63D8 63D4 62D4 58D5 MAA_BA<1> N9 BA1 VDD#D10 D10 63D8 63D4 62D7 58D5 MAA_BA<1> N9 BA1 VDD#D10 D10
BI BI
63D8 63D4 62D4 58D5 MAA_BA<2> M4 BA2 VDD#G8 G8 63D8 63D4 62D7 58D5 MAA_BA<2> M4 BA2 VDD#G8 G8
BI BI
VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2
62D4 62B3 58B5 CLKA0_DP J8 CK VDD#N10 N10 62D7 62B3 58B5 CLKA0_DP J8 CK VDD#N10 N10
IN IN
62C4 62B5 58B5 CLKA0_DN K8 CK VDD#R2 R2 62C7 62B5 58B5 CLKA0_DN K8 CK VDD#R2 R2
IN IN
62C4 58B5 CKEA0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU 62C7 58B5 CKEA0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
IN IN
62C4 58C5 ODTA0 K2 ODT VDDQ#A2 A2 62C7 58C5 ODTA0 K2 ODT VDDQ#A2 A2
IN IN
62C4 58B5 CSA0#_0 L3 CS VDDQ#A9 A9 62C7 58B5 CSA0#_0 L3 CS VDDQ#A9 A9
IN IN
62C4 58B5 RASA0# J4 RAS VDDQ#C2 C2 62C7 58B5 RASA0# J4 RAS VDDQ#C2 C2
IN IN
62C4 58B5 CASA0# K4 CAS VDDQ#C10 C10 62C7 58B5 CASA0# K4 CAS VDDQ#C10 C10
IN IN
62C4 58A5 WEA0# L4 WE VDDQ#D3 D3 62C7 58A5 WEA0# L4 WE VDDQ#D3 D3
IN IN
VDDQ#E10 E10 VDDQ#E10 E10
58C5 DQSA0_DP F4 DQSL VDDQ#F2 F2 58C5 DQSA3_DP F4 DQSL VDDQ#F2 F2
BI BI
58C5 DQSA1_DP C8 DQSU VDDQ#H3 H3 58C5 DQSA2_DP C8 DQSU VDDQ#H3 H3
BI BI
VDDQ#H10 H10 VDDQ#H10 H10
C 58D5 DQMA<0> E8 DML 58D5
DQMA<3> E8 DML C
BI DQMA<1> BI DQMA<2>
58D5 D4 DMU VSS#A10 A10 58D5 D4 DMU VSS#A10 A10
BI BI
VSS#B4 B4 VSS#B4 B4
VSS#E2 E2 VSS#E2 E2
58C5 DQSA0_DN G4 DQSL VSS#G9 G9 58C5 DQSA3_DN G4 DQSL VSS#G9 G9
BI BI
58C5 DQSA1_DN B8 DQSU VSS#J3 J3 58C5 DQSA2_DN B8 DQSU VSS#J3 J3
BI BI
VSS#J9 J9 VSS#J9 J9
VSS#M2 M2 VSS#M2 M2
VSS#M10 M10 VSS#M10 M10
65C8 65C4 64C7 64C4 63C8 63C4 62C4 58A1 VM_RESET T3 RESET VSS#P2 P2 65C8 65C4 64C7 64C4 63C8 63C4 62C7 58A1 VM_RESET T3 RESET VSS#P2 P2
IN IN
R5509 VSS#P10 P10 R5508 VSS#P10 P10
1 2 L9 ZQ_ZQ0 VSS#T2 T2 1 2 L9 ZQ_ZQ0 VSS#T2 T2
VSS#T10 T10 VSS#T10 T10
243_1%_2 243_1%_2
VSSQ#B2 B2 VSSQ#B2 B2
B10 R5540 R5541 B10
VSSQ#B10
62C4 58B5 CLKA0_DN 1 2 1 2 CLKA0_DP 58B5 62D4
VSSQ#B10
VSSQ#D2 D2 IN IN VSSQ#D2 D2
62C7 56_5%_2 56_5%_2 62D7
VSSQ#D9 D9 VSSQ#D9 D9
1
J2 E3 J2 E3
0.01UF_50V_2
NC_ODT VSSQ#E3 NC_ODT VSSQ#E3
C5516
L2 NC_CSI VSSQ#E9 E9 L2 NC_CSI VSSQ#E9 E9
J10 NC_CE1 VSSQ#F10 F10 J10 NC_CE1 VSSQ#F10 F10
L10 NC_ZQ1 VSSQ#G2 G2 L10 NC_ZQ1 VSSQ#G2 G2
VSSQ#G10 G10 VSSQ#G10 G10
2
B B
A1 NC NC T1 A1 NC NC T1
SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU
2
4.99K_1%_2
4.99K_1%_2
R5504
R5506
P1V5S_DGPU
P1V5S_DGPU
2
VRAM_VREFC_A<2> VRAM_VREFD_A<1>
2
R5500
4.99K_1%_2
2 1
62D4 IN 62D4 IN
4.99K_1%_2
1
R5502
4.99K_1%_2
0.1uF_16V_2
0.1uF_16V_2
C5502
C5503
R5507
4.99K_1%_2
R5505
1
VRAM_VREFC_A<0>
1
62D7 VRAM_VREFD_A<3>
IN 62D7 IN
1
1
4.99K_1%_2
0.1uF_16V_2
1
C5500
R5501
4.99K_1%_2
R5503
0.1uF_16V_2
C5501
2
1
2
A A
P1V5S_DGPU
P1V5S_DGPU
1
1
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5528
C5529
C5530
C5531
C5532
2.2UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5520
C5521
C5522
C5523
C5524
C5525
C5533 C5534
C5526 C5527
10UF_6.3V_3 10UF_6.3V_3
10UF_6.3V_3 10UF_6.3V_3
INVENTEC
2
2
2
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5503
U5502 VRAM_VREFC_A<6> M9 E4 DQA<35>
VRAM_VREFC_A<4> M9 E4 DQA<54> 63A4 IN VREFCA DQL0
BI 58D8
63A8 IN VREFCA DQL0
BI 58D8 VRAM_VREFD_A<5> H2 F8 DQA<38>
63A3 58D8
63A6 VRAM_VREFD_A<7> H2 F8 DQA<51> 58D8 IN VREFDQ DQL1
BI
IN VREFDQ DQL1
BI F3 DQA<33> 58D8
F3 DQA<53> 58D8
DQL2
BI
DQL2
BI 63D8 62D8 62D4 58D4 58A5 MAA<13..0> 0 MAA<0> N4 F9 DQA<37> 58D8
63D4 62D8 62D4 58D4 58A5 MAA<13..0> 0 MAA<0> N4 F9 DQA<49> 58D8 BI A0 DQL3
BI
BI A0 DQL3
BI 1 MAA<1> P8 H4 DQA<32> 58D8
1 MAA<1> P8 H4 DQA<52> 58D8
A1 DQL4
BI
A1 DQL4
BI 2 MAA<2> P4 H9 DQA<39> 58D8
2 MAA<2> P4 H9 DQA<50> 58D8
A2 DQL5
BI
A2 DQL5
BI 3 MAA<3> N3 G3DQA<34> 58D8
3 MAA<3> N3 G3DQA<55> 58D8
A3 DQL6
BI
A3 DQL6
BI 4 MAA<4> P9 H8 DQA<36> 58D8
4 MAA<4> P9 A4 DQL7 H8 DQA<48> 58D8
A4 DQL7
BI
BI 5 MAA<5> P3 A5
5 MAA<5> P3 A5
6 MAA<6> R9 A6
6 MAA<6> R9 A6
7 MAA<7> R3 D8 DQA<44> 58D8
7 MAA<7> R3 D8 DQA<62> 58D8
A7 DQU0
BI
A7 DQU0
BI 8 MAA<8> T9 C4 DQA<43> 58D8
8 MAA<8> T9 C4 DQA<60> 58D8
A8 DQU1
BI
A8 DQU1
BI 9 MAA<9> R4 C9 DQA<47> 58D8
9 MAA<9> R4 C9 DQA<58> 58D8
A9 DQU2
BI
A9 DQU2
BI 10 MAA<10> L8 C3 DQA<42> 58D8
10 MAA<10> L8 C3 DQA<61> 58D8
A10_AP DQU3
BI
A10_AP DQU3
BI 11 MAA<11> R8 A8 DQA<46> 58D8
11 MAA<11> R8 A8 DQA<59> 58D8
A11 DQU4
BI
A11 DQU4
BI 12 MAA<12> N8 A3 DQA<40> 58D8
12 MAA<12> N8 A3 DQA<57> 58D8
A12 DQU5
BI
D
A12 DQU5
BI 13 MAA<13> T4 B9 DQA<45> 58D8
13 MAA<13> T4 B9 DQA<56> 58D8
A13 DQU6
BI
A13 DQU6
BI T8 A4 DQA<41> 58D8 D
T8 A14 DQU7 A4 DQA<63> 58D8
A14 DQU7
BI
BI P1V5S_DGPU M8 A15_BA3 P1V5S_DGPU
M8 A15_BA3
63D8 62D7 62D4 58D5 MAA_BA<0> M3 B3

63D4 62D7 62D4 58D5 MAA_BA<0> M3 B3 BI BA0 VDD#B3
BI BA0 VDD#B3
63D8 62D7 62D4 58D5 MAA_BA<1> N9 D10
63D4 62D7 62D4 58D5 MAA_BA<1> N9 D10 BI BA1 VDD#D10
BI BA1 VDD#D10
63D8 62D7 62D4 58D5 MAA_BA<2> M4 G8
63D4 62D7 62D4 58D5 MAA_BA<2> M4 BA2 VDD#G8 G8 BI BA2 VDD#G8
BI VDD#K3 K3
VDD#K3 K3
VDD#K9 K9
VDD#K9 K9
VDD#N2 N2
N2
VDD#N2
63D8 63B4 58B5 CLKA1_DP J8 N10
63D4 63B4 58B5 CLKA1_DP J8 N10 IN CK VDD#N10
IN CK VDD#N10
63C8 63B5 58B5 CLKA1_DN K8 R2
63D4 63B5 58B5 CLKA1_DN K8 R2 IN CK VDD#R2
P1V5S_DGPU
IN CK VDD#R2
63C8 58B5 CKEA1 K10 R10
63C4 58B5 CKEA1 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU IN CKE_CKE0 VDD#R10
IN
63C8 58B5 ODTA1 K2 A2
63C4 58B5 ODTA1 K2 A2 IN ODT VDDQ#A2
IN ODT VDDQ#A2
63C8 58B5 CSA1#_0 L3 A9
63C4 58B5 CSA1#_0 L3 A9 IN CS VDDQ#A9
IN CS VDDQ#A9
63C8 58B5 RASA1# J4 C2
63C4 58B5 RASA1# J4 C2 IN RAS VDDQ#C2
IN RAS VDDQ#C2
63C8 58B5 CASA1# K4 C10
63C4 58B5 CASA1# K4 C10 IN CAS VDDQ#C10
IN CAS VDDQ#C10
63C8 58A5 WEA1# L4 D3
63C4 58A5 WEA1# L4 WE VDDQ#D3 D3 IN WE VDDQ#D3
IN VDDQ#E10 E10
E10
VDDQ#E10
58C5 DQSA4_DP F4 F2
58C5 DQSA6_DP F4 F2 BI DQSL VDDQ#F2
BI DQSL VDDQ#F2
58C5 DQSA5_DP C8 H3
58C5 DQSA7_DP C8 DQSU VDDQ#H3 H3 BI DQSU VDDQ#H3
BI VDDQ#H10 H10
H10
VDDQ#H10 DQMA<4> E8
C DQMA<6> E8 58D5 BI DML
C
58C5 BI DML DQMA<5> D4 A10
58C5
DQMA<7> D4 DMU VSS#A10 A10 58C5 BI DMU VSS#A10
BI VSS#B4 B4
VSS#B4 B4
VSS#E2 E2
E2
VSS#E2
58C5 DQSA4_DN G4 G9
58C5 DQSA6_DN G4 G9 BI DQSL VSS#G9
BI DQSL VSS#G9
58C5 DQSA5_DN B8 J3
58C5 DQSA7_DN B8 DQSU VSS#J3 J3 BI DQSU VSS#J3
BI VSS#J9 J9
VSS#J9 J9
VSS#M2 M2
VSS#M2 M2
VSS#M10 M10
M10
VSS#M10
65C8 65C4 64C7 64C4 63C8 62C7 62C4 58A1 VM_RESET T3 P2
64C7 64C4 63C4 62C7 62C4 58A1 VM_RESET T3 RESET VSS#P2 P2 IN RESET VSS#P2
IN R5518 VSS#P10 P10
65C8 65C4 R5519 VSS#P10 P10
1 2 L9 ZQ_ZQ0 VSS#T2 T2
VSS#T10 T10
VSS#T10 T10
243_1%_2
243_1%_2 B2
B2 CLKA1_DN 1 R5542 2 1 R5543 2 CLKA1_DP VSSQ#B2
VSSQ#B2 63C8 58B5 58B5 63D4
IN IN VSSQ#B10 B10
VSSQ#B10 B10 63D4 56_5%_2 56_5%_2 63D8
VSSQ#D2 D2
1
VSSQ#D2 D2
D9
0.01UF_50V_2
VSSQ#D9
D9
C5517
VSSQ#D9
J2 NC_ODT VSSQ#E3 E3
L2 NC_CSI VSSQ#E9 E9
J10 NC_CE1 VSSQ#F10 F10
L10 NC_ZQ1 VSSQ#G2 G2
L10 G2
2
NC_ZQ1 VSSQ#G2
VSSQ#G10 G10
VSSQ#G10 G10
B B
A1 NC NC T1
A1 NC NC T1
A11 NC NC T11
A11 NC NC T11
SAM_K4B1G1646D_HCF7_FBGA_100P
P1V5S_DGPU P1V5S_DGPU
2
4.99K_1%_2
4.99K_1%_2
2
R5514
R5516
4.99K_1%_2
4.99K_1%_2
R5510
R5512
VRAM_VREFC_A<6> VRAM_VREFD_A<5>
2 1
2 1
VRAM_VREFC_A<4> VRAM_VREFD_A<7> 63D4 IN 63D4
IN
1
1
63D8 63D8
IN IN
4.99K_1%_2
4.99K_1%_2
0.1uF_16V_2
0.1uF_16V_2
C5506
R5515
C5507
R5517
1
2
1
4.99K_1%_2
0.1uF_16V_2
C5505
R5513
4.99K_1%_2
0.1uF_16V_2
C5504
R5511
1
P1V5S_DGPU
2
1
2
P1V5S_DGPU
A A
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5543
C5544
C5545
C5546
C5547
C5548 C5549
1
1
2.2UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5535
C5536
C5537
C5538
C5539
C5540
10UF_6.3V_3 10UF_6.3V_3
C5541 C5542
2
2
10UF_6.3V_3 10UF_6.3V_3
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5504 U5505
64A8 VRAM_VREFC_B<0> M9 VREFCA DQL0 E4 DQB<31> 58D4 64B4 VRAM_VREFC_B<2> M9 VREFCA DQL0 E4 DQB<13> 58D4
IN BI IN BI
64A7 VRAM_VREFD_B<3> H2 VREFDQ DQL1 F8 DQB<27> 58D4 64B2 VRAM_VREFD_B<1> H2 VREFDQ DQL1 F8 DQB<10> 58D4
IN BI IN BI
DQL2 F3 DQB<29> 58D4 DQL2 F3 DQB<9> 58D4
BI BI
65D8 65D4 64D4 58D1 58A1 MAB<13..0> 0 MAB<0> N4 A0 DQL3 F9 DQB<25> 58D4 65D8 65D4 64D7 58D1 58A1 MAB<13..0> 0 MAB<0> N4 A0 DQL3 F9 DQB<15> 58D4
BI BI BI BI
1 MAB<1> P8 A1 DQL4 H4DQB<30> 58D4 1 MAB<1> P8 A1 DQL4 H4 DQB<12> 58D4
BI BI
2 MAB<2> P4 A2 DQL5 H9 DQB<24> 58D4 2 MAB<2> P4 A2 DQL5 H9 DQB<14> 58D4
BI BI
3 MAB<3> N3 A3 DQL6 G3DQB<28> 58D4 3 MAB<3> N3 A3 DQL6 G3DQB<8> 58D4
BI BI
4 MAB<4> P9 A4 DQL7 H8DQB<26> 58D4 4 MAB<4> P9 A4 DQL7 H8 DQB<11> 58D4
BI BI
5 MAB<5> P3 A5 5 MAB<5> P3 A5
6 MAB<6> R9 A6 6 MAB<6> R9 A6
7 MAB<7> R3 A7 DQU0 D8 DQB<6> 58D4 7 MAB<7> R3 A7 DQU0 D8 DQB<20> 58D4
BI BI
8 MAB<8> T9 A8 DQU1 C4 DQB<3> 58D4 8 MAB<8> T9 A8 DQU1 C4 DQB<19> 58D4
BI BI
9 MAB<9> R4 A9 DQU2 C9DQB<2> 58D4 9 MAB<9> R4 A9 DQU2 C9 DQB<23> 58D4
BI BI
10 MAB<10> L8 A10_AP DQU3 C3DQB<7> 58D4 10 MAB<10> L8 A10_AP DQU3 C3 DQB<16> 58D4
BI BI
11 MAB<11> R8 A11 DQU4 A8 DQB<1> 58D4 11 MAB<11> R8 A11 DQU4 A8 DQB<21> 58D4
BI BI
12 MAB<12> N8 A12 DQU5 A3 DQB<4> 58D4 12 MAB<12> N8 A12 DQU5 A3 DQB<17> 58D4
D BI BI
13 MAB<13> T4 A13 DQU6 B9 DQB<0> 58D4 13 MAB<13> T4 A13 DQU6 B9 DQB<22> 58D4
BI BI D
T8 A14 DQU7 A4 DQB<5> 58D4 T8 A14 DQU7 A4 DQB<18>
BI P1V5S_DGPU BI P1V5S_DGPU
M8 A15_BA3 M8 A15_BA3
65D8 65D4 64D4 58D1 MAB_BA<0> M3 BA0 VDD#B3 B3 65D8 65D4 64D7 58D1 MAB_BA<0> M3 BA0 VDD#B3 B3
BI BI
65D8 65D4 64D4 58D1 MAB_BA<1> N9 BA1 VDD#D10 D10 65D8 65D4 64D7 58D1 MAB_BA<1> N9 BA1 VDD#D10 D10
BI BI
65D8 65D4 64D4 58D1 MAB_BA<2> M4 BA2 VDD#G8 G8 65D8 65D4 64D7 58D1 MAB_BA<2> M4 BA2 VDD#G8 G8
BI BI
VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2
64D4 64B3 58B1 CLKB0_DP J8 CK VDD#N10 N10 64D7 64B3 58B1 CLKB0_DP J8 CK VDD#N10 N10
IN IN
64C4 64B5 58B1 CLKB0_DN K8 CK VDD#R2 R2 64C7 64B5 58B1 CLKB0_DN K8 CK VDD#R2 R2
IN IN
64C4 58B1 CKEB0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU 64C7 58B1 CKEB0 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU
IN IN
64C4 58C1 ODTB0 K2 ODT VDDQ#A2 A2 64C7 58C1 ODTB0 K2 ODT VDDQ#A2 A2
IN IN
64C4 58B1 CSB0#_0 L3 CS VDDQ#A9 A9 64C7 58B1 CSB0#_0 L3 CS VDDQ#A9 A9
IN IN
64C4 58B1 RASB0# J4 RAS VDDQ#C2 C2 64C7 58B1 RASB0# J4 RAS VDDQ#C2 C2
IN IN
64C4 58B1 CASB0# K4 CAS VDDQ#C10 C10 64C7 58B1 CASB0# K4 CAS VDDQ#C10 C10
IN IN
64C4 58A1 WEB0# L4 WE VDDQ#D3 D3 64C7 58A1 WEB0# L4 WE VDDQ#D3 D3
IN IN
VDDQ#E10 E10 VDDQ#E10 E10
58C1 DQSB3_DP F4 DQSL VDDQ#F2 F2 58C1 DQSB1_DP F4 DQSL VDDQ#F2 F2
BI BI
58C1 DQSB0_DP C8 DQSU VDDQ#H3 H3 58C1 DQSB2_DP C8 DQSU VDDQ#H3 H3
BI BI
VDDQ#H10 H10 VDDQ#H10 H10
C 58D1
DQMB<3> E8 DML 58D1
DQMB<1> E8 DML C
BI DQMB<0> BI DQMB<2>
58D1 D4 DMU VSS#A10 A10 58D1 D4 DMU VSS#A10 A10
BI BI
VSS#B4 B4 VSS#B4 B4
VSS#E2 E2 VSS#E2 E2
58C1 DQSB3_DN G4 DQSL VSS#G9 G9 58C1 DQSB1_DN G4 DQSL VSS#G9 G9
BI BI
58C1 DQSB0_DN B8 DQSU VSS#J3 J3 58C1 DQSB2_DN B8 DQSU VSS#J3 J3
BI BI
VSS#J9 J9 VSS#J9 J9
VSS#M2 M2 VSS#M2 M2
VSS#M10 M10 VSS#M10 M10
65C8 65C4 64C4 63C8 63C4 62C7 62C4 58A1 VM_RESET T3 RESET VSS#P2 P2 65C8 65C4 64C7 63C8 63C4 62C7 62C4 58A1 VM_RESET T3 RESET VSS#P2 P2
IN IN
R5529 VSS#P10 P10 R5528 VSS#P10 P10
1 2 L9 ZQ_ZQ0 VSS#T2 T2 1 2 L9 ZQ_ZQ0 VSS#T2 T2
VSS#T10 T10 VSS#T10 T10
243_1%_2 243_1%_2
VSSQ#D2 D2 VSSQ#D2 D2
D9 CLKB0_DN 1 R5544 2 1 R5545 2 CLKB0_DP D9
VSSQ#D9 64C4 58B1 IN IN 58B1 64D4 VSSQ#D9
J2 NC_ODT VSSQ#E3 E3 64C7 56_5%_2 56_5%_2 64D7 J2 NC_ODT VSSQ#E3 E3
1
L2 NC_CSI VSSQ#E9 E9 L2 NC_CSI VSSQ#E9 E9
0.01UF_50V_2
J10 F10 J10 F10
C5518
NC_CE1 VSSQ#F10 NC_CE1 VSSQ#F10
L10 NC_ZQ1 VSSQ#G2 G2 L10 NC_ZQ1 VSSQ#G2 G2
VSSQ#G10 G10 VSSQ#G10 G10
B B
A1 T1 A1 T1
2
NC NC NC NC
SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU SAM_K4B1G1646D_HCF7_FBGA_100P P1V5S_DGPU
2
4.99K_1%_2
4.99K_1%_2
R5524
R5526
P1V5S_DGPU
P1V5S_DGPU
2
VRAM_VREFC_B<2> VRAM_VREFD_B<1>
2
R5520
4.99K_1%_2
2 1
64D4 IN 64D4 IN
4.99K_1%_2
1
R5522
4.99K_1%_2
0.1uF_16V_2
0.1uF_16V_2
C5510
C5511
R5527
4.99K_1%_2
R5525
1
VRAM_VREFC_B<0>
1
64D7 VRAM_VREFD_B<3>
IN 64D7 IN
1
1
4.99K_1%_2
0.1uF_16V_2
1
C5508
R5521
4.99K_1%_2
R5523
0.1uF_16V_2
C5509
2
1
2
A A
P1V5S_DGPU
P1V5S_DGPU
1
1
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5558
C5559
C5560
C5561
C5562
2.2UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5550
C5551
C5552
C5553
C5554
C5555
C5563 C5564
C5556 C5557
10UF_6.3V_3 10UF_6.3V_3
10UF_6.3V_3 10UF_6.3V_3
INVENTEC
2
2
2
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5507
U5506 VRAM_VREFC_B<6> M9 E4 DQB<39>
VRAM_VREFC_B<4> M9 E4 DQB<55> 65A4 IN VREFCA DQL0
BI 58D4
65A8 IN VREFCA DQL0
BI 58D4 VRAM_VREFD_B<5> H2 F8 DQB<35>
65A3 58D4
65A6 VRAM_VREFD_B<7> H2 VREFDQ DQL1 F8 DQB<52> 58D4 IN VREFDQ DQL1
BI
IN BI DQL2 F3 DQB<36> 58D4
F3 DQB<51> 58D4 BI
DQL2
BI 65D8 64D7 64D4 58D1 58A1 MAB<13..0> 0 MAB<0> N4 F9 DQB<37> 58D4
65D4 64D7 64D4 58D1 58A1 MAB<13..0> 0 MAB<0> N4 A0 DQL3 F9 DQB<54> 58D4 BI A0 DQL3
BI
BI BI 1 MAB<1> P8 A1 DQL4 H4 DQB<32> 58D4
1 MAB<1> P8 A1 DQL4 H4 DQB<48> 58D4 BI
BI 2 MAB<2> P4 A2 DQL5 H9 DQB<34> 58D4
BI 3 MAB<3> N3 A3 DQL6 G3 DQB<33> 58D4
3 MAB<3> N3 A3 DQL6 G3 DQB<49> 58D4 BI
BI 4 MAB<4> P9 A4 DQL7 H8 DQB<38> 58D4
BI 5 MAB<5> P3 A5
5 MAB<5> P3 A5
6 MAB<6> R9 A6
6 MAB<6> R9 A6
7 MAB<7> R3 A7 DQU0 D8 DQB<41> 58D4
7 MAB<7> R3 A7 DQU0 D8 DQB<59> 58D4 BI
BI 8 MAB<8> T9 A8 DQU1 C4 DQB<44> 58D4
8 MAB<8> T9 A8 DQU1 C4 DQB<63> 58D4 BI
BI 9 MAB<9> R4 A9 DQU2 C9 DQB<42> 58D4
9 MAB<9> R4 A9 DQU2 C9 DQB<62> 58D4 BI
BI 10 MAB<10> L8 A10_AP DQU3 C3 DQB<45> 58D4
10 MAB<10> L8 A10_AP DQU3 C3 DQB<58> 58D4 BI
BI 11 MAB<11> R8 A11 DQU4 A8 DQB<40> 58D4
11 MAB<11> R8 A11 DQU4 A8 DQB<60> 58D4 BI
BI 12 MAB<12> N8 A12 DQU5 A3 DQB<47> 58D4
12 MAB<12> N8 A12 DQU5 A3 DQB<56> 58D4 BI
D BI 13 MAB<13> T4 A13 DQU6 B9 DQB<43> 58D4
13 MAB<13> T4 A13 DQU6 B9 DQB<61> 58D4 BI
BI T8 A14 DQU7 A4 DQB<46> 58D4 D
T8 A14 DQU7 A4 DQB<57> 58D4 BI
BI P1V5S_DGPU M8 A15_BA3 P1V5S_DGPU
M8 A15_BA3
65D8 64D7 64D4 58D1 MAB_BA<0> M3 B3

65D4 64D7 64D4 58D1 MAB_BA<0> M3 B3 BI BA0 VDD#B3
BI BA0 VDD#B3
65D8 64D7 64D4 58D1 MAB_BA<1> N9 D10
65D4 64D7 64D4 58D1 MAB_BA<1> N9 D10 BI BA1 VDD#D10
BI BA1 VDD#D10
65D8 64D7 64D4 58D1 MAB_BA<2> M4 G8
65D4 64D7 64D4 58D1 MAB_BA<2> M4 BA2 VDD#G8 G8 BI BA2 VDD#G8
BI VDD#K3 K3
VDD#K3 K3
VDD#K9 K9
VDD#K9 K9
VDD#N2 N2
N2
VDD#N2
65D8 65B4 58B1 CLKB1_DP J8 N10
65D4 65B4 58B1 CLKB1_DP J8 N10 IN CK VDD#N10
IN CK VDD#N10
65C8 65B5 58B1 CLKB1_DN K8 R2
65D4 65B5 58B1 CLKB1_DN K8 R2 IN CK VDD#R2
IN CK VDD#R2
65C8 58B1 CKEB1 K10 R10 P1V5S_DGPU
65C4 58B1 CKEB1 K10 CKE_CKE0 VDD#R10 R10 P1V5S_DGPU IN CKE_CKE0 VDD#R10
IN
65C8 58B1 ODTB1 K2 A2
65C4 58B1 ODTB1 K2 A2 IN ODT VDDQ#A2
IN ODT VDDQ#A2
65C8 58B1 CSB1#_0 L3 A9
65C4 58B1 CSB1#_0 L3 A9 IN CS VDDQ#A9
IN CS VDDQ#A9
65C8 58B1 RASB1# J4 C2
65C4 58B1 RASB1# J4 C2 IN RAS VDDQ#C2
IN RAS VDDQ#C2
65C8 58B1 CASB1# K4 C10
65C4 58B1 CASB1# K4 C10 IN CAS VDDQ#C10
IN CAS VDDQ#C10
65C8 58A1 WEB1# L4 D3
65C4 58A1 WEB1# L4 WE VDDQ#D3 D3 IN WE VDDQ#D3
IN VDDQ#E10 E10
E10
VDDQ#E10
58C1 DQSB4_DP F4 F2
58C1 DQSB6_DP F4 F2 BI DQSL VDDQ#F2
BI DQSL VDDQ#F2
58C1 DQSB5_DP C8 H3
58C1 DQSB7_DP C8 DQSU VDDQ#H3 H3 BI DQSU VDDQ#H3
BI VDDQ#H10 H10
H10
VDDQ#H10 DQMB<4> E8
C DQMB<6> E8 58D1 BI DML
C
58C1 BI DML DQMB<5> D4 A10
58C1
DQMB<7> D4 DMU VSS#A10 A10 58C1 BI DMU VSS#A10
BI VSS#B4 B4
VSS#B4 B4
VSS#E2 E2
E2
VSS#E2
58C1 DQSB4_DN G4 G9
58C1 DQSB6_DN G4 G9 BI DQSL VSS#G9
BI DQSL VSS#G9
58C1 DQSB5_DN B8 J3
58C1 DQSB7_DN B8 DQSU VSS#J3 J3 BI DQSU VSS#J3
BI VSS#J9 J9
VSS#J9 J9
VSS#M2 M2
VSS#M2 M2
VSS#M10 M10
M10
VSS#M10
65C8 64C7 64C4 63C8 63C4 62C7 62C4 58A1 VM_RESET T3 P2
64C4 63C8 63C4 62C7 62C4 58A1 VM_RESET T3 RESET VSS#P2 P2 IN RESET VSS#P2
IN R5538 VSS#P10 P10
65C4 64C7 R5539 VSS#P10 P10
VSS#T10 T10
VSS#T10 T10
243_1%_2
243_1%_2 B2
VSSQ#B2
VSSQ#B2 B2
VSSQ#B10 B10
B10 R5546 R5547
VSSQ#B10
65C8 58B1 CLKB1_DN 1 2 1 2 CLKB1_DP 58B1 65D4 VSSQ#D2 D2
VSSQ#D2 D2 IN IN
65D4 56_5%_2 56_5%_2 65D8 VSSQ#D9 D9
VSSQ#D9 D9
1
J2 E3
0.01UF_50V_2
NC_ODT VSSQ#E3
L2 E9
C5519
NC_CSI VSSQ#E9
VSSQ#G10 G10
VSSQ#G10 G10
2
B B
A1 NC NC T1
A1 NC NC T1
A11 NC NC T11
A11 NC NC T11
2
4.99K_1%_2
4.99K_1%_2
2
R5534
R5536
4.99K_1%_2
4.99K_1%_2
R5530
R5532
VRAM_VREFC_B<6> VRAM_VREFD_B<5>
2 1
2 1
65D4 65D4
VRAM_VREFC_B<4> VRAM_VREFD_B<7> IN IN
1
1
65D8 65D8
0.1UF_16V_2
0.1UF_16V_2
IN IN
4.99K_1%_2
4.99K_1%_2
C5514
R5535
C5515
R5537
1
2
2
1
0.1UF_16V_2
4.99K_1%_2
C5513
R5533
4.99K_1%_2
0.1UF_16V_2
R5531
C5512
1
P1V5S_DGPU
2
1
1
2
P1V5S_DGPU
A A
1
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5573
C5574
C5575
C5576
C5577
C5578 C5579
1
1
2.2UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
1UF_6.3V_2
C5565
C5566
C5567
C5568
C5569
C5570
10UF_6.3V_3 10UF_6.3V_3
C5571 C5572
2
2
10UF_6.3V_3 10UF_6.3V_3
2
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
P5V0A_USB3
CN2001
1 VCC G1 G1
L2001
51C2
30C5 USB_P2_DN 1 2 USB_L_P2_DN 2 DATA- G2 G2
BI
51C2
30C5 USB_P2_DP 4 3 USB_L_P2_DP 3 DATA+ G3 G3
BI
4 GND G4 G4
WCM_2012_900T
SUYIN_020173GR004M555ZL_4P
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REFERENCE 9000~9999(SMALL BOARD)
D
D
POWER BUTTON
SW9000
PAD9000
4 A B 1 1
SMDPAD_1P_40X120
1
5 2
6 C D 3 C9000
MISAKI_NTC017_DA1G_E160T_6P 1000PF_50V_2_DY
PAD9001
1
SMDPAD_1P_40X120
2
DGND_PWRSW_DB D9000
C PHP_PESD5V2S2UT_SOT23_3P_DY C
B B
FIX9000 FIX9001 FIX9002 FIX9003 FIX9004 FIX9005

1
1
FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK FIX_MASK
S9000
1
SCREW540_700_NP_1P
S9001
1
SCREW540_700_NP_1P
A A
DGND_PWRSW_DB
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
D
C C
B B
A A
INVENTEC
TITLE
Block Diagram
DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS

XXX 21-OCT-2002
8 7 6 5 4 3 2 1

Toshiba Satellite C850 C855 - INVENTEC DAKAR10F DAKAR10FG PDF

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Toshiba Satellite C850 C855 - INVENTEC DAKAR10F DAKAR10FG PDF

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8 7 6 5 4 3 2 1

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC

F HSF Property:ROHS or Halogen-Free(5L3?) F

EE DATE POWER DATE

21-OCT-2002 SIZE= VER: SIZE CODE DOC.NUMBER REV

PAGE PAGE PAGE

1. COVER PAGE 26. CARDREADER 51. PCH 5 USB

9. POWER VCCIO 34. LCM CONN 60. VGA 5

19. LED 44. CPU 4 POWER

CHANGE by DATE SHEET 2 of 68

BATTERY CHARGER &

CHANGE by DATE SHEET 3 of 68

ADAPTOR +VBAT +V5A_+-5% +V5S

EC_SMB2 POWER BUDGET 12.139 A POWER BUDGET 4.711AINRUSH 0.9A

+VCORE1_+-0.5% TPS51123 AO6402L AM2321P

POWER BUDGET 20.070A V1.5_+-5% +V0.75S

POWER BUDGET 13.7 A

AVG CURRENT ~~TEST RESULT(MAX CURRENT) MODEL,PROJECT,FUNCTION

CHANGE by DATE SHEET 4 of 68

NMOS_4D3S NMOS_4D3S NMOS_4D3S

470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5 CSC0805_DY

CHANGE by DATE SHEET 5 of 68

330UF_6.3V VRP5V0A_VIN VRP5V0A_LDO

VOUT=((R6100/R6101)+1)*2 VRP5V0A_LG 6B3 14D5

CHANGE by DATE SHEET 6 of 68

CHANGE by DATE SHEET 7 of 68

CHANGE by DATE SHEET 8 of 68

14B7 EN_VCCP PVBAT

VSS_SENSE_VCCIO 0_5%_2_DY 3 10 VRP1V0_VCCP_LG L6300

CHANGE by DATE SHEET 9 of 68

SA_PG 14A6 21B6

CHANGE by DATE SHEET 10 of 68

44C2 11A3 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

21D3 EN_PVCORE R6731

1 2 VREF_CPU 11A7 11B7 11C8 11D4 11D6 11D7

A R6730 P3V3A P1V05S A

11D7 11D6 11D4 11C8 11B7 11A4 VREF_CPU 1 2

PVAXG_PG VR_SVID_DATA MODEL,PROJECT,FUNCTION

CHANGE by DATE SHEET 11 of 68

CHANGE by DATE SHEET 12 of 68

R6753 8.66K_1%_2 P3V3S_DGPU

P.S. R6750(R1) R6751(R2) R6753(R3) R6754(R4)

CHANGE by DATE SHEET 13 of 68

VCCIO VCCSA DGPU P1V8S

21B6 14A6 10A5 SA_PG SA_PG

14B8 13D2 13A2 SLP_S3#_3R 3 1

CHANGE by DATE SHEET 14 of 68

CHANGE by DATE SHEET 15 of 68

0 : KEEP DGPU IN RESET

16C7 16A6 DGPU_PWR_EN_3R 1 G SSM3K7002FU

16C4 16A1 0_5%_2

CHANGE by DATE SHEET 16 of 68

REFERENCE 0~49(PCB SCREW)

BOUNDARY SCAN TEST POINT

TP30 TP30 TP30

PCB CPU GPU WLAN

CHANGE by DATE SHEET 17 of 68

REFERENCE 50-99(HALL SENSOR)

OUT 2 LID_SW#_3 21D3

CHANGE by DATE SHEET 18 of 68

DC IN / BATTERY CHARGE LED

D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

CHANGE by DATE SHEET 19 of 68