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Abstractwe present an ultra low power (200 nA current and noise from inherently deficient matching in the summing
consumption) reverse bandgap voltage reference operational from current mirror because this mirror is outside of the bandgap
supply voltages down to 0.75 V. The reference is a part of micro- feedback loop.
processor system on chip implemented in a digital 130 nm CMOS
process and has a total area of 0.07 mm . The reference accuracy A range of solutions make use of the standard bandgap cir-
is 2.5% (5 sigma) over a temperature range of 20 to 85 C cuit topology while using the of MOS diodes as the absolute
without trimming. With trimming 0.5% accuracy is achieved. voltage reference source [2], [3]. Since MOS s are poorly
Index TermsVoltage reference, low voltage, low power, reverse controlled in a manufacturing environment, an extensiveun-
bandgap, supply supervisor. realistic for high-volume productiontrimming is required to
achieve the accurate reference voltage.
Another class of circuits implements a reverse voltage
I. INTRODUCTION bandgap principle as shown in [4]. The accuracy of these
circuits is in par with traditional bandgap but it needs the high
(2)
range of and the reference target value has been chosen based . During the non-inverting input is connected to
on simulations. Only slight adjustment have been done after (the proximity of and ensures that the offset shift
silicon bench testing (simulated magic value was 185 mV between and , caused by limited common-mode rejection
instead of measured 186 mV). of the amplifier is also small). The inverting input is connected
The trim capability was designed in for the absolute value of through capacitor to the resistive divider . The ampli-
the 256 mV and 900 mV outputs as well as for the temperature fier output voltage, , is equal to
coefficient by adjusting the . Since has excellent repeata- during sub-phase and
bility on the process used (less than 2 mV lot to lot variation), during sub-phase .
the absolute value trim is omitted and the reference magnitude The schematic of amplifier is shown in Fig. 4. Since the
is trimmed to 186 mV by 4-bit variation of N between 50 to 80 input voltage is always low, a simple two gain stage struc-
with nominal . This trim range is translating to approxi- ture (input PMOS differential pair and output device
mately V/K range of the reference temperature coefficient ) with folded cascode is used. A
with mV variation of the reference value at room temper- second gain stage is needed to increase gain and provide high
ature. We start with gain trimming of the amplifier which com- output voltage and current sourcing capability. provides the
pensates for changes (absolute value). This value is fixed cascoded Miller compensation of this 2-stage amplifier.
according to a measurement and compared with a golden Enough headroom is available for all transistor operation
value. Current trimming is used to correct the slope (changing even at 0.75 V supply due to the low of the devices used
the PTAT portion of ). All trimming is done at 25 C. (around 0.3 V for NMOS and 0.4 V for PMOS). All devices,
except , are sized for operation in weak inver-
III. SCALING AMPLIFIER sion, which improves offset, noise and gain of the amplifier.
For the chosen values and nA the mag- The absolute value of 256 mV and 900 mV output voltages
nitude of the temperature-stable is 186 mV and has to be can be trimmed in production by changing the scaling amplifier
accurately scaled up to 256 mV and 900 mV levels needed by feedback resistor ratio ( in Fig. 3).
the system. This is done via amplifier as shown in Fig. 3.
To eliminate the offset-induced error, is auto-zeroed. IV. SAMPLE/VERY LONG HOLD CIRCUIT
During the non-inverting amplifier input is connected to Ultra low energy consumption of the bandgap reference can
the biasing voltage approximately equal to while the be achieved in two ways:
amplifier output is connected to the non-inverting input. is By decreasing currents running in the core with use of the
generated in biasing part as fraction of by splitting resistor prohibitively large resistors in 100s of MOhms range.
by the ratio of capacitors (see Fig. 2). It operates in Even if these resistors were realistic they would increase
a follower configuration, averaging the offset on the capacitor the bandgap noise. We could not find any publications
1518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012
on the noise in ultra low power bandgaps, but according The generation in our circuit takes approximately
to simulations the peak-to-peak noise in the bandgap 250 s. The total current consumption of the reference core and
with 100200 nA consumption becomes a dominant error scaling amplifier during this period is about 6 A. We chose
source. a 100 ms period between refreshlonger than most of system
By activating bandgap core for short periods of time and events-so the average current consumption of the reference
sampling reference voltage on the capacitor. Low charge core itself is around 1520 nA. The total consumption of the
leakage from this capacitor during long hold periods is circuit ( 200 nA) is dominated by service circuitry (start-up,
critical for accuracy of such a reference. biasing, timing oscillator, etc.).
The reference value varies between every sampling de- Charge leakage from the capacitor in the standard
pending on the peak-to-peak noise and errors in the reference sample/hold (S/H) circuit [Fig. 5(a)], is dominated by the junc-
core and scaling amplifier during the sampling process. tion leakage of the switch (drain-body plus drain-source
Throughout the hold period the reference voltage is virtually currents). Junction leakage is roughly proportional to the
noiseless as the hold capacitor does not generate noise. In such voltage drop across junction. Therefore low leakage and long
a sampled operation mode it can be an advantage when refresh hold time S/H can be realized by keeping zero voltage across
timing of the reference is correlated with system events. drain-source and drain-body of the switch.
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1519
The circuit shown in Fig. 5(b) keeps the voltage across drain-
body and drain-source of equal to the offset of the fol-
lower . The output current of this follower is equal to
the total of junction leakages from . These leakages
do not exceed a few pA even at high temperature. A follower
tail current of 2 nA is more than sufficient to provide the output.
While consuming only 2 nA current, active control of the S/H
leakage proved to be quite efficient. Test chip measurements
Fig. 12. Layout of the reference. show that the voltage decay across (5 pF value) is well inside
1520 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012
the reference error window during the 100 ms hold time even at that voltage from capacitor has to be buffered. This buffer
85 C. should:
Sampling of the voltage is done during part of each provide up to 1 mA output current;
of the (256 mV output) and (900 mV output) time be stable with any load capacitor (few pF of on-chip ca-
steps. To allow for transient settling a 510 s delay at the pacitance in parallel with unpredictable external load);
beginning of the phases is introduced. consume only few A from supply.
These requirements are achieved using a nested gain design
V. SAMPLING AND BUFFERING OF THE 256 MV REFERENCE [6] as shown in Fig. 7. The main gain path consists of the differ-
The S/H circuit of Fig. 5(b) is utilized for sampling the ential pair , the folded cascode , and the
900 mV voltage needed by the POR comparator. A comple- follower . The current gain of the transistor is boosted
mentary circuit for sampling the 256 mV voltage needed for by the loop, which is amended by circuit controlling
the ADC is not possible in the process due to the substrate body the minimum current through and providing pull-down ca-
connection of all NMOS devices on chip. pability in the buffer. This circuit includes pull-down transistor
To circumvent this limitation, the switch used in the and voltage source .
complimentary S/H circuit of Fig. 6 is PMOS type instead of While consuming only 1 A this buffer has 500 kHz band-
NMOS. To turn it ON during sampling its gate is driven below width and is stable with an on-chip load capacitor of only 20 pF
substrate by the charge pump . as well as with external one of 0.1 F or more.
The 256 mV reference is used by the on-chip ADC, but The offset of the buffer (up to 5 mV) can significantly
also may be routed to the pin for external use, which means damage accuracy of the 256 mV reference.
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1521
TABLE I
REFERENCE PARAMETERS AND COMPARISON
The 20 kHz oscillator has an RC ring topology and consumes the sub-volt class of voltage references. Using switched-capac-
approximately half of the 200 nA current budget of the refer- itor techniques for reference generation is not only solving lim-
ence. It is also clock to a state machine which provides digital itations imposed by the digital CMOS process, but also allows
signals to enable the bandgap core once every 100 ms as well us to decrease the minimum operating voltage by 150 mV, com-
as all the timing signals for the reference sampling sequence. pared to the reverse bandgap presented in [4]. This technique
well aligns to the introduced S/H buffer approach which enables
the design of a voltage reference with nano-power consumption
VII. SIMULATION AND MEASUREMENTS RESULTS
while preserving low noise and high accuracy.
This bandgap reference is implemented in a standard dig-
ital CMOS process with 130 nm minimum channel length. The ACKNOWLEDGMENT
layout of the cell is shown in Fig. 12. It occupies 70,000 m of The authors thank Gerd Poeschl for measuring the statistical
area. Approximately 30% of it is taken by the resistors, mainly data, Thomas Tost and Estelle Tay for floor planning and layout,
in the biasing core (Fig. 10). Having a high-ohmic resistor and Alicia Fresno-Delso for laboratory measurement support.
option available would therefore significantly shrink the circuit
size. REFERENCES
The highest error of the reference voltage comes from ripple
[1] H. Banba, A. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,
during the sampling procedure. This ripple on the 256 mV ref- and K. Sakui, A CMOS bandgap reference circuit with sub-1-V oper-
erence output can be as large as 20 mV peak to peak. A typical ation, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670674, May
ripple waveform is shown in Fig. 13. The ripple can be elimi- 1999.
[2] K. N. Leung and P. K. T. Mok, A CMOS voltage reference based on
nated by better timing and non-overlapping control in the sam- weighted DVGS for CMOS low dropout linear regulators, IEEE J.
pling circuitry, combined with charge injection compensation. Solid-State Circuits, vol. 38, no. 1, pp. 146150, Jan. 2003.
However, for the use case in this system this is not needed. The [3] K. Ueono, T. Hirose, T. Asai, and Y. Amemiya, A 300 nW 15 ppm/ C
20 ppm/V CMOS voltage reference circuit consisting of subthreshold
sampling is timed to system events and the reference is not used MOSFETs, IEEE J. Solid-State Circuits, vol. 44, pp. 20472054, July
during ripple moments. 2009.
Comparing SPICE simulation results, the temperature vari- [4] K. Sanborn, D. Ma, and V. Ivanov, A sub-1-V low-noise bandgap
voltage reference, IEEE J. Solid-State Circuits, vol. 42, pp.
ation of the reverse bandgap reference voltage is similar to a 24662481, Nov. 2007.
classic bandgap curvature as shown in Fig. 14. Its curvature is [5] Y. Tsividis, Accurate analysis of temperature effects in
even lower than the classic bandgap temperature variation in the characteristics with application to bandgap reference sources, IEEE
J. Solid-State Circuits, vol. 15, no. 5, pp. 10761084, Dec. 1980.
same temperature range % due to the complicated temper- [6] V. Ivanov, Design methodology and circuit techniques for any-load
ature dependence of the diode biasing current. This biasing cur- stable LDOs with instant load regulation and low noise, in Advanced
rent is defined by the voltage drop across resistor of Fig. 2 Analog Circuit Design. New York: Springer, 2008.
(which has a negative TC) and the nonlinear temperature depen- Vadim Ivanov (M96) received the M.S.E.E. degree
dence of the poly resistor itself. in 1980, and the Ph.D. in 1987, both in the USSR.
The measured temperature variation of the 256 mV reference He designed electronic systems and ASICs for
naval navigation equipment from 1980 to 1991 in
voltage of the trimmed set of 180 units is shown in Fig. 15 and St. Petersburg, Russia and mixed signal ASICs for
supply variation is in Fig. 16. All data has been taken on pack- sensors, GPS/GLONASS receivers and for motor
aged parts. control between 1991 and 1995. He joined Burr
Brown (presently Texas Instruments/Tucson) in
The slightly negative dependence of the output voltage is at- 1996 as a senior member of technical staff, where
tributed to incorrect capacitance layout extraction which caused he designed multiple operational, instrumentation,
a change in the capacitor divider ratio. power amplifiers and voltage references as well as
switching and linear voltage regulators. He has more than 60 US patents and
The distribution of the untrimmed and trimmed reference applications on analog circuit techniques and authored around 30 technical
values in production is shown in Fig. 17. The data out of 90,000 papers and three books: Power Integrated Amplifiers (Leningrad, Rumb, 1987),
units from five wafer lots are taken for the purpose. Analog System Design Using ASICs (Leningrad, Rumb, 1988), both in Russian,
and Operational Amplifier Speed and Accuracy Improvement (Kluwer, 2004).
Untrimmed references have approximately % variation
in reference voltage (3 sigma). This is similar to the classic
bandgap spread. With trimming precision of less than 0.5%
(3 sigma) is achieved. Table I compares this design to prior Ralf Brederlow (SM06) was born in Munich, Ger-
many, in 1970. He received the Dipl.-Phys. degree
state of the art references. With the exception of [4] the new from the Technical University of Munich in 1996 and
concepts allows for higher precision at a lower power and the Dr.-Ing. degree from the Technical University of
similar area. Since [4] uses complementary bipolar transistors Berlin in 1999.
In 1996 he was associated with Siemens Corpo-
it cannot be used in standard digital CMOS technologies. rate Research, working on the characterization, mod-
eling and reliability of noise in analog circuits. 1999
he joined Corporate Research of Infineon Technolo-
VIII. CONCLUSION gies, working as designer and project manager for de-
sign/technology co-optimization. During this period
We have introduced a new reference circuit concept able to he worked on noise tolerant analog and digital module design, on design for
operate down to supply voltages as low as 0.75 V. The circuit manufacturing for analog CMOS circuits, polymer electronics for RFID, and
sensor systems for bio-chemical applications. In 2005 he joined Infineon Tech-
consumes 170 nW of power and the reverse bandgap operation nologies Smart Card division. There he was responsible for the development of
principle for reference generation enables the best accuracy in the analog power and communication interface block for a new dual mode smart
IVANOV et al.: AN ULTRA LOW POWER BANDGAP OPERATIONAL AT SUPPLY FROM 0.75 V 1523
card IC family. In October 2006 he joined Texas Instrument Germany as Senior Johannes Gerber (M98) received the Dipl.-Ing. de-
Member of Technical Staff and leader of a design team for analog peripherals for gree in electrical engineering from the University of
TIs ultra low power 16 bit microcontrollers (MSP430). This included designs Erlangen-Nuernberg, Germany, in 1993.
of analog-to-digital, and digital-to-analog converters, power management and From 1993 to 1998, he worked at the Fraunhofer
clock circuitry, and communication interface blocks. From September 2008 to Institute for Integrated Circuits IIS in Erlangen, Ger-
January 2011 he was responsible for new IP development (analog, digital, and many in the field of integrated sensors in CMOS and
memory) within TIs MSP430 microcontroller family. Since February 2011 he analog circuit design. In 1998 he joined the RF de-
is a Distinguished Member Technical Staff responsible for predevelopment of sign group at Texas Instruments in Freising, Germany
new technology and IP for the ultra low power microcontroller families at Texas where he concentrated on the CMOS integration of
Instruments. frequency synthesizers and high speed serial commu-
Dr. Brederlow has authored or co-authored more than 50 technical publica- nication devices. He later focused on low power/low
tions and holds 10 patents. He has been General Program Chair of the 2008 voltage circuits. He is currently working in the MSP430 microcontroller de-
International Electron Device Meeting (IEDM), is a member of the European partment. His research interests include bandgaps, operational amplifiers, oscil-
Solid State Device and Circuit (ESSDERC/ESSCIRC) steering committee, and lators, LDOs with low and ultra low power consumption.
the European Solid State Circuit Conference technical committee. From 2000 to
2005 he participated in the International Roadmap for Semiconductors (ITRS)
as member and sub-group lead in the wireless technology and the design tech-
nical working group. Ralf Brederlow is a Senior Member of IEEE, and a member
of VDE and of DPG.